Integrated circuit comprising at least one memory cell having an anti-fuse device

Abstract

An integrated circuit includes a memory cell, the memory cell including an anti-fuse device. The anti-fuse device includes a state transistor having a control gate and a second gate configured to float. A dielectric layer between the control gate and the second gate is selectively disconnected to impart a breakdown state on the anti-fuse device, wherein the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the anti-fuse device is in a non-breakdown state for storing a second logic state.

Description

[0001] Priority claim

[0002] This application claims priority from French patent application No. 1857840, filed on August 31, 2018, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments relate to integrated circuits, in particular, to integrated anti-fuse devices, and more particularly, to protecting integrated circuits from reverse engineering, such as protecting memory-storage integrated circuits from attacks via probes. Background Art

[0004] Integrated circuits, in particular those provided with memories containing sensitive information, must be protected to the greatest extent possible against reverse engineering operations, in particular those aimed at revealing the stored data.

[0005] The stored data may be, for example, binary information and may be stored on an anti-fuse device comprising two terminals, the anti-fuse device being in a broken down (or on) state to represent a first binary value, or in a non-broken down (or off) state to represent a second binary value of the data.

[0006] A possible attack could be performed after thinning the integrated circuit to get as close as possible to the anti-fuse device in order to measure the resistance between the two terminals of the anti-fuse device and in this way learn its state.

[0007] Schemes exist that allow the operation of thinning an integrated circuit to be detected and, if a thinning operation has occurred, render the stored data unreadable.

[0008] While these schemes are effective, they can be difficult to implement or circumvent in certain circumstances.

[0009] There is a need to fabricate a technically simple anti-fuse device structure that is easy to read, particularly when used in a memory cell. Summary of the invention

[0010] According to an embodiment, a new anti-fuse device structure is proposed, which may be particularly useful for data storage and whose analysis is complex in the context of reverse engineering operations, most particularly in the context of memory modules having a matrix architecture.

[0011] According to one aspect, an integrated circuit is provided, which includes at least one memory cell, the at least one memory cell including an anti-fuse device, the anti-fuse device including a state transistor having a control gate and a second gate, the second gate being configured to be floating so as to impart a non-breakdown state to the anti-fuse device, or to be electrically coupled to the control gate so as to impart a breakdown state to the anti-fuse device.

[0012] It is technically simple to incorporate an anti-fuse device into a dual-gate state transistor structure (a structure having a control gate and a floating gate) because the present embodiment employs the existing dual-gate state transistor structure and only requires the dielectric layer between the two gates to be broken down or not broken down.

[0013] Furthermore, combining the anti-fuse device with a MOS transistor advantageously allows the state of the anti-fuse device to be read by biasing the transistor, thereby avoiding the formation of contacts on the second gate. Thus, it is not possible for an attacker to measure the resistance between the two gates to achieve the purpose of knowing the state of the anti-fuse device.

[0014] The state transistor may include at least a first polysilicon region and a second polysilicon region separated by a dielectric material layer, the second gate includes the first polysilicon region, and the control gate includes the second polysilicon region, and the breakdown state of the anti-fuse device results in an electrical connection between the first polysilicon region and the second polysilicon region through the dielectric material layer.

[0015] The integrated circuit may include a conductive connection element including a first end electrically coupled to the second gate and a free second end located outside the integrated circuit.

[0016] The integrated circuit may include a seal ring including metal traces and vias extending around the entire periphery of the integrated circuit, the connection element includes an intersection portion intersecting the seal ring, and the second end is located outside the seal ring.

[0017] This sealing ring advantageously allows the integrated circuit to be protected, in particular during the dicing step.

[0018] According to one embodiment, an integrated circuit includes: a semiconductor well, the bottom of which is defined by a buried semiconductor region and includes an insulated vertical electrode, which extends downward from the upper surface of the well to a region near the bottom of the well; a heavily n-doped region, providing electrical continuity between the vertical electrode and the buried semiconductor layer, the vertical electrode including the first polysilicon region and forming a second gate, and the state transistor is a vertical transistor.

[0019] The memory cells may advantageously be interconnected according to a matrix architecture, each memory cell comprising an access transistor coupled between a MOS transistor and a read line common to all memory cells.

[0020] For a memory cell to be read, it is required that the access transistor of the memory cell be turned on and other access transistors on the line remain in the off state in order to prevent parasitic currents from propagating on the read line and tampering with the result.

[0021] Therefore, the attacker has to use a different probe for each access transistor on the line, which makes the read operation very complicated or even impossible when the matrix includes a large number of columns (eg, more than 10 columns or so).

[0022] A plurality of memory cells may share the same first polysilicon region.

[0023] According to one aspect, a semiconductor wafer is proposed, comprising a first region, the first region comprising an integrated circuit as defined above; the first regions are separated from each other by a second region comprising a cutting line, wherein the second end of a connecting element of at least one integrated circuit is located in the second region, so that the integrated circuit and the second end are located on both sides of the corresponding cutting line.

[0024] Thus, the memory cells can be programmed via the connecting elements before the step of sawing the integrated circuit.During the sawing operation, the connecting elements are severed so that the first polysilicon region is no longer connected to the fixed potential.

[0025] According to one aspect, a method for programming at least one memory cell is proposed, which memory cell includes an anti-fuse device as defined above, the method comprising: forming an electrical connection between a control gate and a second gate so as to have operation in the breakdown state, or placing the second gate in a floating state so as to have operation in the non-breakdown state.

[0026] The operation of programming the at least one memory cell may include: setting the potential of the second gate to a first reference potential via a connecting element; applying or not applying the second reference potential so as to place the anti-fuse device in a breakdown state or a non-breakdown state, respectively; and cutting the connecting element so that the second end of the connecting element is free.

[0027] According to an aspect, a method for reading at least one memory cell of an integrated circuit as defined above is proposed, wherein a control gate of a state transistor is biased and a drain current of the state transistor is read. A drain current read below a threshold value indicates a non-breakdown state of an anti-fuse device, and a drain current read above said threshold value indicates a breakdown state of the anti-fuse device.

[0028] According to another aspect, a chip card incorporating an integrated circuit as defined above is proposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Other advantages and features of the present invention will become apparent upon examination of the detailed description of complete non-limiting embodiments and examples of the present invention and of the accompanying drawings, in which:

[0030] Figure 1 is a top view of a semiconductor wafer;

[0031] Figure 2 is a schematic cross-sectional view of an integrated circuit;

[0032] Figure 3 yes Figure 2 sectional view of;

[0033] Figure 4 Illustrate the steps of the programming method;

[0034] Figure 5 The diagram shows the singulation steps;

[0035] Figure 6 illustrates the operation of reading information contained in a memory cell;

[0036] Figure 7 This is a partial schematic diagram from the electrical point of view of the wiring of the matrix;

[0037] Figure 8 illustrates an alternative embodiment using vertical transistors; and

[0038] Fig. 9 The diagram shows a system (eg a chip card CP) comprising an integrated circuit. DETAILED DESCRIPTION

[0039] Figure 1 A view from above of a semiconductor wafer 1 (eg made of silicon) is shown.

[0040] The wafer 1 comprises a first zone Z1 containing the integrated circuits CI and a second zone Z2 separating the first zone Z1 and containing a cutting path LD along which the wafer 1 will be cut in order to singulate the integrated circuits CI.

[0041] The operation of cutting semiconductor wafers can be conventionally performed using a special circular saw with a diamond blade and / or using a cutting laser. This operation is conventional and known per se.

[0042] Each integrated circuit CI comprises a memory module MM including a plurality of memory cells.

[0043] Located at the periphery of the integrated circuit is a sealing ring AT which advantageously allows the integrated circuit CI to be protected from the potential propagation of chips, fragments or any other impurities during the operations of dicing the wafer 1 .

[0044] The sealing ring AT also forms a barrier to prevent water vapor from intruding into the interconnection part of the integrated circuit (also called BEOL (back end of line), involving the interconnection metallization layer), which is particularly advantageous when the interconnection part includes an insulating area with a low dielectric constant (low dielectric constant material, low-K material).

[0045] The integrated circuit CI may include a plurality of sealing rings in order to further improve the sealing performance of the integrated circuit.

[0046] Each integrated circuit CI includes at least one connecting element LI, which extends from the memory module MM to the outside of the integrated circuit CI, into the second zone Z2 and further across the cutting line. Each connecting element LI includes a crossing portion and a crossover portion, the crossing portion crosses the sealing ring without being electrically coupled to the sealing ring, and the crossover portion crosses the cutting line. Therefore, the cutting operation cuts off the connecting element LI.

[0047] Figure 2 is a schematic cross-sectional view of an integrated circuit CI. The integrated circuit C is manufactured in and on a semiconductor substrate SB (for example, a P-type doped substrate here), which itself is covered by an interconnection portion INT (which includes a pre-metallization layer area and multiple metallization layers). The substrate S can be divided into multiple wells CN by isolation regions 10 (for example, shallow trench isolation (STI)) or by local oxidation of silicon (LOCOS).

[0048] Figure 2 Particularly shown is a portion of a first zone Z1 of an integrated circuit comprising memory cells CM of a memory module, a sealing ring AT and a portion of a connecting element LI which is produced to extend further into a second zone Z2 and adjoins the first zone Z1 .

[0049] The sealing ring AT comprises a first contact 7 (for example made of tungsten) forming a wall, and a series of superimposed metal traces and vias associated with the metallization layers.

[0050] For simplicity, the figure only shows the first metal traces PST10 and PST11 located on the first metallization layer and the second metallization layer, and the via 9 forming the wall between the two first traces PST10 and PST11. In practice, the sealing ring AT may include as many vias and metal traces as possible according to the expected height of the sealing ring.

[0051] The sealing ring AT is manufactured on the stacked structure STR, or the lower part of the sealing ring is directly manufactured on the substrate SB. Figure 3 It is along Figure 2 Cross-sectional view along cutting line III-III.

[0052] The stacking structure STR includes:

[0053] - a first polycrystalline silicon strip 3, produced on a first dielectric layer 2 and covered by a second dielectric layer 4, for example layers 2 and 4 made of silicon oxide or oxide-nitride-oxide alloy layers (known by the acronym ONO to those skilled in the art). The strip 3 is thus encapsulated in a dielectric material;

[0054] a second polysilicon strip 5 covering part of the length of the dielectric layer 4; and

[0055] A metal silicide layer 80 covering the entire length of the second polysilicon strip 5 .

[0056] In the example described here, the structure STR includes two polysilicon strips 3 and 5. This is because the manufacturing steps used to manufacture the structure STR generally correspond to the steps used to manufacture floating gate transistors elsewhere on the integrated circuit, as will be discussed below. Specifically, the manufacture of the floating gate includes manufacturing a stack of two polysilicon strips separated by an insulating layer.

[0057] Therefore, it is particularly advantageous and economical to adapt the floating gate manufacturing process to the manufacturing of the structure STR, since this can avoid performing specific manufacturing steps for the structure STR.

[0058] That is, the structure STR of the sealing ring AT may include only a single polysilicon strip, such as the first polysilicon strip 3, which is insulated from the substrate SB by a dielectric layer, such as the second dielectric layer 2. In this case, the contact 7 will be directly manufactured on the dielectric layer 4, and the first strip 3 can be insulated from the sealing ring AT only by this layer.

[0059] The structure STR forming the lower part of the seal ring comprises a cross-section TRA of connecting elements. The cross-section is formed here by a polysilicon strip 3 which is electrically insulated from the substrate SB and the rest of the seal ring by a second layer 4 of dielectric material and the second polysilicon strip.

[0060] The cross-section CHE of the connecting element LI here comprises:

[0061] - a second metal contact 72 (here a tungsten contact), which contacts the polysilicon strip 3 via the first silicided region 81;

[0062] a second metal trace PST2 coupled to a second metal contact 72 formed in the first metal layer and extending from the first zone Z1 across the cut line LD into the second zone Z2; and

[0063] A third tungsten metal contact 73 , which is coupled to the second metal trace PST2 and to the substrate SB via the second silicided region 82 .

[0064] The memory module MM has a capacity of 1 kilobit (ie it comprises 1024 binary memory cells), each of which can contain a piece of binary information. For the sake of simplicity, a single memory cell CM is shown here.

[0065] The memory cell CM comprises an element allowing the storage of binary information, here an anti-fuse device DIS, and an access transistor allowing the reading of said information, for simplicity, Figure 2 The access transistor is not shown.

[0066] Typically, the anti-fuse device includes a state transistor TR having a control gate EC, a second gate FG separated from the control gate EC by a dielectric layer 41, and another dielectric layer 2 separating the second gate FG from a well CN therebelow.

[0067] Therefore, the anti-fuse device has the structure of a dual gate state transistor, as will be described in more detail below, whose second gate can be floating or electrically connected to the control gate EC according to the breakdown state or non-breakdown state of the anti-fuse device.

[0068] The transistor TR comprises a first polysilicon region POL1 , here part of a first polysilicon strip 3 , and a second polysilicon region POL2 , here part of a second polysilicon strip 5 , which is separated from the first polysilicon region POL1 by a dielectric layer 41 , wherein the dielectric layer 41 is part of the second insulating layer 4 .

[0069] Therefore, the second polysilicon region POL2 forms the control gate EC of the MOS transistor, and the first polysilicon region POL1 forms the second gate FG of the MOS transistor TR.

[0070] On the source S, drain D regions and the control electrode EC, contacts (not shown) are formed via the silicided region 8 .

[0071] The material continuation CNT between the first polysilicon strip 3 and the first polysilicon region POL1 and between the second dielectric layer 4 and the portion 41 is shown as a dotted line. These materials are not in Figure 2 in the plane.

[0072] The portion 41 of the second dielectric layer 4 located below the control electrode includes a first portion DL1 and a second portion DL2. The first portion DL1 has a first thickness, for example, 100 angstroms here. To 200 Angstroms The second portion is thinned relative to the rest of the dielectric layer DL and has a thickness of 15 Å. and 30 angstroms The remaining portion of the second dielectric layer 4 has the first thickness.

[0073] The anti-fuse device is configured to be broken down when a voltage between the first polysilicon region POL1 and the second polysilicon region POL2 is higher than a breakdown voltage (eg, about 5 volts here) of the anti-fuse device DIS.

[0074] When the voltage is exceeded, an electrical path is formed at the thinned portion DL2 between the first polysilicon region POL1 and the second polysilicon region POL2 .

[0075] The entirety of the portion 41 of the second dielectric layer 4 may have the second thickness. That is, the presence of the defined thinned portion enables better control of the breakdown voltage.

[0076] Therefore, the memory module MM can be programmed by breaking down or not breaking down the anti-fuse device of each memory cell CM. Figure 4 Graphical programming method.

[0077] Breakdown is achieved by applying a reference potential, here ground potential, to the first polysilicon region POL1 via the connecting element LI (step E1), and by applying a potential to the second polysilicon region POL2 so as to obtain a voltage greater than 5 Volts between the first polysilicon region POL1 and the second polysilicon region POL2 (step E20).

[0078] In order not to break down the anti-fuse device DIS, the second polysilicon region POL2 may be unbiased, or the second polysilicon region POL2 may be biased so that the voltage between the polysilicon regions is lower than the breakdown voltage (step E21 ).

[0079] The second potential may be applied to the second polysilicon region POL2 through a bias circuit inside the integrated circuit CI.

[0080] Since all connection elements LI of the integrated circuit CI connected to the second gates of the anti-fuse devices are coupled to the substrate SB here, the substrate SB can be coupled to ground so as to apply the ground potential to all first polysilicon regions POL1 of the memory cells.

[0081] The first polysilicon regions may also be coupled to each other and to one or more common connection elements by a continuation of the polysilicon material.

[0082] Once the programming is performed, Figure 5 As shown, in the cutting step, a saw SC is used to singulate each integrated circuit CI along the cutting line LD ( Figure 4Step E3 of ). The connecting element LI is thus cut off at the peripheral edge of the circuit and the first polysilicon region POL1 is no longer connected to the fixed potential (and thus forms a floating node) because the second end of the connecting element is free. Before the cutting, the charge of the first polysilicon region was very low due to its coupling to ground. It is also possible to cut the stack of the two polysilicon strips 3 and 5 of the structure STR outside the sealing ring AT (for example between the sealing ring AT and the second metal contact 72) so that at the cutting position at the peripheral edge of the circuit, it is more difficult to achieve a potential contact with the floating node through the cut integrated circuit CI.

[0083] If the anti-fuse device DIS is not broken down, biasing of the substrate of the transistor TR (i.e., the region in which the channel is formed) will occur through the portion 41 of the insulating layer 4, the second gate FG, and the gate oxide 2. In this case, the threshold voltage of the MOS transistor will not be reached, and the MOS transistor will remain in the off state.

[0084] If the anti-fuse device DIS is broken down, the control gate EC and the second gate FG are electrically coupled to each other. The two polysilicon regions POL1 and POL2 form the same gate, and biasing of the substrate of the transistor TR occurs only through the gate oxide.

[0085] In this case, the threshold voltage of the MOS transistor will be reached and the MOS transistor will be in the on state.

[0086] like Figure 6 As shown, the operation of reading the information contained in the memory cell CM is performed by biasing the control gate EC with a determined reading voltage (for example, 2 volts here) (step E4) and reading the drain current of the MOS transistor TR via the access transistor (step E5).

[0087] If the anti-fuse device DIS is not broken down, the bias voltage is below the threshold voltage of transistor TR and the drain current will be zero or very small, and more generally below threshold. The absence of drain current during reading is therefore an indication that the information contained in the memory cell CM is the first binary value.

[0088] If the anti-fuse device DIS is broken down, the bias voltage is above the threshold voltage of the transistor TR and the drain current will be non-zero, and more generally above said threshold.The presence of the drain current during reading is therefore an indication that the information contained in the memory cell CM is the second binary value.

[0089] As an indication, the value of the current threshold is of the order of 1 to 50 μA, and preferably of the order of 1 to 10 μA.

[0090] The binary memory cells CM of the memory module MM may advantageously be organized according to a matrix architecture. Figure 7 This is a partial schematic diagram from the electrical perspective of the wiring of such a matrix.

[0091] In practice, the matrix may include 16 rows and 64 columns of memory cells.

[0092] Here, each transistor TR of each memory cell CM is coupled in series with an access transistor ACC located between a ground line and a read line LL.

[0093] When reading the information contained in the memory cell CMi, it is necessary to apply a bias voltage to the corresponding control gate EC to bias the access transistor so as to turn it on and read the drain current flowing through the read line LL (bit line).

[0094] The access transistors of the other memory cells CM also need to be biased so as to keep them in the off state in order to avoid parasitic currents on the read line that would tamper with the read operation.

[0095] When analyzing the integrated circuit CI in the context of reverse engineering, reading a memory cell is very complicated.

[0096] Specifically, the attacker here would need a first probe for biasing the control gate, a second probe for biasing the access transistor ACC, and a number of probes equal to the number of remaining cells on the line in order to keep the other access transistors in the off state.

[0097] Here, for example, for a matrix of 64 columns, 66 probes are required, which makes reading in the context of a reverse engineering operation practically impossible.

[0098] The attacker will also not be able to measure the resistance between the control gate EC and the second gate FG because the floating gate FG has no contacts on which the attacker can place a probe.

[0099] The circuit is therefore reliably protected against reverse engineering.

[0100] according to Figure 8 In the illustrated alternative embodiment, the transistor TR may be a vertical transistor.

[0101] In this case, the well CN includes a vertical electrode EV extending downward from the front of the well to an area near the bottom of the well, including an insulating wall made of, for example, silicon oxide and a polysilicon filling forming a first polysilicon region POL1, which is covered by a portion 41 of the second insulating layer 4, and a second polysilicon region POL2 is manufactured on the portion 41.

[0102] The bottom of the well CN is here bounded by a heavily n-doped buried semiconductor layer CSE, commonly referred to by those skilled in the art by the term “NISO”, and a heavily n-doped region RN is fabricated below the vertical electrode in order to provide electrical continuity between the vertical electrode EV and the NISO layer.

[0103] The drain D of the transistor TR here is formed by a heavily n-doped region level with the surface of the well CN placed in parallel with the vertical electrode EV, and the source region S here is formed by the region RN and the NISO layer.

[0104] exist Figure 8 In the figure, for simplicity, the continuation of the material between the polysilicon strip 3 and the second gate FG is not shown.

[0105] The above combination Figures 1 to 8 The described integrated circuit may be included in any type of system, such as Fig. 9 The chip card CP is shown.

Claims

1. An integrated circuit comprising at least one memory cell, wherein the at least one memory cell comprises: an anti-fuse device comprising a state transistor having a control gate and a second gate, wherein the second gate is configured to float relative to the control gate so as to impart a non-breakdown state on the anti-fuse device, or wherein the second gate is configured to be electrically coupled to the control gate so as to impart a breakdown state on the anti-fuse device; as well as The integrated circuit further comprises a memory module comprising a plurality of the memory cells interconnected according to a matrix architecture, wherein each memory cell comprises an access transistor coupled between the state transistor and a read line common to all the memory cells.

2. The integrated circuit of claim 1 , wherein the state transistor comprises: a first polysilicon region, wherein the control gate comprises the first polysilicon region; a second polysilicon region separated from the first polysilicon region by a dielectric material layer, wherein the second gate includes the second polysilicon region; and The breakdown state of the anti-fuse device is formed by an electrical connection between the first polysilicon region and the second polysilicon region through the dielectric material layer.

3. The integrated circuit of claim 1, further comprising a conductive connection element including a first end electrically coupled to the second gate and a free second end extending to a peripheral edge of the integrated circuit.

4. The integrated circuit of claim 3 , comprising a sealing ring including metal traces and vias extending around the entire periphery of the integrated circuit, the connecting element including an intersection portion intersecting the sealing ring, the second end being located between the sealing ring and the peripheral edge.

5. The integrated circuit of claim 2, further comprising: a semiconductor well having a bottom defined by a buried semiconductor region; an insulated vertical electrode extending in the semiconductor well from an upper surface of the semiconductor well downward to a region near the bottom of the semiconductor well; a heavily n-doped region providing electrical continuity between the vertical electrode and the buried semiconductor region; Wherein the vertical electrode includes the first polysilicon region and forms the second gate, and the state transistor is a vertical transistor. 6 . The integrated circuit of claim 5 , further comprising a conductive connection element including a first end electrically coupled to the second gate and a free second end extending to a peripheral edge of the integrated circuit.

7. The integrated circuit of claim 6, comprising a sealing ring including metal traces and vias extending around the entire periphery of the integrated circuit, the connecting element including an intersection portion intersecting the sealing ring, the second end being located between the sealing ring and the peripheral edge.

8. The integrated circuit of claim 1 , wherein the state transistor comprises: a first polysilicon region, wherein the control gate comprises the first polysilicon region; a second polysilicon region separated from the first polysilicon region by a dielectric material layer, wherein the second gate includes the second polysilicon region; and The breakdown state of the anti-fuse device is formed by an electrical connection between the first polysilicon region and the second polysilicon region through the dielectric material layer.

9. The integrated circuit of claim 8, wherein a plurality of memory cells share the same first polysilicon region.

10. The integrated circuit of claim 1, wherein the integrated circuit is a component of a chip card.

11. The integrated circuit of claim 1 , further comprising means for reading the at least one memory cell by: biasing the control gate of the state transistor; and A drain current of the state transistor is read, wherein a drain current below a threshold value indicates the non-breakdown state of the anti-fuse device, and wherein a drain current above the threshold value indicates a breakdown state of the anti-fuse device.

12. A semiconductor wafer comprising: District 1; a second region including a cut line, the second region separating the first regions from each other; Wherein each first region comprises an integrated circuit, the integrated circuit comprising at least one memory cell, wherein the at least one memory cell comprises: an anti-fuse device comprising a state transistor having a control gate and a second gate, wherein the second gate is configured to float relative to the control gate so as to impart a non-breakdown state on the anti-fuse device, or wherein the second gate is configured to be electrically coupled to the control gate so as to impart a breakdown state on the anti-fuse device; as well as a conductive connection element, comprising a first end and a second end, the first end being electrically coupled to the second gate, the second end extending into the second region, so that the integrated circuit and the second end are located on both sides of the corresponding cutting line; The integrated circuit further comprises a memory module comprising a plurality of the memory cells interconnected according to a matrix architecture, wherein each memory cell comprises an access transistor coupled between the state transistor and a read line common to all the memory cells.

13. The semiconductor wafer of claim 12, wherein the state transistor comprises: a first polysilicon region, wherein the control gate comprises the first polysilicon region; a second polysilicon region separated from the first polysilicon region by a dielectric material layer, wherein the second gate includes the second polysilicon region; and The breakdown state of the anti-fuse device is formed by an electrical connection between the first polysilicon region and the second polysilicon region through the dielectric material layer. 14 . The semiconductor wafer of claim 12 , wherein each first region comprises a seal ring including a metal trace and a via, and wherein the connection element comprises a crossing portion crossing the seal ring.

15. The semiconductor wafer according to claim 13, further comprising: a semiconductor well having a bottom defined by a buried semiconductor region; an insulated vertical electrode extending in the semiconductor well from an upper surface of the semiconductor well downward to a region near the bottom of the semiconductor well; a heavily n-doped region providing electrical continuity between the vertical electrode and the buried semiconductor region; Wherein the vertical electrode includes the second polysilicon region and forms the second gate, and the state transistor is a vertical transistor.

16. A method for programming at least one memory cell in an integrated circuit, the memory cell comprising an anti-fuse device, the anti-fuse device comprising a state transistor having a control gate and a second gate, wherein the second gate is configured to float relative to the control gate so as to impart a non-breakdown state on the anti-fuse device, or wherein the second gate is configured to be electrically coupled to the control gate so as to impart a breakdown state on the anti-fuse device, the integrated circuit further comprising a memory module, the memory module comprising a plurality of the memory cells interconnected according to a matrix architecture, wherein each memory cell comprises an access transistor, the access transistor being coupled between the state transistor and a read line common to all the memory cells; the method comprising: Programming is done through any of the following: forming an electrical connection between the control gate and the second gate so as to have the breakdown state, The second gate is placed in the floating state so as to have the non-breakdown state.

17. The method of claim 16, wherein programming the at least one memory cell comprises: Setting the potential of the second gate to a first reference potential via a connecting element; applying or not applying a second reference potential so as to place the anti-fuse device in a breakdown state or a non-breakdown state, respectively; as well as The connecting element is cut so that the second end of the connecting element is free.

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