Semiconductor structure, method for manufacturing the same, and memory

Abstract

The present invention relates to a semiconductor structure, a manufacturing method thereof, and a memory. The semiconductor structure includes: a substrate; a lower electrode layer located on a part of the substrate; an insulating dielectric layer located on the lower electrode layer, and the insulating dielectric layer exposes a part of the surface of the lower electrode layer; an upper electrode layer located on the insulating dielectric layer, and the upper electrode layer, the insulating dielectric layer, and the lower electrode layer form an antifuse capacitor. The present invention is beneficial to improving the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor structure, a manufacturing method thereof, and a memory. Background Art

[0002] An anti-fuse is a very important programmable interconnect unit. For example, in an integrated circuit, multiple circuit modules with the same function are designed as backups. When it is found that one of the circuit modules fails, the fuse element is used to burn out the circuit module and other functional circuits in the integrated circuit, and another circuit module with the same function is used to replace the failed circuit module.

[0003] The anti-fuse structure is generally a sandwich structure, including upper and lower electrodes and an anti-fuse dielectric layer located between the upper and lower electrodes. According to the different materials of the anti-fuse dielectric layer, the currently more mature anti-fuse structures are mainly divided into: ONO (silicon oxide - silicon nitride - silicon oxide) anti-fuse structure, amorphous silicon anti-fuse structure, and oxide anti-fuse structure. For the oxide anti-fuse, the gate dielectric layer can be used as the anti-fuse dielectric layer in the oxide anti-fuse structure, the gate electrode layer as the upper electrode plate of the anti-fuse structure, and the source, drain, or other doped regions in the substrate as the lower electrode in the oxide anti-fuse structure.

[0004] The performance of the existing semiconductor structure with an anti-fuse capacitor needs to be improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor, a manufacturing method thereof, and a memory, so as to improve the electrical performance of the semiconductor structure.

[0006] To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a lower electrode layer located on a part of the substrate; an insulating dielectric layer located on the lower electrode layer, and the insulating dielectric layer exposes a part of the surface of the lower electrode layer; an upper electrode layer located on the insulating dielectric layer, and the upper electrode layer, the insulating dielectric layer, and the lower electrode layer form an anti-fuse capacitor.

[0007] In addition, the material of the lower electrode layer is different from the material of the upper electrode layer, and the resistance of the upper electrode layer is less than the resistance of the lower electrode layer.

[0008] In addition, the lower electrode layer has a first doping ion for reducing the resistivity of the lower electrode layer; the upper electrode layer has a second doping region, and the second doping ion is used to reduce the resistivity of the upper electrode layer, and the doping concentration of the second doping ion is greater than the doping concentration of the first doping ion.

[0009] In addition, the material of the lower electrode layer includes polysilicon doped with the first doping ions; the material of the upper electrode layer includes polysilicon doped with the second doping ions; the first doping ions include N-type ions or P-type ions; the second doping ions include N-type ions or P-type ions.

[0010] In addition, it further includes: a first electrical connection unit, the first electrical connection unit being electrically connected to the lower electrode layer; a second electrical connection unit, the second electrical connection unit being electrically connected to the upper electrode layer.

[0011] In addition, the insulating dielectric layer exposes a partial top surface of the lower electrode layer; and the first electrical connection unit is in contact with the top surface of the lower electrode layer exposed by the insulating dielectric layer.

[0012] In addition, it further includes: a planarization layer, the planarization layer covering the top surface of the lower electrode layer exposed by the insulating dielectric layer, and the first electrical connection unit includes a first conductive plug penetrating through the planarization layer, the first conductive plug being in contact with a partial surface of the lower electrode layer.

[0013] In addition, it further includes: a gate dielectric layer located on the substrate; a first gate electrode layer located on the gate dielectric layer, the first gate electrode layer being in the same layer as the lower electrode layer, and the material of the first gate electrode layer being the same as that of the lower electrode layer; a second gate electrode layer located on the first gate electrode layer, the second gate electrode layer being in the same layer as the upper electrode layer, and the material of the second gate electrode layer being the same as that of the upper electrode layer.

[0014] In addition, it further includes: an intermediate dielectric layer, the intermediate dielectric layer being located between the first gate electrode layer and the second gate electrode layer, and the intermediate dielectric layer being in the same layer as the insulating dielectric layer.

[0015] In addition, it further includes: an isolation dielectric layer, the isolation dielectric layer being located between the lower electrode layer and the substrate, the isolation dielectric layer being in the same layer as the gate dielectric layer, and the material of the isolation dielectric layer being the same as that of the gate dielectric layer.

[0016] In addition, it further includes: an isolation structure located within the substrate, and the substrate exposes the top surface of the isolation structure, and the antifuse capacitor is located directly above the isolation structure.

[0017] In addition, the insulating dielectric layer has modified ions, and the modified ions are used to adjust the breakdown performance of the insulating dielectric layer.

[0018] In addition, the modified ions include germanium ions or carbon ions.

[0019] In addition, the ion concentration of the modified ions is 1E13 atom / cm 3 ~1E14 atom / cm 3 .

[0020] Correspondingly, an embodiment of the present invention further provides a memory including the above semiconductor structure.

[0021] Correspondingly, an embodiment of the present invention further provides a method for manufacturing a semiconductor structure, including: providing a substrate; forming a lower electrode layer on the substrate; forming an insulating dielectric layer on the lower electrode layer, and the insulating dielectric layer exposes a part of the surface of the lower electrode layer; forming an upper electrode layer on the insulating dielectric layer, and the upper electrode layer, the insulating dielectric layer and the lower electrode layer form an anti-fuse capacitor.

[0022] In addition, it further includes: forming a gate dielectric layer on the substrate; forming a first gate electrode layer on the gate dielectric layer, and in the process of forming the first gate electrode layer, the lower electrode layer is formed simultaneously; forming a second gate electrode layer on the first gate electrode layer, and in the process of forming the second gate electrode layer, the upper electrode layer is formed simultaneously.

[0023] In addition, it further includes forming an isolation dielectric layer, the isolation dielectric layer is located between the lower electrode layer and the substrate, and in the process of forming the gate dielectric layer, the isolation dielectric layer is formed simultaneously.

[0024] In addition, it further includes: performing a modified ion implantation treatment on the insulating dielectric layer to dope modified ions into the insulating dielectric layer.

[0025] In addition, after forming the upper electrode layer, the modified ion implantation treatment is performed.

[0026] Compared with the prior art, the technical solution provided by the present invention has the following advantages:

[0027] An embodiment of the present invention provides a semiconductor structure with excellent structural performance. Among them, the upper electrode layer, the insulating dielectric layer and the lower electrode layer are stacked in a direction perpendicular to the surface of the substrate, and the upper electrode layer and the lower electrode layer serve as the upper electrode plate and the lower electrode plate of the anti-fuse capacitor respectively, without using a source or a drain in the substrate as one of the electrode plates of the anti-fuse capacitor, so that the electrical performance of the anti-fuse capacitor is more independent, can meet more electrical application requirements, and thus improve the electrical performance of the semiconductor structure.

[0028] In addition, the lower electrode layer has first doping ions for reducing the resistivity of the lower electrode layer; the upper electrode layer has a second doping region, and the second doping ions are used to reduce the resistivity of the upper electrode layer, and the doping concentration of the second doping ions is greater than that of the first doping ions. The relatively high doping ion concentration in the upper electrode layer is beneficial to reducing the resistance of the upper electrode layer, and the relatively low doping ion concentration in the lower electrode layer can avoid the problem of doping ions diffusing into the substrate due to the large doping ion concentration, further improving the electrical performance of the semiconductor structure.

[0029] In addition, it further includes: a gate dielectric layer located on the substrate; a first gate electrode layer located on the gate dielectric layer, the first gate electrode layer is in the same layer as the lower electrode layer, and the first gate electrode layer and the lower electrode layer are made of the same material; a second gate electrode layer located on the first gate electrode layer, the second gate electrode layer is in the same layer as the upper electrode layer, and the second gate electrode layer and the upper electrode layer are made of the same material. Such an arrangement makes the antifuse capacitor compatible with the manufacturing process of the transistor and reduces the process cost.

[0030] In addition, the antifuse capacitor is located directly above the isolation structure, which is beneficial to further avoiding the mutual electrical influence between the antifuse capacitor and the transistor. For example, it can prevent damage to the gate dielectric layer of the transistor when the antifuse capacitor is working. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the drawings in the figures do not constitute a scale limitation.

[0032] Figure 1 is a schematic structural diagram of a semiconductor structure with an antifuse capacitor;

[0033] Figure 2 and Figure 3 is a schematic cross-sectional structural diagram of the semiconductor structure provided by an embodiment of the present invention;

[0034] Figures 4 to 10 is a schematic structural diagram corresponding to each step of the manufacturing method of the semiconductor structure provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] As can be seen from the background art, the electrical performance of the existing semiconductor structure needs to be improved.

[0036] Figure 1 is a schematic structural diagram of a semiconductor structure with an antifuse capacitor, refer to Figure 1, the semiconductor structure includes: a substrate 100 and an isolation structure 101 located within the substrate 100; a gate structure (not shown) located on the substrate 100; doping regions 104 located on opposite sides of the gate structure, where one of the doping regions 104 serves as a source and the other doping region 104 serves as a drain; an insulating dielectric layer 102 located on the substrate 100; an electrode layer 103 located on the insulating dielectric layer 102; and a conductive plug 105 electrically connected to the doping region 104.

[0037] Specifically, the gate structure includes a gate dielectric layer and a gate electrode layer located on the gate dielectric layer. The material of the insulating dielectric layer 102 is the same as the material of the gate dielectric layer, and the material of the electrode layer 103 is the same as the material of the gate electrode layer. Among them, the electrode layer 103, the insulating dielectric layer 102, and the doping region 104 form an anti-fuse capacitor. When the electrode layer 103 is connected to a first voltage V1 and the doping region 104 is connected to a second voltage V2, the insulating dielectric layer 102 is broken down, Figure 1 and the breakdown region is indicated by region A.

[0038] In the above semiconductor structure, the doping region 104 serves as a source or a drain on the one hand, and also serves as the lower electrode of the anti-fuse capacitor on the other hand. Therefore, the electrical performance of the anti-fuse capacitor will be affected by the electrical performance of the transistor, or rather, the electrical performance of the anti-fuse capacitor depends on the voltage provided by the source or the drain.

[0039] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a lower electrode layer, the lower electrode layer being located on a part of the substrate; an insulating dielectric layer, the insulating dielectric layer being located on the lower electrode layer and exposing a part of the surface of the lower electrode layer; an upper electrode layer, the upper electrode layer being located on the insulating dielectric layer, and the upper electrode layer, the insulating dielectric layer, and the lower electrode layer form an anti-fuse capacitor. The electrical performance of the anti-fuse capacitor in the semiconductor structure provided by the embodiment of the present invention is independent.

[0040] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present invention, many technical details are provided for the readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions required to be protected by the present application can still be realized.

[0041] It will be understood that the terms "first", "second", etc. used in the present invention may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of the present invention, a first quantity may be referred to as a second quantity, and similarly, a second quantity may be referred to as a first quantity. Both the first quantity and the second quantity are quantities, but they are not the same quantity.

[0042] Figure 2 and Figure 3 is a schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present invention, Figure 2 is a schematic cross-sectional structure diagram cut along a first direction, Figure 3 is a schematic cross-sectional structure diagram cut along a second direction, and the first direction is perpendicular to the second direction.

[0043] Referring to Figure 2 and Figure 3 , the semiconductor structure provided by this embodiment includes: a substrate 200; a lower electrode layer 203, the lower electrode layer 203 is located on a part of the substrate 200; an insulating dielectric layer 204, the insulating dielectric layer 204 is located on the lower electrode layer 203, and the insulating dielectric layer 204 exposes a part of the surface of the lower electrode layer 203; an upper electrode layer 205, the upper electrode layer 205 is located on the insulating dielectric layer 204, and the upper electrode layer 205, the insulating dielectric layer 204, and the lower electrode layer 203 form an antifuse capacitor.

[0044] In the semiconductor structure provided by this embodiment, in the direction perpendicular to the surface of the substrate 200, an antifuse capacitor is formed by the lower electrode layer 203, the insulating dielectric layer 204, and the upper electrode layer 205, without using a source or a drain located in the substrate as one of the electrode plates of the antifuse capacitor, so that the electrical performance of the antifuse capacitor is more independent and can meet more electrical application requirements.

[0045] The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings.

[0046] The substrate 200 may be a semiconductor substrate such as a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V group substrate, or a sapphire substrate. In this embodiment, the substrate 200 is taken as a silicon substrate as an example.

[0047] The lower electrode layer 203 serves as the lower electrode plate of the antifuse capacitor, and the upper electrode layer 205 serves as the upper electrode plate of the antifuse capacitor. In this embodiment, the material of the lower electrode layer 203 is different from that of the upper electrode layer 205, and the resistance of the upper electrode layer 205 is less than that of the lower electrode layer 203. Since the resistance of the upper electrode layer 205 is reduced, during the process of the voltage applied to the upper electrode layer 205 being transmitted to the insulating dielectric layer 204, the voltage loss is small, and the heat generated by the upper electrode layer 205 can be reduced.

[0048] A solution with different doping ion concentrations of the upper electrode layer 205 and the lower electrode layer 203 can be adopted to achieve the purpose of different resistances between the upper electrode layer 205 and the lower electrode layer 203. Specifically, the lower electrode layer 203 has a first doping ion, and the first doping ion is used to reduce the resistivity of the lower electrode layer 203; the upper electrode layer 205 has a second doping ion, and the second doping ion is used to reduce the resistivity of the upper electrode layer 205, and the doping concentration of the second doping ion is greater than that of the first doping ion.

[0049] Since the doping ion concentration in the upper electrode layer 205 is greater than that in the lower electrode layer 203, the upper electrode layer 205 can have a smaller resistance. At the same time, since the doping ion concentration in the lower electrode layer 203 is smaller, the probability of the doping ions in the lower electrode layer 203 diffusing into the substrate 200 is small, thereby avoiding the adverse effects brought by the doping ions in the lower electrode layer 203 diffusing into the substrate 200, which is beneficial to further improving the performance of the semiconductor structure.

[0050] The first doping ion can be an N-type ion or a P-type ion, the second doping ion can be an N-type ion or a P-type ion, the N-type ions include P, As or Sb, and the P-type ions include B, Ga or In. In this embodiment, the first doping ion is the same as the second doping ion. In other embodiments, the first doping ion and the second doping ion can also be different.

[0051] In this embodiment, the material of the lower electrode layer 203 is polysilicon doped with the first doping ion, and the material of the upper electrode layer 205 is polysilicon doped with the second doping ion. The advantage of such a setting is that: since polysilicon can be used as the material of the gate electrode layer of the gate structure, therefore, the manufacturing process of the transistor in the semiconductor structure can be utilized to manufacture the antifuse capacitor at the same time. More specifically, the manufacturing process of the gate electrode layer in the gate structure is utilized to form the lower electrode layer 203 and the upper electrode layer 205.

[0052] It should be noted that the doping concentration of the first doping ion in the lower electrode layer 203 can also be zero, that is to say, the material of the lower electrode layer 202 can be an intrinsic semiconductor material, such as intrinsic polysilicon.

[0053] The insulating dielectric layer 204 serves as the intermediate dielectric layer of the antifuse capacitor. The material of the insulating dielectric layer 204 can be one or more of oxides or nitrides, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbon oxynitride; the material of the insulating dielectric layer 204 can also be a high-k dielectric material, where a high-k dielectric material refers to a material with a relative dielectric constant greater than that of silicon oxide, such as HfO2 or Al2O3, etc. In this embodiment, silicon oxide is taken as an example for the material of the insulating dielectric layer 204.

[0054] It should be noted that the insulating dielectric layer 204 can be a single-layer structure or a stacked structure, such as an ONO (oxide-nitride-oxide) stacked structure.

[0055] The thickness of the insulating dielectric layer 204 is 10 Å to 60 Å, such as 15 Å, 25 Å, 30 Å, 50 Å. In this embodiment, the thickness of the insulating dielectric layer 204 is less than or equal to 20 Å.

[0056] According to different application requirements of the antifuse capacitor, the insulating dielectric layer 204 also has different breakdown performances accordingly. For this reason, in this embodiment, the insulating dielectric layer 204 can also have modified ions, and the modified ions are used to adjust the breakdown performance of the insulating dielectric layer 204. For example, the breakdown voltage of the insulating dielectric layer 204 can be reduced, so that the insulating dielectric layer 204 can be broken down at a lower voltage, thereby realizing the conduction between the upper electrode layer 205 and the lower electrode layer 203.

[0057] The mechanism of the modified ions adjusting the breakdown performance of the insulating dielectric layer 204 is complex. As an explanation, the mechanism of the modified ions adjusting the breakdown performance of the insulating dielectric layer 204 is as follows:

[0058] The introduction of the modified ions can be completed by the ion implantation process. During the ion implantation process, ions with higher energy bombard the insulating dielectric layer 204, making the bond energy of the chemical bonds inside the insulating dielectric layer 204 weaker; when electrons are transmitted in the insulating dielectric layer 204, due to the weaker bond energy of the chemical bonds, the energy released by the expansion of the electrons and the lattice is more likely to cause the chemical bonds to break, so that traps are more easily formed inside the insulating dielectric layer 204; the electrons and holes transmitted in the insulating dielectric layer 204 are captured by the continuously generated traps to form trap charges; when the large defects formed by the randomly generated traps form a channel from the top surface to the bottom surface of the insulating dielectric layer 204, the insulating dielectric layer 204 is broken down.

[0059] In this embodiment, the modified ion is a germanium ion. In other embodiments, the modified ion can also be a carbon ion.

[0060] In this embodiment, the ion concentration of the modified ions is 1E13 atom / cm 3 ~1E14 atom / cm 3 , for example, 2E13 atom / cm 3 , 5E13 atom / cm 3 , 7E13 atom / cm 3 .

[0061] It can be understood that when the modified ions are doped into the insulating dielectric layer 204 after the upper electrode layer 205 is formed, correspondingly, the upper electrode layer 205 also has the modified ions.

[0062] In this embodiment, the insulating dielectric layer 204 exposes a part of the top surface of the lower electrode layer 203, so that the lower electrode layer 203 can be electrically connected to an external power supply or other devices through the exposed top surface. It should be noted that in other embodiments, the insulating dielectric layer can also be located on the entire top surface of the lower electrode layer, and the lower electrode layer is electrically connected to an external power supply or other devices through the side wall surface.

[0063] In order to increase the relative area between the upper electrode plate and the lower electrode plate and improve the capacitance value of the anti-fuse capacitor, in this embodiment, the upper electrode layer 205 is located on the entire top surface of the insulating dielectric layer 204. In this embodiment, in order to further increase the relative area between the upper electrode plate and the lower electrode plate, the side walls of the upper electrode layer 205, the insulating dielectric layer 204 and the lower electrode layer 203 are flush.

[0064] In this embodiment, the semiconductor structure may further include: a first metal silicide layer (not shown) located on the top surface of the upper electrode layer 205. The resistivity of the material of the first metal silicide layer is greater than that of the material of the upper electrode layer 205, which is beneficial to reducing the contact resistance between the upper electrode layer 205 and other electrically connected components. The material of the metal silicide layer can be nickel silicide.

[0065] In order to provide a protective effect on the top surface of the upper electrode layer 205, the semiconductor structure may further include: a first covering layer 206 located on the upper electrode layer 205, and the first metal silicide layer is located between the first covering layer 206 and the upper electrode layer 205. In this embodiment, the material of the first covering layer 206 is silicon nitride; in other embodiments, the material of the first covering layer 206 can also be other suitable insulating materials.

[0066] The semiconductor structure may further include: a first sidewall 210, and the first sidewall 210 covers the side walls of the upper electrode layer 205, the insulating dielectric layer 204 and the lower electrode layer 203. In this embodiment, the first sidewall 201 also covers the sidewall surface of the first covering layer 206.

[0067] The semiconductor structure further includes: a first electrical connection unit 207, the first electrical connection unit 207 is electrically connected to the lower electrode layer 203, and the first voltage is applied to the lower electrode layer 203 through the first electrical connection unit 207; a second electrical connection unit 208, the second electrical connection unit 208 is electrically connected to the upper electrode layer 205, and the second voltage is applied to the upper electrode layer 205 through the second electrical connection unit 208.

[0068] The first electrical connection unit 207 is used to electrically connect the lower electrode layer 203 to an external power source or other devices, so that the first voltage is applied to the lower electrode layer 203; the second electrical connection unit 208 is used to electrically connect the upper electrode layer 205 to an external power source or other devices, so that the second voltage is applied to the upper electrode layer 205.

[0069] In this embodiment, the insulating dielectric layer 204 exposes a partial top surface of the lower electrode layer 203. Correspondingly, the first electrical connection unit 207 is in contact with the partial top surface of the lower electrode layer 203 exposed by the insulating dielectric layer 204.

[0070] In this embodiment, the semiconductor structure further includes: a planarization layer 20, the planarization layer 20 covers the top surface of the lower electrode layer 203 exposed by the insulating dielectric layer 204, and the first electrical connection unit 207 includes a first conductive plug penetrating through the planarization layer 20, and the first conductive plug is in contact with a partial surface of the lower electrode layer 203.

[0071] Wherein, the planarization layer 20 also exposes the top surface of the first covering layer 206, and the second electrical connection unit 208 includes a second conductive plug penetrating through the first covering layer 206, and the second conductive plug is in contact with a partial surface of the upper electrode layer 205. It should be noted that when a first metal silicide layer is formed on the top surface of the upper electrode layer, the second conductive plug is in contact with the first metal silicide layer.

[0072] It can be understood that the planarization layer 20 can also be located on the top surface of the first covering layer 206. Correspondingly, the second conductive plug also penetrates through the planarization layer 20 located on the top surface of the first covering layer 206.

[0073] In this embodiment, the semiconductor structure includes, in addition to the antifuse capacitor, a transistor. Therefore, the manufacturing process of the transistor can be used to fabricate the antifuse capacitor. Specifically, the semiconductor structure further includes: a gate dielectric layer 302 located on the substrate 200; a first gate electrode layer 303 located on the gate dielectric layer 303, the first gate electrode layer 303 being on the same layer as the lower electrode layer 203 and having the same material as the lower electrode layer 203; a second gate electrode layer 305 located on the first gate electrode layer 303, the second gate electrode layer 305 being on the same layer as the upper electrode layer 205 and having the same material as the upper electrode layer 205.

[0074] The first gate electrode layer 303 and the lower electrode layer 203 are on the same layer. It can be understood that the top surface of the first gate electrode layer 303 is flush with the top surface of the lower electrode layer 203.

[0075] In this embodiment, the semiconductor structure further includes: an isolation dielectric layer 202. The isolation dielectric layer 202 is located between the lower electrode layer 203 and the substrate 200, and is on the same layer as the gate dielectric layer 302 and has the same material as the gate dielectric layer 302. It should be noted that when the edge portion of the top surface of the isolation dielectric layer 202 is exposed by the lower electrode layer 203, the first sidewall 210 is located on the top surface of the edge portion of the isolation dielectric layer 202. In other embodiments, the lower electrode layer may also be located on the entire top surface of the isolation dielectric layer.

[0076] Due to the presence of the isolation dielectric layer 202, the bottom surface of the first gate electrode layer 303 is also flush with the bottom surface of the lower electrode layer 203.

[0077] The isolation dielectric layer 202 can not only electrically isolate the substrate 200 from the lower electrode layer 203, but also prevent the first doped ions in the lower electrode layer 203 from diffusing into the substrate 200.

[0078] The second gate electrode layer 305 and the upper electrode layer 205 are on the same layer. It can be understood that the top surface of the second gate electrode layer 305 is flush with the top surface of the upper electrode layer 205. In this embodiment, the first gate electrode layer 303 is in contact with the second gate electrode layer 305. Therefore, compared with the surface of the substrate 200, the bottom surface of the second gate electrode layer 305 is lower than the bottom surface of the upper electrode layer 205.

[0079] It should be noted that in other embodiments, the semiconductor structure may further include: an intermediate dielectric layer. The intermediate dielectric layer is located between the first gate electrode layer and the second gate electrode layer and is on the same layer as the insulating dielectric layer. Correspondingly, the bottom surface of the upper electrode layer is flush with the bottom surface of the second gate electrode layer.

[0080] The first gate electrode layer 303 and the second gate electrode layer 305 together form the gate electrode layer. From the foregoing analysis, it can be seen that the resistance of the second gate electrode layer 305 is less than that of the first gate electrode layer 303. Therefore, compared with the solution where the material of the gate electrode layer is the material of the first gate electrode layer, in this embodiment, the overall resistance of the gate electrode layer is smaller, thereby improving the signal delay problem in the gate electrode layer.

[0081] Moreover, the first gate electrode layer 303 has first doping ions, the second gate electrode layer 305 has second doping ions, and the concentration of the first doping ions is less than that of the second doping ions. That is to say, the concentration of the doping ions in the first gate electrode layer 303 closer to the substrate 200 is relatively small, which is conducive to avoiding the diffusion of the doping ions in the gate electrode layer into the substrate 200, thereby avoiding the adverse effects caused by the diffusion of the doping ions, and further improving the electrical performance of the semiconductor structure.

[0082] Regarding the material description of the first gate electrode layer 303 and the second gate electrode layer 305, reference can be made to the corresponding description of the upper electrode layer 203 and the lower electrode layer 205 above, and details will not be elaborated here.

[0083] In this embodiment, the semiconductor structure may further include: a second metal silicide layer on the top surface of the second gate electrode layer 305; a second capping layer 306 on the second gate electrode layer 305, and the second metal silicide layer is located between the second gate electrode layer 305 and the second capping layer 306; a second sidewall 310 covering the sidewalls of the first gate electrode layer 303, the second gate electrode layer 305, and the second capping layer 306.

[0084] The semiconductor structure further includes: doping regions 301 in the substrate 200 on opposite sides of the first gate electrode layer 303, where one doping region 301 serves as the source electrode and the other doping region 301 serves as the drain electrode. When the transistor is an N-type transistor, the doping ions in the corresponding doping region 301 are N-type ions; when the transistor is a P-type ion, the doping ions in the corresponding doping region 301 are P-type ions.

[0085] In this embodiment, the semiconductor structure further includes: an isolation structure 201 in the substrate 200, and the top surface of the isolation structure 201 is exposed on the substrate 200, and the antifuse capacitor is located directly above the isolation structure 201.

[0086] Specifically, the orthographic projection of the lower electrode layer 203 on the substrate 200 is located inside the top surface of the isolation structure 201. It can be understood that the orthographic projection of the isolation dielectric layer 202 on the substrate 200 may be located inside the top surface of the isolation structure 201, or may be located in other regions outside the top surface of the isolation structure 201.

[0087] The isolation structure 201 can be a shallow trench isolation (STI) structure for electrically isolating adjacent active areas (AAs). In addition, in this embodiment, since the antifuse capacitor is disposed directly above the isolation structure 201, it can prevent the antifuse capacitor from being electrically connected to the doped region 301, thereby avoiding the voltage in the antifuse capacitor during programming from being transmitted to the gate dielectric layer 302 through the doped region 301, and further avoiding damage to the gate dielectric layer 302, and further improving the electrical performance of the semiconductor structure.

[0088] It should be noted that, in other embodiments, the antifuse capacitor can also straddle the isolation structure and a part of the substrate, or the antifuse capacitor can also be located only above the substrate outside the isolation structure.

[0089] This embodiment provides a semiconductor structure with excellent structural performance. The electrical performance of the antifuse capacitor is independent, enabling the antifuse capacitor to be applied to more requirements.

[0090] In addition, the semiconductor structure further includes a transistor, and the lower electrode layer has the same material as and is in the same layer as the first gate electrode layer of the transistor, and the upper electrode layer has the same material as and is in the same layer as the second gate electrode layer of the transistor. Therefore, the antifuse capacitor can be fabricated using the transistor manufacturing process, which is beneficial for saving process costs.

[0091] Correspondingly, an embodiment of the present invention further provides a memory including the above semiconductor structure, and the memory can be a DRAM memory.

[0092] Correspondingly, an embodiment of the present invention further provides a manufacturing method for manufacturing the above semiconductor structure, including: providing a substrate; forming a lower electrode layer on the substrate; forming an insulating dielectric layer on the lower electrode layer, and the insulating dielectric layer exposes a part of the surface of the lower electrode layer; forming an upper electrode layer on the insulating dielectric layer, and the upper electrode layer, the insulating dielectric layer, and the lower electrode layer form an antifuse capacitor. Hereinafter, taking the semiconductor structure further including a transistor as an example, the manufacturing method of the semiconductor structure will be described in detail.

[0093] Figures 4 to 10 FIGURES 20A-20F are schematic diagrams corresponding to the steps of the manufacturing method of the semiconductor structure provided by the embodiments of the present invention.

[0094] Reference Figure 4 , provides a substrate 200; forms a gate dielectric layer 302 on the substrate 200.

[0095] In this embodiment, in the process step of forming the gate dielectric layer 302, an isolation dielectric layer 202 is simultaneously formed on the substrate 200, and the isolation dielectric layer 202 can be used to electrically isolate the substrate 200 from the subsequent formed lower electrode layer.

[0096] Among them, the isolation dielectric layer 202 and the gate dielectric layer 302 are discrete from each other. In other embodiments, the isolation dielectric layer and the gate dielectric layer may also be an integral continuous film layer.

[0097] In this embodiment, it further includes: forming an isolation structure 201 in the substrate 200, and the top of the isolation structure 201 is exposed on the substrate 200.

[0098] It should be noted that in this embodiment, before forming the gate dielectric layer 302, the isolation structure 201 is first formed, so that the formed isolation dielectric layer 202 is located on the top surface of the isolation structure 201.

[0099] Reference Figure 5 , a lower electrode layer 203 is formed on the substrate 200.

[0100] Specifically, a first gate electrode layer 303 is formed on the gate dielectric layer 302. And in the process step of forming the first gate electrode layer 303, the lower electrode layer 203 is formed simultaneously, and the isolation dielectric layer 202 is located between the lower electrode layer 203 and the substrate 200. That is to say, the material of the lower electrode layer 203 is the same as that of the first gate electrode layer 303.

[0101] In this embodiment, the material of the first gate electrode layer 303 is polysilicon, and the first gate electrode layer 303 also has first doping ions; correspondingly, the material of the lower electrode layer 203 is polysilicon, and the lower electrode layer 203 also has first doping ions.

[0102] The process steps of forming the lower electrode layer 203 and the first gate electrode layer 303 may include: forming a first polysilicon film on the substrate 200, and performing a first doping process on the first polysilicon film so that the first polysilicon film has first doping ions. Among them, the first doping process may adopt an ion implantation process or an in-situ doping process; performing a patterning process on the first polysilicon film to form the lower electrode layer 203 and the first gate electrode layer 303.

[0103] In this embodiment, the upper electrode layer 203 is located directly above the isolation structure 201. In other embodiments, the upper electrode layer may also be located above any region of the substrate.

[0104] Reference Figure 6 And Figure 7 , Figure 6 For the structural schematic diagram based on Figure 5 , Figure 7 Perpendicular to the cross-sectional direction of Figure 6 , an insulating dielectric layer 204 is formed on the lower electrode layer 203.

[0105] In this embodiment, the insulating dielectric layer 204 exposes a part of the top surface of the lower electrode layer 203. For the material of the insulating dielectric layer 204, reference can be made to the corresponding description in the foregoing embodiment, which will not be elaborated here.

[0106] The thickness of the insulating dielectric layer 204 can be 10 angstroms to 60 angstroms, such as 15 angstroms, 35 angstroms, or 50 angstroms. In this embodiment, the thickness of the insulating dielectric layer 204 is less than or equal to 20 angstroms.

[0107] It should be noted that in this embodiment, the subsequently formed second gate electrode layer is in contact with the first gate electrode layer 303. In other embodiments, when there is an intermediate dielectric layer between the subsequently formed second gate electrode layer and the first gate electrode layer, an intermediate dielectric layer can also be formed on the top surface of the first gate electrode layer during the process step of forming the insulating dielectric layer.

[0108] Reference Figure 8 and Figure 9 , Figure 8 For the structural schematic diagram based on Figure 6 , an upper electrode layer 205 is formed on the insulating dielectric layer 204. Figure 9 For the structural schematic diagram based on Figure 7 , an upper electrode layer 205 is formed on the insulating dielectric layer 204.

[0109] The upper electrode layer 205, the insulating dielectric layer 204, and the lower electrode layer 203 form an antifuse capacitor.

[0110] Specifically, a second gate electrode layer 305 is formed on the first gate electrode layer 303, and during the process step of forming the second gate electrode layer 305, the upper electrode layer 205 is formed simultaneously. That is to say, the material of the upper electrode layer 205 is the same as that of the second gate electrode layer 305.

[0111] In this embodiment, the material of the second gate electrode layer 305 is polysilicon, and the second gate electrode layer 305 has second doping ions, and the concentration of the second doping ions is greater than the concentration of the first doping ions; correspondingly, the material of the upper electrode layer 205 is polysilicon, and the upper electrode layer 205 also has second doping ions.

[0112] The process steps of forming the upper electrode layer 205 and the second gate electrode layer 305 can include: forming a second polysilicon film on the substrate 200, and performing a second doping process on the second polysilicon film so that the second polysilicon film has second doping ions, where the second doping process can adopt an ion implantation process or an in-situ doping process; performing a patterning process on the second polysilicon film to form the upper electrode layer 205 and the second gate electrode layer 305.

[0113] The concentration of the second doping ions is greater than that of the first doping ions, so that the resistance of the second gate electrode layer 305 is smaller than that of the first gate electrode layer 303, which is beneficial to ensuring that the overall resistance value of the gate electrode layer is relatively small; and because the concentration of the first doping ions in the first gate electrode layer 303 is relatively small, the problem of diffusion of doping ions into the substrate 200 caused by excessive doping ion concentration can be avoided.

[0114] It should be noted that in other embodiments, when an intermediate dielectric layer needs to be formed between the first gate electrode layer and the second gate electrode layer, in the process step of forming the insulating dielectric layer, an intermediate dielectric layer can also be formed on the first gate electrode layer.

[0115] It should also be noted that in this embodiment, taking the example of first patterning the lower electrode layer 203 and then patterning the upper electrode layer 205, in other embodiments, the upper electrode layer and the lower electrode layer can also be formed simultaneously in the same patterning process step. Specifically, the process steps of forming the lower electrode layer, the insulating dielectric layer, the upper electrode layer, the first gate electrode layer, and the second gate electrode layer include: forming a lower electrode film; forming an insulating dielectric film on the lower electrode film; forming an upper electrode film on the insulating dielectric film; patterning the upper electrode film, the insulating dielectric film, and the lower electrode film.

[0116] After forming the first gate electrode layer 303 and the second gate electrode layer 305, an annealing treatment can also be performed to redistribute the first doping ions in the first gate electrode layer 303 and the second doping ions in the second gate electrode layer 305.

[0117] Reference Figure 10 , a modified ion implantation treatment 30 is performed on the insulating dielectric layer 204 to dope modified ions into the insulating dielectric layer 203.

[0118] The modified ion implantation treatment 30 is used to adjust the breakdown performance of the insulating dielectric layer 204. As an explanation, during the modified ion implantation treatment 30, the modified ions bombard the insulating dielectric layer 203, making the chemical bond energy inside the insulating dielectric layer 203 weaker.

[0119] In this embodiment, the modified ions are germanium ions. In other embodiments, the modified ions can also be carbon ions.

[0120] For the modified ion implantation treatment 30, the implanted ion dose should not be too small or too large. If the implanted ion dose is too small, the effect of adjusting the breakdown performance of the insulating dielectric layer 203 is limited; if the implanted ion dose is too large, it is likely to have an adverse impact on the conductive performance of the insulating dielectric layer 203 when breakdown does not occur. Therefore, in this embodiment, in the modified ion implantation treatment 30, the implanted dose of the modified ions is 1E13atom / cm 3 ~1E14atom / cm3 。

[0121] In addition, for the modified ion implantation process 30, the implantation energy should not be too small or too large. If the implantation energy is too small, the effect of adjusting the breakdown performance of the insulating dielectric layer 203 is limited; if the implantation energy is too large, it is likely to have an adverse impact on the conductivity of the insulating dielectric layer 203 when breakdown does not occur, and it is likely to be implanted into the lower electrode layer 203. Therefore, in this embodiment, in the modified ion implantation process 30, the modified ion implantation energy is 5 keV to 20 keV, such as 8 keV, 11 keV, 15 keV, 18 keV.

[0122] In this embodiment, after the upper electrode layer 205 is formed, the insulating dielectric layer 203 is subjected to the modified ion implantation process 30 via the upper electrode layer 205, which is beneficial to reducing the process difficulty of the modified ion implantation process 30. This is because the modified ions reach the insulating dielectric layer 203 only after passing through the upper electrode layer 205. Therefore, the probability of the modified ions entering the lower electrode layer 203 can be significantly reduced, and the process accuracy requirement for the modified ion implantation process 30 is relatively low.

[0123] It should be noted that in other embodiments, the insulating dielectric layer can also be directly subjected to the modified ion implantation process before the upper electrode layer is formed after the insulating dielectric layer is formed.

[0124] Combined with reference Figure 2 and Figure 3 , a first electrical connection unit 207 is formed, and the first electrical connection unit 207 is electrically connected to the lower electrode layer 203; a second electrical connection unit 208 is formed, and the second electrical connection unit 208 is electrically connected to the upper electrode layer 205.

[0125] In this embodiment, after the gate electrode layer is formed, doping regions 301 are formed in the substrate 200 on both opposite sides of the gate electrode layer. In other embodiments, the doping regions can also be formed before the gate electrode layer is formed.

[0126] It may further include steps: forming a first covering layer 206 on the upper electrode layer 205; forming a second covering layer 306 on the second gate electrode layer 305; forming a first sidewall 210, and the first sidewall 210 covers the sidewalls of the lower electrode layer 203, the insulating dielectric layer 204, the upper electrode layer 205, and the first covering layer 206; forming a second sidewall 310, and the second sidewall 310 covers the sidewalls of the first gate electrode layer 303, the second gate electrode layer 305, and the second covering layer 306.

[0127] Specifically, the first electrical connection unit 207 is in contact with the top surface of the lower electrode layer 203 exposed by the insulating dielectric layer 204.

[0128] In this embodiment, before forming the first electrical connection layer 207 and the second electrical connection layer 208, the following steps are further included: forming a planarization layer 20, which covers the top surface of the lower electrode layer 203 exposed by the insulating dielectric layer 204 and is also located on the substrate 200. In this embodiment, an example is that the top surface of the planarization layer 20 is flush with the top surfaces of the first covering layer 206 and the second covering layer 306.

[0129] After forming the planarization layer 20, a first conductive plug penetrating the planarization layer 20 is formed, and the first conductive plug is in contact with a partial top surface of the lower electrode layer 203. The first electrical connection unit 207 includes this first conductive plug.

[0130] A second conductive plug penetrating the first covering layer 206 is formed, and the second conductive plug is in contact with a partial top surface of the upper electrode layer 205. The second electrical connection unit 208 includes this second conductive plug.

[0131] It should be understood that the semiconductor structure provided by the embodiments of the present invention is not limited to being manufactured by the manufacturing method provided in the above embodiments. Moreover, the steps in the above manufacturing method are not necessarily carried out in the order of writing. Unless clearly stated in this article, there is no strict order restriction for the implementation of these steps.

[0132] In the manufacturing method of the semiconductor structure provided in this embodiment, the stacking direction of the upper electrode plate and the lower electrode plate of the anti-fuse capacitor formed is perpendicular to the surface of the substrate 200, without the need to use a source or drain located in the substrate as one of the electrode plates of the anti-fuse capacitor, so that the electrical performance of the anti-fuse capacitor is more independent and can meet more electrical application requirements.

[0133] In addition, in the manufacturing method of the semiconductor structure provided in this embodiment, the process steps of separately forming the first gate electrode layer 303 and the second gate electrode layer 305 are utilized to form the lower electrode layer 203 and the upper electrode layer 205 of the anti-fuse capacitor, making the manufacturing process of the anti-fuse capacitor compatible with the transistor manufacturing process, without the need for additional film layer formation process steps and without the need for additional photomasks, effectively saving process steps.

[0134] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present invention. In practical applications, various changes can be made in form and details without departing from the spirit and scope of the present invention. Any person skilled in the art can make their respective changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A lower electrode layer located on a part of the substrate; An insulating dielectric layer located on the lower electrode layer, and the insulating dielectric layer exposes a part of the surface of the lower electrode layer; An upper electrode layer located on the insulating dielectric layer, and the upper electrode layer, the insulating dielectric layer and the lower electrode layer form an anti-fuse capacitor; the material of the lower electrode layer is different from that of the upper electrode layer, and the resistance of the upper electrode layer is less than that of the lower electrode layer; the lower electrode layer, the upper electrode layer and the source and drain in the substrate are independent of each other.

2. The semiconductor structure according to claim 1, wherein, The lower electrode layer has a first doping ion therein for reducing the resistivity of the lower electrode layer; the upper electrode layer has a second doping ion therein for reducing the resistivity of the upper electrode layer, and the doping concentration of the second doping ion is greater than that of the first doping ion.

3. The semiconductor structure according to claim 2, wherein The material of the lower electrode layer includes polysilicon doped with the first doping ion; the material of the upper electrode layer includes polysilicon doped with the second doping ion; the first doping ion includes an N-type ion or a P-type ion; the second doping ion includes an N-type ion or a P-type ion.

4. The semiconductor structure according to claim 1 or 2, wherein Further comprising: A first electrical connection unit electrically connected to the lower electrode layer; A second electrical connection unit electrically connected to the upper electrode layer.

5. The semiconductor structure according to claim 4, wherein The insulating dielectric layer exposes a part of the top surface of the lower electrode layer; and the first electrical connection unit is in contact with the top surface of the lower electrode layer exposed by the insulating dielectric layer.

6. The semiconductor structure according to claim 5, wherein, Further comprising: A planarization layer covering the top surface of the lower electrode layer exposed by the insulating dielectric layer, and the first electrical connection unit includes a first conductive plug penetrating the planarization layer, and the first conductive plug is in contact with a part of the surface of the lower electrode layer.

7. The semiconductor structure according to claim 1, wherein Further comprising: a gate dielectric layer located on the substrate; a first gate electrode layer located on the gate dielectric layer, the first gate electrode layer being in the same layer as the lower electrode layer and having the same material as the lower electrode layer; a second gate electrode layer located on the first gate electrode layer, the second gate electrode layer being in the same layer as the upper electrode layer and having the same material as the upper electrode layer.

8. The semiconductor structure according to claim 7, wherein, Further comprising: An intermediate dielectric layer located between the first gate electrode layer and the second gate electrode layer, and the intermediate dielectric layer is in the same layer as the insulating dielectric layer.

9. The semiconductor structure according to claim 7, wherein Further comprising: An isolation dielectric layer located between the lower electrode layer and the substrate, the isolation dielectric layer being in the same layer as the gate dielectric layer and having the same material as the gate dielectric layer.

10. The semiconductor structure according to claim 7, wherein Further comprising: An isolation structure located in the substrate, and the substrate exposes the top surface of the isolation structure, and the anti-fuse capacitor is located directly above the isolation structure.

11. The semiconductor structure according to claim 1, wherein, The insulating dielectric layer has a modified ion therein for adjusting the breakdown performance of the insulating dielectric layer.

12. The semiconductor structure according to claim 11, wherein The modified ion includes a germanium ion or a carbon ion.

13. The semiconductor structure according to claim 11 or 12, characterized in that, The ionic concentration of the modified ions is 1E13 atom / cm 3 ~1E14 atom / cm 3 .

14. A memory, characterized in that, Comprising: The semiconductor structure according to any one of claims 1-13.

15. A manufacturing method of a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a lower electrode layer on the substrate; Forming an insulating dielectric layer on the lower electrode layer, and the insulating dielectric layer exposes a part of the surface of the lower electrode layer; Forming an upper electrode layer on the insulating dielectric layer, the upper electrode layer, the insulating dielectric layer and the lower electrode layer form an antifuse capacitor; the material of the lower electrode layer is different from the material of the upper electrode layer, and the resistance of the upper electrode layer is less than the resistance of the lower electrode layer; the lower electrode layer, the upper electrode layer are independent of the source and drain in the substrate.

16. The manufacturing method according to claim 15, characterized in that, Further comprising: Forming a gate dielectric layer on the substrate; Forming a first gate electrode layer on the gate dielectric layer, and in the process of forming the first gate electrode layer, the lower electrode layer is formed simultaneously; forming a second gate electrode layer on the first gate electrode layer, and in the process of forming the second gate electrode layer, the upper electrode layer is formed simultaneously.

17. The manufacturing method according to claim 16, wherein, Further comprising forming an isolation dielectric layer, the isolation dielectric layer is located between the lower electrode layer and the substrate, and in the process of forming the gate dielectric layer, the isolation dielectric layer is formed simultaneously.

18. The manufacturing method according to claim 15, characterized in that, Further comprising: Performing a modified ion implantation treatment on the insulating dielectric layer to dope modified ions into the insulating dielectric layer.

19. The manufacturing method according to claim 18, characterized in that, Performing the modified ion implantation treatment after forming the upper electrode layer.

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