Semiconductor circuits

Abstract

A semiconductor circuit includes: a reference voltage generating circuit that generates a first reference voltage; a voltage control circuit that receives the first reference voltage from the reference voltage generating circuit to output a second reference voltage; a DC-DC conversion circuit that performs DC-DC conversion based on the second reference voltage output from the voltage control circuit and provides its output to a first node; and a voltage regulator that performs voltage regulation based on the first reference voltage output from the reference voltage generating circuit and a voltage of the first node and provides its output to a second node.

Description

[0001] Cross-references to related applications

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0107859 filed on September 10, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a semiconductor circuit. Background Art

[0004] A voltage regulator that performs voltage regulation generally requires an input voltage higher than a desired output voltage to maintain the desired output voltage. However, there may be a problem that as the difference between the input voltage and the output voltage increases, power loss occurs and heat generation may become serious. For example, when the output voltage of the voltage regulator falls within the range of 1V to 5V, if the input voltage is fixed to, for example, 7V, in the case where the output voltage of the voltage regulator is output to about 1V, power loss and heat generation may become serious.

[0005] Specifically, when the voltage regulator and the DC-DC conversion circuit are implemented in an integrated manner, the input voltage of the voltage regulator can be determined based on the output voltage of the DC-DC conversion circuit. If the output of the DC-DC conversion circuit is fixed to, for example, 7V as in the above example, power loss and heat may occur due to fluctuations in the output voltage of the voltage regulator. Summary of the invention

[0006] At least some example embodiments of the present disclosure provide a semiconductor circuit capable of regulating voltage while reducing power loss and heat generation even when an output voltage of a voltage regulator fluctuates.

[0007] However, the exemplary embodiments of the present disclosure are not limited to the exemplary embodiments set forth herein. The above and other exemplary embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0008] According to an example embodiment of the present disclosure, there is provided a semiconductor circuit, comprising: a reference voltage generating circuit configured to generate a first reference voltage; a voltage control circuit configured to receive the first reference voltage from the reference voltage generating circuit and to generate a second reference voltage based on at least the first reference voltage; a DC-DC conversion circuit configured to perform DC-DC conversion based on the second reference voltage to generate an input voltage, and to provide the input voltage to a first node; and a voltage regulator configured to generate an output voltage by performing voltage regulation based on the first reference voltage and the input voltage, and to provide the output voltage to a second node.

[0009] According to another example embodiment of the present disclosure, there is provided a semiconductor circuit, comprising: a reference voltage generating circuit configured to generate a first reference voltage; a DC-DC conversion circuit configured to perform DC-DC conversion based on a second reference voltage to generate an input voltage, and provide the input voltage to a first node, the voltage level of the second reference voltage being different from the voltage level of the first reference voltage; and a voltage regulator configured to generate an output voltage by performing voltage regulation based on the first reference voltage and the input voltage, and provide the output voltage to a second node, wherein the semiconductor circuit is configured to maintain a constant difference between the input voltage output by the DC-DC conversion circuit and the output voltage output by the voltage regulator, so that the constant difference corresponds to the difference between the second reference voltage and the first reference voltage, regardless of changes in the input voltage due to fluctuations in the output voltage.

[0010] According to another example embodiment of the present disclosure, there is provided a semiconductor circuit, comprising: a reference voltage generating circuit configured to generate a first reference voltage; a voltage control circuit configured to receive the first reference voltage from the reference voltage generating circuit and generate a second reference voltage based on at least the first reference voltage; a DC-DC conversion circuit configured to generate an input voltage, the input voltage being applied to a first node, the DC-DC conversion circuit comprising a first comparator having a non-inverting terminal and an inverting terminal, the non-inverting terminal being configured to receive the second reference voltage, the inverting terminal being configured to receive the input voltage applied to the first node; and a voltage regulator configured to generate an output voltage, the voltage regulator comprising a second comparator having an inverting terminal configured to receive the first reference voltage, the output voltage being applied to a second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0012] Figure 1 is a schematic diagram for explaining a semiconductor system according to an example embodiment of the present disclosure;

[0013] Figure 2 is a circuit diagram for explaining a semiconductor system according to an example embodiment of the present disclosure;

[0014] Figure 3 is a schematic diagram illustrating a semiconductor system according to another example embodiment of the present disclosure;

[0015] Figure 4 is a circuit diagram illustrating a semiconductor system according to another example embodiment of the present disclosure;

[0016] Figure 5 is a schematic diagram for explaining a semiconductor system according to yet another example embodiment of the present disclosure;

[0017] Figure 6 is a circuit diagram illustrating a semiconductor system according to yet another example embodiment of the present disclosure;

[0018] Figure 7 is a schematic diagram for explaining a semiconductor system according to yet another example embodiment of the present disclosure;

[0019] Figure 8 is a circuit diagram illustrating a semiconductor system according to yet another example embodiment of the present disclosure;

[0020] Fig. 9 is a schematic diagram for explaining a semiconductor system according to yet another example embodiment of the present disclosure;

[0021] Fig.10 is a circuit diagram illustrating a semiconductor system according to yet another example embodiment of the present disclosure;

[0022] Fig.11 is a schematic diagram for explaining a semiconductor system according to still another example embodiment of the present disclosure; and

[0023] Fig.12 is a circuit diagram illustrating a semiconductor system according to still another example embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] Figure 1 is a schematic diagram for explaining a semiconductor system according to an example embodiment of the present disclosure.

[0025] refer to Figure 1 The semiconductor system 1 according to the exemplary embodiment of the present disclosure includes a DC-DC conversion circuit 100, a voltage regulator 200, and a reference voltage (V REF) generating circuit 300.

[0026] The DC-DC conversion circuit 100 generates a first reference voltage V based on the first reference voltage V provided by the reference voltage generation circuit 300. REF In addition, the DC-DC conversion circuit 100 provides a DC-DC converted output voltage to the first node N0.

[0027] The voltage regulator 200 generates a voltage based on the first reference voltage V provided by the reference voltage generating circuit 300. REF Voltage regulation is performed. Specifically, in example embodiments, the voltage regulator 200 performs voltage regulation using the voltage of the first node N0 as an input voltage. The voltage regulator 200 provides an output to the second node N1. The voltage Vout output from the voltage regulator 200 may be used as a driving voltage for driving another semiconductor device.

[0028] In some example embodiments of the present disclosure, the voltage regulator 200 may include an LDO (Low Drop Out) linear regulator, but the scope of the present disclosure is not limited thereto.

[0029] The reference voltage generating circuit 300 generates a first reference voltage V REF , and provides a first reference voltage V to the DC-DC conversion circuit 100 and the voltage regulator 200 REF The first reference voltage V provided to the DC-DC conversion circuit 100 REF It can be used to adjust the level of the output voltage of the DC-DC conversion circuit 100. On the other hand, the first reference voltage V provided to the voltage regulator 200 REF It can be used to adjust the level of the output voltage of the voltage regulator 200 .

[0030] The voltage level of the first node N0 corresponding to the input of the voltage regulator 200 is higher than the voltage level of the second node N1 corresponding to the output of the voltage regulator 200. However, when the output of the voltage regulator 200 is determined to be, for example, in the range of 1V to 5V, if the voltage of the first node N0 is fixed to, for example, 7V, problems of power loss and heat generation may occur when the output of the voltage regulator 200 is about 1V.

[0031] To solve such a problem, in one or more example embodiments, the DC-DC conversion circuit 100 may include a voltage control circuit 110 .

[0032] As reference below Figure 2 As discussed in more detail, the voltage control circuit 110 receives a first reference voltage V from the reference voltage generating circuit 300. REF To output the second reference voltage V REFThat is, the voltage control circuit 110 prohibits the reference voltage generation circuit 300 from immediately providing the first reference voltage V to the DC-DC conversion circuit 100. REF , outputting a second reference voltage V adjusted to reduce (or alternatively, prevent) the difference between the voltage level of the first node N0 corresponding to the input of the voltage regulator 200 and the voltage level of the second node N1 corresponding to the output of the voltage regulator 200 from increasing REF ', and provide a second reference voltage V to the DC-DC conversion circuit 100 REF '.

[0033] As a result, the DC-DC conversion circuit 100 is based on the second reference voltage V output from the voltage control circuit 110. REF ' performs DC-DC conversion and outputs the output to the first node N0. In addition, the voltage regulator 200 generates a first reference voltage V based on the first reference voltage V output from the reference voltage generating circuit 300. REF The voltage of the first node N0 performs voltage regulation and outputs its output to the second node N1.

[0034] Now refer to Figure 2 An example embodiment of a semiconductor system 1 according to an example embodiment of the present disclosure is described.

[0035] Figure 2 is a circuit diagram for explaining a semiconductor system according to an example embodiment of the present disclosure.

[0036] refer to Figure 2 , a semiconductor system 1 according to an example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage regulator 200 , and a reference voltage generation circuit 300 .

[0037] The DC-DC conversion circuit 100 includes a voltage control circuit 110 , a first comparator 120 , a control circuit 130 , a first transistor M1 , and a second transistor M2 .

[0038] The voltage control circuit 110 receives the first reference voltage V from the reference voltage generating circuit 300. REF , to output the second reference voltage V REF ', and provide the second reference voltage V to the first comparator 120 REF '.

[0039] The first comparator 120 includes a non-inverting terminal (+) and an inverting terminal (-) as input terminals. The second reference voltage V provided from the voltage control circuit 110 REF' is applied to the non-inverting terminal (+). The voltage of the first node N0 corresponding to the output of the DC-DC conversion circuit 100 is applied to the inverting terminal (-). The first comparator 120 provides the control circuit 130 with a result signal obtained by comparing the non-inverting terminal (+) with the inverting terminal (-).

[0040] The control circuit 130 receives the output signal of the first comparator 120 and outputs a first control signal and a second control signal. The control circuit 130 may use the first control signal and the second control signal to turn on or off the first transistor M1 and the second transistor M2 according to the comparison result of the first comparator 120 .

[0041] The first transistor M1 is turned on by a first control signal provided from the control circuit 130 and supplies a power supply voltage VDD to the first node N0. The second transistor M2 is turned on by a second control signal provided from the control circuit 130 and supplies a ground voltage GND to the first node N0.

[0042] In an example embodiment, the first transistor M1 may be a P-type transistor and the second transistor M2 may be an N-type transistor, but the scope of the present disclosure is not limited thereto. In this case, the source of the first transistor M1 is connected to the power supply voltage VDD, the drain of the first transistor M1 is connected to the drain of the second transistor M1, and the source of the second transistor M1 may be connected to the ground voltage GND.

[0043] The voltage regulator 200 includes a second comparator 210 and a third transistor M3 .

[0044] The first reference voltage V provided by the reference voltage generating circuit 300 REF is applied to the inverting terminal (-) of the second comparator 210. The voltage of the second node N1 corresponding to the output of the voltage regulator 200 is applied to the non-inverting terminal (+). The second comparator 210 provides a result signal obtained by comparing the non-inverting terminal (+) with the inverting terminal (-) to the third transistor M3.

[0045] The third transistor M3 is gated by the output signal of the second comparator 210, and provides the voltage of the first node N0 to the second node N1. In this example embodiment, the third transistor M3 may be a P-type transistor, but the scope of the present disclosure is not limited thereto. In this case, the source of the third transistor M3 may be connected to the first node N0, and the drain of the third transistor M3 may be connected to the second node N1.

[0046] When the third transistor M3 is a P-type transistor, if the voltage of the second node N1 is greater than the first reference voltage V REF, the voltage level of the result signal of the second comparator 210 increases. Alternatively, if the voltage of the second node N1 is less than the first reference voltage V REF , the voltage level of the result signal of the second comparator 210 decreases.

[0047] When the voltage level of the result signal of the second comparator 210 increases, the voltage level of the second node N1 decreases because the amount of current flowing from the source to the drain of the third transistor M3 decreases. When the voltage level of the second node N1 decreases to become lower than the first reference voltage V REF When the voltage level of the result signal of the second comparator 210 decreases, the amount of current flowing from the source to the drain of the third transistor M3 increases. As a result, the voltage level of the second node N1 increases. By repeating this process, the voltage level of the second node N1 becomes equal to the first reference voltage V REF voltage level.

[0048] The voltage control circuit 100 is arranged in the DC-DC conversion circuit 100 and adds the voltage difference voltage to the first reference voltage V REF , to generate a second reference voltage V REF Here, the differential voltage refers to a voltage corresponding to a voltage obtained by subtracting the output voltage of the voltage regulator 200 from the output voltage of the DC-DC conversion circuit 100. For example, the differential voltage may correspond to a voltage obtained by subtracting the voltage level of the second node N1 from the voltage level of the first node N0. As another example, the differential voltage may correspond to the gate-source voltage V of the third transistor M3 of the voltage regulator 200. Gs .

[0049] In some example embodiments of the present disclosure, the voltage control circuit 100 may include a level shift circuit that shifts and outputs the level of the input voltage. However, the scope of the present disclosure is not limited thereto, and the voltage control circuit 100 may be implemented to shift the first reference voltage V REF Any circuit that converts a voltage level to another value.

[0050] According to example embodiments, during operation of the semiconductor circuit of the present disclosure, the dropout voltage is maintained constant, and the output voltage of the DC-DC conversion circuit 100 is changed according to the fluctuation of the output voltage of the voltage regulator 200 .

[0051] For example, when the target output voltage of the voltage regulator 200 is 5V, the first reference voltage V REF In this case, when the voltage difference voltage is determined to be 0.5V, the voltage control circuit 100 may output a second reference voltage V of 5.5V obtained by adding 0.5V to 5V. REFAs a result, the output voltage of the DC-DC conversion circuit 100 will have a voltage level of about 5.5V.

[0052] As another example, when the target output voltage of the voltage regulator 200 is 1V, the first reference voltage V REF In this case, when the voltage difference voltage is determined to be 0.5V, the voltage control circuit 100 may output a second reference voltage V of 1.5V obtained by adding 0.5V to 1V. REF As a result, the output voltage of the DC-DC conversion circuit 100 will have a voltage level of about 1.5V.

[0053] That is, the output voltage of the DC-DC conversion circuit 100 changes according to the fluctuation of the output voltage of the voltage regulator 200 so that the dropout voltage becomes constant. As a result, the semiconductor system 1 solves the problem of power loss and heat generation due to the fluctuation of the output voltage of the voltage regulator 200.

[0054] Figure 3 is a schematic diagram illustrating a semiconductor system according to another example embodiment of the present disclosure.

[0055] Reference Figure 3 , a semiconductor system 2 according to another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage control circuit 110 , a voltage regulator 200 , and a reference voltage generation circuit 300 .

[0056] In an exemplary embodiment, the voltage control circuit 110 is provided outside the DC-DC conversion circuit 100. In addition, the voltage control circuit 110 provides the second reference voltage V to the DC-DC conversion circuit 100 through the third node N2. REF '.

[0057] As a result, the DC-DC conversion circuit 100 receives the second reference voltage V outputted from the voltage control circuit 110 through the third node N2. REF ', and after performing DC-DC conversion based thereon, outputs its output to the first node N0. In addition, the voltage regulator 200 outputs the first reference voltage V based on the first reference voltage V outputted from the reference voltage generating circuit 300. REF and the voltage of the first node N0 perform voltage regulation, and provide its output to the second node N1.

[0058] Figure 4 is a circuit diagram illustrating a semiconductor system according to another example embodiment of the present disclosure.

[0059] Reference Figure 4, a semiconductor system 2 according to another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage control circuit 110 , a voltage regulator 200 , and a reference voltage generation circuit 300 .

[0060] The DC-DC conversion circuit 100 includes a first comparator 120 , a control circuit 130 , a first transistor M1 , and a second transistor M2 .

[0061] The non-inverting terminal (+) of the first comparator 120 is connected to the third node N2. Therefore, the second reference voltage V supplied from the voltage control circuit 110 via the third node N2 is REF ' is applied to the non-inverting terminal (+) of the first comparator 120. The first comparator 120 provides the control circuit 130 with a result signal obtained by comparing the non-inverting terminal (+) with the inverting terminal (-) to which the voltage of the first node N0 is applied.

[0062] The voltage control circuit 110 is disposed outside the DC-DC conversion circuit 100 and receives a first reference voltage V from the reference voltage generation circuit 300. REF To output the second reference voltage V REF ', and provide the second reference voltage V to the third node N2 REF '.

[0063] In addition, no Figure 2 According to the exemplary embodiment, the output voltage of the DC-DC conversion circuit 100 varies according to the fluctuation of the output voltage of the voltage regulator 200, so that the differential voltage becomes constant. As a result, the semiconductor system 2 solves the problems of power loss and heat generation caused by the fluctuation of the output voltage of the voltage regulator. In addition, by setting the voltage control circuit 110 outside the DC-DC conversion circuit 100, the scalability and design flexibility can be enhanced.

[0064] Figure 5 is a schematic diagram for explaining a semiconductor system according to still another example embodiment of the present disclosure.

[0065] refer to Figure 5 , a semiconductor system 3 according to still another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage regulator 200 , a reference voltage generation circuit 300 , and a device under test (DUT) 400 .

[0066] The device under test 400 includes a semiconductor circuit formed by a semiconductor manufacturing process. The device under test 400 may be, for example: a volatile memory device including SRAM (static RAM), DRAM (dynamic RAM), SDRAM (synchronous DRAM), etc.; and a non-volatile memory device including ROM (read-only memory), PROM (programmable ROM), EPROM (electrically programmable ROM), EEPROM (electrically erasable programmable ROM), flash memory, PRAM (phase change RAM), MRAM (magnetic RAM), RRAM (resistive RAM), FRAM (ferroelectric RAM), etc. Alternatively, the device under test 400 may be a non-memory device, such as a microprocessor, a controller, a logic circuit, etc. Alternatively, the device under test 400 may be a system semiconductor device, such as a system LSI (large scale integration) in which a logic circuit and a memory circuit are integrated.

[0067] On the other hand, the device under test 400 may be a semiconductor device at the wafer level in which circuit elements are formed by a semiconductor manufacturing process before performing a packaging process. Alternatively, the device under test 400 may be a semiconductor die in which a semiconductor wafer having a semiconductor circuit formed thereon is divided by a cutting process. Alternatively, the device under test 400 may be a semiconductor package in which a semiconductor die having a semiconductor circuit formed thereon is packaged. Alternatively, the device under test 400 may have the form of an integrated package in which a plurality of semiconductor packages of the same type or different types are integrated into a single package.

[0068] In example embodiments, the voltage regulator 200 can provide the driving voltage Vout to the device under test 400 through the second node N1. That is, the semiconductor system 3 according to example embodiments is a system for testing the device under test 400, and can supply power to the device under test 400 using the integrated DC-DC conversion circuit 100 and the voltage regulator 200.

[0069] Figure 6 is a circuit diagram illustrating a semiconductor system according to still another example embodiment of the present disclosure.

[0070] refer to Figure 6 , a semiconductor system 3 according to still another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage regulator 200 , a reference voltage generation circuit 300 , and a device under test 400 .

[0071] The DC-DC conversion circuit 100 includes a voltage control circuit 110, a first comparator 120, a control circuit 130, a first transistor M1 and a second transistor M2. Figure 2 The contents described in are repeated, so their description will not be provided here.

[0072] The voltage regulator 200 includes a second comparator 210 , a third comparator 220 , and a third transistor M3 .

[0073] The first reference voltage V provided by the reference voltage generating circuit 300 REF is applied to the inverting terminal (-) of the second comparator 210. The output of the third comparator 220 is connected to the non-inverting terminal (+). The second comparator 210 provides a result signal obtained by comparing the non-inverting terminal (+) with the inverting terminal (-) to the third transistor M3.

[0074] The non-inverting terminal (+) of the third comparator 220 is connected to one end of the device under test 400, and the inverting terminal (-) of the third comparator 220 is connected to the other end of the device under test 400. The third comparator 220 provides the second comparator 210 with a result signal obtained by comparing the non-inverting terminal (+) with the inverting terminal (-).

[0075] The third transistor M3 is gated by the output signal of the second comparator 210 and provides the voltage of the first node N0 to the second node N1. In example embodiments, the third transistor M3 may be a P-type transistor, but the scope of the present disclosure is not limited thereto. In this case, the source of the third transistor M3 may be connected to the first node N0, and the drain of the third transistor M3 may be connected to the second node N1.

[0076] Will not provide Figure 2 and Figure 4 According to the exemplary embodiment, the output voltage of the DC-DC conversion circuit 100 varies according to the fluctuation of the output voltage of the voltage regulator 200, so that the differential voltage becomes constant. As a result, the semiconductor system 3 solves the problems of power loss and heat generation caused by the fluctuation of the output voltage of the voltage regulator. In addition, by sensing the electrical characteristics of the device under test 400 using the third comparator 220, the test accuracy of the device under test 400 can be improved.

[0077] Figure 7 is a schematic diagram for explaining a semiconductor system according to still another example embodiment of the present disclosure.

[0078] refer to Figure 7 , a semiconductor system 4 according to yet another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage control circuit 110 , a voltage regulator 200 , a reference voltage generation circuit 300 , and a device under test 400 .

[0079] In an exemplary embodiment, the voltage control circuit 110 is provided outside the DC-DC conversion circuit 100. In addition, the voltage control circuit 110 provides the second reference voltage V to the DC-DC conversion circuit 100 through the third node N2. REF '.

[0080] As a result, the DC-DC conversion circuit 100 receives the second reference voltage V outputted from the voltage control circuit 110 through the third node N2. REF ', performs DC-DC conversion based thereon, and then provides its output to the first node N0. In addition, the voltage regulator 200 performs DC-DC conversion based on the first reference voltage V output from the reference voltage generating circuit 300. REF and the voltage of the first node N0 to perform voltage regulation, and can provide its output as a driving voltage Vout to the device under test 400 through the second node N1.

[0081] Figure 8 is a circuit diagram illustrating a semiconductor system according to another example embodiment of the present disclosure.

[0082] refer to Figure 8 , a semiconductor system 4 according to yet another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage control circuit 110 , a voltage regulator 200 , a reference voltage generation circuit 300 , and a device under test 400 .

[0083] The DC-DC conversion circuit 100 includes a first comparator 120 , a control circuit 130 , a first transistor M1 , and a second transistor M2 .

[0084] The non-inverting terminal (+) of the first comparator 120 is connected to the third node N2. Therefore, the second reference voltage V provided from the voltage control circuit 110 through the third node N2 is REF ' is applied to the non-inverting terminal (+) of the first comparator 120. The first comparator 120 provides the control circuit 130 with a result signal obtained by comparing the non-inverting terminal (+) with the inverting terminal (-) to which the voltage of the first node N0 is applied.

[0085] The voltage control circuit 110 is disposed outside the DC-DC conversion circuit 100 and receives a first reference voltage V from the reference voltage generation circuit 300. REF To output the second reference voltage V REF ', and provide the second reference voltage V to the third node N2 REF '.

[0086] In addition, no Figure 6. According to the example embodiment, the output voltage of the DC-DC conversion circuit 100 changes according to the fluctuation of the output voltage of the voltage regulator 200, so that the differential voltage becomes constant. As a result, the semiconductor system 4 solves the problems of power loss and heating caused by the fluctuation of the output voltage of the voltage regulator. In addition, by arranging the voltage control circuit 110 outside the DC-DC conversion circuit 100, the scalability and design flexibility can be enhanced. In addition, by using the third comparator 220 to sense the electrical characteristics of the device under test 400, the test accuracy of the device under test 400 can be improved.

[0087] Fig. 9 is a schematic diagram for explaining a semiconductor system according to still another example embodiment of the present disclosure.

[0088] refer to Fig. 9 , a semiconductor system 5 according to yet another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage regulator 200 , a reference voltage generation circuit 300 , a device under test 400 , and a voltage adjustment circuit 500 .

[0089] The voltage adjustment circuit 500 sends a command signal CMD to the voltage control circuit 110, so that the voltage control circuit 110 can adjust the second reference voltage V based on the command signal CMD. REF According to the above embodiment, the voltage control circuit 110 determines the second reference voltage V REF ' to meet the purpose of keeping the voltage difference constant. However, for example, in order to grasp the maximum efficiency of the device under test 400, to grasp the balance of various parameters or for various other purposes, it may be desirable to change the second reference voltage V during the test of the device under test 400. REF In this case, the user can customize the operation of the voltage control circuit 110 via the voltage adjustment circuit 500.

[0090] The command signal CMD sent by the voltage adjustment circuit 500 to the voltage control circuit 110 can be implemented in various ways according to various rules. For example, when the voltage control circuit 110 is designed to be able to output multiple voltage levels, the command signal CMD can be implemented as a signal for selecting one of the multiple voltage levels. Alternatively, when the voltage control circuit 110 is designed to be able to dynamically change the voltage level, the command signal CMD can make the value associated with the voltage level variable. These examples do not limit the scope of the present disclosure.

[0091] In the example embodiment, the voltage adjustment circuit 500 sends a command signal CMD to the voltage control circuit 110 according to the purpose of testing the device under test 400, and the voltage regulator 200 can provide the driving voltage Vout to the device under test 400 through the second node N1. That is, the semiconductor system 5 according to the example embodiment is a system for testing the device under test 400, and can supply power matching a specific test purpose to the device under test 400 using the DC-DC conversion circuit 100 and the voltage regulator 200 implemented in an integrated manner.

[0092] Fig.10 is a circuit diagram illustrating a semiconductor system according to still another example embodiment of the present disclosure.

[0093] refer to Fig.10 , a semiconductor system 5 according to yet another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage regulator 200 , a reference voltage generation circuit 300 , a device under test 400 , and a voltage adjustment circuit 500 .

[0094] The DC-DC conversion circuit 100 includes a voltage control circuit 110, a first comparator 120, a control circuit 130, a first transistor M1 and a second transistor M2. Figure 2 The contents described in are repeated, so their description will not be provided here.

[0095] The voltage regulator 200 includes a second comparator 210, a third comparator 220 and a third transistor M3. Figure 6 The contents described in are repeated, so their description will not be provided here.

[0096] According to example embodiments, the test range of the device under test 400 may be widened by supplying power matching a specific test purpose to the device under test 400. In addition, by sensing electrical characteristics of the device under test 400 using the third comparator 220, the test accuracy of the device under test 400 may be improved.

[0097] Fig.11 is a schematic diagram for explaining a semiconductor system according to still another example embodiment of the present disclosure.

[0098] refer to Fig.11 , a semiconductor system 6 according to yet another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage control circuit 110 , a voltage regulator 200 , a reference voltage generation circuit 300 , a device under test 400 , and a voltage adjustment circuit 500 .

[0099] In an exemplary embodiment, the voltage control circuit 110 is provided outside the DC-DC conversion circuit 100. In addition, the voltage control circuit 110 provides the second reference voltage V to the DC-DC conversion circuit 100 through the third node N2. REF '.

[0100] As a result, the DC-DC conversion circuit 100 receives the second reference voltage V outputted from the voltage control circuit 110 through the third node N2. REF ', performs DC-DC conversion based thereon, and then provides its output to the first node N0. In addition, the voltage regulator 200 performs DC-DC conversion based on the first reference voltage V output from the reference voltage generating circuit 300. REF and the voltage of the first node N0 to perform voltage regulation, and can provide its output as a driving voltage Vout to the device under test 400 through the second node N1.

[0101] Fig.12 is a circuit diagram illustrating a semiconductor system according to still another example embodiment of the present disclosure.

[0102] refer to Fig.12 , a semiconductor system 6 according to yet another example embodiment of the present disclosure includes a DC-DC conversion circuit 100 , a voltage control circuit 110 , a voltage regulator 200 , a reference voltage generation circuit 300 , a device under test 400 , and a voltage adjustment circuit 500 .

[0103] The DC-DC conversion circuit 100 includes a first comparator 120 , a control circuit 130 , a first transistor M1 , and a second transistor M2 .

[0104] The non-inverting terminal (+) of the first comparator 120 is connected to the third node N2. Therefore, the second reference voltage V provided from the voltage control circuit 110 through the third node N2 is REF ' is applied to the non-inverting terminal (+) of the first comparator 120. The first comparator 120 provides the control circuit 130 with a result signal obtained by comparing the non-inverting terminal (+) with the inverting terminal (-) to which the voltage of the first node N0 is applied.

[0105] The voltage control circuit 110 is disposed outside the DC-DC conversion circuit 100 and receives a first reference voltage V from the reference voltage generation circuit 300. REF To output the second reference voltage V REF ', and provide the second reference voltage V to the third node N2 REF '.

[0106] In addition, no Fig.10. According to the example embodiment, by supplying power matching a specific test purpose to the device under test 400, the test range of the device under test 400 can be widened. In addition, by arranging the voltage control circuit 110 outside the DC-DC conversion circuit 100, the scalability and design flexibility can be enhanced. In addition, by using the third comparator 220 to sense the electrical characteristics of the device under test 400, the test accuracy of the device under test 400 can be improved.

[0107] In some example embodiments, elements of the semiconductor system 1 (e.g., the voltage control circuit 110, the control circuit 130, the reference voltage generating circuit 300, and / or the voltage adjusting circuit 500) may be implemented using hardware, a combination of hardware and software, or a non-transitory storage medium storing software executable to perform its functions.

[0108] The hardware may be implemented using processing circuitry such as, but not limited to, one or more processors, one or more central processing units (CPUs), one or more controllers, one or more arithmetic logic units (ALUs), one or more digital signal processors (DSPs), one or more microcomputers, one or more field programmable gate arrays (FPGAs), one or more systems on a chip (SoCs), one or more programmable logic units (PLUs), one or more microprocessors, one or more application specific integrated circuits (ASICs), or any other device or devices capable of responding to and executing instructions in a defined manner.

[0109] Software may include computer programs, program codes, instructions, or a combination thereof to independently or collectively instruct or configure hardware devices to operate as desired. Computer programs and / or program codes may include programs or computer-readable instructions, software components, software modules, data files, data structures, etc. that can be implemented by one or more hardware devices (e.g., one or more of the hardware devices mentioned above). Examples of program code include machine code generated by a compiler and higher-level program code executed using an interpreter.

[0110] For example, when the hardware device is a computer processing device (for example, one or more processors, CPUs, controllers, ALUs, DSPs, microcomputers, microprocessors, etc.), the computer processing device can be configured to execute program code by performing arithmetic, logic, and input / output operations according to the program code. Once the program code is loaded into the computer processing device, the computer processing device can be programmed to execute the program code, thereby transforming the computer processing device into a special-purpose computer processing device. In a more specific example, when the program code is loaded into the processor, the processor is programmed to execute the program code and the operation corresponding thereto, thereby transforming the processor into a special-purpose processor. In another example, the hardware device can be an integrated circuit customized in a special-purpose processing circuit (for example, ASIC).

[0111] A hardware device such as a computer processing device can run an operating system (OS) and one or more software applications running on the OS. In addition, the computer processing device can also access, store, manipulate, process, and create data in response to the execution of the software. For simplicity, one or more example embodiments may be shown as a computer processing device; however, those skilled in the art will appreciate that the hardware device may include multiple processing elements and multiple types of processing elements. For example, the hardware device may include multiple processors or a processor and a controller. In addition, other processing configurations are also possible, such as parallel processors.

[0112] According to one or more example embodiments, the storage medium may also include one or more storage devices at the unit and / or device. One or more storage devices may be tangible or non-temporary computer-readable storage media, such as random access memory (RAM), read-only memory (ROM), permanent mass storage device (such as disk drive) and / or any other similar data storage mechanism capable of storing and recording data. One or more storage devices may be configured to store computer programs, program codes, instructions or some combinations thereof for one or more operating systems and / or for implementing the example embodiments described herein. A drive mechanism may also be used to load a computer program, program code, instruction or some combination thereof from a separate computer-readable storage medium into one or more storage devices and / or one or more computer processing devices. This separate computer-readable storage medium may include a universal serial bus (USB) flash drive, a memory stick, a Blu-ray / DVD / CD-ROM drive, a memory card and / or other similar computer-readable storage media. A computer program, program code, instruction or some combination thereof may be loaded into one or more storage devices and / or one or more computer processing devices from a remote data storage device via a network interface rather than via a computer-readable storage medium. In addition, a computer program, program code, instruction, or some combination thereof may be loaded into one or more storage devices and / or one or more processors from a remote computing system configured to transmit and / or distribute the computer program, program code, instruction, or some combination thereof via a network. The remote computing system may transmit and / or distribute the computer program, program code, instruction, or some combination thereof via a wired interface, an air interface, and / or any other similar medium.

[0113] One or more hardware devices, storage media, computer programs, program codes, instructions, or some combination thereof may be specially designed and constructed for the purposes of the example embodiments, or they may be known devices that have been altered and / or modified for the purposes of the example embodiments.

[0114] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the exemplary embodiments without substantially departing from the principles of the present disclosure. Therefore, the disclosed exemplary embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A semiconductor circuit, include: A reference voltage generating circuit configured to generate a first reference voltage; a voltage control circuit configured to receive the first reference voltage from the reference voltage generating circuit and generate a second reference voltage by adding a differential voltage to the first reference voltage, the differential voltage corresponding to a difference between an output voltage and an input voltage; a DC-DC conversion circuit configured to perform DC-DC conversion based on the second reference voltage to generate the input voltage, and provide the input voltage to the first node; as well as A voltage regulator is configured to generate the output voltage by performing voltage regulation based on the first reference voltage and the input voltage, and to provide the output voltage to a second node.

2. The semiconductor circuit according to claim 1, in, The semiconductor circuit is configured to maintain the differential voltage at a constant voltage level during operation of the semiconductor circuit regardless of a change in the input voltage generated by the DC-DC conversion circuit due to a fluctuation in the output voltage generated by the voltage regulator.

3. The semiconductor circuit according to claim 1, in, The DC-DC conversion circuit comprises: a first comparator having a non-inverting terminal and an inverting terminal, the non-inverting terminal being configured to receive the second reference voltage, the inverting terminal being configured to receive the input voltage from the first node, a control circuit configured to receive an output signal of the first comparator and generate a first control signal and a second control signal based on the output signal, a first transistor having a gate configured to receive the first control signal, the first transistor being configured to selectively provide a power supply voltage to the first node based on the first control signal, and A second transistor has a gate configured to receive the second control signal, and the second transistor is configured to selectively provide a ground voltage to the first node based on the second control signal.

4. The semiconductor circuit according to claim 3, in, The first transistor is a P-type transistor, The second transistor is an N-type transistor, and The drain of the first transistor is connected to the drain of the second transistor.

5. The semiconductor circuit according to claim 1, in, The voltage regulator comprises: a second comparator having an inverting terminal configured to receive the first reference voltage and a non-inverting terminal configured to receive the output voltage of the second node, and A third transistor has a gate configured to receive an output signal of the second comparator, and is configured to selectively provide the voltage of the first node to the second node based on the output signal.

6. The semiconductor circuit according to claim 5, in, The third transistor is a P-type transistor, and the third transistor has a source and a drain. The source of the third transistor is connected to the first node so that the source of the third transistor receives the input voltage, and the drain of the third transistor is connected to the second node so that the drain of the third transistor outputs the output voltage.

7. The semiconductor circuit according to claim 1, in, The voltage control circuit comprises: Level shift circuit.

8. The semiconductor circuit according to claim 1, in, The voltage control circuit is arranged inside the DC-DC conversion circuit.

9. The semiconductor circuit according to claim 1, in, The voltage control circuit is provided outside the DC-DC conversion circuit, such that the voltage control circuit is configured to provide the second reference voltage to the DC-DC conversion circuit through a third node.

10. The semiconductor circuit according to claim 1, in, The voltage regulator is configured to provide a driving voltage to the device under test through the second node, and the voltage regulator includes: a third comparator having a non-inverting terminal and an inverting terminal, the non-inverting terminal being configured to receive a first input from the device under test, and the inverting terminal being configured to receive a second input from the device under test, a second comparator having an inverting terminal and a non-inverting terminal, the inverting terminal being configured to receive the first reference voltage and the non-inverting terminal being configured to receive an output signal of the third comparator, and A third transistor has a gate configured to receive an output signal of the second comparator, and the third transistor is configured to selectively provide the input voltage of the first node to the second node based on the output signal.

11. The semiconductor circuit according to claim 10, in, The third transistor is a P-type transistor, and the third transistor has a source and a drain, the source of the third transistor is connected to the first node so that the source of the third transistor receives the input voltage, and the drain of the third transistor is connected to the second node so that the drain of the third transistor outputs the output voltage.

12. The semiconductor circuit according to claim 1, further comprising: include: The voltage adjustment circuit is configured to send a command signal to the voltage control circuit, wherein the voltage control circuit is configured to adjust the level of the second reference voltage based on the command signal.

13. A semiconductor circuit, include: A reference voltage generating circuit configured to generate a first reference voltage; a DC-DC conversion circuit configured to perform DC-DC conversion based on a second reference voltage to generate an input voltage, and to provide the input voltage to a first node, the second reference voltage having a voltage level different from that of the first reference voltage; as well as a voltage regulator configured to generate an output voltage by performing voltage regulation based on the first reference voltage and the input voltage, and to provide the output voltage to a second node, wherein the semiconductor circuit is configured to maintain a constant difference between the input voltage output by the DC-DC conversion circuit and the output voltage output by the voltage regulator, so that the constant difference corresponds to the difference between the second reference voltage and the first reference voltage, regardless of changes in the input voltage caused by fluctuations in the output voltage.

14. The semiconductor circuit according to claim 13, in, The DC-DC conversion circuit comprises: a first comparator having a non-inverting terminal and an inverting terminal, the non-inverting terminal being configured to receive the second reference voltage, the inverting terminal being configured to receive the input voltage from the first node, a control circuit configured to receive an output signal of the first comparator and generate a first control signal and a second control signal based on the output signal, a first transistor having a gate configured to receive the first control signal, the first transistor being configured to selectively provide a power supply voltage to the first node based on the first control signal, and A second transistor has a gate configured to receive the second control signal, and the second transistor is configured to selectively provide a ground voltage to the first node based on the second control signal.

15. The semiconductor circuit according to claim 14, in, The first transistor is a P-type transistor, The second transistor is an N-type transistor, and The drain of the first transistor is connected to the drain of the second transistor.

16. The semiconductor circuit according to claim 13, in, The voltage regulator comprises: a second comparator having an inverting terminal configured to receive the first reference voltage and a non-inverting terminal configured to receive the output voltage of the second node, and A third transistor has a gate configured to receive an output signal of the second comparator, and is configured to selectively provide the voltage of the first node to the second node based on the output signal.

17. The semiconductor circuit according to claim 16, in, The third transistor is a P-type transistor, and the third transistor also has a source and a drain. The source of the third transistor is connected to the first node so that the source of the third transistor receives the input voltage, and the drain of the third transistor is connected to the second node so that the drain of the third transistor outputs the output voltage.

18. The semiconductor circuit according to claim 13, in, The voltage regulator is configured to provide a driving voltage to the device under test (DUT) through the second node, and the voltage regulator includes: a third comparator having a non-inverting terminal and an inverting terminal, the non-inverting terminal being configured to receive a first input from the device under test, and the inverting terminal being configured to receive a second input from the device under test, a second comparator having an inverting terminal and a non-inverting terminal, the inverting terminal being configured to receive the first reference voltage and the non-inverting terminal being configured to receive an output signal of the third comparator, and A third transistor has a gate configured to receive an output signal of the second comparator, and the third transistor is configured to selectively provide the input voltage of the first node to the second node based on the output signal.

19. A semiconductor circuit, include: A reference voltage generating circuit configured to generate a first reference voltage; a voltage control circuit configured to receive the first reference voltage from the reference voltage generating circuit and generate a second reference voltage by adding a differential voltage to the first reference voltage, the differential voltage corresponding to a difference between an output voltage and an input voltage; a DC-DC conversion circuit configured to generate an input voltage, the input voltage being applied to a first node, the DC-DC conversion circuit comprising a first comparator having a non-inverting terminal and an inverting terminal, the non-inverting terminal being configured to receive the second reference voltage, the inverting terminal being configured to receive the input voltage applied to the first node; as well as A voltage regulator is configured to generate an output voltage, the voltage regulator comprising a second comparator having an inverting terminal configured to receive the first reference voltage, the output voltage being applied to a second node.

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