Voltage drop monitoring circuit and system on chip

Abstract

A voltage drop monitoring circuit and a system on chip are provided. In one embodiment, the voltage drop monitoring circuit includes a ring oscillator circuit block, which is configured to generate a plurality of oscillation signals and is configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of a functional circuit block. The voltage drop monitoring circuit also includes a counter and a drop detector, the counter being configured to generate a count value based on the selected oscillation signal, and the drop detector being configured to detect a drop in the power supply voltage of the functional circuit block based on the count value and at least one threshold.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2018-0110784 filed in the Korean Intellectual Property Office on September 17, 2018, Korean Patent Application No. 10-2019-0014363 filed in the Korean Intellectual Property Office on February 7, 2019, and U.S. Patent Application No. 16 / 519,621 filed on July 23, 2019, the disclosures of each of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor circuit, and more particularly, to a voltage drop monitoring circuit, a system on chip including the voltage drop monitoring circuit, and / or a method of operating the system on chip. Background Art

[0004] In semiconductor circuits, especially high-performance semiconductor circuits, the supply voltage may swing depending on the operating environment and the level of operations performed within the circuit. Typically, the voltage provided to support the worst case when the voltage drops significantly is set to a value greater than that required in a normal state. However, this conventional method increases the power consumption of the semiconductor circuit, thereby weakening the competitiveness of the product.

[0005] In order to overcome the above disadvantages, when the power supply voltage of the circuit begins to drop, the drop in the power supply voltage is detected. Based on the result of the detection, the operating speed or working level of the circuit is changed to allow normal operation to be performed even when the voltage drops. In order to achieve this goal, it is important to know the voltage state of the circuit quickly and accurately. The way of monitoring the voltage of the semiconductor circuit is classified into a digital way and an analog way. Summary of the invention

[0006] At least one embodiment is directed to a voltage sag monitoring circuit.

[0007] In one embodiment, the voltage drop monitoring circuit includes a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal. The first control signal is based on a power supply voltage of the functional circuit block. The voltage drop monitoring circuit also includes a counter and a drop detector, the counter being configured to generate a count value based on the selected oscillation signal, and the drop detector being configured to detect a drop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

[0008] In another embodiment, a voltage drop monitoring circuit includes: a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals; a counter configured to generate a count value based on the selected oscillation signal; and a drop detector configured to detect a drop in a power supply voltage of a functional circuit block based on the count value and at least a first threshold and a second threshold. The second threshold is greater than the first threshold. The drop detector is configured to detect a drop in the power supply voltage in response to the count value dropping below the first threshold; and the drop detector is configured to detect an end of the drop in the power supply voltage in response to the count value exceeding the second threshold.

[0009] In one embodiment, a voltage drop monitoring circuit includes: a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals; a counter configured to generate a count value based on the selected oscillation signal; and a drop detector configured to detect a drop in a power supply voltage of a functional circuit block based on the count value and at least a first threshold and a second threshold, such that a greater drop level is detected in response to the count value dropping below the first threshold than when the count value drops below the second threshold. The second threshold is greater than the first threshold.

[0010] At least one embodiment relates to a system on a chip.

[0011] In one embodiment, a system on chip includes: a voltage drop monitoring circuit configured to monitor a drop in a power supply voltage of a functional circuit block and generate an error signal based on the monitoring; a clock modulation circuit configured to modulate an input clock signal based on the error signal to generate an adaptive clock signal, and configured to output the adaptive clock signal to the functional circuit block.

[0012] At least one embodiment is directed to a method of monitoring a voltage drop.

[0013] In one embodiment, the method includes: selecting an oscillation signal from a plurality of oscillation signals based on a power supply voltage of a functional circuit block; generating a count value based on the selected oscillation signal; and detecting a drop in the power supply voltage of the functional circuit block based on the count value and at least one threshold value.

[0014] At least one embodiment is directed to another method.

[0015] In one embodiment, the method includes: generating an error signal based on monitoring a drop in a power supply voltage of a functional circuit block; modulating an input clock signal based on the error signal to generate an adaptive clock signal; and outputting the adaptive clock signal to the functional circuit block. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Example embodiments will be described in more detail below with reference to the accompanying drawings.

[0017] Figure 1 is a circuit block diagram illustrating a system on chip (SoC) according to some example embodiments.

[0018] Figure 2A is a diagram showing a method according to some example embodiments Figure 1 A circuit block diagram of an example of a voltage drop monitoring circuit in FIG.

[0019] Figure 2B is a diagram showing a method according to some example embodiments Figure 2A A circuit block diagram of an example of a controller in a voltage drop monitoring circuit.

[0020] Figure 3A An example relationship between temperature, the level of supply voltage provided to the ring oscillator, and the speed of the ring oscillator is shown.

[0021] Figure 3B is a diagram showing a method according to some example embodiments Figure 1 A circuit block diagram of an example of a clock modulation circuit in a SoC.

[0022] Figure 3C is a diagram showing a method according to some example embodiments Figure 1 FIG. 1 is another circuit block diagram of an example of a clock modulation circuit in a SoC.

[0023] Figure 4 is a diagram showing a method according to some example embodiments Figure 2A FIG. 1 is a circuit block diagram of an example of a ring oscillator circuit block in FIG.

[0024] Figure 5A is a diagram showing a method according to some example embodiments Figure 4 A circuit block diagram of an example of a first ring oscillator.

[0025] Figure 5B is a diagram showing a method according to some example embodiments Figure 4 A circuit block diagram of another example of the first ring oscillator in FIG.

[0026] Figure 6 Shows Figure 5A or Figure 5B One of the delay units in .

[0027] Fig. 7A is a diagram showing a method according to some example embodiments Figure 2A A circuit block diagram of an example of a drop detector in FIG.

[0028] Figure 7B is a diagram showing a method according to some example embodiments Figure 2A A circuit block diagram of another example of a falling detector in FIG.

[0029] Figure 8 According to some example embodiments Figure 2A Operation example of the voltage drop monitoring circuit.

[0030] Fig. 9 is a circuit block diagram illustrating another example of a SoC according to some example embodiments.

[0031] Fig.10 is a diagram showing a method according to some example embodiments Fig. 9 A circuit block diagram of an example of a functional circuit.

[0032] Fig.11 is a diagram showing a method according to some example embodiments Fig. 9 A circuit block diagram of another example of a functional circuit in FIG.

[0033] Fig.12 is a diagram showing a method according to some example embodiments Fig.11 A circuit block diagram of an example of a voltage drop monitoring circuit in FIG.

[0034] Fig.13 is a diagram showing a method according to some example embodiments Fig.12 A circuit block diagram of an example of a drop detector in FIG.

[0035] Fig.14 is a diagram showing a method according to some example embodiments Fig. 9 A circuit block diagram of another example of a functional circuit in FIG.

[0036] Fig.15 is a flow chart illustrating a method of operating a voltage sag monitoring circuit according to some example embodiments.

[0037] Fig.16 is a circuit block diagram illustrating a data processing system including a SoC according to some example embodiments.

[0038] Fig.17 is a flowchart illustrating a method of operating a SoC according to some example embodiments.

[0039] Fig.18 is a circuit block diagram illustrating a mobile system including a SoC according to some example embodiments. DETAILED DESCRIPTION

[0040] Various example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments are shown.

[0041] Figure 1 is a circuit block diagram illustrating a system on chip (SoC) according to example embodiments.

[0042] Figure 1 The SoC 10 may also be referred to as an adaptive clock system.

[0043] refer to Figure 1 , the SoC 10 includes a functional circuit 110 , a clock modulation circuit 120 , a clock generator 130 , and a voltage drop monitoring circuit 200 .

[0044] The functional circuit 110 may operate by receiving the power supply voltage VDD through the power line PL, and may perform a plurality of functions.

[0045] The voltage drop monitoring circuit 200 may receive the power supply voltage VDD through the power line PL, may monitor the level of the power supply voltage VDD, and may provide an error signal ERR to the clock modulation circuit 120 if the power supply voltage VDD drops. The error signal ERR may be a first error signal ERR1 including a single bit or a second error signal ERR2 including a plurality of bits.

[0046] The clock generator 130 may be implemented using a phase locked loop (PLL) and may generate at least one clock signal CLK based on the reference clock RCLK and provide the clock signal CLK to the clock modulation circuit 120. The clock generator 130 may provide a plurality of clock signals CLK to the clock modulation circuit 120.

[0047] The clock modulation circuit 120 may receive the error signal ERR and the clock signal CLK, may generate a corresponding adaptive clock signal ACLK by modulating the clock signal CLK, and provide the adaptive clock signal ACLK to the functional circuit 110 .

[0048] The clock modulation circuit 120 may adjust the frequency of the clock signal CLK by dividing the clock signal CLK or multiplexing the clock signal CLK in response to the error signal to output the adaptive clock signal ACLK. The clock modulation circuit 120 may include a plurality of frequency dividers and a multiplexer. Each frequency divider may divide the frequency of the clock signal CLK, and the multiplexer may output at least one of the outputs of the frequency divider as the adaptive clock signal ACLK. In an example embodiment, the clock modulation circuit 120 may include a plurality of multipliers, and the multiplier may multiply the clock signal CLK by a certain ratio (e.g., 90% or 80%). In this case, the multiplexer may output one of the outputs of the frequency divider or one of the outputs of the multiplier as the adaptive clock signal ACLK.

[0049] In an example embodiment, the functional circuit 110 may provide a status signal STS to the voltage drop monitoring circuit 200, the status signal STS indicating an operating state (e.g., temperature, operating voltage, change in operating voltage, etc.) and operating speed of the functional circuit 110. The functional circuit 110, or other circuits external or internal to the voltage drop monitoring circuit 200, may provide the reference voltage VREF. The reference voltage VREF may be generated according to any dynamic voltage frequency scaling (DVFS) technique (which may also affect the operating voltage level VDD scheme).

[0050] Figure 1 The SoC 10 may detect a drop in the power supply voltage VDD and may adjust the frequency of the clock signal CLK in the clock modulation circuit 120 so that the functional circuit 110 may operate at a lower voltage.

[0051] Figure 2A is a diagram showing a method according to some example embodiments Figure 1 A circuit block diagram of an example of a voltage drop monitoring circuit in FIG.

[0052] refer to Figure 2A , the voltage drop monitoring circuit 200 may include a controller 210, a ring oscillator circuit block 300, a counter 230, and a drop detector 250. The controller 210 may include a processing circuit (such as hardware including a logic circuit), a hardware / software combination (such as a processor that executes software), or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0053] The ring oscillator circuit block 300 may include a plurality of ring oscillators operating based on a power supply voltage VDD. The plurality of ring oscillators generate a plurality of oscillation signals. The ring oscillator circuit block 300 may select one of the plurality of oscillation signals to output the selected oscillation signal OSS.

[0054] The counter 230 may count the switching of the selected oscillation signal OSS during the reference interval to output a count signal (or count value) CV.

[0055] The drop detector 250 may compare the count value CV with at least one threshold value to output an error signal ERR indicating whether a drop in the power supply voltage VDD occurs. For example, if the count value CV drops below the threshold value, the drop detector 250 detects the drop. If a drop in the power supply voltage VDD occurs, the drop detector 250 may activate the error signal ERR with a first logic (high) level. If the drop in the power supply voltage VDD disappears, the drop detector 250 may deactivate the error signal ERR with a second logic (low) level. In an example embodiment, if a drop in the power supply voltage VDD occurs, the drop detector 250 may output an error signal ERR including a plurality of bits indicating the degree of drop in the power supply voltage VDD.

[0056] The controller 210 controls the ring oscillator circuit block 300, the counter 230, and the falling detector 250. The controller 210 may provide information about the reference interval to the counter 230, and may provide at least one threshold value to the falling detector 250. The controller 210 controls the ring oscillator circuit block 300 by providing a first control signal CTL1 to the ring oscillator circuit block 300, controls the counter 230 by providing a second control signal CTL2 to the counter 230, and controls the falling detector 250 by providing a third control signal CTL3 to the falling detector 250.

[0057] The controller 210 receives a power supply voltage VDD, a reference voltage VREF, and a state signal STS, and may generate first to third control signals CTL1, CTL2, and CTL3 based on the level of the power supply voltage VDD. In an example embodiment, the controller 210 may further generate first to third control signals CTL1, CTL2, and CTL3 based on the state signal STS.

[0058] Figure 2B is a diagram showing a method according to some example embodiments Figure 2A A circuit block diagram of an example of a controller in a voltage drop monitoring circuit.

[0059] refer to Figure 2B , the controller 210 may include a level detector 211 and a signal generator 213 .

[0060] The level detector 211 compares the level of the power voltage VDD with the reference voltage VREF and may output a detection signal DS having a first logic (high) level if the level of the power voltage VDD is lower than the reference voltage VREF.

[0061] The signal generator 213 may generate the first to third control signals CTL1, CTL2, and CTL3 based on the detection signal DS having the first logic level, and may further generate the first to third control signals CTL1, CTL2, and CTL3 based on the state signal STS. In an alternative embodiment, the controller 210 may include one or more registers, a lookup table, etc., which output the first to third control signals CTL1, CTL2, and CTL3 based on the power supply voltage VDD and the state signal STS. The generation of the control signals CTL1, CTL2, and CTL3 will be described in more detail below.

[0062] Figure 3A An example relationship between temperature, the level of supply voltage provided to the ring oscillator, and the speed of the ring oscillator is shown.

[0063] refer to Figure 3A In a relatively low voltage range, the example ring oscillator of the ring oscillator in the ring oscillator circuit block 300 operates faster at a higher temperature at a specific voltage, while in a relatively high voltage range, the ring oscillator operates faster at a lower temperature at a specific voltage. When the SoC 10 operates, since various temperature changes occur and the level of the power supply voltage VDD changes frequently according to the DVFS, the temperature and DVFS may be considered when the ring oscillator is used for voltage drop monitoring. The controller 210 may provide the ring oscillator circuit block 300 with information related to the temperature and DVFS in the voltage drop monitoring circuit 200. The controller 210 may include the information about the temperature and DVFS in the first control signal CTL1 and provide the first control signal CTL1 to the ring oscillator circuit block 300. In response to the first control signal CTL1, the ring oscillator circuit block 300 may output a selected oscillation signal OSS that is robust to changes in temperature.

[0064] Figure 3B is a diagram showing a method according to some example embodiments Figure 1 A circuit block diagram of an example of a clock modulation circuit in a SoC.

[0065] refer to Figure 3B The clock modulation circuit 120a may include a plurality of frequency dividers 121, 122, 123 and 124, a multiplexer 125a and a signal generator 126a.

[0066] The signal generator 126 a receives the first error signal ERR1 , generates a selection signal SS1 corresponding to the first error signal ERR1 , and provides the selection signal SS1 to the multiplexer 125 a .

[0067] Frequency dividers 121, 122, 123, and 124 receive a clock signal CLK, divide the clock signal CLK with different frequency division ratios, and generate divided clock signals DCLK1, DCLK2, DCLK3, and DCLK4 with different frequencies. The frequency of the divided clock signal DCLK1 may be the same as the frequency of the clock signal CLK, and each frequency of the divided clock signals DCLK2, DCLK3, and DCLK4 may be less than the frequency of the clock signal CLK. The frequencies of the divided clock signals DCLK3 and DCLK4 may be less than the frequency of the divided clock signal DCLK2, and the frequency of the divided clock signal DCLK4 may be less than the frequency of the divided clock signal DCLK3. The clock modulation circuit 120a may include any number of frequency dividers.

[0068] The multiplexer 125a selects one of the divided clock signals DCLK1, DCLK2, DCLK3, and DCLK4 in response to the selection signal SS1, and outputs the selected signal as the adaptive clock signal ACLK. In an exemplary embodiment, the lookup table in the signal generator 126a is programmed based on post-manufacturing testing so that: (1) if the input error signal ERR1 indicates a fall, the selection signal SS1 having a first selection value is output from the lookup table, and (2) if the input error signal ERR1 indicates the end of the fall, the selection signal SS1 having one or more second selection values ​​over time is output. By providing several selection options (e.g., dividers) during manufacturing, a desired divider option for a fall state and a desired divider option over time for a non-fall state can be set based on experimental research on the SoC 10 after manufacturing.

[0069] Figure 3C is a diagram showing a method according to some example embodiments Figure 1 FIG. 1 is another circuit block diagram of an example of a clock modulation circuit in a SoC.

[0070] refer to Figure 3C The clock modulation circuit 120b may include a plurality of frequency dividers 121, 122, 123 and 124, a plurality of multipliers 127, 128 and 129, a multiplexer 125b and a signal generator 126b.

[0071] In this embodiment, the signal generator 126b receives the second error signal ERR2 including a plurality of bits indicating a falling level, generates a selection signal SS2 corresponding to the second error signal ERR2, and provides the selection signal SS2 to the multiplexer 125b.

[0072] Frequency dividers 121, 122, 123 and 124 receive a clock signal CLK, divide the clock signal CLK at different frequency division ratios, and generate divided clock signals DCLK1, DCLK2, DCLK3 and DCLK4 with different frequencies, as shown in FIG. Figure 3B As described in the embodiment of the present invention. Multipliers 127, 128 and 129 multiply the clock signal CLK with different multiplication ratios to generate multiplied clock signals MCLK1, MCLK2 and MCLK3. For example, the frequency of the multiplied clock signal MCLK1 may correspond to 90% of the frequency of the clock signal CLK, the frequency of the multiplied clock signal MCLK2 may correspond to 80% of the frequency of the clock signal CLK, and the frequency of the multiplied clock signal MCLK3 may correspond to 70% of the frequency of the clock signal CLK. The clock modulation circuit 120b may include any number of frequency dividers and any number of multipliers.

[0073] The multiplexer 125b selects one of the divided clock signals DCLK1, DCLK2, DCLK3, and DCLK4 and the multiplied clock signals MCLK1, MCLK2, and MCLK3 in response to the selection signal SS2, and outputs the selected signal as the adaptive clock signal ACLK. In an exemplary embodiment, the lookup table in the signal generator 126a is programmed based on post-manufacturing testing so that: (1) the selection signal SS2 selects the divider / multiplier based on the droop level indicated by the error signal ERR2. By providing several selection options (e.g., divider or multiplier) during manufacturing, the desired option associated with the droop level can be set based on experimental studies of the SoC 10 after manufacturing.

[0074] Figure 4 is a diagram showing a method according to some example embodiments Figure 2A FIG. 1 is a circuit block diagram of an example of a ring oscillator circuit block in FIG.

[0075] refer to Figure 4 The ring oscillator circuit block 300 may include a first selection circuit 310 , a plurality of unit oscillator circuits UOC1 to UOCk (k is an integer greater than 2), and a second selection circuit 350 .

[0076] A plurality of unit oscillator circuits UOC1 to UOCk generate a plurality of oscillation signals OS1 to OSk based on a power supply voltage VDD, respectively. Each of the unit oscillator circuits UOC1 to UOCk may include a corresponding ring oscillator in a plurality of ring oscillators 320a to 320k and a corresponding logic gate in a plurality of logic gates 341 to 34k. Basically, each ring oscillator in the ring oscillator circuit block 300 may output an oscillation signal with a higher frequency as the voltage level increases. In addition, each ring oscillator may have different frequency characteristics according to the manufacturing process, the units included in each ring oscillator, and the temperature.

[0077] The ring oscillators 320a to 320k can generate intermediate oscillation signals IOS1 to IOSk, respectively, based on the power supply voltage VDD, and each of the logic gates 341 to 34k can perform a logic operation on a corresponding intermediate oscillation signal among the intermediate oscillation signals IOS1 to IOSk and an enable signal EN to generate a corresponding oscillation signal among the oscillation signals OS1 to OSk. For example, the logic gates 341 to 34k can be NAND gates that perform a "NAND" operation. The oscillation signal corresponding to the corresponding output of the logic gates 341 to 34k is fed back to the corresponding first delay unit DC1 of the corresponding ring oscillator among the ring oscillators 320a to 320k (see the following discussion). Figure 5A and Figure 5B ). The enable signal EN may be selectively provided from the first selection circuit 310 based on the chain selection signal CHSS.

[0078] The first selection circuit 310 may provide an enable signal EN to at least some of the logic gates 341 to 34 k in response to the chain selection signal CHSS.

[0079] The second selection circuit 350 may select one of the oscillation signals OS1 to OSk in response to the chain selection signal CHSS to output the selected oscillation signal OSS.

[0080] The chain selection signal CHSS may determine the number of unit oscillator circuits associated with generating the selected oscillation signal OSS.

[0081] In example embodiments, the controller 210 provides the enable signal EN and the chain selection signal CHSS as part of the first control signal CTL1 .

[0082] In an exemplary embodiment, the controller 210 generates the enable signal EN periodically and at fixed intervals. The period and interval are design parameters set through experimental studies. These setting values ​​can be programmed in the controller 210, etc.

[0083] In an example embodiment, the controller 210 includes a lookup table that outputs the chain selection signal CHSS based on one or more of the power supply voltage or voltage level (eg, from the status signal STS). The lookup table is a design parameter set through experimental studies.

[0084] In some example embodiments, the ring oscillators 320a to 320k may further generate intermediate oscillation signals IOS1 to IOSk based on the delay configuration control signal DCFG, which will be described below in conjunction with Figure 5B describe.

[0085] Figure 5A is a diagram showing a method according to some example embodiments Figure 4 A circuit block diagram of an example of a first ring oscillator.

[0086] exist Figure 5A , a first ring oscillator 320aa is shown, and each of the other ring oscillators 320b to 320k may have the same architecture as the first ring oscillator 320aa.

[0087] refer to Figure 5A The first ring oscillator 320aa includes first to m-th delay units DC1 to DCm (m is an integer greater than 3) connected in cascade. The first to m-th delay units DC1 to DCm operate based on the power supply voltage VDD.

[0088] The output of the mth delay unit is provided as the first intermediate oscillation signal IOS1, and the first oscillation signal OC1 corresponding to the output of the NAND gate 341 is fed back to the first delay unit DC1.

[0089] Figure 5B is a diagram showing a method according to some example embodiments Figure 4 A circuit block diagram of another example of the first ring oscillator in FIG.

[0090] exist Figure 5B , a first ring oscillator 320ab is shown, and each of the other ring oscillators 320b to 320k may have the same architecture as the first ring oscillator 320ab.

[0091] refer to Figure 5B The first ring oscillator 320ab includes first to mth delay units DC1 to DCm (m is an integer greater than 3) connected in cascade and a third selection circuit 323. The first to mth delay units DC1 to DCm operate based on the power supply voltage VDD.

[0092] The outputs of the second delay unit to the mth delay unit DC2 to DCm are provided to the third selection circuit 323, and the third selection circuit 323 can select one of the outputs of the second delay unit to the mth delay unit DC2 to DCm in response to the delay configuration control signal DCFG to output the first intermediate oscillation signal IOS1. Since the third selection circuit 323 can select one of the outputs of the second delay unit to the mth delay unit DC2 to DCm in response to the delay configuration control signal DCFG, the delay configuration control signal DCFG can determine the number of delay units associated with generating the intermediate oscillation signal IOS1. That is, the delay configuration control signal DCFG can adjust the delay amount of the first intermediate oscillation signal IOS1. In this way, the delay configuration control signal DCFG affects the inherent speed of the ring oscillator under the current operating conditions (e.g., voltage and temperature) and changes the sensitivity (oscillation speed) of detecting the decline. In an example embodiment, the controller 210 provides the delay configuration control signal DCFG as part of the first control signal CTL1. In an example embodiment, the controller 210 includes a lookup table that outputs the delay configuration control signal DCFG based on one or more of the power supply voltage or voltage level (eg, from the status signal STS). The lookup table is a design parameter set through experimental studies.

[0093] exist Figure 5A and Figure 5B In the embodiment, each of the first to mth delay units DC1 to DCm may include one of an inverter, a NAND gate, and a NOR gate, each of which operates based on a power supply voltage VDD.

[0094] Figure 6 Shows Figure 5A or Figure 5B One of the delay units in .

[0095] exist Figure 6 , a configuration of the first delay unit DC1 is shown, and each of the other delay units DC2 to DCm may have the same architecture as the first delay unit DC1.

[0096] refer to Figure 6 , the first delay unit DC1 includes a p-channel metal oxide semiconductor (PMOS) transistor PM1 and an n-channel metal oxide semiconductor (NMOS) transistor NM1 connected between a power supply voltage VDD and a ground voltage VSS.

[0097] The PMOS transistor PM1 has a source connected to the power supply voltage VDD, a gate connected to the first node N11, and a drain connected to the second node N12. The NMOS transistor NM1 has a drain connected to the second node N12, a source connected to the ground voltage VSS, and a gate connected to the first node N11. That is, the first delay unit DC1 can be implemented as an inverter.

[0098] The switching speed of the first delay unit DC1 implemented as an inverter is sensitive to the power supply voltage VDD. Therefore, the output of the ring oscillators 320a to 320k can reflect the change of the power supply voltage VDD. An increase in the count value CV obtained by counting the switching of the selected oscillation signal OSS during the reference interval can indicate an increase in the level of the power supply voltage VDD, and a decrease in the count value CV can indicate a decrease in the level of the power supply voltage VDD.

[0099] Back to Figure 2A , the controller 210 provides an enable signal EN and a reset signal as the second control signal CTL2 to the counter 230. The controller 210 sets the reset signal to reset the counter 230 at the beginning of the enable period. The counter 230 counts the selected oscillation signal pulses during the enable period to generate a count value CV. It can be understood that the enable signal EN provided to the counter 230 can be delayed compared to the enable signal EN provided to the ring oscillator circuit block 300 to take into account the delay in the ring oscillator circuit block 300.

[0100] In an alternative embodiment, if the level of the power supply voltage VDD is lower than the reference voltage VREF, the signal generator 213 may activate the enable signal included in the first control signal CTL1 and provide the activated enable signal to the ring oscillator circuit block 300 and the counter 230. This reduces power consumption.

[0101] Fig. 7A is a diagram showing a method according to some example embodiments Figure 2A A circuit block diagram of an example of a drop detector in FIG.

[0102] refer to Fig. 7A , the falling detector 250 a may include a register 251 and a comparator 253 .

[0103] The register 251 stores a first threshold value LTH and a second threshold value UNTH, and provides the first threshold value LTH and the second threshold value UNTH to the comparator 253 . Figure 2AThe controller 210 in the embodiment may provide the first threshold LTH and the second threshold UNTH as part of the third control signal CTL3 to the falling detector 250, and the controller 210 may adjust the levels of the first threshold LTH and the second threshold UNTH according to the DVFS (e.g., the change of the reference voltage VREF) and the change of the power supply voltage VDD. In an example embodiment, the controller 210 includes a lookup table that outputs these thresholds based on the reference voltage VREF and / or the power supply voltage VDD. The lookup table is a design parameter set by experimental research. In addition, the reference voltage VREF changes due to various voltage changes according to the DVFS, and the count value CV of the ring oscillator also changes. Therefore, the DVFS can be considered.

[0104] The comparator 253 compares the count value CV with the first threshold value LTH and the second threshold value UNTH to output a first error signal ERR1 .

[0105] Figure 7B is a diagram showing a method according to some example embodiments Figure 2A A circuit block diagram of another example of a falling detector in FIG.

[0106] refer to Figure 7B , the falling detector 250 b may include a register 252 and a comparator 254 .

[0107] The register 252 stores a plurality of threshold values ​​RTH1 to RTHt (t is an integer greater than 2), and provides the threshold values ​​RTH1 to RTHt to the comparator 254 . Figure 2A The controller 210 in the embodiment can provide the threshold values ​​RTH1 to RTHt as part of the third control signal CTL3 to the falling detector 250, and the controller 210 can adjust the levels of the threshold values ​​RTH1 to RTHt according to the changes of the DVFS (e.g., the reference voltage VREF) and the power supply voltage VDD. In an example embodiment, the controller 210 includes a lookup table that outputs these threshold values ​​based on the reference voltage VREF and / or the power supply voltage VDD. The lookup table is a design parameter set by experimental research. In addition, the reference voltage VREF changes due to various voltage changes according to the DVFS, and the count value CV of the ring oscillator also changes. Therefore, the DVFS can be taken into account.

[0108] The comparator 254 compares the count value CV with the threshold values ​​RTH1 to RTHt to output a second error signal ERR2. The comparator 254 outputs the second error signal ERR2 including a plurality of bits indicating the difference between the count value CV and at least one of the threshold values ​​RTH1 to RTHt. That is, the second error signal ERR2 may indicate the degree of decrease of the power supply voltage VDD. Figure 3CThe signal generator 126b in the clock modulation circuit 120b generates the selection signal SS2 in response to the second error signal ERR2, so that the clock modulation circuit 120b can output the adaptive clock signal ACLK whose frequency depends on the degree of the drop (voltage drop).

[0109] Figure 8 According to some example embodiments Figure 2A Operation example of the voltage drop monitoring circuit.

[0110] exist Figure 8 In FIG. 2 , VREF represents a reference voltage provided to the controller 210 , LTH represents a first threshold, UNTH represents a second threshold, and RO count value represents a count value of the counter 230 .

[0111] refer to Figures 2A to 8 , the falling detector 250 may transition the first error signal ERR1 to a first logic level in response to the count value CV corresponding to the power supply voltage VDD being lower than the first threshold value LTH.

[0112] If the count value CV increases after the power supply voltage VDD drops and the count value CV rises above the second threshold value UNTH, the drop detector 250 may transition the first error signal ERR1 from the first logic level to the second logic level in response to the corresponding count value.

[0113] exist Figure 8 , the first error signal ERR1 indicates that a drop in the power supply voltage VDD occurs between the first timing point T1 and the second timing point T2, and indicates that a drop in the power supply voltage VDD occurs between the third timing point T3 and the fourth timing point T4.

[0114] If the power supply voltage VDD drops, the frequency of the clock signal CLK needs to be adjusted quickly, and the clock signal CLK is divided or multiplexed in the clock modulation circuit 120 to provide an adaptive clock signal ACLK from the clock modulation circuit 120 instead of adjusting the frequency of the clock signal CLK in the clock generator 130.

[0115] If the frequency of the clock signal CLK is reduced at the falling error point where the falling occurs, and then the frequency of the clock signal CLK is restored to its original frequency when the falling error disappears, there is a possibility that another falling occurs in the power supply voltage VDD due to the faster operation of the circuit. In order to prevent another immediate falling, the falling error is released at a level equal to or higher than the level when the falling error occurs. This prevents swinging back and forth between the falling state and the non-falling state of operation.

[0116] In addition, the frequency of the clock signal CLK can be gradually increased. For example, the frequency of the clock signal CLK can be gradually increased to its original frequency in a circuit that operates very fast, and the frequency of the clock signal CLK can be increased to its original frequency more quickly in a circuit that operates slowly.

[0117] For example, in one embodiment, Figure 3B The signal generator 126a is configured such that: if the error signal ERR1 indicates a fall, the signal generator 126a generates a selection signal SS1 to select a divider (or a multiplexer, etc.) that divides the clock signal (e.g., divides the clock signal CLK in half) to generate an adaptive clock signal ACLK, wherein the ratio ACLK / CLK of the two clocks is a first ratio (e.g., 1 / 2). And, the signal generator 126a is configured to, in response to the error signal ERR1 indicating no fall, periodically change the selection signal SS1 so that a different divider is selected, and the ratio ACLK / CLK of the two clocks increases successively (e.g., 2 / 3, 3 / 4, 4 / 5, 1) until the adaptive clock signal ACLK returns to a pre-fall or non-fall state (e.g., equal to the clock signal CLK (e.g., divided by 1)). Although not in Figure 3B , but the clock signal CLK may also be directly provided as an input to the multiplexer 125a. In one embodiment, the voltage drop monitoring circuit 200 may employ a calibration operation that automatically calculates a count value CV of the ring oscillator corresponding to a changed level of the power supply voltage VDD that changes according to the DVFS.

[0118] Therefore, the voltage drop monitoring circuit 200 and the SoC 10 including the voltage drop monitoring circuit 200 can count the oscillation signal that changes in response to the power supply voltage VDD provided to the functional circuit 110, detect the drop of the power supply voltage VDD, and can reduce the operating voltage by reducing the frequency of the clock signal provided to the functional circuit 110. Therefore, the voltage drop monitoring circuit 200 can reduce the power consumption of the SoC 10.

[0119] In addition, if the voltage drop monitoring circuit 200 adopts Figure 7B If the falling detector 250b is configured, the SoC 10 may adaptively adjust the frequency of the clock signal CLK in response to the second error signal ERR2 indicating the falling degree.

[0120] In this embodiment, and with reference to Figure 3C, the signal generator 126b is configured to generate a selection signal SS2 based on the drop level indicated by the error signal ERR2. For example, if the error signal ERR2 indicates that there is no drop, the signal generator 126b generates the selection signal SS2 so that the multiplexer 125b selects a frequency divider that divides the clock signal CLK by 1, or a multiplier that multiplies the clock signal by 1. Alternatively, if there is no drop, the clock signal CLK can be directly provided to the multiplexer 125b and selected. If the error signal ERR2 indicates a drop, the error signal ERR2 also indicates a drop level. For example, the thresholds RTH1 to RTHt are decreasing values ​​that define the drop level. The count value CV falling between RTH1 and RTH2 indicates a first drop level, the count value CV falling between RTH2 and RTH3 indicates a second drop level greater than the first drop level, and so on. The signal generator 126b generates the selection signal SS2 so that the multiplexer 125b selects a frequency divider or multiplier corresponding to the drop level. For example, for the first falling level, the clock signal CLK may be reduced by 4 / 5; for the second falling level, the clock signal CLK may be reduced by 3 / 4; for the third falling level, the clock signal CLK may be reduced by 2 / 3; and so on, to generate the adaptive clock signal ACLK. In this way, the clock modulation circuit 120 is configured to change the frequency of the adaptive clock signal ACLK based on the falling level. More specifically, the clock modulation circuit 120 is configured to reduce the frequency of the adaptive clock signal ACLK as the falling level increases, and is configured to increase the frequency of the adaptive clock signal ACLK as the falling level decreases.

[0121] and Fig. 7A As in the embodiment of the present invention, each of the plurality of first thresholds RTH1 to RTHt may have a corresponding one of the plurality of second thresholds URTH1 to URTHt, wherein each of the plurality of second thresholds is greater than the corresponding first threshold. Here, as described above, the values ​​of the plurality of first thresholds RTH1 to RTHt decrease and are associated with different drop levels of the power supply voltage. Here, the transition from a larger drop level to a lower drop level requires the count value CV to fall above the corresponding second threshold. This prevents swinging back and forth between different drop levels. In one embodiment, while the second threshold is greater than the corresponding first threshold, the second threshold is less than the next first threshold indicating a lower drop level.

[0122] Thus, the drop detector 250 is configured to detect a drop in response to the count value CV dropping below a first threshold among a plurality of first thresholds, is configured to detect a drop level based on a lowest first threshold among a plurality of first thresholds below which the count value drops, and is configured to detect a reduced drop level in response to the count value rising above a second threshold associated with the lowest first threshold among a plurality of first thresholds below which the count value drops.

[0123] Fig. 9 is a circuit block diagram illustrating another example of a SoC according to example embodiments.

[0124] refer to Fig. 9 , the SoC 20 includes a functional circuit 400 , a clock modulation circuit 120 c , a clock generator 130 a , and a voltage drop monitoring circuit (VDMC) 500 .

[0125] The voltage drop monitoring circuit 500 may be disposed in the functional circuit 400 .

[0126] The functional circuit 400 may operate by receiving the power supply voltage VDD through the power line PL, and may perform a plurality of functions.

[0127] The voltage drop monitoring circuit 500 may receive the power supply voltage VDD through the power line PL, may monitor the level of the power supply voltage VDD, and may provide an error signal ERR to the clock modulation circuit 120 c if the power supply voltage VDD drops.

[0128] The clock generator 130 a may be implemented using a phase-locked loop (PLL), may generate at least one clock signal CLK based on a reference clock RCLK, and may provide the clock signal CLK to the clock modulation circuit 120 c.

[0129] The clock modulation circuit 120c may receive the error signal ERR and the clock signal CLK, may generate a corresponding adaptive clock signal ACLK by modulating the clock signal CLK, and may provide the adaptive clock signal ACLK to the functional circuit 400. The clock modulation circuit 120c may be the same as the clock modulation circuit 120a or 120b, and the error signal ERR may include a single bit or multiple bits (as described above with respect to Figures 1 to 8 ).

[0130] Functional circuit 400 may include a plurality of functional circuit blocks that operate based on adaptive clock signal ACLK.

[0131] Fig.10 is a diagram showing a method according to some example embodiments Fig. 9 A circuit block diagram of an example of a functional circuit.

[0132] refer to Fig.10 , the functional circuit 400 a may include a plurality of functional circuit blocks 410 , 420 , 430 , 440 , and 450 and a voltage drop monitoring circuit 500 a mounted on a circuit board 401 .

[0133] The functional circuit blocks 410 , 420 , 430 , 440 , and 450 respectively perform corresponding functions by receiving the power supply voltage VDD, and may adjust operation speeds based on the frequency of the adaptive clock signal ACLK.

[0134] The voltage drop monitoring circuit 500a can receive the power supply voltage VDD through the power line PL, can monitor the level of the power supply voltage VDD, can generate an error signal ERR indicating whether the power supply voltage VDD drops, and can provide the error signal ERR to the Fig. 9 The clock modulation circuit 120c in the voltage drop monitoring circuit 500a can be used Figure 2A The voltage drop monitoring circuit 200 is provided.

[0135] Fig.11 is a diagram showing a method according to some example embodiments Fig. 9 A circuit block diagram of another example of a functional circuit in FIG.

[0136] refer to Fig.11 , the functional circuit 400b may include a plurality of functional circuit blocks 410, 420, 430, 440 and 450 mounted on a circuit board 401, a plurality of ring oscillator circuit blocks (ROBs) 415, 425, 435 and 445, and a voltage drop monitoring circuit 500b.

[0137] The functional circuit blocks 410 , 420 , 430 , 440 , and 450 respectively perform corresponding functions by receiving the power supply voltage VDD, and may adjust operation speeds based on the frequency of the adaptive clock signal ACLK.

[0138] The ring oscillator circuit blocks 415, 425, 435 and 445 are distributed and arranged on the circuit board 401. The ring oscillator circuit blocks 415, 425, 435 and 445 generate the selected oscillation signals OSS11, OSS12, OSS13 and OSS14 and provide the selected oscillation signals OSS11, OSS12, OSS13 and OSS14 to the voltage drop monitoring circuit 500b.

[0139] Ring oscillator circuit block 415 may be adjacent to functional circuit block 410, ring oscillator circuit block 425 may be adjacent to functional circuit block 430, ring oscillator circuit block 435 may be adjacent to functional circuit block 440, and ring oscillator circuit block 445 may be adjacent to functional circuit block 450. Each of ring oscillator circuit blocks 415, 425, 435, and 445 may provide a corresponding selected oscillation signal OSS11, OSS12, OSS13, and OSS14 to voltage drop monitoring circuit 500b. Each of the selected oscillation signals OSS11, OSS12, OSS13, and OSS14 may reflect a voltage change of a power supply voltage VDD provided to a corresponding one of the adjacent functional circuit blocks.

[0140] The voltage drop monitoring circuit 500b receives the selected oscillation signals OSS11, OSS12, OSS13 and OSS14 and sends a voltage drop monitoring circuit to the selected oscillation signal OSS11, OSS12, OSS13 and OSS14 if a drop is detected in at least one of the selected oscillation signals OSS11, OSS12, OSS13 and OSS14. Fig. 9 The clock modulation circuit 120c in the embodiment provides an error signal ERR. As described in the previous embodiment, the error signal ERR may include a single bit or a plurality of bits as described above. The voltage drop monitoring circuit 500b may generate a count value by counting the switching of the selected oscillation signals OSS11, OSS12, OSS13, and OSS14, may compare the count value with at least one threshold value, and if at least one count value is equal to or less than at least one threshold value, may output an error signal ERR having a first logic level indicating the occurrence of a drop. In an example embodiment, the voltage drop monitoring circuit 500b may compare the count value with a plurality of threshold values, and may output an error signal ERR including a plurality of bits for indicating a drop level as described in the previous embodiment.

[0141] Fig.12 is a diagram showing a method according to some example embodiments Fig.11 A circuit block diagram of an example of a voltage drop monitoring circuit in FIG.

[0142] refer to Fig.12 , the voltage drop monitoring circuit 500b includes a controller 510, a counter 530, and a drop detector 550. The controller 510 may include a processing circuit (such as hardware including a logic circuit), a hardware / software combination (such as a processor that executes software), or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0143] The counter 530 may count switching of each of the selected oscillation signals OSS11 , OSS12 , OSS13 , and OSS14 to output a plurality of count values ​​CV11 , CV12 , CV13 , and CV14 .

[0144] The drop detector 550 may compare each of the count values ​​CV11, CV12, CV13, and CV14 with at least one threshold value to generate an error signal ERR indicating whether a drop in the power supply voltage VDD occurs based on the comparison result. If at least one of the count values ​​CV11, CV12, CV13, and CV14 decreases to less than a first threshold value, the drop detector 550 may output an error signal ERR having a first logic level, and if the drop is released or disappears (e.g., exceeds a second threshold value greater than the first threshold value), the error signal ERR may be changed from the first logic level to have a second logic level. If at least one of the count values ​​CV11, CV12, CV13, and CV14 is between the first threshold value and the second threshold value, the drop detector 550 may output an error signal ERR including a plurality of bits indicating a difference between at least one of the count values ​​CV11, CV12, CV13, and CV14 and the threshold value.

[0145] The controller 510 controls the ring oscillator circuit blocks 415, 425, 435, and 445, the counter 530, and the falling detector 550. The controller 510 may provide information about the reference interval to the counter 530, and may provide at least one threshold value to the falling detector 550. The controller 510 controls the ring oscillator circuit blocks 415, 425, 435, and 445 by providing a first control signal CTL41 to the ring oscillator circuit blocks 415, 425, 435, and 445, controls the counter 530 by providing a second control signal CTL42 to the counter 530, and controls the falling detector 550 by providing a third control signal CTL43 to the falling detector 550. The second control signal CTL42 may include information about the reference interval, and the third control signal CTL43 may include at least one threshold value.

[0146] The controller 510 receives the power supply voltage VDD, the reference voltage VREF, and the state signal STS, and may generate first to third control signals CTL41, CTL42, and CTL43 based on the level of the power supply voltage VDD. In an example embodiment, the controller 510 may compare the power supply voltage VDD and the reference voltage VREF, and if the power supply voltage VDD is lower than the reference voltage VREF, the ring oscillator circuit blocks 415, 425, 435, and 445 may be operated by using the first control signal CTL41.

[0147] The controller 510 may include Figure 2B The level detector and signal generator.

[0148] Fig.13 is a diagram showing a method according to some example embodiments Fig.12 A circuit block diagram of an example of a drop detector in FIG.

[0149] refer to Fig.13 , the falling detector 550 may include a register 559, a plurality of comparators 551, 552, 553 and 554, an OR gate 555, a decoder 556, an inverter 557 and a multiplexer 558.

[0150] The register 559 stores a first threshold value LTH and a second threshold value UNTH, and provides the first threshold value LTH and the second threshold value UNTH to each of the comparators 551 , 552 , 553 , and 554 . Fig.12 The controller 510 in the embodiment may provide a first threshold value LTH and a second threshold value UNTH, and may adjust the levels of the first threshold value LTH and the second threshold value UNTH according to changes in the DVFS and the power supply voltage VDD.

[0151] The first comparator 551 compares the first count value CV11 with the first threshold value LTH and the second threshold value UNTH to output a first comparison signal CS11. The second comparator 552 compares the second count value CV12 with the first threshold value LTH and the second threshold value UNTH to output a second comparison signal CS12. The third comparator 553 compares the third count value CV13 with the first threshold value LTH and the second threshold value UNTH to output a third comparison signal CS13. The fourth comparator 554 compares the fourth count value CV14 with the first threshold value LTH and the second threshold value UNTH to output a fourth comparison signal CS14.

[0152] The OR gate 555 performs an OR operation on the first to fourth comparison signals CS11 , CS12 , CS13 , and CS14 to output the sub error signal SERR.

[0153] The decoder 556 decodes the first to fourth comparison signals CS11 , CS12 , CS13 , and CS14 to output a selection signal SS3 .

[0154] The multiplexer 558 may select one of the sub error signal SERR and an output of the inverter 557 that inverts the sub error signal SERR in response to the selection signal SS3 to output the selected signal as the error signal ERR.

[0155] Therefore, if at least one of the first to fourth comparison signals CS11, CS12, CS13, and CS14 has a high level, that is, a falling condition is detected in at least one of the first to fourth count values ​​CS11, CS12, CS13, and CS14, the multiplexer 558 outputs an error signal ERR having a high level. In addition, if each of the first to fourth comparison signals CS11, CS12, CS13, and CS14 has a low level, that is, a falling condition is not detected in each of the first to fourth count values ​​CS11, CS12, CS13, and CS14, the multiplexer 558 outputs an error signal ERR having a low level.

[0156] For example, if the first comparison signal CS11 is high and each of the second to fourth comparison signals CS12, CS13, and CS14 has a low level, the first comparison signal CS11 may indicate that a drop (condition) in the power supply voltage VDD occurs due to the first functional circuit block 410. The OR gate 555 outputs the sub-error signal SERR having a high level in response to the first comparison signal CS11 having a high level, and the decoder 556 outputs the selection signal SS3 having a low level. Therefore, the multiplexer 558 outputs the error signal ERR having a high level.

[0157] If the clock modulation circuit 120a reduces the frequency of the adaptive clock signal ACLK in response to the error signal ERR and releases the drop (condition) caused by the first functional circuit block 410, each of the first to fourth comparison signals CS11, CS12, CS13 and CS14 has a low level.

[0158] The OR gate 555 outputs the sub error signal SERR having a low level, and the decoder 556 outputs the selection signal SS3 having a low level. Therefore, the multiplexer 558 outputs the error signal ERR having a low level.

[0159] Fig.14 is a diagram showing a method according to some example embodiments Fig. 9 A circuit block diagram of another example of a functional circuit in FIG.

[0160] refer to Fig.14 The functional circuit 400c may include a plurality of functional circuit blocks 410, 420, 430, 440 and 450 mounted on a circuit board 401, a plurality of ring oscillators (RO) 416, 426, 436 and 446 and a voltage drop monitoring circuit 500c.

[0161] The functional circuit blocks 410 , 420 , 430 , 440 , and 450 respectively perform corresponding functions by receiving the power supply voltage VDD, and may adjust operation speeds based on the frequency of the adaptive clock signal ACLK.

[0162] The ring oscillators 416, 426, 436 and 446 are distributed and disposed on the circuit board 401. The ring oscillators 416, 426, 436 and 446 generate oscillation signals OS21, OS22, OS23 and OS24 and provide the oscillation signals OS21, OS22, OS23 and OS24 to the voltage drop monitoring circuit 500c.

[0163] The ring oscillator 416 may be disposed adjacent to the functional circuit block 410, the ring oscillator 426 may be disposed adjacent to the functional circuit block 430, the ring oscillator 436 may be disposed adjacent to the functional circuit block 440, and the ring oscillator 446 may be disposed adjacent to the functional circuit block 450. Each of the ring oscillators 416, 426, 436, and 446 may provide a corresponding oscillation signal of the oscillation signals OS21, OS22, OS23, and OS24 to the voltage drop monitoring circuit 500c. Each of the oscillation signals OS21, OS22, OS23, and OS24 may reflect a voltage change of the power supply voltage VDD provided to the corresponding functional circuit block of the adjacent functional circuit blocks.

[0164] The voltage drop monitoring circuit 500c receives the oscillation signals OS21, OS22, OS23, OS24 and sends a voltage drop monitoring circuit to the oscillation signal monitoring circuit 500c if a drop is detected in at least one of the oscillation signals OS21, OS22, OS23, OS24. Fig. 9 The clock modulation circuit 120c in the circuit 500c provides an error signal ERR. The error signal ERR may include a single bit or a plurality of bits as described above. The voltage drop monitoring circuit 500c may generate a count value by counting the switching of the oscillation signals OS21, OS22, OS23, OS24, may compare the count value with at least one threshold value, and if at least one of the count values ​​is equal to or less than at least one threshold value, an error signal ERR having a first logic level indicating the occurrence of a drop may be output. In an example embodiment, the voltage drop monitoring circuit 500c may compare the count value with a plurality of threshold values, and may output an error signal ERR including a plurality of bits indicating the difference between at least one of the count values ​​and the threshold value.

[0165] The voltage drop monitoring circuit 500c may have Fig.12 The voltage drop monitoring circuit 500b is similarly configured.

[0166] Fig.15is a flow chart illustrating a method of operating a voltage sag monitoring circuit according to an example embodiment.

[0167] refer to Figures 2A to 15 , a power management integrated circuit (PMIC) that provides a power supply voltage VDD sets a level of the power supply voltage VDD provided to the delay unit of each ring oscillator (S110).

[0168] The counter 230 in the voltage drop monitoring circuit 200 calculates (calibrates) the count value CV output from each ring oscillator at the set level of the power supply voltage VDD ( S120 ).

[0169] The controller 210 in the voltage drop monitoring circuit 200 calculates a first threshold value LTH and a second threshold value UNTH based on the count value CV ( S130 ).

[0170] The voltage drop monitoring circuit 200 measures the level of the power supply voltage VDD (S140). The voltage drop monitoring circuit 200 counts the selected oscillation signal from the ring oscillator circuit block 300 at the measured level of the power supply voltage VDD to detect whether a drop in the power supply voltage VDD occurs (S150). If a drop is detected, the voltage drop monitoring circuit 200 outputs an error signal ERR having a first logic level.

[0171] Fig.16 is a circuit block diagram illustrating a data processing system including a SoC according to example embodiments.

[0172] refer to Fig.16 , the data processing system 600 may include an application processor 700 , a memory device 850 , and a PMIC 800 .

[0173] Fig.16 The data processing system 600 shown in FIG. 6 may be implemented on various computing systems. According to an embodiment, the data processing system 600 may be a mobile system including the application processor 700 .

[0174] The data processing system 600 may include various types of memory devices 850. In various embodiments, the memory device 850 may be various types of semiconductor devices. According to an embodiment, the memory device 850 may be a dynamic random access memory (DRAM), such as a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate (LPDDR) SDRAM, a graphic double data rate (GDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), etc.

[0175] The application processor 700 can be implemented using a SoC according to an example embodiment. The SoC may include a system bus (not shown) that operates according to a protocol based on a predetermined standard bus specification and various intellectual property cores connected to the system bus. The standard specification of the system bus may be an advanced microcontroller bus architecture (AMBA) protocol of an advanced RISC machine (ARM). The bus types of the AMBA protocol include an advanced high-performance bus (AHB), an advanced peripheral bus (APB), an advanced extensible interface (AXI), AXI4, an AXI consistency extension (ACE), etc. In addition, other types of protocols may be used, such as SONICs' uNetwork, IBM's CoreConnect, and an open core protocol of OCP-IP, etc.

[0176] The application processor 700 may include a central processing unit (CPU) 710 , a clock modulation circuit (CMU) 720 , a clock generator 730 , a voltage droop monitoring circuit 740 , a DVFS controller 750 , and a memory control interface (MCI) 760 .

[0177] The CPU 710 may control functional circuit blocks in the application processor 710. The CPU 710 may provide a data access request to the memory device 850 via the memory control interface 760.

[0178] The memory control interface 760 may output a command to the memory device 850 according to a request from the CPU 710. The memory control interface 760 may write data to the memory device 850 or read data from the memory device 850 based on an operation of the application processor 700. The memory control interface 760 may interface with the memory device 850 and may provide various commands to the memory device 850.

[0179] The PMIC 800 may provide a first power supply voltage VDD1 and a second power supply voltage VDD2 to the application processor 700, and may provide a third power supply voltage VDD3 to the memory device 850. The PMIC 800 may provide a first power supply voltage VDD1 to the CPU 710, and may provide a second power supply voltage VDD2 to the clock modulation circuit 720, the clock generator 730, and the DVFS controller 750.

[0180] The PMIC 800 may adjust the first power voltage to a level of at least one of the third power voltages VDD1 , VDD2 , and VDD3 based on the voltage control signal VCTL from the DVFS controller 750 .

[0181] The clock generator 730 may generate a clock signal CLK to provide the clock signal CLK to the clock modulation circuit 720 .

[0182] The clock modulation circuit 720 may generate a first adaptive clock signal ACLK1 and a second adaptive clock signal ACLK2 based on the clock signal CLK, may provide the first adaptive clock signal ACLK1 to the CPU 710 , and may provide the second adaptive clock signal ACLK2 to the memory control interface 760 .

[0183] The voltage drop monitoring circuit 740 monitors the level of the first power supply voltage VDD1 provided to the CPU 710, and provides an error signal ERR to the clock modulation circuit 720 and the DVFS controller 750 if the first power supply voltage VDD1 drops. The voltage drop monitoring circuit 740 may be implemented as Figure 2A The voltage drop monitoring circuit 200 may include a controller, a ring oscillator circuit block, a counter, and a drop detector.

[0184] The DVFS controller 750 provides the PMIC 800 with a voltage control signal VCTL based on the error signal ERR, and the PMIC 800 may adjust the level of the first power supply voltage VDD1 based on the voltage control signal VCTL.

[0185] The DVFS controller 750 may receive a status signal STS21 from the CPU 710, and may receive a status signal STS22 from the memory control interface 760. The status signal STS21 may indicate an operating speed of the CPU 710, and the status signal STS22 may indicate an operating speed of the memory device 850. The DVFS controller 750 may determine or estimate the operating speeds of the CPU 710 and the memory device 850 based on the status signals STS21 and STS22. The DVFS controller 750 may provide a voltage control signal VCTL indicating the determined operating speed to the PMIC 800. The PMIC 800 may adjust the levels of the first power supply voltage VDD1 and the third power supply voltage VDD3 based on the voltage control signal VCTL.

[0186] The application processor 700 may provide the memory voltage control signal VCTLM to the memory device 850. In example embodiments, the DVFS controller 750 may generate the memory voltage control signal VCTLM and may provide the memory voltage control signal VCTLM to the memory device 850 through the memory control interface 760.

[0187] The DVFS controller 750 may receive a state signal STS22 indicating an operating state of the memory device 850 from the memory control interface 760, and may generate a memory voltage control signal VCTLM to adjust a level of an operating voltage of the memory device 850 based on the memory voltage control signal VCTLM. The memory control interface 760 may check a workload on the memory device 850, and may determine whether to perform a high-speed memory operation or a low-speed memory operation according to the degree of the checked workload.

[0188] The memory device 850 may adjust the level of the third power voltage VDD3 in response to the memory voltage control signal VCTLM, and may generate an operating voltage of the adjusted level as an internal voltage.

[0189] According to an embodiment, the memory device 850 may pre-adjust the level of the operating voltage before the operating speed is changed (or before the frequency of the second adaptive clock signal ACLK2 is changed).

[0190] In addition, the memory device 850 can set the adjustment time point of the level of the operating voltage in response to the change of the operating speed in various ways. For example, in the case where the memory voltage control signal VCTLM is a signal requesting an increase in the level of the operating voltage, the memory device 850 can increase the level of the operating voltage before the operating speed is actually increased, so that high-speed memory operations can be stably performed. In addition, in the case where the memory voltage control signal VCTLM is a signal requesting a decrease in the level of the operating voltage, the memory device 850 can decrease the level of the operating voltage at a time point when the operating speed is decreased (or at a time point when a clock signal with a low frequency is received) without decreasing the level of the operating voltage in advance, thereby stably performing high-speed memory operations.

[0191] exist Fig.16 In the embodiment, each of application processor 700 and PMIC 800 may be a SoC respectively, or application processor 700 and PMIC 800 may constitute a SoC. In addition, each of CPU 710, clock modulation circuit 720, clock generator 730, DVFS controller 750, and memory control interface 760 may correspond to a functional circuit.

[0192] Fig.17 is a flowchart illustrating a method of operating a SoC according to example embodiments.

[0193] refer to Figures 1 to 17, a method of operating a SoC 10 is provided, the SoC 10 includes a functional circuit 110 operating based on a power supply voltage VDD and a voltage drop monitoring circuit 200 including a plurality of ring oscillators and monitoring the power supply voltage VDD. In the method, a plurality of ring oscillators 320a to 320k generate a plurality of oscillation signals OS1 to OSk that are robust to temperature changes based on the power supply voltage VDD (S210).

[0194] One of the oscillation signals OS1 to OSk is selected and provided as a selected oscillation signal OSS ( S220 ).

[0195] The counter 230 in the voltage drop monitoring circuit 200 generates a count value CV by counting the switching of the selected oscillation signal OSS ( S230 ).

[0196] The voltage drop detector 250 in the voltage drop monitoring circuit 200 generates an error signal ERR by comparing the count value CV with at least one threshold value ( S240 ).

[0197] The clock modulation circuit 120 in the SoC 10 adjusts the frequency of the clock signal CLK based on the error signal ERR to provide an adaptive clock signal ACLK to the functional circuit 110 (S250). If the error signal ERR indicates that the power supply voltage VDD has dropped, the clock modulation circuit 120 may reduce the frequency of the clock signal CLK to generate an adaptive clock signal ACLK, and may provide the adaptive clock signal ACLK to the functional circuit 110.

[0198] Fig.18 is a circuit block diagram illustrating a mobile system including a SoC according to example embodiments.

[0199] refer to Fig.18 , the mobile system 2000 may include an adaptive clock system 2020 , a processor (AP / ModAP) 2100 , a buffer memory 2200 , a display / touch module 2300 , and a storage device 2400 .

[0200] Adaptive Clock System 2020 is available Figure 1 The adaptive clock system 2020 may detect a voltage drop of at least one power line, may generate an adaptive clock signal based on the detected result, and may provide the adaptive clock signal to the processor 2100.

[0201] Although not shown, the mobile system 2000 may also include a security chip. The security chip may be implemented to provide security functions. The security chip may include software and / or tamper-proof hardware, allowing a high level of security, and working in conjunction with the trusted execution environment (TEE) of the processor 2100.

[0202] The security chip may include a native operating system (OS), a secure storage device as an internal data storage, an access control circuit block for controlling access rights to the security chip, a security function circuit block for performing ownership management, key management, digital signature, and encryption / decryption, and a firmware update circuit block for updating the firmware of the security chip. The security chip may be, for example, a universal IC card (UICC) (such as USIM, CSIM, and ISIM), a subscriber identity module (SIM) card, an embedded security element (eSE), a micro SD, or a sticker.

[0203] The processor 2100 may be implemented to control overall operations of the mobile system 2000 and wired / wireless communications with external entities. For example, the processor 2100 may be, for example, an application processor (AP) or an integrated modem application processor (ModAP).

[0204] The buffer memory 2200 may be implemented to temporarily store data required for the processing operation of the mobile system 2000. The display / touch module 2300 may be implemented to display data processed by the processor 2100 or receive data from the touch panel. The storage device 2400 may be implemented to store user data. The storage device 2400 may be an embedded multimedia card (eMMC), a solid state drive (SSD), or a universal flash storage (UFS). The storage device 2400 may include at least one non-volatile memory device.

[0205] The non-volatile memory device may be a NAND flash memory, a vertical NAND (VNAND) flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), or a spin transfer torque random access memory (STT-RAM).

[0206] The mobile system 2000 may enhance performance and may reduce power consumption by modulating the clock signal independently of the frequency of the clock signal in the case of voltage reduction.

[0207] Aspects of the inventive concept may be applied to various SoCs using a power supply voltage and a clock signal.

[0208] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that various modifications may be made in the example embodiments without substantially departing from the novel teachings and advantages of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims.

Claims

1. A voltage drop monitoring circuit, include: a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals based on a first control signal, the first control signal being based on a power supply voltage of the functional circuit block; a counter configured to generate a count value based on the selected oscillation signal; as well as a drop detector configured to detect a drop in the power supply voltage of the functional circuit block based on the count value and at least a first threshold and a second threshold, such that a greater drop level is detected in response to the count value dropping below the first threshold than in response to the count value dropping below the second threshold, wherein the drop detector is configured to detect a drop in the power supply voltage in response to the count value dropping below the first threshold, and The drop detector is configured to detect the end of the drop of the power supply voltage in response to the count value exceeding the second threshold, and the second threshold is greater than the first threshold.

2. The voltage drop monitoring circuit according to claim 1, in: The ring oscillator circuit block includes a plurality of ring oscillators, each ring oscillator generates a corresponding oscillation signal among the plurality of oscillation signals, and the ring oscillator circuit block is configured to selectively set a natural speed of one or more ring oscillators among the plurality of ring oscillators based on the first control signal.

3. The voltage drop monitoring circuit according to claim 1, in: The ring oscillator circuit block includes a plurality of ring oscillators, each of which generates a corresponding oscillation signal among the plurality of oscillation signals based on the power supply voltage.

4. The voltage drop monitoring circuit according to claim 1, further comprising: include: A controller is configured to set the first threshold and the second threshold based on a reference voltage associated with a power supply voltage of the functional circuit block.

5. The voltage drop monitoring circuit according to claim 1, further comprising: include: A controller is configured to set the first threshold based on a reference voltage associated with a power supply voltage of the functional circuit block.

6. The voltage drop monitoring circuit according to claim 1, in: The drop detector is configured to detect a drop level of the power supply voltage based on the count value and a plurality of first threshold values.

7. The voltage drop monitoring circuit according to claim 6, in: The values ​​of the plurality of first thresholds decrease in sequence and are associated with different decreasing levels of the power supply voltage; and The drop detector is configured to detect a drop in response to the count value dropping below one of the plurality of first thresholds, and is configured to detect a drop level based on a lowest first threshold of the plurality of first thresholds below which the count value drops.

8. The voltage drop monitoring circuit according to claim 6, in: The drop detector is configured to detect a drop level of the power supply voltage based on the count value, the plurality of first thresholds, and a plurality of second thresholds, each of the plurality of second thresholds being associated with a corresponding first threshold of the plurality of first thresholds, and each of the plurality of second thresholds being greater than the corresponding first threshold; as well as The values ​​of the plurality of first thresholds decrease in sequence and are associated with different decreasing levels of the power supply voltage; as well as The drop detector is configured to detect a drop in response to the count value dropping below one of the plurality of first thresholds, to detect a drop level based on a lowest first threshold among the plurality of first thresholds below which the count value drops, and to detect a reduced drop level in response to the count value rising above a second threshold associated with the lowest first threshold among the plurality of first thresholds below which the count value drops.

9. The voltage drop monitoring circuit according to claim 8, further comprising: include: A controller is configured to set the plurality of first thresholds and the plurality of second thresholds based on a reference voltage associated with a power supply voltage of the functional circuit block.

10. The voltage drop monitoring circuit according to claim 6, further comprising: include: A controller is configured to set the plurality of first thresholds based on a reference voltage associated with a power supply voltage of the functional circuit block.

11. The voltage drop monitoring circuit according to claim 1, further comprising: include: The controller is configured to generate the first control signal based on the power supply voltage of the functional circuit block.

12. A voltage drop monitoring circuit, include: a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals; a counter configured to generate a count value based on the selected oscillation signal; as well as a drop detector configured to detect a drop in the power supply voltage of the functional circuit block based on the count value and at least a first threshold and a second threshold, such that a greater drop level is detected in response to the count value dropping below the first threshold than when the count value drops below the second threshold, the second threshold being greater than the first threshold, wherein the drop detector is configured to detect a drop in the power supply voltage in response to the count value dropping below the first threshold, and The falling detector is configured to detect the end of the falling of the power supply voltage in response to the count value exceeding the second threshold.

13. A system on a chip, include: a voltage drop monitoring circuit configured to monitor a drop in a power supply voltage of a functional circuit block and to generate an error signal based on said monitoring; as well as a clock modulation circuit configured to modulate an input clock signal based on the error signal to generate an adaptive clock signal, and configured to output the adaptive clock signal to the functional circuit block, The voltage drop monitoring circuit further includes: a ring oscillator circuit block configured to generate a plurality of oscillation signals and configured to output a selected oscillation signal from one of the plurality of oscillation signals; a counter configured to generate a count value based on the selected oscillation signal; and a drop detector configured to detect a drop in the power supply voltage of the functional circuit block based on the count value and at least a first threshold and a second threshold, such that a greater drop level is detected in response to the count value dropping below the first threshold than in response to the count value dropping below the second threshold, wherein the drop detector is configured to detect a drop in the power supply voltage in response to the count value dropping below the first threshold, and The drop detector is configured to detect the end of the drop of the power supply voltage in response to the count value exceeding the second threshold, and the second threshold is greater than the first threshold.

14. The system on chip according to claim 13, in: The clock modulation circuit is configured to reduce a frequency of the adaptive clock signal in a pre-drop state in response to the error signal indicating a drop in the power supply voltage.

15. The system on chip according to claim 14, in: The clock modulation circuit is configured to incrementally return the frequency of the adaptive clock signal to the frequency in the pre-drop state in response to the error signal indicating that the drop of the power supply voltage has ended.

16. The system on chip according to claim 13, in: The voltage droop monitoring circuit is configured to generate the error signal such that the error signal indicates a droop level; and The clock modulation circuit is configured to vary a frequency of the adaptive clock signal based on a falling level.

17. The system on chip according to claim 16, in: The clock modulation circuit is configured to decrease the frequency of the adaptive clock signal as the droop level increases, and is configured to increase the frequency of the adaptive clock signal as the droop level decreases.

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