Memory devices and memory cell writing methods for performing asymmetric write operations

Abstract

A memory device may be provided, comprising a variable-resistance memory cell including a variable-resistance element, a first cell transistor, and a second cell transistor. A first end of the variable-resistance element is connected to a bit line, and a second end of the variable-resistance element, the first end of the first cell transistor, and the first end of the second cell transistor are connected to a common node. The second ends of the first cell transistor and the second cell transistor are connected to a source line. A word line control circuit is configured to separate a sub-word line connected to the gate electrode of the second cell transistor from a word line connected to the gate electrode of the first cell transistor during a first write operation, and is configured to connect the word line and the sub-word line to each other during a second write operation.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2018-0110186, filed on September 14, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the inventive concept described herein relate to memory devices, and more specifically, to memory devices configured to perform asymmetric write operations according to the write direction. Background Technology

[0004] There is a growing demand for non-volatile semiconductor memory devices that enable higher integration and larger capacities. A representative example of a non-volatile semiconductor memory device is flash memory, which is used as a memory device in portable electronic devices. Other devices with random accessibility and improved performance characteristics are being developed as alternatives to flash memory, for example. Magnetic random access memory (MRAM) using variable resistive elements (e.g., tunneling magnetoresistive (TMR) layers) is one example of such an alternative device.

[0005] Write operations to variable-resistive elements include bit-line write operations and source-line write operations, in which the current directions are different. Bidirectional write schemes may cause overcurrent when performing bit-line write operations on variable-resistive memory cells, and may cause reduced drive capability due to the resistance of the variable-resistive element when performing source-line write operations on variable-resistive memory cells, thus causing some problems with the durability and / or reliability of the memory device. Summary of the Invention

[0006] Some exemplary embodiments of the present invention can provide a memory device configured to perform asymmetric write operations in terms of the write direction.

[0007] According to an example embodiment, a memory device may be provided, which may include: a variable-resistance memory cell including a variable-resistance element, a first cell transistor and a second cell transistor, a first end of the variable-resistance element being connected to a bit line, a second end of the variable-resistance element, a first end of the first cell transistor and a first end of the second cell transistor being connected to a common node, and a second end of the first cell transistor and a second end of the second cell transistor being connected to a source line; and a word line control circuit configured to separate a sub-word line connected to the gate electrode of the second cell transistor from a word line connected to the gate electrode of the first cell transistor in a first write operation, and configured to connect the word line and the sub-word line to each other in a second write operation.

[0008] According to an example embodiment, a memory device may include: a variable resistor element having a first end connected to a bit line; and word line control circuitry configured to select at least one of a first path and a second path, the second end of the variable resistor element being connected to a source line on both the first path and the second path.

[0009] According to an example embodiment, a method for writing to a memory cell includes a variable resistor element having a first end connected to a bit line and a second end connected to a source line via at least one of a first path and a second path. The method may include: determining whether a write operation to the memory cell is a bit line write operation or a source line write operation; selecting at least one of the first path and the second path based on the determination result; and performing the bit line write operation or the source line write operation via the selected at least one path. Attached Figure Description

[0010] The above and other objects and features of the present invention will become apparent from a detailed description of some exemplary embodiments of the invention with reference to the accompanying drawings.

[0011] Figure 1 This is a diagram illustrating the configuration of a storage device according to an example embodiment of the present disclosure.

[0012] Figure 2 It is shown Figure 1 A diagram showing an example configuration of a memory device.

[0013] Figure 3 It is shown Figure 2 A diagram showing the configuration of the memory cell array.

[0014] Figure 4 It is shown Figure 2 or Figure 3 A diagram showing an example configuration of the memory cells.

[0015] Figure 5 and Figure 6 It is shown according to the storage Figure 4 The data in the memory cell determines the magnetization direction of the variable resistor element.

[0016] Figure 7 The diagram illustrates the characteristics of bitline write operations and source line write operations.

[0017] Figure 8 The diagram illustrates other characteristics of bitline write operations and source line write operations.

[0018] Figure 9This is a diagram illustrating a portion of a memory device according to an exemplary embodiment of the present disclosure.

[0019] Figures 10 to 11 It is shown Figure 9 A diagram showing an example configuration of the word line control circuit.

[0020] Figure 12 It is shown Figure 10 and Figure 11 The diagram shows the switching circuit included in the word line control circuit.

[0021] Figure 13 This is a diagram illustrating a voltage output table according to an exemplary embodiment of the present disclosure.

[0022] Figure 14 This is a flowchart illustrating an asymmetric write operation according to an example embodiment of the present disclosure.

[0023] Figure 15 This is a circuit diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.

[0024] Figure 16 This is a diagram illustrating an electronic system according to an example embodiment of the present disclosure. Detailed Implementation

[0025] Below, some exemplary embodiments of the inventive concept will be described in detail and clearly, enabling those skilled in the art to easily implement the inventive concept.

[0026] The components described in the specific implementation and the functional blocks shown in the figures can be implemented using software, hardware, or a combination thereof, with reference to the terms "part," "unit," "module," "component," "device," etc. Software can be machine code, firmware, embedded code, or application software. Hardware can include electrical circuits, electronic circuits, processors, computers, integrated circuits, integrated circuit cores, pressure sensors, inertial sensors, microelectromechanical systems (MEMS), passive components, or a combination thereof.

[0027] Although the terms “identical” or “equivalent” are used in the description of the example embodiments, it should be understood that some inaccuracies may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that the element or value is identical to the other element or value within the expected range of manufacturing or operational tolerances (e.g., ±10%).

[0028] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it is intended that the relevant numerical value include manufacturing or operational tolerances above or below the stated value (e.g., ±10).

[0029] %). Furthermore, when the terms “generally” and “substantially” are used in conjunction with geometry, it is intended not to require precision of the geometry, but rather a tolerance of the shape within the scope of this disclosure.

[0030] Figure 1 This is a diagram illustrating the configuration of a storage device according to an exemplary embodiment of the present disclosure. The storage device 10 may include a controller 12 and a memory device 14. Although not shown in the figure, the storage device 10 may also include a buffer that temporarily stores data read from or to be stored in the memory device 14.

[0031] The controller 12 can control the read and write operations of the memory device 14. To this end, the controller 12 can send the command CMD, the address ADDR, and the control signal CTRL to the memory device 14. In response to signals received from the controller 12, the memory device 14 can store data "DATA" from the controller 12 or provide data to the controller 12. Furthermore, the controller 12 can generate error correction codes for the write data to be stored in the memory device 14, and can perform error detection and correction on the read data read from the memory device 14.

[0032] The memory device 14 can be configured to store and output data. The memory device 14 may include memory cells implemented using, for example, variable resistance elements. A variable resistance element can refer to an element that determines the data based on a variable resistance value.

[0033] In an example embodiment, memory device 14 may include spin-transfer torque magnetoresistive RAM (STT-MRAM) cells. In this case, each memory cell included in memory device 14 may include a magnetic tunnel junction (MTJ) element having a magnetic material.

[0034] In an example embodiment, memory device 14 may include phase-change random access memory (PRAM) cells. In this case, each memory cell included in memory device 14 may include an element formed of a phase change material. For example, the phase change material may include a chalcogenide material containing germanium (Ge), antimony (Sb), and / or tellurium (Te) (i.e., GST material).

[0035] In an example embodiment, memory device 14 may include resistive RAM (ReRAM). In this case, each memory cell included in memory device 14 may include an element formed of perovskite and / or transition metal oxide.

[0036] However, the memory device 14 conceived according to the present invention is not limited to the elements described above. The memory device 14 of this disclosure can be understood to include various variable resistance elements that determine data based on a variable resistance value. For ease of description, the term "variable resistance element VR" may be used in the specification; however, this term should be understood to include the various elements described above.

[0037] Meanwhile, the storage device 10 can be combined with the host device to form an electronic device. For example, the electronic device can be a smartphone or a wearable device. In this case, the host device can perform operations (e.g., read operations and write operations) to operate the storage device 10.

[0038] For example, the host device may include a main processor (e.g., a central processing unit (CPU) or an application processor (AP)), a dedicated processor (e.g., a graphics processing unit (GPU) or a modulator / demodulator (modem)) or an image sensor.

[0039] Figure 2 It is shown Figure 1 A diagram showing an example configuration of memory device 14. Memory device 100 includes a memory cell array 110, a row decoder 120, a column decoder 130, word line control circuitry 140, a write driver and a read amplifier 150, a data buffer 160, and control logic 170.

[0040] The memory cell array 110 may include variable-resistance memory cells implemented using variable-resistance elements. As described above, the variable-resistance memory cells may include STT-MRAM cells, PRAM cells, ReRAM cells, etc. However, in this embodiment, it is assumed that the memory cell array 110 includes STT-MRAM cells.

[0041] Each memory cell MC in the memory cell array 110 can be configured to perform an asymmetric write operation. For this purpose, each memory cell MC may include a variable resistor element and two cell transistors. In each memory cell MC, the two cell transistors can each be connected to a word line WL and a sub-word line WL'. For example, in a bit line write operation, one of the word line WL and the sub-word line WL' can be driven with respect to the memory cell MC. In a source line write operation, both the word line WL and the sub-word line WL' can be driven with respect to the memory cell MC. The structure of the memory cell MC and the asymmetric write operation of this disclosure will be described more fully later.

[0042] The row decoder 120 can receive the row address RA and the row control signal R_CTRL, and can decode the row address RA. The row decoder 120 can select and drive the word line WL connected to the memory cell MC that performs the read or write operation based on the row address RA and the row control signal R_CTRL. In other words, the row decoder 120 can provide a drive voltage to the word line WL.

[0043] The column decoder 130 can receive the column address CA and the column control signal C_CTRL, and can decode the column address CA. The column decoder 130 can select and drive the bit line BL and source line SL connected to the memory cell MC that performs a read operation or a write operation based on the column address CA and the column control signal C_CTRL.

[0044] The word line control circuit 140 can support asymmetric write operations based on the word line control signal WL_CTRL. For example, in a bit line write operation, the word line control circuit 140 can perform a switching operation to drive the word line WL. In a source line write operation, the word line control circuit 140 can perform a switching operation to drive both the word line WL and the sub-word line WL'.

[0045] During a write operation, the write driver and sense amplifier 150 can provide write data to memory cells selected by the row decoder 120 and column decoder 130. The write driver and sense amplifier 150 can receive data from the data buffer 160 and can drive the bit line BL and / or source line SL connected to the column decoder 130 based on the received data. That is, the write driver and sense amplifier 150 can provide a drive voltage (e.g., bit line voltage or source line voltage) to the bit line BL and / or source line SL.

[0046] During a read operation, the write driver and sense amplifier 150 can sense data stored in memory cells selected by the row decoder 120 and column decoder 130. For example, the write driver and sense amplifier 150 can compare the voltage of the bit line BL connected to the selected memory cell with the voltage of a reference bit line (not shown), and can amplify the difference corresponding to the comparison result. The write driver and sense amplifier 150 can latch the voltage corresponding to the amplified difference and can determine the data.

[0047] Data buffer 160 can store write data received from an external source or read data read from memory cell array 110. Data buffer 160 may include a deserializer (not shown) for deserializing write data and a serializer (not shown) for serializing read data.

[0048] Control logic 170 can decode commands received from an external source. For example, control logic 170 can decode activation commands, write commands, read commands, precharge commands, etc. For example, control logic 170 can generate a row control signal R_CTRL based on an activation command or precharge command used to control row decoder 120. For example, control logic 170 can generate a column control signal C_CTRL based on a write command or read command used to control column decoder 130. For example, control logic 170 can generate a word line control signal WL_CTRL based on a write command used to control word line control circuitry 140.

[0049] Figure 3 It is shown Figure 2 A diagram showing the configuration of the memory cell array 110.

[0050] The memory cell array 110 may include a plurality of memory cells MC arranged along the row and column directions. Each memory cell MC may include a variable resistor element VR and two cell transistors CT1 and CT2. In an embodiment, the variable resistor element VR is a magnetic tunnel junction element. According to some example embodiments, the variable resistor element VR is not limited to a magnetic tunnel junction element, as long as the resistance value of the variable resistor element VR varies with the magnitude and direction of the current (or voltage) supplied to the variable resistor element VR. The resistance value can be maintained even if no current (or voltage) is supplied to the variable resistor element VR. That is, the variable resistor element VR may have non-volatile characteristics.

[0051] A memory cell MC may have a structure in which two cell transistors CT1 and CT2 share a variable resistor element VR. One end (or a first end) of the variable resistor element VR may be connected to a bit line (e.g., BLn), and the other end (or a second end) of the variable resistor element VR may be connected to one end of cell transistor CT1 and one end of cell transistor CT2. The other ends of cell transistor CT1 and cell transistor CT2 may be connected to a source line (e.g., SLn). The gate electrode of the first cell transistor CT1 may be connected to a word line (e.g., WL1), and the gate electrode of the second cell transistor CT2 may be connected to a sub-word line (e.g., WL1'). Each of the cell transistors CT1 and CT2 may be turned on or off by a signal provided via the respective word line and / or the respective sub-word line.

[0052] Meanwhile, word lines WL1 to WLm can be controlled via word line control circuit 140 (reference). Figure 2 Connect to line decoder 120 (reference) Figure 2 As will be described later, in the word line control signal WL_CTRL (see...) Figure 2Under the control of [the system / mechanism], sub-word lines WL1' to WLm' can be connected to word lines WL1 to WLm respectively. For example, in a bit-line write operation, sub-word lines WL1' to WLm' may not be connected to word lines WL1 to WLm respectively. In a source-line write operation, sub-word lines WL1' to WLm' can be connected to word lines WL1 to WLm respectively.

[0053] Figure 4 It is shown Figure 2 or Figure 3 A diagram showing an example configuration of a memory cell MC. The memory cell MC may include a variable resistive element VR and cell transistors CT1 and CT2.

[0054] The gate electrode of the first transistor CT1 can be connected to a word line (e.g., the first word line WL1), and one end of the first transistor CT1 can be connected to a bit line (e.g., the first bit line BL1) via a variable resistor element VR. The other end of the first transistor CT1 can be connected to a source line (e.g., the first source line SL1).

[0055] The gate electrode of the second transistor CT2 can be connected to a sub-word line (e.g., the first sub-word line WL1'), and one end of the second transistor CT2 can be connected to a bit line (e.g., the first bit line BL1) via a variable resistor element VR. The other end of the second transistor CT2 can be connected to a source line (e.g., the first source line SL1).

[0056] The variable resistive element VR may include a pinned layer PL, a free layer FL, and a blocking layer BL (or tunneling layer) inserted between the pinned layer PL and the free layer FL. The magnetization direction of the pinned layer PL may be fixed, and the magnetization direction of the free layer FL may be the same as or opposite to the magnetization direction of the pinned layer PL depending on the conditions. The memory cell MC may also include, for example, an antiferromagnetic layer (not shown) for fixing the magnetization direction of the pinned layer PL.

[0057] The free layer FL can include materials with variable magnetization direction. The magnetization direction of the free layer FL can be changed by electromagnetic factors provided from the outside and / or inside of the memory cell MC. The free layer FL can include ferromagnetic materials containing at least one of cobalt (Co), iron (Fe), and nickel (Ni). For example, the free layer FL can include FeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O. 12 At least one of them.

[0058] The barrier layer BL can have a thickness thinner than the spin diffusion distance. The barrier layer BL can include a non-magnetic material. For example, the barrier layer BL can include at least one of the following: oxides of magnesium (Mg), titanium (Ti), aluminum (Al), magnesium zinc (MgZn) or magnesium boron (MgB), and nitrides of titanium (Ti) or nitrides of vanadium (V).

[0059] The pinning layer PL can have a magnetization direction fixed by the antiferromagnetic layer. The pinning layer PL can comprise a ferromagnetic material. For example, the pinning layer PL can comprise CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb, CrO2, MnOFe2O3, FeOFe2O3, NiOFe2O3, CuOFe2O3, MgOFe2O3, EuO, and Y3Fe5O 12 At least one of them.

[0060] The antiferromagnetic layer (not shown) may include an antiferromagnetic material. For example, the antiferromagnetic layer may include at least one of PtMn, IrMn, MnO, MnS, MnTe, MnF2, FeCl2, FeO, CoCl2, CoO, NiCl2, NiO, and Cr.

[0061] In a read operation associated with memory cell MC, a logic high voltage can be applied to the first word line WL1, thus turning on the first cell transistor CT1. To measure the resistance value of the variable resistor element VR, a read current can be provided between the first bit line BL1 and the first source line SL1. The data stored in the variable resistor element VR can be determined based on the measured resistance value.

[0062] In a write operation associated with memory cell MC, a logic high voltage can be applied to the first word line WL1, or a logic high voltage can be applied to both the first word line WL1 and the first sub-word line WL1', and thus, the first cell transistor CT1 or the second cell transistor CT2 can be turned on. To change the resistance value of the variable resistor element VR, a write current can be provided between the first bit line BL1 and the first source line SL1.

[0063] Figure 5 and Figure 6 It is shown according to the storage Figure 4 The data in the memory cell determines the magnetization direction of the variable resistor element VR.

[0064] In the example embodiment, Figure 5A bitline write operation is illustrated. In a bitline write operation, a first write current I1 can flow when a bitline voltage is applied to the first bitline BL1 and a ground voltage is applied to the first sourceline SL1. In this case, the magnetization directions of the free layer FL and the pinned layer PL can become identical (i.e., inparallel), thus reducing the resistance value of the variable resistor element VR. For example, a bitline write operation can correspond to a logic "0" programming operation.

[0065] In the example embodiment, Figure 6 A source line write operation is illustrated. In a source line write operation, a second write current I2 can flow when a source line voltage is applied to the first source line SL1 and a ground voltage is applied to the first source line BL1. In this case, the magnetization directions of the free layer FL and the pinned layer PL can become opposite to each other (i.e., anti-parallel), and therefore, the resistance value of the variable resistor element VR can increase. For example, the source line write operation can correspond to a logic "1" programming operation.

[0066] Data in the memory cell can be generated by the write driver and the sense amplifier 150 (see...). Figure 2 The direction of the write current driven by the first write current I2 switches between a first value (e.g., logic "0") and a second value (e.g., logic "1"). For example, when a second write current I2 is applied to a memory cell storing the first value, the value stored in the memory cell can switch from the first value to the second value. Conversely, when a first write current I1 is applied to a memory cell storing the second value, the value stored in the memory cell can switch from the second value to the first value.

[0067] As is customary, in a source-line write operation associated with a memory cell comprising a unit transistor and a variable resistor element VR, the gate-source voltage of the unit transistor may be reduced due to the resistance of the variable resistor element VR connected to the source electrode of the unit transistor, thereby reducing the current drive capability t in the source-line write operation.

[0068] like Figure 5 and Figure 6 As shown, two unit transistors CT1 and CT2 can be used to increase the current drive capability during source line write operations. However, using two unit transistors CT1 and CT2 may generate overcurrent during bit line write operations. This can lead to undesirable excessive power consumption, write errors due to back-hopping switching, and / or reduced durability.

[0069] Figure 7The diagram illustrates the characteristics of bitline write operations and source line write operations. For better understanding, please refer to [the relevant documentation / reference]. Figure 5 Provide a description.

[0070] In an example embodiment, the operation of programming a first value (e.g., logic "0") to a memory cell may correspond to a bit line write operation, and the operation of programming a second value (e.g., logic "1") to a memory cell may correspond to a source line write operation.

[0071] In a bit-line write operation, a threshold current or greater can be applied during the time interval t1 to t2 in order to program a first value (e.g., logic "0") into a memory cell. Figure 7 In the graph, the horizontal axis represents the time spent programming the first value into the memory cell. Figure 7 In the diagram, the vertical axis represents the current used to program the first value into the memory cell. The amount of charge corresponding to the area of ​​the shaded box is sufficient to perform a bitline write operation, or sufficient to switch from a second value (e.g., logic "1") to a first value (e.g., logic "0").

[0072] In a bit-line write operation, if the write voltage to be applied to the first bit line BL is set as a reference voltage, the reference voltage may be insufficient to perform the source-line write operation due to the reduction in the gate-source voltages of the unit transistors CT1 and CT2 as described above. This is conceptually represented as the value of the second write current I2 being lower than the threshold in the source-line write operation.

[0073] Figure 8 The diagram illustrates additional characteristics of bitline write operations and source line write operations. For better understanding, please refer to [the relevant documentation / reference]. Figure 6 Provide a description.

[0074] In an example embodiment, the operation of programming a first value (e.g., logic "0") to a memory cell may correspond to a bit line write operation, and the operation of programming a second value (e.g., logic "1") to a memory cell may correspond to a source line write operation.

[0075] In a bit-line write operation, where the write voltage applied to source line SL1 to successfully program a second value (e.g., logic "1") is set as a reference voltage, this reference voltage may be excessive for performing the bit-line write operation. This is conceptually illustrated as the value of the first write current I1 exceeding a threshold in the bit-line write operation (e.g., shaded area). Overcurrent can lead to undesirable excessive power consumption, write errors due to debounce switching, and / or reduced durability.

[0076] Figure 9This is a diagram illustrating a portion of a memory device according to an exemplary embodiment of the present disclosure. For simplicity, word line control circuitry 140 and a memory cell are shown.

[0077] A memory cell may include a variable resistive element VR and unit transistors CT1 and CT2. Figure 9 In this diagram, "N" represents the common node to which the variable resistor VR, the first transistor CT1, and the second transistor CT2 are connected. The path passing through the first source line BL1, the variable resistor VR, the common node "N", the first transistor CT1, and the first source line SL1 can be called the "first path". The path passing through the first source line BL1, the variable resistor VR, the common node "N", the second transistor CT2, and the first source line SL1 can be called the "second path".

[0078] The word line control circuit 140 can be configured to control unit transistors CT1 and CT2. In an example embodiment, the word line control circuit 140 may include a switching element SW, which is configured to be switched under the control of a word line control signal WL_CTRL. For example, the switching element SW may include, but is not limited to, one or more transistors.

[0079] During a bitline write operation, the word line control circuit 140 can control unit transistors CT1 and CT2 such that only one of the unit transistors CT1 and CT2 is turned on. For example, during a bitline write operation, the power supply voltage V can be switched by appropriately switching the switching element SW. SS This is provided to the gate electrode of the second unit transistor CT2. Here, the power supply voltage V... SS It can be the voltage used to turn off the second unit transistor CT2 (e.g., ground voltage).

[0080] Since only one of the unit transistors CT1 and CT2 is turned on (e.g., the first unit transistor CT1), current flows only through the first path. That is, since a small amount of current flows compared to the case where both unit transistors CT1 and CT2 are turned on and therefore current flows through the first and second paths, overcurrent from the first line BL1 to the variable resistor element VR can be mitigated or prevented.

[0081] During a source line write operation, the word line control circuit 140 can control unit transistors CT1 and CT2, causing both unit transistors CT1 and CT2 to be turned on. For example, during a source line write operation, by appropriately switching the switching element SW, a first sub-word line WL1' can be connected to a first word line WL1, and a word line voltage can be provided to the gate electrodes of unit transistors CT1 and CT2. Here, the word line voltage can be a voltage sufficient to turn on unit transistors CT1 and CT2.

[0082] When both unit transistors CT1 and CT2 are turned on, current flows through both the first path and the second path. Because the intensity of the current flowing from the first source line SL1 to the variable resistor element VR increases, the reduction in drive capability caused by the decrease in the gate-source voltage of unit transistors CT1 and CT2 can be mitigated or prevented.

[0083] Meanwhile, the word line control circuit 140 in Figure 2 and Figure 9 The word line control circuit 140 is shown as a component independent of the line decoder 120. However, according to some example embodiments, the word line control circuit 140 may be included in the line decoder 120. That is, the word line control circuit 140 and the line decoder 120 may be implemented as functional units of a single component.

[0084] Figures 10 to 11 It is shown Figure 9 A diagram showing an example configuration of the word line control circuit. In an example embodiment, the word line control circuit 140 includes a level shifter 142, a first control transistor TR1, and a second control transistor TR2.

[0085] Level shifter 142 can be configured to shift the first power supply voltage V DD Shift to an appropriate voltage level. Here, an appropriate voltage level can mean a voltage level suitable for turning on or off control transistors TR1 and TR2. For example, the first supply voltage V DD This could be the bit line voltage to be supplied to the first word line BL1. Level shifter 142 can shift the bit line voltage to the level of the word line voltage to be supplied to the first word line WL1. Level shifter 142 can be configured to receive and output a second power supply voltage V. SS Without modifying it. In this case, the second power supply voltage V SS It can be ground voltage. The shifted voltage is applied through the common line CL to the gate electrode of the first control transistor TR1 and / or the gate electrode of the second control transistor TR2.

[0086] The gate electrode of the first control transistor TR1 and the gate electrode of the second control transistor TR2 can be connected to the output terminal of the level shifter 142. One end of the first control transistor TR1 can be connected to the first word line WL1, and one end of the second control transistor TR2 can be connected to the second power supply voltage V. SSThe other end of the first control transistor TR1 and the other end of the second control transistor TR2 can be connected together to the first sub-word line WL1'. The first word line WL1 can be connected to the gate electrode of the first unit transistor CT1, and the first sub-word line WL1' can be connected to the gate electrode of the second unit transistor CT2. For example, the first control transistor TR1 can be a PMOS transistor, and the second control transistor TR2 can be an NMOS transistor.

[0087] exist Figure 10 The diagram illustrates the operation of the word line control circuit 140 during a bit line write operation. As described above, according to the bit line write operation of this disclosure, only one of the cell transistors CT1 and CT2 (e.g., the first cell transistor CT1) is turned on to mitigate or prevent the level of the first write current I1 from becoming too high.

[0088] Level shifter 142 can shift the first power supply voltage V DD The voltage is shifted to an appropriate voltage level (e.g., word line voltage). When the shifted voltage is applied to the gate electrode of the first control transistor TR1, the first control transistor TR1 can be turned off. In this case, the first word line WL1 can be electrically disconnected (or isolated) from the first sub-word line WL1'. Similarly, the second supply voltage V can be shifted... SS The gate electrode of the second unit transistor CT2 is applied, so the second unit transistor CT2 can be turned off.

[0089] Furthermore, when the first control transistor TR1 is turned off, the word line voltage supplied to the first word line WL1 is applied only to the first unit transistor CT1, thus turning on the first unit transistor CT1. In this way, the first write current I1 flows through the first unit transistor CT1 to the first source line SL1, but not through the second unit transistor CT2.

[0090] exist Figure 11 The diagram illustrates the operation of the word line control circuit 140 during a source line write operation. As described above, according to the source line write operation of this disclosure, all cell transistors CT1 and CT2 can be turned on to mitigate or prevent a decrease in the level of the second write current I2.

[0091] Level shifter 142 can receive and output a second power supply voltage V SS When the second power supply voltage V SS When applied to the gate electrode of the second control transistor TR2, the second control transistor TR2 can be turned off. In this case, the first sub-word line WL1' is connected to the second power supply voltage V. SS Electrical separation (or isolation). Furthermore, when the second power supply voltage V... SSWhen an application is made to the gate electrode of the first control transistor TR1, the first control transistor TR1 can be turned on. In this case, word line WL1 can be electrically connected to the first sub-word line WL1'.

[0092] The word line voltage supplied through the first word line WL1 can be applied to the gate electrode of the first unit transistor CT1, thus turning on the first unit transistor CT1. Furthermore, because the word line voltage supplied through the first word line WL1 is applied to the gate electrode of the second unit transistor CT2 through the first sub-word line WL1', the second unit transistor CT2 can also be turned on. Therefore, the second write current I2 can flow to the first bit line BL1 through both the first unit transistor CT1 and the second unit transistor CT2.

[0093] The level shifter 142 configured in the word line control circuit 140 is not limited to... Figure 10 and Figure 11 The level shifter shown can be one of various logic elements (e.g., inverters and inverter chains) configured to change voltage levels.

[0094] Figure 12 It is shown Figure 10 and Figure 11 A diagram of the switching circuit included in the word line control circuit. For better understanding, [the diagram will be shown below]. Figure 10 and Figure 11 The level shifter 142 and the common line CL are shown together. For better understanding, please refer to [reference needed]. Figure 10 and Figure 11 Provide a description.

[0095] Switching circuit 144 can be configured to select a first power supply voltage V in response to word line control signal WL_CTRL. DD Or the second power supply voltage V SS For example, the switching circuit 144 can be implemented differently using transistors or multiplexers. In an example embodiment, when performing a bit line write operation, the switching circuit 144 can select and output a first power supply voltage V. DD Conversely, in the case of performing a source-line write operation, the switching circuit 144 can select and output a second power supply voltage V. SS .

[0096] In an example embodiment, the switching circuit 144 may be implemented as part of the word line control circuit 140. In another example embodiment, the switching circuit 144 may be implemented separately from the word line control circuit 144.

[0097] Figure 13 This is a diagram illustrating a voltage output table according to an exemplary embodiment of the present disclosure. For better understanding, it will be referenced together with... Figure 10 and11 Provide a description.

[0098] In this table, the top row indicates the voltage of the word line WL, common line CL, sub-word line WL', bit line BL, and source line SL. Figure 10 and Figure 11 The first word line WL1, the first bit line BL1, and the first source line SL1 shown in the table can be understood as corresponding to the word line WL, the bit line BL, and the source line SL, respectively. In this table, the leftmost column indicates the unselected memory cell Unsel, the source line write operation, and the bit line write operation.

[0099] Control logic 170 can generate word line control signals WL_CTRL based on commands CMD received from an external source (e.g., a host). Word line control signals WL_CTRL can include various information required to perform the bit line write operation and source line write operation of this disclosure. For example, as described above, word line control signals WL_CTRL can control control transistors TR1 and TR2 such that during a bit line write operation, the first control transistor TR1 is turned off and the second control transistor TR2 is turned on. Word line control signals WL_CTRL can also control control transistors TR1 and TR2 such that during a source line write operation, the first control transistor TR1 is turned on and the second control transistor TR2 is turned off.

[0100] Control logic 170 can be based on Figure 13 The voltmeter shown controls the word line WL, bit line BL, and source line SL. In the example embodiment, Figure 13 The table shown can be stored in a separate register located in control logic 170 or can be stored in memory device 14 (see [link]). Figure 1 ) in a separate area.

[0101] Referring to the source line write operation in the reference table, in the source line write operation, the source line voltage V SL The source line SL and the bit line BL can be applied to the ground voltage GND, respectively. Furthermore, the word line voltage V... WL Word lines WL and subword lines WL' can be applied to the selected memory cell. (See reference...) Figure 11 As mentioned above, because the second power supply voltage V SS (For example, ground voltage GND) is applied to the second control transistor TR2 through the common line CL, and therefore the second control transistor TR2 is turned off, so the word line voltage V WL It can be applied to the sub-word line WL'.

[0102] Meanwhile, referring to the bit line write operation in the reference table, in the bit line write operation, the bit line voltage V BLThe word line voltage GND can be applied to the bit line BL and the source line SL, respectively. Furthermore, the word line voltage V... WL The ground voltage GND can be applied to the word line WL and sub-word line WL' of the selected memory cell, respectively. (See reference...) Figure 10 As stated above, because the shifted first power supply voltage (e.g., word line voltage) is applied to the second control transistor TR2 through the common line CL and therefore the second control transistor TR2 is turned on, the second power supply voltage V SS (For example, ground voltage GND) is applied to sub-word line WL'.

[0103] As described above, the asymmetric write operation according to this disclosure can mitigate or prevent overcurrent flowing into the bit line during bit line write operations, and can mitigate or prevent the reduction in drive capability during source line write operations.

[0104] Figure 14 This is a flowchart illustrating an asymmetric write operation according to an example embodiment of the present disclosure. For better understanding, it will be referenced together with... Figure 9 Provide a description. Figure 9 The first word line WL1, the first bit line BL1, and the first source line SL shown can be understood as corresponding to respectively Figure 14 The word line WL, bit line BL, and source line SL are shown in the figure.

[0105] In operation S110, a target memory cell is selected. The target memory cell can be selected by driving the bit lines and source lines connected to the target memory cell based on the address received from an external source.

[0106] In operation S120, it is determined whether the write operation to the target memory cell is a bit-line write operation or a source-line write operation. If it is determined that the write operation is a bit-line write operation, operation S130 is executed; and if it is determined that the write operation is a source-line write operation, operation S150 is executed.

[0107] In operation S130, only one of the unit transistors CT1 and CT2 connected to the variable resistor element VR can be turned on. In the example embodiment, the second power supply voltage V used to turn off the second unit transistor CT2 can be switched by appropriately switching the switching element SW of the word line control circuit 140. SS It is applied to the second unit transistor CT2.

[0108] In operation S140, the bit line voltage V can be... BL Apply the bit line BL, and the ground voltage GND can be applied to the source line SL. Because only one of the unit transistors CT1 and CT2 is turned on, overcurrent that may occur when current flows through both unit transistors CT1 and CT2 can be mitigated or prevented.

[0109] In operation S150, both unit transistors CT1 and CT2 connected to the variable resistor element VR can be turned on. In the example embodiment, by appropriately switching the switching element SW of the word line control circuit 140, the word line WL can be electrically connected to the sub-word line WL', so that the word line voltage can be applied to the gate electrode of unit transistor CT1 and the gate electrode of unit transistor CT2.

[0110] In operation S160, ground voltage GND can be applied to bit line BL, and source line voltage V can be applied to bit line BL. SL It is applied to the source line SL. When all cell transistors CT1 and CT2 are turned on, it can mitigate or prevent insufficient drive capability that may occur when current flows through only one cell transistor.

[0111] Figure 15 This is a circuit diagram illustrating a memory device according to an exemplary embodiment of the present disclosure. The memory device 100 may include memory cells arranged along row and column directions, and word line control circuitry 140. The above exemplary embodiments are described in detail below. Figure 15 The layout and connection relationships of the components shown are omitted to avoid redundancy.

[0112] Figure 16 This is a diagram illustrating an electronic system 1000 according to an example embodiment of the present disclosure.

[0113] Electronic system 1000 may include at least one processor 1100, communication module 1200, working memory 1300, storage device 1400, user interface 1500, and bus 1600. For example, electronic system 1000 may be one of the electronic devices such as desktop computers, laptop computers, tablet computers, smartphones, wearable devices, video game consoles, workstations, servers, and electric vehicles.

[0114] Processor 1100 can control the overall operation of electronic system 1000. Processor 1100 can handle various arithmetic and / or logical operations. Processor 1100 may include application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated microprocessors, microprocessors, etc. For example, processor 1100 may include one or more processor cores and may be implemented using general-purpose processors, dedicated processors, or application processors.

[0115] The communication module 1200 can communicate with external devices / systems of the electronic system 1000. For example, the communication module 1200 may be a functional block, circuit, or semiconductor chip manufactured independently of the processor 1100. In the case where the processor 1100 is implemented using an application processor, at least a portion of the functionality of the communication module 1200 may be incorporated into the application processor 1100.

[0116] For example, the communication module 1200 may support at least one of various wireless communication protocols (e.g., Long Term Evolution (LTE), WiMax, GSM, CDMA, Bluetooth, NFC, Wi-Fi, and RFID), and / or at least one of various wired communication protocols (e.g., Transmission Control Protocol / Internet Protocol (TCP / IP), USB, and FireWire).

[0117] The working memory 1300 can store data that will be used for the operation of the electronic system 1000. For example, the working memory 1300 can temporarily store data that is processed by the processor 1100 or will be processed by the processor 1100. For example, the working memory 1300 may include volatile memory (e.g., dynamic random access memory (DRAM) or synchronous DRAM (SDRAM)) and / or non-volatile memory (e.g., phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (ReRAM), or ferroelectric RAM (FRAM)).

[0118] Storage device 1400 may include one or more memory devices and a controller. The memory devices of storage device 1400 can store data regardless of power supply. For example, storage device 1400 may include non-volatile memory (e.g., flash memory, PRAM, MRAM, ReRAM, or FRAM). For example, storage device 1400 may include storage media (e.g., solid-state drive (SSD), removable storage, or embedded storage).

[0119] Specifically, when the working memory 1300 or the storage device 1400 includes a variable resistive memory (e.g., MRAM, PRAM, or ReRAM) of this disclosure, the working memory 1300 or the storage device 1400 can be configured to perform the asymmetric write operation of this disclosure. This can mitigate or prevent overcurrent that may occur in bit line write operations and insufficient drive capability that may occur in source line write operations, thus improving the reliability of the write operation.

[0120] User interface 1500 can perform communication arbitration between the user and electronic system 1000. For example, user interface 1500 may include input interfaces (e.g., keyboard, mouse, keypad, buttons, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyroscope sensor, and / or vibration sensor). For example, user interface 1500 may include output interfaces (e.g., liquid crystal display (LCD), light-emitting diode (LED) display, organic LED (OLED) display, active-matrix OLED (AMOLED) display, speaker, or motor).

[0121] Bus 1600 can provide a communication path between components of electronic system 1000. Components of electronic system 1000 can exchange data with each other based on the bus format of bus 1600. For example, the bus format may include one or more of the following various interface protocols: such as USB, Small Computer System Interface (SCSI), Peripheral Component Interconnect Fast (PCIe), Mobile PCIe (M-PCIe), Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), Enhanced IDE (EIDE), Non-Volatile Memory Fast (NVMe), or Universal Flash (UFS).

[0122] This disclosure provides a memory device that mitigates or prevents overcurrent during bit line write operations and / or mitigates or prevents a reduction in drive capability during source line write operations.

[0123] Although the inventive concept has been described with reference to some exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made to the inventive concept without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. A memory device, comprising: A variable resistance memory cell includes a variable resistance element, a first unit transistor, and a second unit transistor. The first end of the variable resistance element is connected to a bit line, and the second end of the variable resistance element, the first end of the first unit transistor, and the first end of the second unit transistor are connected to a common node. The second ends of the first unit transistor and the second end of the second unit transistor are connected to a source line. and A word line control circuit is configured to, during a bit line write operation, separate a sub-word line connected to the gate electrode of the second unit transistor from a word line connected to the gate electrode of the first unit transistor, such that the second unit transistor is turned off and only the first unit transistor is turned on, and is configured to, during a source line write operation, connect the word line and the sub-word line to each other, such that both the second unit transistor and the first unit transistor are turned on.

2. The memory device according to claim 1, wherein, The word line control circuit includes: A first control transistor is configured to be turned off in response to a first power supply voltage, such that the word line and the sub-word line are disconnected from each other, and to be turned on in response to a second power supply voltage, such that the word line is connected to the sub-word line. A second control transistor is configured to be turned on in response to the first power supply voltage, such that the second power supply voltage is supplied to the gate electrode of the second unit transistor, and to be turned off in response to the second power supply voltage, such that the second power supply voltage is not supplied to the gate electrode of the second unit transistor.

3. The memory device according to claim 2, wherein, The word line control circuit further includes a level shifter configured to receive and shift the first power supply voltage or the second power supply voltage, and to input the shifted voltage to both the gate electrode of the first control transistor and the gate electrode of the second control transistor.

4. The memory device according to claim 3, wherein, When the shifted voltage is based on the first power supply voltage, the level of the shifted voltage is the same as the level of the word line voltage applied to the word line.

5. The memory device according to claim 2, wherein, The first control transistor is a PMOS transistor, and the second control transistor is an NMOS transistor.

6. The memory device according to claim 1, further comprising: A line decoder configured to provide word line voltages for driving the word lines; and A write driver and a sense amplifier are configured to generate a bit line voltage for driving the bit line or a source line voltage for driving the source line.

7. The memory device according to claim 6, wherein, The memory device is configured such that: In the bit line write operation, the bit line voltage is applied to the bit line and the ground voltage is applied to the source line; and During the source line write operation, the source line voltage is applied to the source line and the ground voltage is applied to the bit line.

8. The memory device according to claim 1, wherein, The variable resistance element includes: A free layer, which has a variable magnetization direction; Pinned layers, which have a fixed magnetization direction; and A barrier layer is located between the free layer and the pinning layer.

9. A memory device, comprising: A variable resistor element having a first end connected to a bit line; and A word line control circuit configured to select at least one of a first path and a second path, wherein the second terminal of the variable resistor element is connected to a source line on both the first path and the second path. The first path includes a first unit transistor having a gate electrode connected to a word line; the second path includes a second unit transistor having a gate electrode connected to a sub-word line; and The memory device is configured such that: During a bitline write operation, the first cell transistor is turned on to enable the first path, and During a source line write operation, the first cell transistor and the second cell transistor are turned on to enable both the first path and the second path.

10. The memory device according to claim 9, wherein, The memory device is configured such that: In the bit line write operation, a bit line voltage is applied to the bit line and a ground voltage is applied to the source line, and In the source line write operation, a source line voltage is applied to the source line and a ground voltage is applied to the bit line.

11. The memory device according to claim 9, wherein, The word line control circuit includes a first control transistor and a second control transistor. The first control transistor is configured to be turned off in response to a first power supply voltage, causing the word line to disconnect from the sub-word line, and to be turned on in response to a second power supply voltage, causing the word line to connect to the sub-word line. The second control transistor is configured to be turned on in response to the first power supply voltage, such that the second power supply voltage is supplied to the gate electrode of the second unit transistor, and to be turned off in response to the second power supply voltage, such that the second power supply voltage is not supplied to the gate electrode of the second unit transistor.

12. The memory device according to claim 11, wherein, The word line control circuit further includes a level shifter configured to receive and shift the first power supply voltage or the second power supply voltage, and to input the shifted voltage to the gate electrode of the first control transistor and the gate electrode of the second control transistor.

13. The memory device according to claim 12, wherein, When the shifted voltage is based on the first power supply voltage, the level of the shifted voltage is the same as the level of the word line voltage applied to the word line.

14. The memory device according to claim 9, wherein, The variable resistance element includes: A free layer, which has a variable magnetization direction; Pinned layers, which have a fixed magnetization direction; and A barrier layer is located between the free layer and the pinning layer.

15. A method of writing to a memory cell, the memory cell comprising a variable resistive element, a first cell transistor, and a second cell transistor, the variable resistive element having a first terminal connected to a bit line, a second terminal of the variable resistive element, the first terminal of the first cell transistor, and the first terminal of the second cell transistor being connected to a common node, the second terminal of the first cell transistor and the second terminal of the second cell transistor being connected to a source line, the method comprising: Determine whether the write operation to the memory cell is a bit line write operation or a source line write operation; Based on the determined result, select at least one of the first path and the second path; and The bit line write operation or the source line write operation is performed by at least one of the selected first path and second path. In the bit line write operation, the first unit transistor is turned on to enable the first path, and in the source line write operation, the first unit transistor and the second unit transistor are turned on to enable both the first path and the second path.

16. The method according to claim 15, wherein, The selection includes: In response to an indication that the write operation is a determination result of the bitline write operation, the first path is selected by word line control circuitry configured to control the first path and the second path; and In response to the determination that the write operation is the result of the source line write operation, the word line control circuit selects the first path and the second path.

17. The method according to claim 16, wherein, When the bit line write operation is performed, in response to an indication that the write operation is a determined result of the bit line write operation, a bit line voltage is applied to the bit line and a ground voltage is applied to the source line, and When the source line write operation is performed, in response to indicating that the write operation is the result of the source line write operation, a source line voltage is applied to the source line and a ground voltage is applied to the bit line.

18. The method according to claim 15, wherein, The variable resistance element includes: A free layer, which has a variable magnetization direction; Pinned layers, which have a fixed magnetization direction; and A barrier layer is located between the free layer and the pinning layer.

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