Storage computing chip and manufacturing method thereof

Abstract

The invention provides a memory computing chip and a manufacturing method thereof, which are characterized in that a logic chip with a computing processor, a buffer chip and a DRAM (dynamic random access memory) chip (or a DRAM chip stack) are vertically stacked through silicon through holes, and the chips can be directly communicated through the silicon through holes, so that the chip area can be saved, the integration level is high, the wafer processing difficulty is reduced, and the manufacturing cost is reduced. The logic chip can visit the low-speed DRAM chip in parallel in a large number through the buffer chip, high-bandwidth and large-capacity cache is provided, inter-chip communication between the buffer chip and the logic chip does not need a physical layer interface, and cost of hardware resources is greatly reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a storage computing chip and a manufacturing method thereof. BACKGROUND

[0002] Referring to Figure 1 As shown in the figure, a common storage computing chip usually vertically stacks multiple layers of DRAM chips 40 and a basic chip 50, and places a logic chip 70 with a computing processor 10 side by side on an interposer 90, and respectively bonds to the interposer 90 through micro bumps 80. The logic chip 70 generally includes a physical layer (PHY) interface 60, a memory controller 30, and a computing processor 10, etc. The computing processor 10 can be an AI processor, a GPU (Graphics Processing Unit), or a CPU (Central Processing Unit), or other high-end processors, etc. That is, the physical layer interface 60, the memory controller 30, and the computing processor 10 are implemented on the same wafer. The basic chip 50 has a physical layer interface (PHY) 500a. The physical layer interface 60 and the physical layer interface 500a are connected through the micro bumps 80 and the wiring in the interposer 90. Therefore, the memory controller 30 and the basic chip 50 need to communicate between chips through the physical interface 60, 500a, and the micro bumps 80, etc.

[0003] The physical interface 60, 500a is a physical connection layer between the memory controller 60 of the logic chip 70 and the DRAM chip 40, responsible for high-speed data transmission and signal processing. It mainly consists of the following parts: data interface, clock interface, control interface, and power interface. Among them, the data interface is used to transmit data and address information, the clock interface provides a clock signal to synchronize data transmission, the control interface is responsible for controlling the reading and writing of data and other operations, and the power interface provides power supply to ensure normal operation.

[0004] The above scheme has the following problems:

[0005] 1. The memory controller 30 of the logic chip 70 and the basic chip 50 need to introduce a parallel high-speed physical interface 60, 500a to realize inter-chip communication, which consumes a lot of hardware resources;

[0006] 2. As the bandwidth and capacity of DRAM chip 40 increase, the logic of memory controller 30 becomes increasingly complex. In addition, there are differences between the process technology of DRAM chip and logic chip 70. This solution of implementing memory controller 30 and computing processor 10 on the same wafer layer will increase the area and cost of storage computing chip, waste resources, and make it difficult to meet the needs of higher performance products. Summary of the Invention

[0007] The purpose of this invention is to provide a storage computing chip and its manufacturing method, which can save chip area and hardware resources and meet the needs of higher performance products.

[0008] To achieve the above objectives, the present invention provides a storage computing chip, which includes a logic chip, a buffer chip, and at least one layer of DRAM chip stacked vertically in sequence, wherein the logic chip and the buffer chip, and the buffer chip and the DRAM chip are directly connected through through-silicon vias and a hybrid bonding layer.

[0009] The logic chip includes a computing processor, and the buffer chip internally houses a memory controller and multiple parallel inter-chip communication bus interfaces that communicate with the memory controller. Each inter-chip communication bus interface is connected to the computing processor through several through-silicon vias (TSVs) and a hybrid bonding layer. The memory controller is connected to the DRAM chip through several TSVs.

[0010] The inter-chip communication bus interface operates at a frequency higher than that of the DRAM chip.

[0011] Optionally, each of the inter-chip communication bus interfaces is connected to the computing processor via a plurality of through-silicon vias passing through a first side of the buffer chip, a multilayer hybrid bonding layer, and a plurality of through-silicon vias passing through a first or second side of the logic chip; and / or,

[0012] The memory controller is connected to the DRAM chip through several through-silicon vias passing through the second side of the buffer chip, a multilayer hybrid bonding layer, and several through-silicon vias passing through the second side of the DRAM chip.

[0013] Optionally, the memory controller includes a built-in self-test circuit for performing a first built-in self-test on the first stacked structure after the buffer chip and the DRAM chip are stacked, and / or for performing a second built-in self-test on the second stacked structure after the logic chip, the buffer chip and the DRAM chip are stacked.

[0014] The content of the first built-in self-test is the same as the content of the second built-in self-test, or the content of the second built-in self-test is less than the content of the first built-in self-test.

[0015] Optionally, the memory controller further comprises at least one of (1) to (7) as follows:

[0016] (1) an address mapping circuit, configured to map an address range received by the inter-chip communication bus interface into the DRAM chip;

[0017] (2) a command arbitration circuit, configured to perform priority arbitration on a plurality of commands sent by the computing processor through the inter-chip communication bus interface.

[0018] (3) a timing control circuit, configured to insert appropriate delays between commands according to specification requirements of various timing parameters;

[0019] (4) a refresh management circuit, configured to perform refresh on the DRAM chip according to a refresh command transmitted by the computing processor through the inter-chip communication bus interface;

[0020] (5) an error detection and correction circuit, configured to perform error detection and correction on data read from the DRAM chip when the computing processor reads data through the inter-chip communication bus interface, and / or perform error detection and correction on data written into the DRAM chip when the computing processor writes data through the inter-chip communication bus interface;

[0021] (6) a temperature detection circuit, configured to detect temperature changes of the inter-chip communication bus interface and / or the DRAM chip, and adjust corresponding parameters according to the temperature changes;

[0022] (7) a power management circuit, configured to control the DRAM chip to enter or exit at least one low-power state.

[0023] Optionally, each inter-chip communication bus interface is connected to the computing processor through a plurality of through-silicon vias, and provides a plurality of signal channels between the memory controller and the computing processor, each signal channel using the same handshaking mechanism to realize information transmission between the computing processor and the memory controller.

[0024] Optionally, the handshaking mechanism uses a pair of handshake signals to perform communication handshaking between the computing processor and the memory controller; the plurality of signal channels comprises:

[0025] a write data channel, configured to transmit the multi-bit data signal from the computing processor to the memory controller after completing handshaking of the pair of handshake signals in the channel;

[0026] a read data lane for transmitting the multi-bit data signal from the memory controller to the compute processor upon completion of a handshake of a handshake signal pair in its lane;

[0027] a write address lane for transmitting a write address from the compute processor to the memory controller upon completion of a handshake of a handshake signal pair in its lane;

[0028] a write response lane for transmitting a write response signal from the memory controller to the compute processor upon completion of a handshake of a handshake signal pair in its lane;

[0029] a read address lane for transmitting a read address from the compute processor to the memory controller upon completion of a handshake of a handshake signal pair in its lane.

[0030] Optionally, at least one of the write data lane and the read data lane is provided with cascaded first and second register slices, the first register slice being coupled to the compute processor, each of the first and second register slices being provided with at least one stage of data register circuits, each stage of the data register circuits being configured to transmit a multi-bit data signal in parallel upon completion of a handshake of a handshake signal pair in the data lane.

[0031] Optionally, a shortest stage of data register circuits in the first register slice from the compute processor is removed from being driven by a handshake signal sent from the compute processor to the first register slice, the remaining stages of data register circuits in the second register slice and / or the first register slice being driven by the handshake signal pair in common.

[0032] Optionally, each stage of the data register circuits comprises a plurality of parallel data register branches, each of the data register branches being provided in one-to-one correspondence with each bit of the data signal and being driven by the handshake signal pair or one of the handshake signal pair.

[0033] Optionally, each of the handshake signal pair is a one-bit signal, the handshake signal pair being synchronously driven to the plurality of parallel data register branches of the data register circuits of a corresponding same stage.

[0034] Optionally, each of the data register branches comprises combinational logic and a one-bit data register coupled to the combinational logic, the handshake signal pair being synchronously driven to the combinational logic of the plurality of parallel data register branches of the data register circuits of a corresponding same stage.

[0035] Optionally, the first register slice is a forward register slice, a backward register slice or a bidirectional register slice, and the second register slice is a forward register slice, a backward register slice or a bidirectional register slice; wherein the forward register slice has forward register circuits, the backward register slice has backward register circuits, and the bidirectional register slice is combined by forward register circuits and backward register circuits.

[0036] Optionally, in the first register slice of the write data channel, the first-level data register circuit with the shortest signal path to the computing processor is located in the forward register circuit of the first register slice, and is driven by only the handshake signal received by the computing processor without the driving of the handshake signal sent by the computing processor.

[0037] In the first register slice of the read data channel, the first-level data register circuit with the shortest signal path to the computing processor is located in the backward register circuit of the first register slice, and is driven by only the handshake signal received by the computing processor without the driving of the handshake signal sent by the computing processor.

[0038] Optionally, the handshake signal pair includes a valid signal and a ready signal. Optionally, the handshake signal pair includes a valid signal and a ready signal.

[0039] Based on the same inventive concept, the present application also provides a manufacturing method of a storage computing chip as described in the present application, comprising the following steps:

[0040] providing at least one DRAM wafer and one buffer wafer formed with a memory controller and an inter-chip communication interface, vertically stacking and hybrid bonding the buffer wafer and the DRAM wafer in sequence to form a first stacked structure, and directly connecting the DRAM wafer and the buffer wafer through a through-silicon via;

[0041] performing a first built-in self-test on the first stacked structure;

[0042] providing a logic wafer formed with a computing processor, and vertically stacking and hybrid bonding the logic wafer and the first stacked structure that passes the test to form a second stacked structure, and

[0043] cutting the second stacked structure to form a storage computing chip.

[0044] Optionally, the manufacturing method of the storage computing chip further comprises: performing a second built-in self-test on the second stacked structure before cutting the second stacked structure.

[0045] The content of the first built-in self-test is the same as the content of the second built-in self-test, or the content of the second built-in self-test is less than the content of the first built-in self-test.

[0046] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0047] 1. A logic chip (Logic Die) with a computing processor, a buffer chip (Buffer Die) and at least one layer of DRAM chip (Dram Die) are vertically stacked through corresponding through-silicon vias (TSVs) and hybrid bonding layers, and the three chips can directly communicate through the TSVs. Since the pitch of the TSVs can be smaller than that of micro bumps, the chip area can be saved, the integration is high, and a large-capacity cache can be realized.

[0048] 2. The memory controller and the high-speed parallel inter-chip communication bus interface are arranged in the buffer chip, so that the logic chip can access the low-speed DRAM chip in a large number of parallel ways through the buffer chip. Not only can a high-bandwidth and large-capacity cache be provided, but also the buffer chip and the logic chip directly communicate through the multiple inter-chip communication bus interfaces (providing multiple IOs) without the need for a physical layer interface to complete the inter-chip communication, greatly reducing the hardware resource overhead.

[0049] 3. The memory controller is placed in the buffer chip, so that functions such as built-in self-test, address mapping, temperature detection, error detection and correction do not need to be crowded with the computing processor of the logic chip in the same wafer, reducing the chip area and the difficulty of wafer manufacturing.

[0050] 4. After the buffer chip and the DRAM chip are vertically stacked at the wafer level to form a first stacked structure, the first stacked structure can be subjected to a built-in self-test, and then the first stacked structure that passes the test is vertically stacked with the logic chip at the wafer level, which can avoid the problem of wasting the logic chip due to bad chips in the buffer chip and the DRAM chip when the built-in self-test is performed after the logic chip is vertically stacked, thereby saving the resources and costs of the logic chip. BRIEF DESCRIPTION OF DRAWINGS

[0051] Those skilled in the art will understand that the provided drawings are for better understanding of the present application and do not constitute any limitation on the scope of the present application. Among them:

[0052] Figure 1 is a schematic diagram of a chip stack of a storage computing chip in the prior art.

[0053] Figure 2 is a schematic diagram of a chip stack of a storage computing chip in an embodiment of the present application.

[0054] Figure 3 is a schematic diagram of an internal circuit of a memory controller in a storage computing chip according to an embodiment of the present application.

[0055] Figure 4 is a schematic diagram of a signal channel of an inter-chip communication bus interface in a storage computing chip according to an embodiment of the present application.

[0056] Figure 5 is a schematic diagram of a data channel of an inter-chip communication bus interface in a storage computing chip according to an embodiment of the present application.

[0057] Figure 6 is a schematic diagram of an example structure of an inter-chip communication bus interface in a storage computing chip during a write operation according to an embodiment of the present application.

[0058] Figure 7 is a timing diagram of an inter-chip communication bus interface in a storage computing chip during a write operation according to an embodiment of the present application. Figure 6

[0059] is a timing diagram of an internal register in an inter-chip communication bus interface in a storage computing chip during a write operation according to an embodiment of the present application. Figure 8 Figure 6 is a schematic diagram of an example structure of an inter-chip communication bus interface in a storage computing chip during a read operation according to an embodiment of the present application.

[0060] Figure 9 is a timing diagram of an internal register in an inter-chip communication bus interface in a storage computing chip during a read operation according to an embodiment of the present application.

[0061] Figure 10 Figure 8 is a schematic diagram of another example structure of an inter-chip communication bus interface in a storage computing chip during a write operation according to an embodiment of the present application.

[0062] Figure 11 is a schematic diagram of another example structure of an inter-chip communication bus interface in a storage computing chip during a read operation according to an embodiment of the present application.

[0063] Figure 12 is a schematic diagram of another example structure of an inter-chip communication bus interface in a storage computing chip during a read operation according to an embodiment of the present application. DETAILED DESCRIPTION

[0064] ​​In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon reading this disclosure that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application. It should be understood that the present application can be practiced with departure from these specific details, and that specific details can be implemented only in some embodiments. There are many

[0065] Referring to Figure 2 In one embodiment, the present application provides a memory computing chip, which includes a logic chip 70, a buffer chip 100 and at least one DRAM chip 40 stacked vertically in sequence, wherein the logic chip 70 and the buffer chip 100, and the buffer chip 100 and the DRAM chip 40 are directly connected through through-silicon vias (TSVs) and hybrid bonding (HB) layers. In other embodiments, the DRAM chip 40 includes multiple layers, and the multiple layers of DRAM chips 40 are stacked vertically to form a DRAM chip 40 stack, wherein the DRAM chips 40 in the DRAM chip 40 stack are also directly connected through TSVs and HB layers.

[0066] In one embodiment, the present application provides a memory computing chip, which includes a logic chip 70, a buffer chip 100 and at least one DRAM chip 40 stacked vertically in sequence, wherein the logic chip 70 and the buffer chip 100, and the buffer chip 100 and the DRAM chip 40 are directly connected through through-silicon vias (TSVs) and hybrid bonding (HB) layers. In other embodiments, the DRAM chip 40 includes multiple layers, and the multiple layers of DRAM chips 40 are stacked vertically to form a DRAM chip 40 stack, wherein the DRAM chips 40 in the DRAM chip 40 stack are also directly connected through TSVs and HB layers.

[0067] The logic chip 70 internally has a computing processor 10, which can have at least one processor core, and can be a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a network processor, an application processor (AP), a field programmable gate array (FPGA), a special-purpose processor, or any other type of processor with computing processing capability, and can be configured to execute instructions or software (including code, an operating system, or an application program, etc.) that can be executed by one or more computers, firmware, or a combination thereof. The logic chip 70 can be any suitable computing-capable chip, such as a conventional CPU chip, a GPU chip, or an emerging AI chip, etc.

[0068] The buffer chip 100 internally has a memory controller 30 and a plurality of parallel inter-chip communication bus interfaces 20 in communication with the memory controller 30, each of which is connected to the computing processor 10 through a plurality of through-silicon vias (TSVs) and a hybrid bonding layer (HB) (or the memory controller 30 is directly connected to the computing processor 10 through the TSVs), and can perform address, data, command, etc. transmission between the computing processor 10 and the memory controller (i.e., the memory controller 30). The memory controller 30 is connected to the DRAM chip 40 (or the DRAM chip 40 stack) through a plurality of TSVs and a hybrid bonding layer (HB), and can convert the read, write, refresh, etc. instructions issued by the computing processor 10 to the DRAM chip 40 (or the DRAM chip 40 stack) into signals recognizable by the DRAM chip 40 (or the DRAM chip 40 stack), and complete the decoding of the write address or read address between the computing processor 10 and the DRAM chip 40 (or the DRAM chip 40 stack), the conversion of the data format (such as data bit width), and the conversion of the operation command, so as to achieve the necessary control (including the control of the address signal, the data signal, and various command signals) of the refresh operation, the read-write operation, etc. access to the DRAM chip 40 (or the DRAM chip 40 stack).

[0069] The working frequency of the inter-chip communication bus interface 20 is higher than the working frequency of the DRAM chip 40. In an embodiment, the working frequency of the high-speed circuit part (e.g., the inter-chip communication bus interface 20) of the logic chip 70 and the buffer chip 100 is higher than the working frequency of the DRAM chip 40, for example, can be multiple times of the working frequency of the DRAM chip 40, and correspondingly, the data bit width of the inter-chip communication bus interface 20 is multiple (e.g., 4 times) of the data bit width of the IO interface (not shown) of the DRAM chip 40, and the data bit width of the computing processor 10 is multiple (e.g., 4 times) of the data bit width of each inter-chip communication bus interface 20.

[0070] For example, the data bit width of the IO interface of a DRAM chip 40 is 256 bits, and the DRAM chip 40 can support a lower working frequency (e.g., 50M-400M), when it adopts the architecture shown in Figure 1 In the embodiment, since the memory controller 30 and the DRAM chip 40 can be large-area and pure bonded through the TSV and the HB, and the memory controller 30 and the inter-chip communication bus interface 20 are integrated in the buffer chip 100 and vertically stacked with the logic chip 70 having the computing processor 10 and directly communicate through the TSV, in the embodiment, the IO interface of the DRAM chip 40 can be called by the memory controller 30 in a large amount and in parallel, so as to meet the high-speed communication requirement of the inter-chip communication bus interface 20 (e.g., the AXI interface) between the memory controller 30 and the computing processor 10, and when the buffer chip 100 supports a working frequency of 800M, the highest bandwidth of the communication between the buffer chip 100 and the logic chip 70 (e.g., including 4 AXI subsystems, each AXI subsystem including 4 AXI interfaces, each AXI interface supporting a maximum data bit width of 1024 bits) can reach 1024*4*4*800M. Obviously, compared with the architecture shown in Figure 1 The architecture of the embodiment greatly improves the bandwidth of the inter-chip communication between the DRAM chip 40 and the logic chip 70.

[0071] That is, compared with the architecture shown in Figure 1The shown storage computing chip, on one hand, moves the memory controller 30 out of the logic chip 70 with computing function, and makes a separate buffer chip 100, which not only can reduce the pressure of the logic chip 70, save the area of the logic chip 70, but also can reduce the manufacturing difficulty and cost of the logic chip 70, and is beneficial to make the memory controller 30 realize the storage management function of more layers of DRAM chips 40; on the other hand, the through silicon via TSV and the multiple inter-chip communication bus interfaces 20 in the buffer chip 100 are used to replace the traditional physical layer interface PHY and micro bump, and the intermediate board, which not only directly realizes high-speed inter-chip communication, but also greatly reduces the hardware resource overhead, and can also use the characteristic that the distance of the through silicon via TSV is smaller than that of the micro bump to place more inter-chip communication bus interfaces 20, realize more IOs and higher bandwidth.

[0072] In an example, each inter-chip communication bus interface 20 is connected with the computing processor 10 through a plurality of through silicon vias TSVs passing through the first side of the buffer chip 100, a plurality of mixed bonding layers HB, and a plurality of through silicon vias TSVs passing through the first side of the logic chip 70. Wherein, the first side of the buffer chip 100 is the back surface (Back) of the buffer chip 100, the memory controller 30 and other structures in the buffer chip 100 are made on the front surface (Face) of the buffer chip 100, the first side of the logic chip 70 is the back surface (Back) of the logic chip 70, the computing processor and other structures in the logic chip 70 are made on the front surface (Face) of the logic chip 70, at this time, the buffer chip 100 and the logic chip 70 are bonded back to back (B2B) through the through silicon via TSV and the mixed bonding layer.

[0073] Wherein, the through silicon via TSV in the buffer chip 100 can include a through-type through silicon via and / or a half-insertion-type through silicon via, the through-type through silicon via penetrates from the back surface of the buffer chip 100 to the front surface of the buffer chip 100, and both the front surface and the back surface of the through-type through silicon via are exposed to the buffer chip 100 for electrical contact between the corresponding mixed bonding layer HB of the buffer chip 100 and the logic chip 70, the half-insertion-type through silicon via penetrates from the front surface of the buffer chip 100 to a certain depth of the buffer chip 100, and is electrically connected with the inter-chip communication bus interface 20 and other electrical structures on the front surface of the buffer chip 100, the back surface of the half-insertion-type through silicon via is exposed to the back surface of the buffer chip 100 for electrical contact between the corresponding mixed bonding layer HB of the buffer chip 100 and the logic chip 70.

[0074] The through-silicon vias (TSVs) in the logic chip 70 can include through- silicon vias and / or semi-inserted through-silicon vias, the through-silicon vias penetrating through the back side of the logic chip 70 to the front side of the logic chip 70, both the front side and the back side of the through-silicon vias being exposed by the logic chip 70 for electrically contacting the corresponding hybrid bonding layers HB between the buffer chip 100 and the logic chip 70, the semi-inserted through-silicon vias penetrating through the front side of the buffer chip 100 to a certain depth in the logic chip 70 and electrically connected to the computing processor 10 and other electrical structures on the front side of the logic chip 70, the back side of the semi-inserted through-silicon vias being exposed by the back side of the logic chip 70 for electrically contacting the corresponding hybrid bonding layers HB between the buffer chip 100 and the logic chip 70.

[0075] Optionally, at least some of the through-silicon vias (TSVs) in the buffer chip 100 are vertically aligned with at least some of the through-silicon vias (TSVs) in the logic chip 70.

[0076] In an embodiment, the multi-layer hybrid bonding layer HB further includes a multi-layer metal layer, a hybrid via layer, and a hybrid pad layer.

[0077] In another example, each of the inter-chip communication bus interfaces 20 is connected to the computing processor 10 through a plurality of through-silicon vias (TSVs) penetrating through the first side of the buffer chip 100, the multi-layer hybrid bonding layer HB, and a plurality of through-silicon vias (TSVs) penetrating through the second side of the logic chip 70. Here, the first side of the buffer chip 100 is the back side (Back) of the buffer chip 100, the memory controller 30 and other structures in the buffer chip 100 are fabricated on the front side (Face) of the buffer chip 100, the second side of the logic chip 70 is the front side (Face) of the logic chip 70, the computing processor and other structures in the logic chip 70 are fabricated on the front side (Face) of the logic chip 70, and the buffer chip 100 and the logic chip 70 are back-to-front bonded (B2F) through the through-silicon vias (TSVs) and the hybrid bonding layer HB. In an embodiment, the multi-layer hybrid bonding layer HB further includes a multi-layer metal layer, a hybrid via layer, and a hybrid pad layer.

[0078] In an example, the memory controller 30 is connected with the DRAM chip 40 through a plurality of through-silicon vias (TSVs) passing through the second side of the buffer chip 100, a plurality of multi-layer hybrid bonding layers (HBs), and a plurality of through-silicon vias (TSVs) passing through the second side of the DRAM chip 40. Here, the second side of the buffer chip 100 is the front face (Face) of the buffer chip 100, the memory controller 30 and other structures in the buffer chip 100 are fabricated on the front face (Face) of the buffer chip 100, the second side of the DRAM chip 40 is the front face (Face) of the DRAM chip 40, the memory array and other structures in the DRAM chip 40 are fabricated on the front face (Face) of the DRAM chip 40, and at this time, the buffer chip 100 and the DRAM chip 40 are directly bonded (F2F) through the through-silicon vias (TSVs) and the hybrid bonding layers (HBs). The reason for selecting the F2F bonding mode for the buffer chip 100 and the DRAM chip 40 is that there are a large number of through-silicon vias (TSVs) between the buffer chip 100 and the DRAM chip 40, and the F2F bonding mode can make most of the through-silicon vias (TSVs) on the front face of the buffer chip 100 be half-inserted through-silicon vias that pass through the front face of the buffer chip 100 to a certain depth of the buffer chip 100 and are electrically connected with the memory controller 30 and other electrical structures inside the buffer chip 100, and the front face of the half-inserted through-silicon vias is exposed on the front face of the buffer chip 100 to be electrically connected with the corresponding hybrid bonding layers (HBs) between the buffer chip 100 and the DRAM chip 40, which is conducive to reducing the manufacturing difficulty of the through-silicon vias (TSVs) on the front face of the buffer chip 100 and ensuring the reliability of the buffer chip 100.

[0079] Optionally, part of the through-silicon vias (TSVs) passing through the second side of the buffer chip 100 can further vertically pass through the buffer chip 100 to be exposed on the first side of the buffer chip 100 to be bonded with the corresponding through-silicon vias (TSVs) in the logic chip 70 through the hybrid bonding layers (HBs).

[0080] Optionally, at least part of the through-silicon vias (TSVs) passing through the second side of the DRAM chip 40 can further vertically pass through the DRAM chip 40 to be exposed on the first side of the DRAM chip 40 to be bonded with the corresponding through-silicon vias (TSVs) on the second side of another DRAM chip through the hybrid bonding layers (HBs).

[0081] Further optionally, at least part of the through-silicon vias (TSVs) on the second side of the buffer chip 100 are vertically aligned with the corresponding through-silicon vias (TSVs) on the second side of the DRAM chip 40.

[0082] In an example, when the DRAM chip 40 is vertically stacked in multiple layers and the memory array and other structures in the DRAM chip 40 are fabricated on the front face (Face) of the DRAM chip 40, the buffer chip 100 and the DRAM chip 40 are directly bonded (F2F) through the through-silicon vias (TSVs) and the hybrid bonding layers (HBs) in the following manner:Figure 2 The front side of the upper DRAM chip 40 and the back side of the lower DRAM chip 40 are bonded together by the through silicon via TSV and the hybrid bonding layer HB, that is, the two adjacent DRAM chips are front-to-back bonded (F2B).

[0083] Further optionally, when the DRAM chips 40 are vertically stacked in multiple layers, the through silicon vias TSV in the DRAM chips 40 are vertically aligned with each other.

[0084] Optionally, the memory controller 30 is not only used to manage and schedule the data storage and transmission between the computing processor 10 (as a master device) and the DRAM chip 40 or the DRAM chip 40 stack (as a slave device), and to convert the read, write, refresh and other commands issued by the computing processor 10 into signals recognizable by the DRAM chip 40 (or the DRAM chip 40 stack), but also to realize various functions such as address decoding and data bit width conversion between the computing processor 10 and the DRAM chip 40 (or the DRAM chip 40 stack), built-in self-test, temperature detection, error detection and correction (ECC), etc.

[0085] In an example, the memory controller 30 can include any one or more logic circuits required, such as an address remapping circuit 300, a built-in self-test (BIST) circuit 301, a command arbitration circuit 302, a timing control circuit 303, a refresh management circuit 304, an error detection and correction (ECC) circuit 305, a temperature detection circuit 306, and a power management circuit 307, etc.

[0086] Among them, please combine Figure 2 and Figure 3 The address remapping circuit 300 is used to map the address range sent by the computing processor 10 to the inter-chip communication bus interface 20 (i.e. the address range received by the inter-chip communication bus interface 20) to the vertically stacked DRAM chips 40 (or DRAM chip 40 stack) on the buffer chip 100.

[0087] Please combine Figure 2 and Figure 3The built-in self-test circuit 301 is configured to perform a first built-in self-test on the first stacked structure after the buffer chip 100 and the DRAM chip 40 are vertically stacked at the wafer level to form the first stacked structure, and / or perform a second built-in self-test on the second stacked structure after the logic chip 70, the buffer chip 100, and the DRAM chip 40 are vertically stacked at the wafer level (the logic chip 70 can be vertically stacked with the first stacked structure, or the logic chip 70, the buffer chip 100, and the DRAM chip 40 can be directly vertically stacked) to form the second stacked structure. The first built-in self-test and the second built-in self-test can have the same content or different content.

[0088] In an example, since the logic chip 70 is a large chip with an advanced process and high cost, the buffer chip 100 at the wafer level (i.e., the buffer wafer) and the DRAM chip 40 at the wafer level (i.e., the DRAM wafer) can be vertically stacked together by a WOW (wafer on wafer) process at the wafer level to form a first stacked structure at the wafer level. The first stacked structure is mixedly bonded by TSV (through silicon via) HB (hybrid bonding) between chips. After the first stacked structure at the wafer level is formed, a first built-in self-test at the wafer level is performed by the built-in self-test circuit 301 in the memory controller 30 (during the test process, the first stacked structure can be provided with test excitation by the computing processor 10 or other test host). After the first built-in self-test is passed, the first stacked structure at the wafer level and the logic chip 70 at the wafer level (i.e., the logic wafer) are vertically stacked together by a WOW (wafer on wafer) process. The buffer chip 100 and the logic chip 70 are mixedly bonded by TSV (through silicon via) HB (hybrid bonding), thereby forming a second stacked structure at the wafer level (also referred to as a storage computing chip at the wafer level). Then, a second built-in self-test can be performed on the second stacked structure. In this way, the problem of wasting the logic chip due to the discovery of a bad chip after the logic chip 70, the buffer chip 100, and the DRAM chip 40 (or the DRAM chip 40 stacked body) are directly vertically stacked at the wafer level can be avoided.

[0089] Further optionally, the content of the second built-in self-test can be less than the content of the first built-in self-test, thereby improving the test efficiency and test cost after the logic chip 70 is stacked. For example, the content of the first built-in self-test includes a comprehensive test of the DRAM chip 40 or includes a comprehensive test of the DRAM chip 40 and a self-test of the buffer chip 100. The content of the second built-in self-test can include a test of the communication function between the logic chip 70 and the buffer chip 100, and / or an inspection test of the performance parameters of the DRAM chip 40.

[0090] In addition, after the second built-in self-test is completed, the wafer-level second stacked structure is cut to obtain a plurality of discrete memory computing chips. In other embodiments, the memory computing chips obtained after cutting and packaging can also be further subjected to other tests (e.g., FT tests).

[0091] Please refer to Figure 2 and Figure 3 , the command arbitration circuit 302 is configured to prioritize and schedule a plurality of commands (or "requests") sent by the computing processor 10 through the inter-chip communication bus interface 20, so that the commands are executed in sequence.

[0092] Please refer to Figure 2 and Figure 3 , the timing control circuit 303 is configured to insert appropriate delays between commands according to the specification requirements of various timing parameters.

[0093] Please refer to Figure 2 and Figure 3 , the refresh management circuit 304 is configured to refresh the DRAM chip 40 (or the DRAM chip 40 stack) according to the refresh command transmitted by the computing processor 10 through the inter-chip communication bus interface 20. The refresh management circuit 304 can be configured to interleave the refresh operation of the DRAM chip 40 with normal requests (e.g., read and write requests) and avoid the problem of high latency caused by the refresh operation.

[0094] Please refer to Figure 2 and Figure 3 , the error detection and correction circuit 305 is configured to perform error detection and correction (ECC) on the data read from the DRAM chip 40 (or the DRAM chip 40 stack) when the computing processor 10 reads data through the inter-chip communication bus interface 20, and / or perform error detection and correction on the data written into the DRAM chip 40 (or the DRAM chip 40 stack) when the computing processor 10 writes data through the inter-chip communication bus interface 20.

[0095] Please refer to Figure 2 and Figure 3 , the temperature detection circuit 306 is configured to detect the temperature change of the inter-chip communication bus interface 20 and / or the DRAM chip 40 (or the DRAM chip 40 stack), and adjust the corresponding parameters according to the detected temperature change, such as adjusting the self-refresh frequency (or the refresh period), adjusting the working mode, etc.

[0096] Please refer to Figure 2 and Figure 4 , the power management circuit 307 is configured to control the DRAM chip 40 (or the DRAM chip 40 stack) to enter or exit at least one low-power state.

[0097] Please refer to Figure 4 and Figure 4 The inter-chip communication bus interface 20 can provide multiple signal channels (e.g., between the computing processor 10 and the memory controller 30) Figure 4 As shown in 20a-20e, each signal channel uses the same handshake mechanism to realize the information transfer between the computing processor 10 and the memory controller 30. This handshake mechanism uses a handshake signal pair (which consists of a handshake signal sent by the computing processor 10 to the memory controller 30 and another handshake signal sent by the memory controller 30 to the computing processor 10, such as a valid signal and a ready signal) to perform the communication handshake between the computing processor 10 and the memory controller 30.

[0098] Optionally, each inter-chip communication bus interface 20 includes at least one of a write address channel 20a, a write data channel 20b, a write response channel 20c, a read address channel 20d, and a read data channel 20e. Each signal channel contains a set of information signals and a handshake signal pair, and each signal channel uses the handshake signal pair within the signal channel to perform a handshake. For example, the handshake signal pair can be a valid signal and a ready signal.

[0099] Please refer to Figure 4 The write address channel 20a is used to transmit the write address (i.e., the starting address of the data to be written) waddr from the computing processor 10 to the memory controller 30 after completing the handshake between the write address valid signal awvalid and the write address ready signal awready in this channel. The write address valid signal awvalid is sent by the computing processor 10 to the memory controller 30; awvalid = 1 indicates that the write address and control information in the write address channel 20a are valid, and awvalid = 0 indicates that the write address and control information in the write address channel 20a are invalid. The write address ready signal awready is sent by the memory controller 30 to the computing processor 10; awready = 1 indicates that the memory controller 30 is ready to receive the write address and control information in the write address channel 20a, and awready = 0 indicates that the memory controller 30 is not yet ready to receive the write address and control information in the write address channel 20a. The transmission of the write address waddr in the write address channel 20a only actually occurs when awready = 1 and awvalid = 1.

[0100] Please refer to Figure 4The write data channel 20b is used to transmit the write data signal (i.e. data to be written) wdata of multiple bits (e.g. n bits, n is an integer greater than 1) from the computing processor 10 to the memory controller 30 after the handshake of the write data valid signal wvalid and the write data ready signal wready in the channel is completed. The write data channel 20b can include a data bus of 8-1024 bit (i.e. n = 8-1024) data bit width, such as 8 bit, 16 bit, 32 bit, 64 bit, 128 bit, 256 bit, 512 bit or 1024 bit. The write data channel 20b can support burst transmission to transmit multiple blocks of data continuously in one transaction. The write data channel 20b can identify the last data transmission cycle of a burst transmission by the write end signal wlast. The write data channel 20b can specify the byte lane containing valid information in its data bus by the write byte enable signal wstrb (Write strobes). The write data valid signal wvalid is sent from the computing processor 10 to the memory controller 30, wvalid = 1 indicates that the write data signal wdata (n bit) and control information in the write data channel 20b are valid, and wvalid = 0 indicates that the write data signal wdata (n bit) and control information in the write data channel 20b are invalid. The write data ready signal wready is sent from the memory controller 30 to the computing processor 10, wready = 1 indicates that the memory controller 30 is ready to receive the write data signal wdata (n bit) and control information in the write data channel 20b, and wready = 0 indicates that the memory controller 30 is not ready to receive the write data signal wdata (n bit) and control information in the write data channel 20b. Only when wready = 1 and wvalid = 1, the transmission of the write data signal wdata (n bit) in the write data channel 20b actually occurs.

[0101] Please refer to Figure 4The write response channel 20c is used to transmit the write response status signal wresp from the memory controller 30 to the computing processor 10 to indicate that the write data operation is completed after the handshake of the write response valid signal bvalid and the write response ready signal bready in the channel is completed. The write response valid signal bvalid is sent from the memory controller 30 to the computing processor, bvalid = 1 indicates that the write response status signal wresp and the control information in the write response channel 20c are valid, and bvalid = 0 indicates that the write response status signal wresp and the control information in the write response channel 20c are invalid. The write response ready signal bready is sent from the computing processor 10 to the memory controller 30, bready = 1 indicates that the computing processor is ready to receive the write response status signal wresp and the control information in the write response channel 20c, and bready = 0 indicates that the computing processor 10 is not ready to receive the write response status signal wresp and the control information in the write response channel 20c. Only when bready = 1 and bvalid = 1, the transmission of the write response status signal wresp in the write response channel 20c really occurs. wresp = 1 indicates that the write data signal wdata (which is n bit) is written successfully, and wresp = 0 indicates that the write data signal wdata (which is n bit) is written unsuccessfully.

[0102] Please refer to Figure 2 The read address channel 20d is used to transmit the read address (i.e. the start address of the data to be read) raddr from the computing processor 10 to the memory controller 30 after the handshake of the read address valid signal arvalid and the read address ready signal arready in the channel is completed. The read address valid signal arvalid is sent from the computing processor 10 to the memory controller 30, arvalid = 1 indicates that the read address and the control information in the read address channel 20d are valid, and arvalid = 0 indicates that the read address and the control information in the read address channel 20d are invalid. The read address ready signal arready is sent from the memory controller 30 to the computing processor 10, arready = 1 indicates that the memory controller 30 is ready to receive the read address and the control information in the read address channel 20d, and arready = 0 indicates that the memory controller 30 is not ready to receive the read address and the control information in the read address channel 20d. Only when arready = 1 and arvalid = 1, the transmission of the read address raddr in the read address channel 20d really occurs.

[0103] Please refer to Figure 4The read data channel 20e is used to transmit the read data signal (i.e. data to be read) rdata of multiple bits (e.g. n bits) from the memory controller 30 to the computing processor 10 after the handshake of the read data valid signal rvalid and the read data ready signal rready in the channel is completed. The read data channel 20e can include a data bus of 8-1024 bit (i.e. n = 8-1024) data bit width, such as 8 bit, 16 bit, 32 bit, 64 bit, 128 bit, 256 bit, 512 bit or 1024 bit. The read data channel 20e can support burst transmission to transmit multiple blocks of data continuously in one transaction. The read data channel 20e can identify the last data transmission cycle of a burst transmission by the read last signal rlast. The read data valid signal rvalid is sent from the memory controller 30 to the computing processor 10, where rvalid = 1 indicates that the read data signal rdata (n bit) and control information in the read data channel 20b are valid, and rvalid = 0 indicates that the read data signal rdata (n bit) and control information in the read data channel 20b are invalid. The read data ready signal rready is sent from the memory controller 10 to the computing processor 30, where rready = 1 indicates that the computing processor 10 is ready to receive the read data signal rdata (n bit) and control information in the read data channel 20b, and rready = 0 indicates that the computing processor 10 is not ready to receive the read data signal rdata (n bit) and control information in the read data channel 20b. The transmission of the read data signal rdata in the read data channel 20b actually occurs only when rready = 1 and rvalid = 1.

[0104] In the inter-chip communication bus interface 20, the data bit width is large (e.g. 1024 bit), and each bit needs to form a TSV via between the buffer chip 100 and the logic chip 70. The arrangement of these TSV vias is a lateral arrangement. The data channels in the layout correspond to the positions of the TSVs, which are relatively far apart, and thus additional delay is introduced. Moreover, the buffer chip 100 and the logic chip 70 can work at different process corners, and the buffer chip 100 works at a high-frequency clock, while the DRAM chip 40 works at a low-frequency clock, which can cause some circuits (e.g. voltage converters level shifter) to introduce corresponding delay. Thus, under the condition of high-speed TSV communication, the timing in each data channel of the inter-chip communication bus interface 20 is difficult to converge using the conventional handshake mechanism.

[0105] Based on this, in an example, please refer toFigure 5 and Figure 5 In at least one data lane (which can be a write data lane, or a read data lane, or both a write data lane and a read data lane) of the inter-chip communication bus interface 20, a first register slice 201 and a second register slice 202 are cascaded, the first register slice 201 is further coupled to the compute processor 10, and the second register slice 202 is further coupled to the memory controller 30. Each of the first register slice 201 and the second register slice 202 is provided with at least one stage of data register circuits 200a, each stage of the data register circuits 200a is configured to transmit the multi-bit data signal data in parallel after completing the handshake of a handshake signal pair (e.g., a valid signal valid and a ready signal ready) in the data lane.

[0106] In which, the shortest signal path between the first register slice 201 and the compute processor 10 is removed from driving the handshake signal pair sent by the compute processor 10 to the first register slice 201 (i.e., the handshake signal pair sent by the compute processor 10 to the memory controller 30), and the remaining stages of data register circuits 200a in the second register slice 202 and / or the first register slice 201 are all driven by the handshake signal pair.

[0107] Thus, by reducing the number of handshake signals sent by the compute processor 10 in the data lane (i.e., reducing the number of through-silicon via (TSV) paths driven by the handshake signals sent by the compute processor 10 in the data lane), the inter-chip timing is converged as soon as possible when the buffer chip 100 and the logic chip 70 are vertically stacked.

[0108] In an example, please refer to Figure 6When the data signal is an n-bit signal, each stage of data register circuit 200a includes n parallel data register branches in the first register slice 201 and the second register slice 202 of the corresponding data lane of the inter-chip communication bus interface 20, each data register branch corresponding to each bit of the data signal data and driven by one of the handshake signal pair. Each handshake signal of the handshake signal pair is a 1-bit signal, and the handshake signal pair can synchronously drive the n parallel data register branches of the corresponding stage of data register circuit 200a. In further embodiments, each data register branch includes a combinational logic comb and a 1-bit data register data reg coupled to the combinational logic comb, and the handshake signal pair (e.g., valid and ready signals) synchronously drives the combinational logic comb of the n parallel data register branches of the corresponding stage of data register circuit 200a. For example, when n = 1024 and the handshake signal pair is valid and ready signals, each stage of data register circuit 200a can transmit 1024-bit data signal data in parallel under the drive of 1-bit valid signal and / or 1-bit ready signal.

[0109] Optionally, referring to Figure 9 each stage of data register circuit 200a in the first register slice 201 and the second register slice 202 further includes a first handshake signal transmission circuit 200b and a second handshake signal transmission circuit 200c. The first handshake signal transmission circuit 200b is configured to transmit one of the handshake signals, and the second handshake signal transmission circuit 200c is configured to transmit the other handshake signal.

[0110] In this embodiment, the design of two-stage register slices is inserted in the corresponding data channel of the inter-chip communication bus interface 20, and the driving of the same handshake signal is reduced for each data register branch in the first-stage data register circuit 200a, which has the shortest signal path with the computing processor 10. Although this way increases the toggle times of the cache data of the first-stage data register circuit 200a, it does not affect the handshake of the handshake signal pair (such as the valid and ready signals) in the data channel, and since the first-stage data register circuit 200a reduces the driving of the handshake signal (the valid signal when writing data, and the ready signal when reading data) sent by the computing processor 10, the number of loads of the handshake signal (i.e., the number of TSV paths driven by the handshake signal, each TSV path including a TSV and a data register branch) can be reduced, thereby reducing the timing pressure of the communication handshake in the data channel, facilitating the timing convergence of the data channel communication handshake as soon as possible, supporting large data bit width and high-speed synchronous transmission of inter-chip data between the logic chip 70 and the buffer chip 100, and ensuring the accuracy and stability of the data. In addition, the remaining-stage data register circuits are still driven by the handshake signal pair (such as the valid and ready signals) in the data channel, which can prevent additional power consumption caused by frequent toggling of data.

[0111] Please refer to Figures 11-12 、 Figure 5 and Figure 11 The first register slice 201 can be a forward register slice (Forward Register slice) FR, a backward register slice (Backward Register slice) BR, or a bidirectional register slice (Full Register slice), which is not limited in the present application.

[0112] The forward direction is the direction in which the data source sends data data to the data destination. Please refer to Figure 11 and Figure 5 The forward register slice has a forward register circuit FR, which includes a first-stage data register circuit 200a, a first handshake signal transmission circuit 200b, and a second handshake signal transmission circuit 200c. The data register circuit 200a has n data register branches, each of which is composed of a combination logic comb0 and a 1-bit data register wdata reg0 (for the sake of clarity, Figure 12The data register circuit 200a has n data register branches, each of which is composed of combinatorial logic comb 1 and a 1-bit data register rdata reg 1 (for the sake of clarity of the drawing, only one data register branch in the data register circuit is shown). Each data register branch is capable of strobing the 1-bit data signal data transmitted thereby. The first handshake signal transmission circuit 200b is composed of combinatorial logic comb 2 and a first handshake signal register valid reg 0, and is used to transmit one of the handshake signals (e.g., the valid signal valid) and strobe the handshake signal during transmission. The second handshake signal transmission circuit 200c is composed of combinatorial logic comb 4, and is used to transmit the other handshake signal (e.g., the ready signal ready) in the handshake signal pair. The forward register slice FR is capable of strobing both the n-bit data signal data and one of the handshake signals (e.g., the valid signal valid) in the data lane.

[0113] The backward is the direction in which the data receiving end transmits the handshake signal (e.g., the ready signal ready) to the data sending end. The backward register slice has a backward register circuit BR, which includes a data register circuit 200a, a first handshake signal transmission circuit 200b, and a second handshake signal transmission circuit 200c. The data register circuit 200a has n data register branches, each of which is composed of combinatorial logic comb 1 and a 1-bit data register rdata reg 1 (for the sake of clarity of the drawing, only one data register branch in the data register circuit is shown). Each data register branch is capable of strobing the 1-bit data signal data transmitted thereby. Figure 9 Figure 5 The first handshake signal transmission circuit 200b is composed of combinatorial logic comb 3 and a first handshake signal register valid reg 1, and is used to transmit one of the handshake signals (e.g., the valid signal valid) and strobe the handshake signal during transmission. The second handshake signal transmission circuit 200c is composed of combinatorial logic comb 5 and a second handshake signal register ready reg 0, and is used to transmit the other handshake signal (e.g., the ready signal ready) in the handshake signal pair and strobe the handshake signal during transmission. The backward register slice BR is capable of strobing both the handshake signal pair and the n-bit data signal data in the data lane, so as to prevent data from being missed or repeatedly sampled. Figure 6

[0114] The backward register slice BR is capable of strobing both the handshake signal pair and the n-bit data signal data in the data lane, so as to prevent data from being missed or repeatedly sampled. Figure 9 Figure 6 Figure 9 ​​​​, the bidirectional register slice is combined by the forward register circuit FR and the backward register circuit BR, and includes the first handshake signal transmission circuit 200b, the second handshake signal transmission circuit 200c and two-stage cascaded data register circuits 200a. The first handshake signal transmission circuit 200b in the bidirectional register slice can be sequentially coupled by the combinational logic comb2, the first handshake signal register valid reg0, the combinational logic comb3 and the first handshake signal register valid reg1, and can beat the first handshake signal (for example, the valid signal valid). The second handshake signal transmission circuit 200c in the bidirectional register slice can be sequentially coupled by the combinational logic comb4, the second handshake signal register ready reg0, the combinational logic comb5, and can beat the second handshake signal (for example, the ready signal ready). Each stage of the data register circuit 200a in the bidirectional register slice has n data register branches (for the sake of clear illustration, Figure 5 and Figure 6 only one data register branch is shown in each of

[0115] Similarly, please refer to Figure 9 , Figures 11-12 , Figure 6 and Figure 9 , the second register slice 202 can be a forward register slice (Forward Register slice) FR, a backward register slice (Backward Register slice) BR or a bidirectional register slice (Full Register slice), and the present application does not make specific limitation thereon. The second register slice 202 and the first register slice 201 adopt the same circuit design, and can also adopt different circuit designs. For example, in the examples shown in Figure 11 and Figure 12 , the second register slice 202 and the first register slice 201 both adopt the circuit design of the bidirectional register slice; in the example shown in Figures 2-8 , the second register slice 202 and the first register slice 201 both adopt the circuit design of the forward register slice; in the example shown inFigure 11 In the illustrated example, the second register slice 202 employs the same backward register slice circuit design as the first register slice 201. In other examples, the first register slice 201 employs a forward register slice circuit design, the second register slice 202 employs a bidirectional register slice circuit design, or the first register slice 201 employs a bidirectional register slice circuit design and the second register slice 202 employs a backward register slice circuit design, etc.

[0116] In the present embodiment, please refer to Figures 2-6 and Figure 6 The inter-slice communication bus interface 20 has a write data channel 20b in which the two-stage register slices of the first register slice 201 and the second register slice 202 are inserted, the first register slice 201 is coupled between the computing processor 10 and the second register slice 202, and the second register slice 202 is coupled between the first register slice 201 and the memory controller 30. The first-stage data register circuit 200a in the first register slice 201 which has the shortest signal path between the computing processor 10 is removed from the driving of the write data valid signal wvalid sent by the computing processor 10, and the rest of the stage data register circuits 200a are commonly driven by the corresponding write data valid signal wvalid and the write data ready signal wready. Compared with the rest of the stage data register circuits 200a, the first-stage data register circuit 200a in the first register slice 201 which has the shortest signal path between the computing processor 10 reduces the driving of the write data valid signal wvalid (i.e. the number of loads of the write data valid signal wvalid).

[0117] In an example, please refer to Figure 7, the first register slice 201 and the second register slice 202 are both designed as bidirectional register slices, the first-stage data register circuit in the first register slice 201 with the shortest signal path between the first register slice 201 and the computing processor 10 is a data register circuit 200a in the forward register circuit FR of the first register slice 201, which has n data register branches, each of which is composed of a combinational logic comb0 and a write data register wdata reg0 in the first register slice 201, and each of which is driven by only the write data ready signal wready. The remaining-stage data register circuits include: (1) a data register circuit 200a in the backward register circuit BR of the first register slice 201, which has n data register branches (further, each of which is composed of a combinational logic comb1 and a write data register wdata reg1 in the first register slice 201), and each of which is driven by the write data valid signal wvalid and the write data ready signal wready; (2) a data register circuit 200a in the forward register circuit FR of the second register slice 202, which has n data register branches (further, each of which is composed of a combinational logic comb0 and a write data register wdata reg0 in the second register slice 202), and each of which is driven by the write data valid signal wvalid and the write data ready signal wready; (3) a data register circuit 200a in the backward register circuit BR of the second register slice 202, which has n data register branches (further, each of which is composed of a combinational logic comb1 and a write data register wdata reg1 in the second register slice 202), and each of which is driven by the write data valid signal wvalid and the write data ready signal wready. Comparing the first-stage data register circuit 200a (further, which has n combinational logics comb0 and n write data registers wdata reg0, one comb0 and one wdata reg0 constitute one data register branch) in the first register slice 201 and the second register slice 202, it can be found that the first-stage data register circuit 200a in the first register slice 201 is driven by only the write data ready signal wready without the write data valid signal wvalid, while the first-stage data register circuit 200a in the second register slice 201 is driven by both the write data valid signal wvalid (see the red line in FIG. 6) and the write data ready signal wready. Figure 5

[0118] ​When the computing processor 10 writes data to the DRAM chip 40 (or DRAM chip 40 stack) through the inter-chip communication bus interface 20 and the memory controller 30, the write timing in the inter-chip communication bus interface 20 is as shown in Figures 6-8 , the signal timing of the write response channel 20c and the first register slice 201 in the write data channel 20b of the inter-chip communication bus interface 20 is as shown in Figure 8 . Please refer to Figure 5 (especially the red box part in Figure 11 ) for details. As can be seen, when wvalid is 0, the toggle of the data cached in the data register wdata_reg0 (i.e. the data register in the data register circuit 200 with the shortest signal path to the computing processor 10) in the first register slice 201 caused by the toggle of the wdata provided by the computing processor 10 will increase the power consumption to a certain extent, but will not affect the handshake of wvalid and wready in the write data channel. In addition, since the combination logic comb0 coupled to the data register wdata_reg0 omits the driving of wvalid, the number of TSV paths between the buffer chip 100 and the logic chip 70 is reduced, which can reduce the timing pressure of the handshake of the write data channel 20b, facilitate the timing convergence of the write data channel 20b, support the large data bit width and high-speed synchronous transmission of inter-chip data between the buffer chip 100 and the logic chip 70, and ensure the accuracy and stability of the writing of data from the computing processor 10 to the memory controller 30 and the DRAM chip 40 (or DRAM chip 40 stack). In addition, the data register circuit in the second register slice 202 is still driven by the wvalid and wready signals, which can prevent the additional power consumption caused by frequent toggling of data.

[0119] In another example, please refer to Figure 6 and Figure 5, the first register slice 201 and the second register slice 202 both adopt the circuit design of the forward register slice. Among them, the data register circuit 200a in the first register slice 201 has the shortest signal path between the data register circuit 200a and the computing processor 10, and has n data register branches (further, each data register branch is composed of the corresponding combination logic comb0 and the write data register wdata reg0 in the first register slice 201), and each data register branch is driven by the write data ready signal wready. The data register circuit 200a in the second register slice 202 has n data register branches (further, each data register branch is composed of the corresponding combination logic comb0 and the write data register wdata reg0 in the second register slice 202), and each data register branch is driven by the write data valid signal wvalid and the write data ready signal wready. This example not only can realize the wvalid and wready handshake in the write data channel, reduce the timing pressure of the write data channel handshake, and be more conducive to the timing convergence of the write data channel, thereby supporting the large data bit width and high-speed synchronous transmission of the inter-chip data between the buffer chip 100 and the logic chip 70, guaranteeing the accuracy and stability of the data, but also has a simpler circuit and lower circuit cost compared with the example shown in Figure 9 .

[0120] In this embodiment, please refer to Figure 12 , Figure 9 and Figure 9 , the inter-chip communication bus interface 20 has a read data channel 20e, in which two levels of register slices, the first register slice 201 and the second register slice 202, are inserted, the first register slice 201 is coupled between the computing processor 10 and the second register slice 202, and the second register slice 202 is coupled between the first register slice 201 and the memory controller 30. The first register slice 201 has the shortest signal path between the data register circuit 200a and the computing processor 10, and the first register slice 201 is removed from the driving of the read data ready signal rready sent by the computing processor 10 in the handshake signal pair (such as rvalid / rready), and the rest of the data register circuit 200a is driven by the corresponding read data valid signal rvalid and the read data ready signal rready.

[0121] In an example, please refer to Figure 10, the first register slice 201 and the second register slice 202 are both designed as bidirectional register slices, and the data register circuit 200a in the first register slice 201 closest to the signal path of the computing processor 10 is the data register circuit in the backward register circuit BR of the first register slice 201, which has n data register branches (further, each data register branch is composed of the corresponding combinational logic comb1 and the read data register rdata reg1 in the first register slice 201). The remaining level data register circuits include: (1) the data register circuit 200a in the forward register circuit FR of the first register slice 201, which has n data register branches (further, each data register branch is composed of the corresponding combinational logic comb0 and the read data register rdata reg0 in the first register slice 201), and each data register branch is driven by the read data valid signal rvalid and the read data ready signal rready; (2) the data register circuit 200a in the backward register circuit BR of the second register slice 202, which has n data register branches (further, each data register branch is composed of the corresponding combinational logic comb1 and the read data register rdata reg1 in the second register slice 202), and each data register branch is driven by the read data valid signal rvalid and the read data ready signal rready; (3) the data register circuit 200a in the forward register circuit FR of the second register slice 202, which has n data register branches (further, each data register branch is composed of the corresponding combinational logic comb0 and the read data register rdata reg0 in the second register slice 202), and each data register branch is driven by the read data valid signal rvalid and the read data ready signal rready. Comparing the data register circuit 200a closest to the computing processor 10 in the first register slice 201 (each data register branch of which is composed of the corresponding combinational logic comb1 and the read data register rdata reg1) with the data register circuit 200a in the second register slice 201, it can be found that the data register circuit 200a in the first register slice 201 has no driving of the read data ready signal rready provided by the computing processor 10, while the data register circuit 200a in the second register slice 201 is driven by the read data ready signal rready (see the red line in FIG. 1) and the read data valid signal rvalid provided by the first register slice 201. Figure 9

[0122] ​When the computing processor 10 reads data from the DRAM chip 40 (or DRAM chip 40 stack) through the inter-chip communication bus interface 20 and the memory controller 30, the signal timing of the first register slice 201 in the read data channel 20e of the inter-chip communication bus interface 20 is as shown in Figure 10 . Please refer to the red box part of Figure 12 and Figure 2 , it can be seen that when ready_reg0 is 0, the toggle of the nbit read data rdata provided by the memory controller 30 will also cause the data cached by the data register rdata_reg1 (i.e. the data register in the first level data register circuit 200a with the shortest signal path between the computing processor 10) inside the first register slice 201 to toggle, which will bring a certain increase in power consumption, but does not affect the handshake of the handshake signal pair rvalid and rready in the read data channel, and since each data register branch in the level data register circuit 200 (further, the data register branch is composed of the combinational logic comb1 coupled to the read data register rdata_reg1) omits the driving of rready sent by the computing processor 10 in the handshake signal pair, the number of rready driving load is reduced (i.e. the number of TSV paths between the buffer chip 100 and the logic chip 70 for rready driving buffer is reduced), which in turn can reduce the timing pressure of the read data channel handshake, and is more conducive to the timing convergence of the read data channel, and in turn can support large data bit width, high-speed synchronous transmission of inter-chip data between the buffer chip 100 and the logic chip 70, and guarantee the accuracy and stability of the computing processor 10 reading data from the DRAM chip 40 (or DRAM chip 40 stack). In addition, the data register circuit 200a in the second register slice 202 is still driven by the handshake signal pair rvalid and rready, which can prevent additional power consumption caused by frequent data toggling.

[0123] In another example, please refer to ​The first register slice 201 and the second register slice 202 are both designed by the circuit of the backward register slice. The data register circuit 200a in the first register slice 201 with the shortest signal path between the first register slice 201 and the computing processor 10 has n data register branches, and each data register branch is further composed of the corresponding combinational logic comb1 and the read data register rdata reg1 in the first register slice 201, so that the driving of the read data ready signal rready provided by the computing processor 10 is reduced. The data register circuit 200a in the second register slice 202 has n data register branches, and each data register branch is further composed of the corresponding combinational logic comb1 and the read data register rdata reg1 in the second register slice 202, so that each data register branch of the data register circuit 200a in the second register slice 202 is driven by the read data valid signal rvalid and the read data ready signal rready.

[0124] In the embodiment, the two-stage register slices are arranged in the corresponding data channel of the inter-chip communication bus interface, and the data register circuit with the shortest signal path between the first register slice 201 and the computing processor 10 is reduced in driving of the handshake signal sent by the computing processor. Although this way increases the toggle times of the multi-bit data signal cached by the data register circuit, it does not affect the handshake of the handshake signal pair in the data channel. Moreover, the data register circuit with the shortest signal path between the first register slice 201 and the computing processor 10 removes the driving of the handshake signal sent by the computing processor, thereby reducing the number of data registers (i.e., the number of loads) driven by the handshake signal, and further reducing the timing pressure of the communication handshake in the data channel, which is beneficial to quickly complete the timing convergence of the data channel, supports the inter-chip data transmission with large data bit width and high speed synchronization, and guarantees the accuracy and stability of the data. The remaining data register circuits are still driven by the handshake signal pair, which can prevent the extra power consumption caused by the frequent toggle of the cached data.

[0125] Please refer to ​ The embodiment also provides a manufacturing method of the storage computing chip, which comprises the following steps:

[0126] First, at least one DRAM wafer (i.e. wafer-level DRAM chip 40) and a buffer wafer (i.e. wafer-level buffer chip 100) are provided, and the buffer wafer and the DRAM wafer are vertically stacked and hybrid bonded in sequence to form a wafer-level first stacked structure, wherein in the first stacked structure, the DRAM wafer (i.e. wafer-level DRAM chip 100) and the buffer wafer (i.e. wafer-level buffer chip 100) are directly connected through through-silicon vias (TSVs) and hybrid bonding layers (HBs); wherein each DRAM wafer includes a plurality of DRAM chips 40, and the buffer wafer includes a plurality of buffer chips 100, and each buffer chip 100 is formed with a memory controller 30 and an inter-chip communication interface 20.

[0127] Next, the wafer-level first stacked structure is subjected to a first built-in self-test, and the first built-in self-test generates a specific test vector through a built-in self-test circuit embedded in the memory controller 30 to comprehensively test the DRAM chips 40. Further optionally, the first built-in self-test can also generate a random vector and a response through the built-in self-test circuit embedded in the memory controller 30 to self-test the memory controller 30 and other related logic circuits in the buffer chip 100.

[0128] Then, a logic wafer (i.e. wafer-level logic chip 70) is provided, and the logic wafer is vertically stacked with the above-mentioned first stacked structure that has passed the first built-in self-test and is hybrid bonded through through-silicon vias (TSVs) to form a wafer-level second stacked structure (which can be referred to as a wafer-level storage computing chip), wherein the logic wafer includes a plurality of logic chips 70 (further, each logic chip 70 has a computing processor 10).

[0129] The logic chip 70 is generally a large chip of an advanced process, which requires high process and high cost. In the manufacturing method of the present embodiment, the first built-in self-test is first performed on the first stacked structure formed by vertically stacking and bonding at least one layer of DRAM chips 40 and buffer chips 100, and only after the test is passed, the logic chip 70 is further vertically stacked and bonded, which can avoid the problem in the prior art that the DRAM chips 40, the buffer chips 100 and the logic chips 70 are directly bonded and then subjected to the built-in self-test, and as a result, the logic chip is wasted when a bad chip is found.

[0130] Optionally, after the logic chip 70 is bonded to form the wafer-level second stacked structure, the manufacturing method of the storage computing chip of the present embodiment further includes: performing a second built-in self-test on the second stacked structure (i.e. wafer-level storage computing chip). The second built-in self-test can be implemented through the built-in self-test circuit embedded in the memory controller 30, and the content of the second built-in self-test can be the same as or different from that of the first built-in self-test.

[0131] Preferably, the second built-in self-test is different from and less than the first built-in self-test, thereby improving test efficiency and reducing test cost. For example, the first built-in self-test includes a full test of the DRAM chip 40 or includes a full test of the DRAM chip 40 and a self-test of the buffer chip 100; the second built-in self-test can include a test of communication function between the logic chip 70 and the buffer chip 100, and / or a spot test of performance parameters of the DRAM chip 40.

[0132] Further, after the second built-in self-test is completed, the wafer-level second stacked structure is subjected to wafer cutting to obtain a plurality of memory computing chips at the die level.

[0133] The above description is merely a description of the preferred embodiments of the present application, and is not intended to limit the scope of the present application in any way. Any modification, alteration, or improvement made by those skilled in the art based on the above disclosure should be considered to fall within the scope of the technical solutions of the present application.

Claims

1. A memory compute chip, comprising: The memory chip includes a logic chip, a buffer chip and at least one DRAM chip which are vertically stacked in sequence, and the logic chip and the buffer chip, and the buffer chip and the DRAM chip are directly connected through through silicon vias and hybrid bonding layers; The logic chip includes a computing processor, the buffer chip includes a memory controller and a plurality of parallel inter-chip communication bus interfaces which are in communication with the memory controller, each of the inter-chip communication bus interfaces is connected to the computing processor through a plurality of through silicon vias, and the memory controller is connected to the DRAM chip through a plurality of through silicon vias and hybrid bonding layers, The working frequency of the inter-chip communication bus interface is higher than the working frequency of the DRAM chip.

2. The memory computing chip of claim 1, wherein, Each of the inter-chip communication bus interfaces is connected to the computing processor through a plurality of through silicon vias penetrating the first side of the buffer chip, a plurality of hybrid bonding layers, and a plurality of through silicon vias penetrating the first side or the second side of the logic chip; and / or, The memory controller is connected to the DRAM chip through a plurality of through silicon vias penetrating the second side of the buffer chip, a plurality of hybrid bonding layers, and a plurality of through silicon vias penetrating the second side of the DRAM chip.

3. The memory computing chip of claim 1, wherein, The memory controller includes a built-in self-test circuit for performing a first built-in self-test on the first stacked structure formed after the buffer chip and the DRAM chip are stacked, and / or for performing a second built-in self-test on the second stacked structure formed after the logic chip, the buffer chip and the DRAM chip are stacked; The content of the first built-in self-test is the same as or less than the content of the second built-in self-test.

4. The memory computing chip of any of claims 1-3, wherein, The memory controller further includes at least one of the following (1) to (7): (1) an address mapping circuit for mapping the address range received by the inter-chip communication bus interface to the DRAM chip; (2) a command arbitration circuit for performing priority arbitration on a plurality of commands transmitted by the computing processor through the inter-chip communication bus interface; (3) a timing control circuit for inserting appropriate delays between commands according to the specification requirements of various timing parameters; (4) a refresh management circuit for refreshing the DRAM chip according to a refresh command transmitted by the computing processor through the inter-chip communication bus interface; (5) an error detection and correction circuit for detecting and correcting errors in the data read from the DRAM chip when the computing processor reads data through the inter-chip communication bus interface, and / or for detecting and correcting errors in the data written into the DRAM chip when the computing processor writes data through the inter-chip communication bus interface; (6) a temperature detection circuit for detecting temperature changes of the inter-chip communication bus interface and / or the DRAM chip, and adjusting the corresponding parameters according to the temperature changes; (7) a power management circuit for controlling the DRAM chip to enter and exit at least one low-power mode.

5. The storage computing chip of any of claims 1-3, wherein, Each of the slice communication bus interfaces is connected to the computing processor through a plurality of through silicon vias, and provides a plurality of signal channels between the memory controller and the computing processor, each of the signal channels using the same handshake signal pair to realize information transmission between the computing processor and the memory controller.

6. The storage compute chip of claim 5, wherein, The handshake signal pair is used to realize handshake between the computing processor and the memory controller. The plurality of signal channels includes: a write data channel, used to transmit the multi-bit data signal from the computing processor to the memory controller after handshake of the handshake signal pair in the channel is completed; a read data channel, used to transmit the multi-bit data signal from the memory controller to the computing processor after handshake of the handshake signal pair in the channel is completed; a write address channel, used to transmit a write address from the computing processor to the memory controller after handshake of the handshake signal pair in the channel is completed; a write response channel, used to transmit a write response signal from the memory controller to the computing processor after handshake of the handshake signal pair in the channel is completed; a read address channel, used to transmit a read address from the computing processor to the memory controller after handshake of the handshake signal pair in the channel is completed.

7. The storage computing chip of claim 6, wherein, At least one of the write data channel and the read data channel is provided with a first register slice and a second register slice in cascade, the first register slice is coupled to the computing processor, and each of the first register slice and the second register slice is provided with at least one level of data register circuit, each level of the data register circuit is used to transmit the multi-bit data signal in parallel after handshake of the handshake signal pair in the data channel is completed.

8. The storage computing chip of claim 7, wherein, The level of the data register circuit in the first register slice with the shortest signal path to the computing processor is removed from driving of the handshake signal in the handshake signal pair sent from the computing processor to the first register slice, and the second register slice and / or the remaining levels of data register circuit in the first register slice are commonly driven by the handshake signal pair.

9. The storage computing chip of claim 7 or 8, wherein, Each level of the data register circuit includes a plurality of parallel data register branches, each of the data register branches is arranged one-to-one with each bit of the data signal and is driven by the handshake signal pair or one handshake signal in the handshake signal pair.

10. The storage computing chip of claim 9, wherein, Each of the handshake signals in the handshake signal pair is a one-bit signal, and the handshake signal pair synchronously drives the plurality of parallel data register branches of the data register circuit in the same level.

11. The storage computing chip of claim 9, wherein, Each of the data register branches includes combinational logic and a one-bit data register coupled to the combinational logic, and the handshake signal pair synchronously drives the combinational logic in the plurality of parallel data register branches of the data register circuit in the same level.

12. The storage compute chip of any of claims 7, 8, 10-11, wherein, The first register slice is a forward register slice, a backward register slice or a bidirectional register slice, and the second register slice is a forward register slice, a backward register slice or a bidirectional register slice; wherein the forward register slice has a forward register circuit, the backward register slice has a backward register circuit, and the bidirectional register slice is combined by a forward register circuit and a backward register circuit.

13. The storage compute chip of claim 12, wherein, In the first register slice of the write data channel, the first-level data register circuit with the shortest signal path to the computing processor is located in the forward register circuit of the first register slice and is driven by only the handshake signal received by the computing processor by removing the driving of the handshake signal sent by the computing processor; In the first register slice of the read data channel, the first-level data register circuit with the shortest signal path to the computing processor is located in the backward register circuit of the first register slice and is driven by only the handshake signal received by the computing processor by removing the driving of the handshake signal sent by the computing processor.

14. The storage computing chip of any of claims 6-8, 10-11, 13, wherein, The handshake signal pair includes a valid signal and a ready signal.

15. A method of storing a manufacturing process of a computing chip, characterized by, The method comprises the following steps: providing at least one DRAM wafer and a buffer wafer, stacking and hybrid bonding the buffer wafer and the DRAM wafer vertically in sequence to form a first stacked structure, and directly connecting the DRAM wafer and the buffer wafer through a through silicon via and a hybrid bonding layer, wherein each DRAM wafer comprises a plurality of DRAM chips, the buffer wafer comprises a plurality of buffer chips, each buffer chip is formed with a memory controller and an inter-chip communication interface; performing first built-in self-test on the first stacked structure; providing a logic wafer, and vertically stacking and hybrid bonding the logic wafer and the first stacked structure that passes the test to form a second stacked structure, and directly connecting the logic wafer and the buffer wafer through a through silicon via and a hybrid bonding layer, wherein the logic wafer comprises a plurality of logic chips; cutting the second stacked structure to form a memory computing chip.

16. The manufacturing method of a memory computing chip according to claim 15, wherein, Before cutting the second stacked structure, the method further comprises performing second built-in self-test on the second stacked structure; wherein the content of the first built-in self-test is the same as the content of the second built-in self-test, or the content of the second built-in self-test is less than the content of the first built-in self-test.

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