Clock generator and method for generating clock signal

Abstract

A clock generator for generating input and output clock signals includes a clock generation circuit for generating an internal clock signal, first and second filter circuits, and an output gate. The first filter circuit receives the internal clock signal and an enable signal, and provides a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the internal clock signal. The second filter circuit receives the first filtered enable signal, provides a second filtered enable signal in response to the first filtered enable signal, and provides a delay signal as a delay of the second filtered enable signal. The output gate receives the internal clock signal from the clock generation circuit, receives the second filtered enable signal from the second filter circuit, and generates an output clock signal.

Description

Technical Field

[0001] The present invention relates to a clock generator, and in particular to a clock signal generating circuit which filters out interference in an input signal, and to a method for generating a non-interference clock signal. Background Art

[0002] Clock generators are used to provide clock signals for various circuits. In some circuits, the clock signal is provided in response to an enable signal. However, since the enable signal is provided by various other circuits, the enable circuit may have interference. As understood, interference can cause the circuit to work incorrectly or even fail in some cases.

[0003] It would be advantageous to provide a glitch-free clock generator and method therefor. Summary of the invention

[0004] This Summary is provided to introduce a selected, simplified version of the concepts that are detailed in the Detailed Description below. This Summary is not intended to identify key or essential features of the claims nor is it intended to limit the scope of the claims.

[0005] According to one embodiment, a clock generator for generating an output clock signal includes:

[0006] A clock generation circuit for generating an internal clock signal;

[0007] a first filtering circuit receiving the internal clock signal and the enable signal, and generating a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the internal clock signal;

[0008] a second filter circuit receiving the first filtered enable signal, generating a second filtered enable signal in response to the first filtered enable signal, and generating a delay signal which is a delay of the second filtered enable signal;

[0009] An output gate receives the internal clock signal from the clock generation circuit and the second filtered enable signal from the second filtering circuit, and generates an output clock signal.

[0010] For example, the first filtering circuit includes:

[0011] a first flip-flop having a first clock input terminal receiving an internal clock signal, a first data input terminal receiving an enable signal, and a first data output terminal providing a first latch signal responsive to the internal clock signal and the enable signal;

[0012] a second flip-flop having a second clock input terminal receiving the internal clock signal, a second data input terminal receiving the first latch signal from the first flip-flop, and a second data output terminal providing a second latch signal responsive to the internal clock signal and the first latch signal; and

[0013] A logic gate receives the first latch signal, the second latch signal, and the enable signal to generate a first filtered enable signal.

[0014] For example, the second filtering circuit includes:

[0015] a flip-flop circuit that receives the first filtered enable signal from the first filter circuit and provides a latched enable signal as a second filtered enable signal, the latched enable signal being a signal in which the first filtered enable signal is latched; and

[0016] A delay circuit receives the latched enable signal and provides a delayed signal.

[0017] For example, the clock generation circuit includes:

[0018] a current source enabled in response to the second filtered enable signal, generating a source current; and

[0019] An oscillator receives the source current and generates an internal clock signal, the oscillator being enabled in response to the delayed signal.

[0020] Illustratively, the delay introduced by the delay circuit is longer than the settling time of the current source.

[0021] Illustratively, the second filtering circuit further includes a selector circuit that receives the delayed signal as a selection signal, receives the first filtered enable signal and its inverted signal as data signals, and outputs the first filtered enable signal or its inverted signal as its output in response to the selection signal.

[0022] Illustratively, the output of the selector circuit is provided to the flip-flop circuit to serve as a clock signal of the flip-flop circuit.

[0023] Illustratively, the output gate comprises an AND gate.

[0024] According to another embodiment, a method for generating a non-interference clock signal includes:

[0025] An internal clock signal is generated by a clock generation circuit;

[0026] The first filter circuit receives an internal clock signal and an enable signal;

[0027] generating, by the first filtering circuit, a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the internal clock signal;

[0028] receiving, by a second filtering circuit, a first filtered enable signal;

[0029] generating, by a second filtering circuit, a second filtered enable signal responsive to the first filtered enable signal;

[0030] providing a delayed signal as a delay of the second filtered enable signal by a second filtering circuit;

[0031] receiving, by the output gate, the internal clock signal and the second filtered enable signal; and

[0032] A glitch-free clock signal based on a first logic operation of the internal clock signal and the second filtered enable signal is provided by the output gate.

[0033] Illustratively, generating the first filtered enable signal includes:

[0034] latching an enable signal by a first flip-flop circuit;

[0035] A first latch signal is generated by a first trigger circuit;

[0036] latching the first latch signal by the second flip-flop circuit;

[0037] generating a second latch signal by a second flip-flop circuit;

[0038] receiving the first latch signal, the second latch signal, and the enable signal by the logic gate; and

[0039] A first filtered enable signal based on a second logic operation of the first latch signal, the second latch signal, and the enable signal is generated by the logic gate.

[0040] For example, the method further comprises:

[0041] enabling a current source of the clock generation circuit in response to the second filtered enable signal to provide a source circuit;

[0042] receiving a source current from an oscillator of a clock generation circuit; and

[0043] An oscillator is enabled in response to the delayed signal to generate an internal clock signal.

[0044] Illustratively, providing the delay signal includes:

[0045] The second filtered enable signal is delayed by a delay circuit for a delay time, and the delay time is longer than a settling time of a current source of a clock generation circuit.

[0046] Illustratively, generating the second filtered enable signal includes:

[0047] receiving, by a third flip-flop circuit, a first filtered enable signal;

[0048] latching the first filtered enable signal by a third flip-flop circuit; and

[0049] The latched enable signal is generated by the third flip-flop circuit as the second filtered enable signal.

[0050] For example, the method further comprises:

[0051] receiving, by the selector circuit, the delayed signal, the first filtered enable signal, and an inverted signal of the first filtered enable signal; and

[0052] The first filtered enable signal or an inverted signal thereof is provided by the selector circuit as an output of the selector circuit based on the delayed signal.

[0053] For example, the method further comprises:

[0054] An output of the selector circuit is received as a clock signal of the third flip-flop circuit.

[0055] According to another embodiment, a clock generator for generating an output clock signal in response to an enable signal includes:

[0056] A clock generation circuit for generating an internal clock signal;

[0057] a first filtering circuit receiving the internal clock signal and the enable signal and generating a first filtered enable signal capable of indicating a first validity of the enable signal;

[0058] a second filtering circuit receiving the first filtered enable signal and generating a second filtered enable signal, the second filtering circuit applying a delay to the second filtered enable signal to generate a delayed signal, the clock generation circuit operating in response to the second filtered enable signal and the delayed signal; and

[0059] An output gate receives the second filtered enable signal and the internal clock signal and generates an output clock signal.

[0060] For example, the first filtering circuit includes:

[0061] a first flip-flop latching an enable signal based on an internal clock signal and providing a first latch enable signal;

[0062] a second flip-flop that receives the first latch enable signal and latches the first latch enable signal based on the internal clock signal, and generates a second latch enable signal; and

[0063] A first logic gate generates a first filtered enable signal using the enable signal, the first latch enable signal, and the second latch enable signal.

[0064] For example, the second filtering circuit includes:

[0065] A selector circuit having a data input terminal for receiving a first filter enable signal and an inverted signal of the first filter enable signal, and a selector input terminal for receiving a delay signal from a second filter circuit; and

[0066] The flip-flop has a data input terminal receiving the first filtered enable signal and a clock input terminal receiving the output signal of the selector circuit, and the flip-flop provides the latched enable signal as the second filtered enable signal.

[0067] For example, the clock generation circuit includes:

[0068] a current source receiving the second filtered enable signal and operating in response to the second filtered enable signal to provide a source current; and

[0069] The oscillator receives the source current and the delay signal, and the oscillator is enabled in response to the delay signal to generate an internal clock signal.

[0070] Illustratively, the delay applied to the second filtered enable signal is longer than a settling time of a current source of the clock generation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0072] Figure 1 is a circuit diagram of a clock generator according to an embodiment of the present invention;

[0073] Figure 2 yes Figure 1 A timing diagram of a signal in which the enable signal EN changes from low to high and from high to low during normal operation of the clock generator; and

[0074] Figure 3 yes Figure 1 A timing diagram of a signal in which the enable signal EN of a clock generator changes from low to high and there is interference when the clock generator is not operating normally. DETAILED DESCRIPTION

[0075] like Figure 1 , which shows a circuit diagram of a clock generator 100 according to an exemplary embodiment of the present invention. The clock generator 100 includes a clock generation circuit 102, a first filter circuit 104, a second filter circuit 106, and an output gate 108. The clock generation circuit 102 is configured to generate an internal clock signal CLK. In the preferred embodiment, the clock generation circuit 102 is a module clock generator, which generates an original clock signal, and is provided as an output clock signal CLK_OUT of the clock generator 100 by the output gate 108 under the control of an enable signal EN.

[0076] The first filter circuit 104 includes a first flip-flop 110, a second flip-flop 112, and a logic gate 114. The first flip-flop 110 has a clock input terminal CK, a data input terminal D, and a data output terminal Q. The clock input terminal CK of the first flip-flop 110 receives the internal clock signal CLK from the clock generation circuit 102, the data input terminal D receives the enable signal EN, and the data output terminal Q provides a first latch signal in response to the internal clock signal CLK and the enable signal EN.

[0077] Similarly, the second flip-flop 112 includes a clock input terminal CK, a data input terminal D, and a data output terminal Q. The clock input terminal CK of the second flip-flop 112 receives the internal clock signal CLK from the clock generating circuit 102, the data output terminal D receives the first latch signal from the first flip-flop 110, and the data output terminal Q provides a second latch signal in response to the internal clock signal CLK and the first latch signal.

[0078] In the preferred embodiment, each of the first flip-flop and the second flip-flop is implemented as a D flip-flop. However, in other embodiments, the first and second flip-flops can be implemented as other types of flip-flops. The first and second flip-flops 110 and 112 perform a latching operation and output a latched signal at the falling edge of the internal clock signal CLK.

[0079] The logic gate 114 has a first input terminal receiving the first latch signal from the first flip-flop 110, a second input terminal receiving the second latch signal from the second flip-flop 112, and a third input terminal receiving the enable signal EN. The logic gate 114 performs an OR operation on the input signals to generate a first filtered enable signal EN_S of the first filter circuit 104. The OR operation performed on the enable signal EN itself, the first latch signal from the first flip-flop 110 indicating the state of the enable signal EN in the previous clock cycle, and the second latch signal from the second flip-flop 112 indicating the state of the enable signal EN two clock cycles ago ensures that the enable signal EN can be passed as a valid enable signal only when it has a duration of at least two cycles of the internal clock signal CLK.

[0080] The second filter circuit 106 receives the first filtered enable signal EN_S from the first filter circuit 104 and generates a second filtered enable signal EN_Q in response. The second filter circuit 106 includes a third flip-flop 116 , a delay circuit 118 , and a selector circuit 120 .

[0081] The third flip-flop 116 has a data input terminal D for receiving the first filtered enable signal EN_S from the first filter circuit 104, a clock terminal CK for receiving the clock signal CLK_S output by the selector circuit 120, and a data output terminal Q for providing a third latch signal as the second filtered enable signal EN_Q of the second filter circuit 106. Similar to the first flip-flop 110 and the second flip-flop 112, the third flip-flop 116 can be implemented as a D flip-flop. The third flip-flop 116 provides the third latch signal EN_Q at the rising edge of the input clock signal CLK_S. Figure 1 As shown, the second filtered enable signal EN_Q is used to enable the clock generation circuit 102 .

[0082] The delay circuit 118 delays the second filtered enable signal EN_Q to provide a delayed signal EN_DLY. The delay circuit 118 can be implemented in many ways, such as a plurality of inverters (not gates) connected in series in the present embodiment.

[0083] The selector circuit 120 receives the delayed signal EN_DLY as a selection signal and receives the first filtered enable signal EN_S and its inverse signal at its first and second data input terminals, respectively. The selector circuit 120 provides the first filtered enable signal EN_S or the inverse signal of the first filtered enable signal as an output in response to the received selection signal EN_DLY. The output of the selector circuit 120 is provided to the clock input terminal of the third flip-flop 116 as described above.

[0084] The clock generation circuit 102 includes a current source 122 and an oscillator 124. The current source 122 receives a second filtered enable signal EN_Q, which operates to enable the current source 122, so that the current source generates a source current. The source current is received by the oscillator 124. The oscillator receives the delayed signal EN_DLY as an enable signal and generates an internal clock signal CLK when enabled. The current source 122 has a settling time so that the source current reaches a normal level. In the preferred embodiment, the delay time introduced by the delay circuit 118 is longer than the settling time of the current source 122. In one embodiment, the settling time of the current source 122 is about 4.3 μs.

[0085] The output gate 108 has a first input terminal receiving the second filtered enable signal EN_Q from the third flip-flop 116, and a second input terminal receiving the internal clock signal CLK from the oscillator 124 of the clock generation circuit 102. The output gate 108 generates a final output clock signal CLK_OUT in response. In the preferred embodiment, the output gate 108 includes an AND gate. In the preferred embodiment, if the delayed signal EN_DLY is high, the output clock signal CLK_OUT follows the internal clock signal CLK.

[0086] like Figure 1 As shown, each of the first, second, and third flip-flops 110, 112, and 116 has a reset terminal RB, which receives a reset bit RTB. A valid reset bit RTB resets the output terminal Q of the flip-flop. It should be understood that during the operation of the flip-flop, the reset bit RTB is invalid.

[0087] The operation of the clock generator 100 will refer to Figure 2 , Figure 3 The timing diagram is explained.

[0088] Figure 2 The figure shows the timing of multiple signals when the enable signal EN changes from “0” to “1” and from “1” to “0” when the clock generator 100 operates normally.

[0089] In the standby mode, the reset bit RTB provided to the first, second, and third flip-flops 110, 112, and 116 is low, so that the output of each flip-flop 110, 112, and 116 is reset to a low level. Since the third latch signal EN_Q provided to the third flip-flop 116 is low, the input clock signal CLK_OUT is low, which means that no clock signal is output from the clock generator 100.

[0090] At time t 21 , the reset bit RTB and the enable signal EN jump to a high position. The high enable signal EN pulls the first filtered enable signal EN_S of the first logic gate 114 to a high position. The selector circuit 120 selects the high signal EN_S as its selected output signal CLK_S, so that the output signal CLK_S presents a jump from a low position to a high position. The third flip-flop 116 thus provides a high third latch signal EN_Q. The third latch signal EN_Q activates the current source 122 of the clock generation circuit 102 to start building. However, as Figure 2 As shown, since the delayed signal EN_DLY is at a low level, the oscillator 124 of the clock generation circuit 102 will not be enabled. After the delay time, at time t 22 , the delayed signal EN_DLY jumps to a high level, and enables the oscillator 124 to generate the internal clock signal CLK. Since the second filtered enable signal EN_Q is at a high level, the output gate 108 provides the internal clock signal CLK as the output clock signal CLK_OUT. After the clock generation circuit 102 starts its normal operation, the clock generator 100 will provide the input clock signal CLK_OUT synchronously with the internal clock signal CLK. It can be seen that there is no interference in the output clock signal CLK_OUT.

[0091] At time t 23, the enable signal EN jumps from high to low. The low enable signal EN is triggered by the first flip-flop 110 at the next falling edge t 24 The first latch signal provided at the first data output terminal of the first flip-flop 110 is further latched by the second flip-flop 112 at the next falling edge t of the subsequent internal clock signal CLK. 25 The inverted signal of the low-order first filtered enable signal EN_S is provided by the selector circuit 120 as the selected signal CLK_S, which presents a transition from low to high. Due to the rising edge of the clock signal CLK_S, the third flip-flop 116 provides the state of the first filtered enable signal EN_S before the rising edge, i.e., the low-order, as the third latch signal EN_Q. The low-order second filtered enable signal EN_Q is provided to the clock generation circuit 102 to stop the generation of the clock. On the other hand, since the low-order second filtered enable signal EN_Q is provided to the output gate 108, the output clock signal CLK_OUT provided by the output gate 108 is almost immediately at time t 25 is pulled down to a low level. Figure 2 As shown, since the delay circuit will take some time to transfer the low bit from the second filtered enable signal EN_Q to the delayed signal EN_DLY, the delayed signal EN_DLY is not activated until time t 26 Only then will it jump down from a high position.

[0092] Figure 3 When the enable signal EN changes from "0" to "1" and has interference Figure 1 The timing of the signals on the nodes in the clock generator 100. At time t 31 , the enable signal EN turns high and has interference thereafter. The high bit of the enable signal EN is transmitted to the first filtered enable signal EN_S by the first logic gate 114. Since the delayed signal EN_DLY, which is the selection signal of the selector circuit 120, needs at least the delay time to turn from low to high, as long as the enable signal EN is maintained at a high level within the setup time of the third flip-flop 116, the first filtered enable signal EN_S will be selected as the output. The third flip-flop 116 provides the high bit of the first filtered enable signal EN_S before the rising edge of the output signal CLK_S from the selector circuit 120 as the second filtered enable signal EN_Q.

[0093] It should be understood that the delayed signal EN_DLY remains low before the delay time of the delay circuit 118 has passed. Therefore, since the third flip-flop 116 determines the second filtered enable signal EN_Q as a slight delay of the data input signal EN_S at each rising edge of the clock input signal CLK_S, the data output signal EN_Q of the third flip-flop 116 will be locked at a high level. This is because the rising edge of the clock input signal CLK_S (also the data input signal EN_S) always means that for the data input signal EN_S that has not been slightly delayed by the selector circuit 120, the state before the rising edge is already high, such as the next interference time t 32 At the output logic gate 108, since the delayed signal EN_DLY is still waiting for the delay time to jump to the high level, the oscillator 124 is not enabled, and the final output clock signal CLK_OUT is not affected by the interference in the enable signal EN.

[0094] The time t after the delay time of the delayed signal EN_DLY 33 The high delayed signal EN_DLY is also provided to the selector circuit 120 as a selection signal, which causes the selector circuit 120 to provide the inverted signal of the first filtered enable signal EN_S as the output CLK_S. Thus, depending on the state of the enable signal EN and thus the state of the first filtered enable signal EN_S, the clock signal CLK_S provided to the third flip-flop 116 can become high, low, or unchanged. It is noted that the decrease or no change of the signal will not change the output of the third flip-flop 116. For example, for time t 33 The rising signal shown at indicates that the first filtered enable signal EN_S is at a low level, and the low level of the first filtered enable signal EN_S will be provided as the third latch signal EN_Q, which is a low level. The low level of the second filtered enable signal EN_Q disables the clock generation circuit 102 and stops generating the internal clock signal CLK. It can be seen that during the period when the enable signal EN has interference, there is no output clock signal CLK_OUT, which means that the output clock signal CLK_OUT is not negatively affected by the interference in the enable signal EN. In the preferred embodiment, the weakening time of the current source 122 is about 1.3μs. By Figure 3 It can be seen that the clock generator 100 requires the enable signal EN to be maintained in a valid enable state and last for at least the delay time of the delay circuit 118, so that the output clock signal CLK_OUT can be provided, and any interference in the enable signal EN can be filtered out by the first and second filter circuits 104 and 106.

[0095] On the other hand, after the output clock signal CLK_OUT starts to be provided, if the enable signal EN is disturbed, Figure 2It can be understood that the internal clock signal CLK stops only when the enable signal EN is at a low level for at least two clock cycles.

[0096] Here, the operation of the clock generator 100 when the enable signal EN changes from high to low and there is interference will be described. Figure 1 As described above, the first filtered enable signal EN_S turns low only when the low enable signal EN continues for at least two falling edges of the internal clock signal CLK. The falling edge of the first filtered enable signal EN_S causes the rising edge of the selected signal CLK_S, and the rising edge of the selected signal CLK_S is further provided to the third flip-flop 116. The third flip-flop 116 thus provides the low first filtered enable signal EN_S as the third latch signal EN_Q. The third latch signal EN_Q with a low position immediately stops the current source 122 of the clock generation circuit 102 from providing the source current for generating the internal clock signal CLK. As described above, after the enable signal EN maintains a low position and passes through the duration of two falling edges of the internal clock signal CLK, the clock generation circuit 102 enters the standby mode. After that, the clock generation circuit 102 needs about 4.3 μs to restart providing the source current to generate the internal clock signal.

[0097] The clock generator 100 includes a first filter circuit 104 to filter out interference in the enable signal EN, thereby ensuring that the high enable signal can be provided to the first filtered enable signal EN_S to enable the clock generation circuit 102. As described above, the first filter circuit 104 determines the validity of the enable signal EN, and the provided first filtered enable signal EN_S can indicate the validity. The second filter circuit 106 of the clock generator 100 ensures that when the enable signal EN turns to a low level, the clock generation circuit 102 can be disabled regardless of the interference in the enable signal EN. Therefore, there is no interference in the output clock signal CLK_OUT.

[0098] Various exemplary embodiments are described herein with reference to specific illustrated examples. The illustrative examples are selected to assist those skilled in the art to form a clear understanding of and implement the various embodiments. However, the scope of systems, structures, and devices that can be constructed to include one or more embodiments, as well as the scope of methods implemented according to one or more embodiments, are not limited by the illustrative examples shown. On the contrary, those skilled in the art will understand based on this specification that many other configurations, structures, and methods can be implemented according to the various embodiments.

[0099] It should be understood that, with respect to the various positional indications used in the foregoing description of the present invention, such as top, bottom, upper, and lower, those indications are given only with reference to the corresponding drawings, and other positional relationships may be substituted when the orientation of the device changes during manufacture or operation. As mentioned above, those positional relationships are described only for the sake of clarity and are not limiting.

[0100] The foregoing description of this specification is with reference to specific embodiments and specific drawings, but the invention should not be limited thereto, but should be given by the claims. The various drawings described are exemplary and non-restrictive. In the drawings, the dimensions of the various elements may be exaggerated for illustrative purposes and may not be drawn to a specific scale. This description should also include discontinuous changes in tolerances and properties of various components and working methods. Various weakened implementations of the invention should also be included.

[0101] The word "comprising" as used in the present description and claims does not exclude other elements or steps. Unless otherwise specified, when the singular form such as "a", "an" is used to refer to a definite or indefinite element, the plural form of the element shall be included. Thus, the word "comprising" should not be understood as being limited to the items listed thereafter, nor should it be understood as excluding other elements or steps; the scope of the description "a device comprises items A and B" should not be limited to a device comprising only elements A and B. The description indicates that, for the purpose of this description, only elements A and B of the device are relevant.

[0102] It will be apparent to those skilled in the art that various detailed changes may be made without departing from the scope of the claims of the present invention.

Claims

1. A clock generator for generating an output clock signal, characterized in that: include: A clock generation circuit for generating an internal clock signal; a first filtering circuit receiving the internal clock signal and the enable signal, and generating a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the internal clock signal; a second filter circuit receiving the first filtered enable signal, generating a second filtered enable signal in response to the first filtered enable signal, and generating a delay signal which is a delay of the second filtered enable signal; an output gate receiving an internal clock signal from a clock generation circuit and a second filtered enable signal from a second filtering circuit, and generating an output clock signal; The first filtering circuit comprises: a first flip-flop having a first clock input terminal receiving an internal clock signal, a first data input terminal receiving an enable signal, and a first data output terminal providing a first latch signal responsive to the internal clock signal and the enable signal; a second flip-flop having a second clock input terminal receiving the internal clock signal, a second data input terminal receiving the first latch signal from the first flip-flop, and a second data output terminal providing a second latch signal responsive to the internal clock signal and the first latch signal; and A logic gate receives the first latch signal, the second latch signal, and the enable signal to generate a first filtered enable signal.

2. The clock generator according to claim 1, characterized in that The second filtering circuit comprises: a flip-flop circuit having a data input terminal receiving the first filtered enable signal, the flip-flop circuit providing a latched enable signal as a second filtered enable signal, the latched enable signal being a signal in which the first filtered enable signal is latched; and A delay circuit receives the latched enable signal and provides a delayed signal.

3. The clock generator according to claim 2, wherein: The second filtering circuit further includes a selector circuit, which has a selector input terminal, which receives the delayed signal as a selection signal of the selector circuit. The selector circuit also has a data input terminal that receives the first filtered enable signal and its inverted signal as a data signal. The selector circuit responds to the selection signal and outputs the first filtered enable signal or its inverted signal as its output.

4. A method for generating an interference-free clock signal, characterized in that: include: An internal clock signal is generated by a clock generation circuit; The first filter circuit receives an internal clock signal and an enable signal; generating, by the first filtering circuit, a first filtered enable signal in response to the enable signal having a duration of at least two cycles of the internal clock signal; receiving, by a second filtering circuit, a first filtered enable signal; generating, by a second filtering circuit, a second filtered enable signal responsive to the first filtered enable signal; providing a delayed signal as a delay of the second filtered enable signal by a second filtering circuit; receiving, by the output gate, an internal clock signal and a second filtered enable signal; as well as providing, by the output gate, a glitch-free clock signal of a first logic operation based on the internal clock signal and the second filtered enable signal; Wherein generating the first filtered enable signal comprises: latching an enable signal by a first flip-flop circuit; A first latch signal is generated by a first trigger circuit; latching the first latch signal by the second flip-flop circuit; generating a second latch signal by a second flip-flop circuit; receiving the first latch signal, the second latch signal, and the enable signal by the logic gate; and A first filtered enable signal based on a second logic operation of the first latch signal, the second latch signal, and the enable signal is generated by the logic gate.

5. The method according to claim 4, characterized in that Generating a second filtered enable signal comprises: receiving, by a third flip-flop circuit, a first filtered enable signal; latching the first filtered enable signal by a third flip-flop circuit; and The latched enable signal is generated by the third flip-flop circuit as the second filtered enable signal.

6. A clock generator for generating an output clock signal in response to an enable signal, characterized in that: include: A clock generation circuit for generating an internal clock signal; a first filtering circuit receiving the internal clock signal and the enable signal and generating a first filtered enable signal capable of indicating a first validity of the enable signal; a second filter circuit receiving the first filtered enable signal and generating a second filtered enable signal, the second filter circuit applying a delay to the second filtered enable signal to generate a delayed signal, the clock generation circuit operating in response to the second filtered enable signal and the delayed signal; as well as an output gate receiving the second filtered enable signal and the internal clock signal to generate an output clock signal; The first filtering circuit comprises: a first flip-flop latching an enable signal based on an internal clock signal and providing a first latch enable signal; a second flip-flop that receives the first latch enable signal and latches the first latch enable signal based on the internal clock signal, and generates a second latch enable signal; and A first logic gate generates a first filtered enable signal using the enable signal, the first latch enable signal, and the second latch enable signal.

7. The clock generator according to claim 6, characterized in that The second filtering circuit comprises: A selector circuit having a data input terminal receiving a first filtered enable signal and an inverted signal of the first filtered enable signal, and a selector input terminal receiving a delayed signal from a second filter circuit; and The flip-flop circuit has a data input terminal for receiving the first filtered enable signal and a clock input terminal for receiving the output signal of the selector circuit, and the flip-flop circuit provides a latched enable signal as a second filtered enable signal.

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