Gate clock generator and display device

Abstract

This invention discloses a gate clock generator and a display device. The gate clock generator of the display device includes: a carry clock generator that sequentially generates N carry clock signals (N is an integer greater than or equal to 2) based on carry on and off clock signals; a scan clock generator that generates N scan clock signals based on scan on and off clock signals; and a sensing clock generator that generates N sensing clock signals based on sensing on and off clock signals. In a multi-clock mode, during the on-time of the Kth carry clock signal (K is an integer greater than or equal to 1 and less than N), the scan clock generator outputs a Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan on clock signal, and the sensing clock generator outputs a Kth sensing clock signal having a number of pulses corresponding to the number of pulses of the sensing on clock signal.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a gate clock generator for generating a gate clock signal for a gate driver, and a display device including said gate clock generator. Background Technology

[0002] The gate clock generator of the display device can receive gate clock signals (e.g., carry clock signal, scan clock signal, and sense clock signal) from the controller (e.g., timing controller) of the display device, adjust the voltage level of the gate clock signals to a voltage level suitable for the gate driver of the display device, and provide the gate clock signal with the suitable voltage level to the gate driver. The gate driver can provide scan signals and sense signals to multiple pixels of the display device based on the gate clock signals. However, prior art gate clock generators have the problem that the number of switching or pulses of each gate clock signal is limited to a certain number (e.g., 4). Summary of the Invention

[0003] One object of the present invention is to provide a gate clock generator that supports multiple clock modes.

[0004] Another object of the present invention is to provide a display device including a gate clock generator that supports multiple clock modes.

[0005] However, the technical problem to be solved by the present invention is not limited to the technical problem mentioned above, and various extensions can be made without departing from the concept and scope of the present invention.

[0006] To achieve an objective of the present invention, a gate clock generator for a display device according to an embodiment of the present invention includes: a carry clock generator that sequentially generates N carry clock signals based on a carry-on clock signal and a carry-off clock signal, where N is an integer greater than or equal to 2; a scan clock generator that generates N scan clock signals based on a scan-on clock signal and a scan-off clock signal; and a sensing clock generator that generates N sensing clock signals based on a sensing-on clock signal and a sensing-off clock signal. In a multi-clock mode, during the conduction interval of the Kth carry clock signal among the N carry clock signals, the scan clock generator, as the Kth scan clock signal among the N scan clock signals, outputs the Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan-on clock signal during the conduction interval of the Kth carry clock signal; the sensing clock generator, as the Kth sensing clock signal among the N sensing clock signals, outputs the Kth sensing clock signal having a number of pulses corresponding to the number of pulses of the sensing-on clock signal during the conduction interval of the Kth carry clock signal, where K is an integer greater than or equal to 1 and less than or equal to N.

[0007] In one embodiment, in the multi-clock mode, the carry clock generator may provide the N carry clock signals to the scan clock generator and the sensing clock generator.

[0008] In one embodiment, in the multi-clock mode, the scan clock generator, during the conduction interval of the Kth carry clock signal, changes the Kth scan clock signal to an on level in response to each pulse of the scan on clock signal, and changes the Kth scan clock signal to an off level in response to each pulse of the scan off clock signal. In the multi-clock mode, the sensing clock generator, during the conduction interval of the Kth carry clock signal, changes the Kth sensing clock signal to the on level in response to each pulse of the sensing on clock signal, and changes the Kth sensing clock signal to the off level in response to each pulse of the sensing off clock signal.

[0009] In one embodiment, the carry clock generator may include: a carry mode selection block that determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode; a carry pulse generator block that sequentially generates the N carry clock signals based on the carry on clock signal and the carry off clock signal, and provides the N carry clock signals to the scan clock generator and the sense clock generator in response to the mode signal representing the multi-clock mode; and a carry level shifter block that adjusts the voltage level of the N carry clock signals to a voltage level suitable for the gate driver and provides the N carry clock signals to the gate driver.

[0010] In one embodiment, the scan clock generator may include: a scan mode selection block that determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode; a scan pulse generator block that, in response to the mode signal representing the multi-clock mode, generates the N scan clock signals based on the N carry clock signals, the scan on clock signal, and the scan off clock signal, and generates the N scan clock signals based on the scan on clock signal and the scan off clock signal in response to the mode signal representing the operating mode different from the multi-clock mode; and a scan level shifter block that adjusts the voltage levels of the N scan clock signals to a voltage level suitable for the gate driver and provides the N scan clock signals to the gate driver.

[0011] In one embodiment, the sensing clock generator may include: a sensing mode selection block, which determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode; a sensing pulse generator block, which generates N sensing clock signals based on the N carry clock signals, the sensing on clock signals, and the sensing off clock signals in response to the mode signal representing the multi-clock mode, and generates the N sensing clock signals based on the sensing on clock signals and the sensing off clock signals in response to the mode signal representing the operating mode different from the multi-clock mode; and a sensing level shifter block, which adjusts the voltage levels of the N sensing clock signals to a voltage level suitable for the gate driver and provides the N sensing clock signals to the gate driver.

[0012] In one embodiment, in the multi-clock mode, the carry clock generator may provide a multi-sensor enable signal to the scan clock generator and the sense clock generator.

[0013] In one embodiment, in the multi-clock mode, the scan clock generator, during the first conduction interval of the multi-sensor enable signal, changes the first scan clock signal among the N scan clock signals to a conduction level in response to each pulse of the scan conduction clock signal, and changes the first scan clock signal to a cutoff level in response to each pulse of the scan cutoff clock signal; during the second conduction interval of the multi-sensor enable signal, it changes the second scan clock signal among the N scan clock signals to the conduction level in response to each pulse of the scan conduction clock signal, and changes the second scan clock signal to the cutoff level in response to each pulse of the scan cutoff clock signal. In the multi-clock mode, during the first conduction interval of the multi-sensor enable signal, the sensing clock generator changes the first sensing clock signal among the N sensing clock signals to the conduction level in response to each pulse of the sensing conduction clock signal, and changes the first sensing clock signal to the cutoff level in response to each pulse of the sensing cutoff clock signal. During the second conduction interval of the multi-sensor enable signal, the generator changes the second sensing clock signal among the N sensing clock signals to the conduction level in response to each pulse of the sensing conduction clock signal, and changes the second sensing clock signal to the cutoff level in response to each pulse of the sensing cutoff clock signal.

[0014] In one embodiment, the carry clock generator may include: a carry mode selection block that determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode; a carry pulse generator block that sequentially generates the N carry clock signals based on the carry on clock signal and the carry off clock signal, and generates a multi-sensor enable signal having an on interval when at least one of the N carry clock signals has an on interval in response to the mode signal representing the multi-clock mode; and a carry level shifter block that adjusts the voltage level of the N carry clock signals to a voltage level suitable for the gate driver and provides the N carry clock signals to the gate driver.

[0015] In one embodiment, the scan clock generator may include: a scan mode selection block that determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode; a scan pulse generator block that, in response to the mode signal representing the multi-clock mode, generates the N scan clock signals based on a multi-sensor enable signal received from the carry clock generator, the scan on clock signal, and the scan off clock signal, and generates the N scan clock signals based on the scan on clock signal and the scan off clock signal in response to the mode signal representing the operating mode different from the multi-clock mode; and a scan level shifter block that adjusts the voltage levels of the N scan clock signals to a voltage level suitable for the gate driver and provides the N scan clock signals to the gate driver.

[0016] In one embodiment, the sensing clock generator may include: a sensing mode selection block that determines an operating mode of the gate clock generator and generates a mode signal representing the determined operating mode; a sensing pulse generator block that, in response to the mode signal representing the multi-clock mode, generates the N sensing clock signals based on a multi-sensor enable signal received from the carry clock generator, the sensing on-clock signal, and the sensing off-clock signal, and generates the N sensing clock signals based on the sensing on-clock signal and the sensing off-clock signal in response to the mode signal representing an operating mode different from the multi-clock mode; and a sensing level shifter block that adjusts the voltage levels of the N sensing clock signals to a voltage level suitable for the gate driver and provides the N sensing clock signals to the gate driver.

[0017] To achieve an objective of the present invention, a gate clock generator for a display device according to an embodiment of the present invention includes: a carry clock generator, which receives a carry-on clock signal and a carry-off clock signal from a controller of the display device, and sequentially generates N carry clock signals based on the carry-on clock signal and the carry-off clock signal, where N is an integer greater than or equal to 2; and a scan clock generator, which receives a multi-sensor enable signal, a scan-on clock signal, and a scan-off clock signal from the controller, and generates N scan clock signals based on the multi-sensor enable signal, the scan-on clock signal, and the scan-off clock signal in a multi-clock mode. A clock signal, which generates the N scan clock signals based on the scan on clock signal and the scan off clock signal in an operating mode different from the multi-clock mode; and a sensing clock generator, which receives the multi-sensor enable signal, the sensing on clock signal, and the sensing off clock signal from the controller, and generates N sensing clock signals based on the multi-sensor enable signal, the sensing on clock signal, and the sensing off clock signal in the multi-clock mode, and generates the N sensing clock signals based on the sensing on clock signal and the sensing off clock signal in the operating mode different from the multi-clock mode.

[0018] In one embodiment, in the multi-clock mode, the scan clock generator, during the first conduction interval of the multi-sensor enable signal, changes the first scan clock signal among the N scan clock signals to a conduction level in response to each pulse of the scan conduction clock signal, and changes the first scan clock signal to a cutoff level in response to each pulse of the scan cutoff clock signal; during the second conduction interval of the multi-sensor enable signal, it changes the second scan clock signal among the N scan clock signals to the conduction level in response to each pulse of the scan conduction clock signal, and changes the second scan clock signal to the cutoff level in response to each pulse of the scan cutoff clock signal. In the multi-clock mode, during the first conduction interval of the multi-sensor enable signal, the sensing clock generator changes the first sensing clock signal among the N sensing clock signals to the conduction level in response to each pulse of the sensing conduction clock signal, and changes the first sensing clock signal to the cutoff level in response to each pulse of the sensing cutoff clock signal. During the second conduction interval of the multi-sensor enable signal, the generator changes the second sensing clock signal among the N sensing clock signals to the conduction level in response to each pulse of the sensing conduction clock signal, and changes the second sensing clock signal to the cutoff level in response to each pulse of the sensing cutoff clock signal.

[0019] In one embodiment, the scan clock generator may include: a scan mode selection block that determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode; a scan pulse generator block that, in response to the mode signal representing the multi-clock mode, generates the N scan clock signals based on the multi-sensor enable signal received from the controller, the scan on clock signal, and the scan off clock signal, and generates the N scan clock signals based on the scan on clock signal and the scan off clock signal in response to the mode signal representing the operating mode different from the multi-clock mode; and a scan level shifter block that adjusts the voltage levels of the N scan clock signals to a voltage level suitable for the gate driver and provides the N scan clock signals to the gate driver.

[0020] In one embodiment, the sensing clock generator may include: a sensing mode selection block, which determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode; a sensing pulse generator block, which generates the N sensing clock signals based on the multi-sensor enable signal, the sensing on-clock signal, and the sensing off-clock signal received from the controller in response to the mode signal representing the multi-clock mode, and generates the N sensing clock signals based on the sensing on-clock signal and the sensing off-clock signal in response to the mode signal representing the operating mode different from the multi-clock mode; and a sensing level shifter block, which adjusts the voltage levels of the N sensing clock signals to a voltage level suitable for the gate driver and provides the N sensing clock signals to the gate driver.

[0021] To achieve another objective of the present invention, a display device according to an embodiment of the present invention includes: a display panel including a plurality of pixels; a data driver connected to the plurality of pixels via a plurality of data lines; a sensing circuit connected to the plurality of pixels via a plurality of sensing lines; a controller controlling the data driver and the sensing circuit, and generating a carry-on clock signal, a carry-off clock signal, a scan-on clock signal, a scan-off clock signal, a sensing-on clock signal, and a sensing-off clock signal; a gate clock generator sequentially generating N carry clock signals based on the carry-on clock signal and the carry-off clock signal, generating N scan clock signals based on the scan-on clock signal and the scan-off clock signal, and generating N sensing clock signals based on the sensing-on clock signal and the sensing-off clock signal, where N is an integer greater than or equal to 2; and a gate driver providing a plurality of scan signals and a plurality of sensing signals to the plurality of pixels based on the N carry clock signals, the N scan clock signals, and the N sensing clock signals. In multi-clock mode, during the conduction interval of the Kth carry clock signal among the N carry clock signals, the gate clock generator, as the Kth scan clock signal among the N scan clock signals, outputs the Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan conduction clock signal in the conduction interval of the Kth carry clock signal, and as the Kth sense clock signal among the N sense clock signals, outputs the Kth sense clock signal having a number of pulses corresponding to the number of pulses of the sense conduction clock signal in the conduction interval of the Kth carry clock signal, where K is an integer greater than or equal to 1 and less than or equal to N.

[0022] In one embodiment, the gate clock generator may include: a carry clock generator that sequentially generates the N carry clock signals based on the carry-on clock signal and the carry-off clock signal; a scan clock generator that generates the N scan clock signals based on the scan-on clock signal and the scan-off clock signal; and a sensing clock generator that generates the N sensing clock signals based on the sensing-on clock signal and the sensing-off clock signal.

[0023] In one embodiment, in the multi-clock mode, the carry clock generator may provide the N carry clock signals to the scan clock generator and the sensing clock generator.

[0024] In one embodiment, in the multi-clock mode, the carry clock generator may provide a multi-sensor enable signal to the scan clock generator and the sense clock generator.

[0025] In one embodiment, the controller may provide a multi-sensor enable signal to the scan clock generator and the sense clock generator in the multi-clock mode.

[0026] (Invention Effects)

[0027] In the gate clock generator and display device according to embodiments of the present invention, a carry clock generator may generate N carry clock signals based on a carry-on clock signal and a carry-off clock signal, a scan clock generator may generate N scan clock signals based on a scan-on clock signal and a scan-off clock signal, and a sensing clock generator may generate N sensing clock signals based on a sensing-on clock signal and a sensing-off clock signal. This reduces the number of output pins of the controller in the display device and the number of input pins of the gate clock generator.

[0028] Furthermore, in the gate clock generator and display device according to embodiments of the present invention, in a multi-clock mode, the scan clock generator outputs a Kth scan clock signal with an arbitrary number of pulses during the conduction interval of the Kth carry clock signal; and in a multi-clock mode, the sensing clock generator outputs a Kth sensing clock signal with an arbitrary number of pulses during the conduction interval of the Kth carry clock signal. Thus, the display device is capable of performing multiple sensing operations for each pixel within a frame interval.

[0029] However, the effects of the present invention are not limited to those mentioned above, and various extensions can be made without departing from the concept and scope of the present invention. Attached Figure Description

[0030] Figure 1 This is a block diagram illustrating a gate clock generator according to an embodiment of the present invention.

[0031] Figure 2 This is a block diagram illustrating an example of a gate clock generator according to an embodiment of the present invention.

[0032] Figure 3 This is a timing diagram illustrating an example of the operation of a gate clock generator in a multi-clock mode according to an embodiment of the present invention.

[0033] Figure 4 This is a block diagram illustrating a gate clock generator according to another embodiment of the present invention.

[0034] Figure 5 This is a block diagram illustrating an example of a gate clock generator according to another embodiment of the present invention.

[0035] Figure 6This is a timing diagram illustrating an example of the operation of a gate clock generator in a multi-clock mode according to another embodiment of the present invention.

[0036] Figure 7 This is a block diagram illustrating a gate clock generator according to yet another embodiment of the present invention.

[0037] Figure 8 This is a block diagram illustrating an example of a gate clock generator according to yet another embodiment of the present invention.

[0038] Figure 9 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0039] Figure 10 This is a circuit diagram illustrating an example of pixels included in a display device according to an embodiment of the present invention.

[0040] Figure 11 This is a block diagram illustrating an electronic device including a display device according to an embodiment of the present invention.

[0041] (Explanation of reference numerals in the attached diagram)

[0042] 100, 200, 300: Gate clock generator

[0043] 120, 220, 320: Carry clock generator

[0044] 122, 222, 322: Carry mode selection block

[0045] 124, 224, 324: Carry pulse generator blocks

[0046] 126, 226, 326: Carry-level shifter blocks

[0047] 140, 240, 340: Scan clock generator

[0048] 142, 242, 342: Scan mode selection blocks

[0049] 144, 244, 344: Scan pulse generator blocks

[0050] 146, 246, 346: Scan level shifter blocks

[0051] 160, 260, 360: Sensor Clock Generator

[0052] 162, 262, 362: Sensing mode selection blocks

[0053] 164, 264, 364: Sensing pulse generator blocks

[0054] 166, 266, 366: Sensing level shifter blocks

[0055] 180, 280, 380: Mode Registers

[0056] 400: Display device

[0057] 410: Display panel

[0058] 420: Data Drive

[0059] 430: Sensing Circuit

[0060] 440: Gate Clock Generator

[0061] 450: Gate driver

[0062] 460: Controller Detailed Implementation

[0063] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

[0064] Figure 1 This is a block diagram illustrating a gate clock generator according to an embodiment of the present invention.

[0065] Reference Figure 1 According to an embodiment of the present invention, the gate clock generator 100 of the display device may include a carry clock generator 120, a scan clock generator 140, and a sensing clock generator 160.

[0066] Carry clock generator 120 can receive carry-on clock signal CR_ON_CLK and carry-off clock signal CR_OFF_CLK from the controller of the display device, and sequentially generate N (N is an integer greater than 2) carry clock signals CR_CLKN based on the carry-on clock signal CR_ON_CLK and carry-off clock signal CR_OFF_CLK. For example, carry clock generator 120 can generate 2, 4, 6, 8, etc. carry clock signals CR_CLKN. In one example, carry clock generator 120 can receive two carry-on and carry-off clock signals CR_ON_CLK and CR_OFF_CLK from the controller, and output 8 carry clock signals CR_CLKN. Thus, compared with the prior art gate clock generator that receives 8 carry clock signals CR_CLKN to output 8 carry clock signals CR_CLKN, the number of output pins of the controller and the number of input pins of the gate clock generator 100 can be reduced.

[0067] The carry clock generator 120 can provide N carry clock signals CR_CLKN to the scan clock generator 140 and the sensing clock generator 160 respectively in a multi-clock mode, and not provide N carry clock signals CR_CLKN to the scan clock generator 140 and the sensing clock generator 160 in an operating mode different from the multi-clock mode. In one embodiment, the operating modes of the gate clock generator 100 may include: a normal mode (or a 1-clock mode), in which each scan clock signal SC_CLKN or each sense clock signal SS_CLKN has one pulse; a 2-clock mode, in which each scan clock signal SC_CLKN or each sense clock signal SS_CLKN has two pulses; a 3-clock mode, in which each scan clock signal SC_CLKN or each sense clock signal SS_CLKN has three pulses; a 4-clock mode, in which each scan clock signal SC_CLKN or each sense clock signal SS_CLKN has four pulses; and the multi-clock mode, in which each scan clock signal SC_CLKN or each sense clock signal SS_CLKN has any number of pulses. In this case, the carry clock generator 120 can provide N carry clock signals CR_CLKN to the scan clock generator 140 and the sensing clock generator 160 respectively in the multi-clock mode, and not provide N carry clock signals CR_CLKN to the scan clock generator 140 and the sensing clock generator 160 in the general mode (or the 1-clock mode), the 2-clock mode, the 3-clock mode and the 4-clock mode.

[0068] The scan clock generator 140 can receive a scan-on clock signal SC_ON_CLK and a scan-off clock signal SC_OFF_CLK from the controller, and sequentially generate N scan clock signals SC_CLKN based on the scan-on clock signal SC_ON_CLK and the scan-off clock signal SC_OFF_CLK. For example, the scan clock generator 140 can generate 2, 4, 6, 8, etc. scan clock signals SC_CLKN. In one example, the scan clock generator 140 can receive two scan-on and two scan-off clock signals SC_ON_CLK and SC_OFF_CLK from the controller, and output 8 scan clock signals SC_CLKN. Thus, compared with the prior art gate clock generator that receives 8 scan clock signals SC_CLKN to output 8 scan clock signals SC_CLKN, the number of output pins of the controller and the number of input pins of the gate clock generator 100 can be reduced.

[0069] In the multi-clock mode, the scan clock generator 140 can output the Kth scan clock signal as the Kth scan clock signal among the N scan clock signals SC_CLKN, during the conduction interval (e.g., the high interval) of the Kth carry clock signal (K is an integer greater than 1 and less than N) of the N carry clock signals CR_CLKN, and output the Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan on-clock signal SC_ON_CLK (or the number of pulses of the scan off-clock signal SC_OFF_CLK) in the conduction interval of the Kth carry clock signal. For example, when the period of the scan on-clock signal SC_ON_CLK or the scan off-clock signal SC_OFF_CLK is approximately 1 / 6 of the period of the carry-on clock signal CR_ON_CLK and the carry-off clock signal CR_OFF_CLK, that is, when the scan on-clock signal SC_ON_CLK or the scan off-clock signal SC_OFF_CLK has 6 pulses during the on-interval of each carry clock signal CR_CLKN, the scan clock generator 140 can output a first scan clock signal with 6 pulses during the on-interval of the first carry clock signal, and output a second scan clock signal with 6 pulses during the on-interval of the second carry clock signal, so as to output a corresponding scan clock signal SC_CLKN with 6 pulses during the on-interval of each carry clock signal CR_CLKN.

[0070] In one embodiment, in the multi-clock mode, the scan clock generator 140 can receive N carry clock signals CR_CLKN from the carry clock generator 120, and based on the N carry clock signals CR_CLKN, the scan on clock signal SC_ON_CLK, and the scan off clock signal SC_OFF_CLK, sequentially generate N scan clock signals SC_CLKN, each having a number of pulses corresponding to the number of pulses of the scan on clock signal SC_ON_CLK (or the number of pulses of the scan off clock signal SC_OFF_CLK), so as to output a corresponding scan clock signal SC_CLKN having the corresponding number of pulses during the on interval of each carry clock signal CR_CLKN. For example, during the conduction interval (e.g., the high interval) of the Kth carry clock signal, the scan clock generator 140 may change the Kth scan clock signal to an on level (e.g., high level) in response to each pulse of the scan on clock signal SC_ON_CLK, and change the Kth scan clock signal to an off level (e.g., low level) in response to each pulse of the scan off clock signal SC_OFF_CLK, so as to output the Kth scan clock signal having the stated number of pulses during the conduction interval of the Kth carry clock signal.

[0071] Furthermore, in an operating mode different from the multi-clock mode, the scan clock generator 140 may not receive the N carry clock signals CR_CLKN, and may sequentially generate the scan clock signal SC_CLKN based on the scan on-clock signal SC_ON_CLK and the scan off-clock signal SC_OFF_CLK, independent of the N carry clock signals CR_CLKN. For example, in the general mode (or the 1-clock mode), the scan clock generator 140 may sequentially generate scan clock signals SC_CLKN, each with one pulse, based on the scan on-clock signal SC_ON_CLK and the scan off-clock signal SC_OFF_CLK. Additionally, in the 2-clock mode, the scan clock generator 140 may sequentially generate scan clock signals SC_CLKN, each with two pulses, based on the scan on-clock signal SC_ON_CLK and the scan off-clock signal SC_OFF_CLK. Furthermore, in the 3-clock mode, the scan clock generator 140 can sequentially generate scan clock signals SC_CLKN, each with three pulses, based on the scan on-clock signal SC_ON_CLK and the scan off-clock signal SC_OFF_CLK. Additionally, in the 4-clock mode, the scan clock generator 140 can sequentially generate scan clock signals SC_CLKN, each with four pulses, based on the scan on-clock signal SC_ON_CLK and the scan off-clock signal SC_OFF_CLK.

[0072] The sensing clock generator 160 can receive a sensing on-clock signal SS_ON_CLK and a sensing off-clock signal SS_OFF_CLK from the controller, and sequentially generate N sensing clock signals SS_CLKN based on the sensing on-clock signal SS_ON_CLK and the sensing off-clock signal SS_OFF_CLK. For example, the sensing clock generator 160 can generate 2, 4, 6, 8, etc. sensing clock signals SS_CLKN. In one example, the sensing clock generator 160 can receive two sensing on-clock and off-clock signals SS_ON_CLK and SS_OFF_CLK from the controller, and output 8 sensing clock signals SS_CLKN. Therefore, compared with the prior art gate clock generator that receives 8 sensing clock signals SS_CLKN to output 8 sensing clock signals SS_CLKN, the number of output pins of the controller and the number of input pins of the gate clock generator 100 can be reduced.

[0073] In the multi-clock mode, the sensing clock generator 160 can output the Kth sensing clock signal as the Kth sensing clock signal among the N sensing clock signals SS_CLKN, during the conduction interval (e.g., the high interval) of the Kth carry clock signal (K is an integer greater than 1 and less than N) of the N carry clock signals CR_CLKN, having a number of pulses corresponding to the number of pulses of the sensing on-clock signal SS_ON_CLK (or the number of pulses of the sensing off-clock signal SS_OFF_CLK) in the conduction interval of the Kth carry clock signal. For example, when the period of the sensing on-clock signal SS_ON_CLK or the sensing off-clock signal SS_OFF_CLK is approximately 1 / 6 of the period of the carry-on clock signal CR_ON_CLK and the carry-off clock signal CR_OFF_CLK, that is, when the sensing on-clock signal SS_ON_CLK or the sensing off-clock signal SS_OFF_CLK has 6 pulses during the conduction interval of each carry clock signal CR_CLKN, the sensing clock generator 160 can output a first sensing clock signal with 6 pulses during the conduction interval of the first carry clock signal, and output a second sensing clock signal with 6 pulses during the conduction interval of the second carry clock signal, so as to output a corresponding sensing clock signal SS_CLKN with 6 pulses during the conduction interval of each carry clock signal CR_CLKN.

[0074] In one embodiment, in the multi-clock mode, the sensing clock generator 160 can receive N carry clock signals CR_CLKN from the carry clock generator 120, and based on the N carry clock signals CR_CLKN, the sensing on-clock signal SS_ON_CLK, and the sensing off-clock signal SS_OFF_CLK, sequentially generate N sensing clock signals SS_CLKN, each having a number of pulses corresponding to the number of pulses of the sensing on-clock signal SS_ON_CLK (or the number of pulses of the sensing off-clock signal SS_OFF_CLK), so as to output a corresponding sensing clock signal SS_CLKN having the corresponding number of pulses during the on-interval of each carry clock signal CR_CLKN. For example, during the conduction interval (e.g., the high interval) of the Kth carry clock signal, the sensing clock generator 160 may change the Kth sensing clock signal to the conduction level (e.g., the high level) in response to each pulse of the sensing conduction clock signal SS_ON_CLK, and change the Kth sensing clock signal to the cutoff level (e.g., the low level) in response to each pulse of the sensing cutoff clock signal SS_OFF_CLK, so as to output the Kth sensing clock signal having the number of pulses during the conduction interval of the Kth carry clock signal.

[0075] Furthermore, in an operating mode different from the multi-clock mode, the sensing clock generator 160 may not receive the N carry clock signals CR_CLKN, and may sequentially generate the sensing clock signal SS_CLKN based on the sensing on-clock signal SS_ON_CLK and the sensing off-clock signal SS_OFF_CLK, independent of the N carry clock signals CR_CLKN. For example, in the general mode (or the 1-clock mode), the sensing clock generator 160 may sequentially generate sensing clock signals SS_CLKN, each with one pulse, based on the sensing on-clock signal SS_ON_CLK and the sensing off-clock signal SS_OFF_CLK. Additionally, in the 2-clock mode, the sensing clock generator 160 may sequentially generate sensing clock signals SS_CLKN, each with two pulses, based on the sensing on-clock signal SS_ON_CLK and the sensing off-clock signal SS_OFF_CLK. Furthermore, in the 3-clock mode, the sensing clock generator 160 can sequentially generate sensing clock signals SS_CLKN, each with three pulses, based on the sensing on-clock signal SS_ON_CLK and the sensing off-clock signal SS_OFF_CLK. Additionally, in the 4-clock mode, the sensing clock generator 160 can sequentially generate sensing clock signals SS_CLKN, each with four pulses, based on the sensing on-clock signal SS_ON_CLK and the sensing off-clock signal SS_OFF_CLK.

[0076] On the other hand, a prior art gate clock generator receives eight carry clock signals CR_CLKN, eight scan clock signals SC_CLKN, and eight sense clock signals SS_CLKN from a prior art controller, and outputs eight carry clock signals CR_CLKN, eight scan clock signals SC_CLKN, and eight sense clock signals SS_CLKN. Therefore, the prior art controller may have multiple output pins, and the prior art gate clock generator may have multiple input pins. However, the gate clock generator 100 according to an embodiment of the present invention can receive two carry-on and cut-off clock signals CR_ON_CLK and CR_OFF_CLK, two scan-on and cut-off clock signals SC_ON_CLK and SC_OFF_CLK, and two sense-on and cut-off clock signals SS_ON_CLK and SS_OFF_CLK. Based on the two carry-on and cut-off clock signals CR_ON_CLK and CR_OFF_CLK, it outputs N carry clock signals CR_CLKN; based on the two scan-on and cut-off clock signals SC_ON_CLK and SC_OFF_CLK, it outputs N scan clock signals SC_CLKN; and based on the two sense-on and cut-off clock signals SS_ON_CLK and SS_OFF_CLK, it outputs N sense clock signals SS_CLKN. Therefore, compared with the prior art controller and the prior art gate clock generator, the number of output pins of the controller and the number of input pins of the gate clock generator 100 can be reduced.

[0077] Furthermore, in the absence of the multi-clock mode in the gate clock generator 100, for example, in the presence of the general mode (or the 1-clock mode), the 2-clock mode, the 3-clock mode, and the 4-clock mode, each scan clock signal SC_CLKN or each sensing clock signal SS_CLKN generated from the gate clock generator 100 may have only a limited number of pulses (e.g., at most 4 pulses). Such a gate clock generator 100 may not be suitable for display devices requiring multiple sensing operations (e.g., tens or hundreds of sensing operations) for each pixel. However, it is permissible for the gate clock generator 100 according to an embodiment of the present invention to have the multi-clock mode, in which the scan clock generator 140 outputs the Kth scan clock signal with an arbitrary number of pulses during the conduction interval of the Kth carry clock signal, and the sensing clock generator 160 outputs the Kth sensing clock signal with an arbitrary number of pulses during the conduction interval of the Kth carry clock signal. Thus, the display device including the gate clock generator 100 according to an embodiment of the present invention is able to perform the plurality of sensing operations for each pixel within a frame interval.

[0078] Figure 2 This is a block diagram illustrating an example of a gate clock generator according to an embodiment of the present invention. Figure 3 This is a timing diagram illustrating an example of the operation of a gate clock generator according to an embodiment of the present invention.

[0079] Reference Figure 2 The gate clock generator 100 of the display device may include a carry clock generator 120, a scan clock generator 140, and a sensing clock generator 160. The carry clock generator 120 may include a carry mode selection block 122, a carry pulse generator block 124, and a carry level shifter block 126. The scan clock generator 140 may include a scan mode selection block 142, a scan pulse generator block 144, and a scan level shifter block 146. The sensing clock generator 160 may include a sensing mode selection block 162, a sensing pulse generator block 164, and a sensing level shifter block 166. In one embodiment, the gate clock generator 100 may also include a mode register 180.

[0080] The mode register 180 can store information indicating the operating mode of the gate clock generator 100. In one embodiment, the information stored in the mode register 180 can represent: a normal mode (or a 1-clock mode), where each scan / sensing clock signal has one pulse; a 2-clock mode, where each scan / sensing clock signal has two pulses; a 3-clock mode, where each scan / sensing clock signal has three pulses; a 4-clock mode, where each scan / sensing clock signal has four pulses; or the multi-clock mode, where each scan / sensing clock signal has any number of pulses. Additionally, in one embodiment, when the display device is powered on, the controller of the display device can (e.g., via inter-integrated circuit (I2C) communication) write information indicating the operating mode into the mode register 180 of the gate clock generator 100.

[0081] Carry mode selection block 122 can determine the operating mode of gate clock generator 100 and generate a mode signal SMODE representing the determined operating mode. In one embodiment, carry mode selection block 122 can receive a sensing signal SENSE from the controller, determine the operating mode as the general mode (or the 1-clock mode) during the period when the sensing signal SENSE has a cutoff level (e.g., low level), and generate a mode signal SMODE representing the general mode (or the 1-clock mode). Alternatively, during the period when the sensing signal SENSE has a conduction level (e.g., high level), i.e., during the conduction interval (e.g., high interval) of the sensing signal SENSE, carry mode selection block 122 can determine the operating mode of gate clock generator 100 based on the information stored in mode register 180. For example, if the information stored in mode register 180 indicates the multi-clock mode, carry mode selection block 122 can determine the operating mode as the multi-clock mode and generate a mode signal SMODE representing the multi-clock mode.

[0082] The carry pulse generator block 124 can sequentially generate N carry clock signals, such as the first to eighth carry clock signals CR_CLK1 to CR_CLK8, based on the carry-on clock signal CR_ON_CLK and the carry-off clock signal CR_OFF_CLK. Additionally, the carry pulse generator block 124 can receive a mode signal SMODE from the carry mode selection block 122 and, in response to the mode signal SMODE representing the multi-clock mode, provide the first to eighth carry clock signals CR_CLK1 to CR_CLK8 to the scan clock generator 140 and the sensing clock generator 160, respectively. On the other hand, if the mode signal SMODE does not represent the multi-clock mode, i.e., if the mode signal SMODE represents the general mode (or the 1-clock mode), the 2-clock mode, the 3-clock mode, or the 4-clock mode, the carry pulse generator block 124 may not provide the first to eighth carry clock signals CR_CLK1 to CR_CLK8 to the scan clock generator 140 and the sensing clock generator 160.

[0083] The carry-level shifter block 126 can adjust the voltage levels of the first to eighth carry clock signals CR_CLK1 to CR_CLK8 to a voltage level suitable for the gate driver of the display device, and provide the voltage levels of the first to eighth carry clock signals CR_CLK1 to CR_CLK8 to the gate driver. In one embodiment, the carry-level shifter block 126 may include eight level shifters for adjusting the voltage levels of the eight carry clock signals CR_CLK1 to CR_CLK8, but is not limited thereto.

[0084] The scan mode selection block 142 can determine the operating mode of the gate clock generator 100 and generate a mode signal SMODE representing the determined operating mode. In one embodiment, the scan mode selection block 142 can receive a sensing signal SENSE from the controller, determine the operating mode as the general mode (or the 1-clock mode) during the period when the sensing signal SENSE has the off level, and generate a mode signal SMODE representing the general mode (or the 1-clock mode). Alternatively, during the period when the sensing signal SENSE has the on level, i.e., during the on interval of the sensing signal SENSE, the scan mode selection block 142 can determine the operating mode of the gate clock generator 100 based on the information stored in the mode register 180. For example, if the information stored in the mode register 180 indicates the multi-clock mode, the scan mode selection block 142 can determine the operating mode as the multi-clock mode and generate a mode signal SMODE representing the multi-clock mode.

[0085] The scan pulse generator block 144 can receive the mode signal SMODE from the scan mode selection block 142, and in response to the mode signal SMODE representing the multi-clock mode, generate the first to eighth scan clock signals SC_CLK1 to SC_CLK8 based on the first to eighth carry clock signals CR_CLK1 to CR_CLK8, the scan on clock signal SC_ON_CLK, and the scan off clock signal SC_OFF_CLK. For example, during the conduction interval of each carry clock signal (e.g., CR_CLK1), the scan pulse generator block 144 can change the corresponding scan clock signal (e.g., SC_CLK1) to the conduction level in response to each pulse of the scan conduction clock signal SC_ON_CLK, and change the corresponding scan clock signal (e.g., SC_CLK1) to the cutoff level in response to each pulse of the scan cutoff clock signal SC_OFF_CLK, thereby generating the corresponding scan clock signal (e.g., SC_CLK1) with a number of pulses corresponding to the number of pulses of the scan conduction clock signal SC_ON_CLK (or the number of pulses of the scan cutoff clock signal SC_OFF_CLK).

[0086] On the other hand, when the mode signal SMODE represents a working mode different from the multi-clock mode, the scan pulse generator block 144 can generate the first to eighth scan clock signals SC_CLK1 to SC_CLK8 sequentially based on the scan on clock signal SC_ON_CLK and the scan off clock signal SC_OFF_CLK, independent of the first to eighth carry clock signals CR_CLK1 to CR_CLK8. For example, the scan pulse generator block 144 can sequentially generate first to eighth scan clock signals SC_CLK1 to SC_CLK8, each with one pulse, in response to the mode signal SMODE representing the general mode (or the 1-clock mode); sequentially generate first to eighth scan clock signals SC_CLK1 to SC_CLK8, each with two pulses, in response to the mode signal SMODE representing the 2-clock mode; sequentially generate first to eighth scan clock signals SC_CLK1 to SC_CLK8, each with three pulses, in response to the mode signal SMODE representing the 3-clock mode; and sequentially generate first to eighth scan clock signals SC_CLK1 to SC_CLK8, each with four pulses, in response to the mode signal SMODE representing the 4-clock mode.

[0087] The scan level shifter block 146 can adjust the voltage levels of the first to eighth scan clock signals SC_CLK1 to SC_CLK8 to a voltage level suitable for the gate driver, and provide the voltage levels of the first to eighth scan clock signals SC_CLK1 to SC_CLK8 to the gate driver. In one embodiment, the scan level shifter block 146 may include eight level shifters for adjusting the voltage levels of the eight scan clock signals SC_CLK1 to SC_CLK8, but is not limited thereto.

[0088] The sensing mode selection block 162 can determine the operating mode of the gate clock generator 100 and generate a mode signal SMODE representing the determined operating mode. In one embodiment, the sensing mode selection block 162 can receive a sensing signal SENSE from the controller, determine the operating mode as the general mode (or the 1-clock mode) during the period when the sensing signal SENSE has the off level, and generate a mode signal SMODE representing the general mode (or the 1-clock mode). Alternatively, during the period when the sensing signal SENSE has the on level, i.e., during the on interval of the sensing signal SENSE, the sensing mode selection block 162 can determine the operating mode of the gate clock generator 100 based on the information stored in the mode register 180. For example, if the information stored in the mode register 180 indicates the multi-clock mode, the sensing mode selection block 162 can determine the operating mode as the multi-clock mode and generate a mode signal SMODE representing the multi-clock mode.

[0089] The sensing pulse generator block 164 can receive the mode signal SMODE from the sensing mode selection block 162, and in response to the mode signal SMODE representing the multi-clock mode, generate the first to eighth sensing clock signals SS_CLK1 to SS_CLK8 based on the first to eighth carry clock signals CR_CLK1 to CR_CLK8, the sensing turn-on clock signal SS_ON_CLK, and the sensing turn-off clock signal SS_OFF_CLK. For example, during the conduction interval of each carry clock signal (e.g., CR_CLK1), the sensing pulse generator block 164 can change the corresponding sensing clock signal (e.g., SS_CLK1) to the conduction level in response to each pulse of the sensing conduction clock signal SS_ON_CLK, and change the corresponding sensing clock signal (e.g., SS_CLK1) to the cutoff level in response to each pulse of the sensing cutoff clock signal SS_OFF_CLK, thereby generating the corresponding sensing clock signal (e.g., SS_CLK1) with a number of pulses corresponding to the number of pulses of the sensing conduction clock signal SS_ON_CLK (or the number of pulses of the sensing cutoff clock signal SS_OFF_CLK).

[0090] On the other hand, when the mode signal SMODE represents a different working mode than the multi-clock mode, the sensing pulse generator block 164 can generate the first to eighth sensing clock signals SS_CLK1 to SS_CLK8 sequentially based on the sensing turn-on clock signal SS_ON_CLK and the sensing turn-off clock signal SS_OFF_CLK, independent of the first to eighth carry clock signals CR_CLK1 to CR_CLK8. For example, the sensing pulse generator block 164 can sequentially generate first to eighth sensing clock signals SS_CLK1 to SS_CLK8, each having one pulse, in response to the mode signal SMODE representing the general mode (or the 1-clock mode); sequentially generate first to eighth sensing clock signals SS_CLK1 to SS_CLK8, each having two pulses, in response to the mode signal SMODE representing the 2-clock mode; sequentially generate first to eighth sensing clock signals SS_CLK1 to SS_CLK8, each having three pulses, in response to the mode signal SMODE representing the 3-clock mode; and sequentially generate first to eighth sensing clock signals SS_CLK1 to SS_CLK8, each having four pulses, in response to the mode signal SMODE representing the 4-clock mode.

[0091] The sensing level shifter block 166 can adjust the voltage levels of the first to eighth sensing clock signals SS_CLK1 to SS_CLK8 to a voltage level suitable for the gate driver, and provide the voltage levels of the first to eighth sensing clock signals SS_CLK1 to SS_CLK8 to the gate driver. In one embodiment, the sensing level shifter block 166 may include eight level shifters for adjusting the voltage levels of the eight sensing clock signals SS_CLK1 to SS_CLK8, but is not limited thereto.

[0092] The following is for reference Figure 2 as well as Figure 3 An example of the operation of the gate clock generator 100 in the multi-clock mode will be described later.

[0093] Reference Figure 2 as well as Figure 3(For example, when performing sensing operations in the display device) the controller can provide a high-level sensing signal SENSE to the gate clock generator 100. The carry mode selection block 122, scan mode selection block 142, and sensing mode selection block 162 can determine the operating mode of the gate clock generator 100 based on the information stored in the mode register 180 during the period when the sensing signal SENSE is high. Furthermore, when the information stored in the mode register 180 indicates the multi-clock mode, the carry mode selection block 122, scan mode selection block 142, and sensing mode selection block 162 can each generate a mode signal SMODE representing the multi-clock mode.

[0094] The carry pulse generator block 124 can generate a first carry clock signal CR_CLK1 that has a rising edge in response to the first pulse of the carry-on clock signal CR_ON_CLK and a falling edge in response to the first pulse of the carry-off clock signal CR_OFF_CLK, and generate a second carry clock signal CR_CLK2 that has a rising edge in response to the second pulse of the carry-on clock signal CR_ON_CLK and a falling edge in response to the second pulse of the carry-off clock signal CR_OFF_CLK, and so on, generating an eighth carry clock signal CR_CLK8 that has a rising edge in response to the eighth pulse of the carry-on clock signal CR_ON_CLK and a falling edge in response to the eighth pulse of the carry-off clock signal CR_OFF_CLK. Furthermore, the carry pulse generator block 124 can repeat the sequential generation of the first to eighth carry clock signals CR_CLK1 to CR_CLK8 until the sensing signal SENSE becomes low. In addition, the carry pulse generator block 124 can provide the first to eighth carry clock signals CR_CLK1 to CR_CLK8 to the scan clock generator 140 and the sensing clock generator 160 respectively.

[0095] The scan pulse generator block 144 can generate a first scan clock signal SC_CLK1 during the high interval of the first carry clock signal CR_CLK1, which has a rising edge in response to each pulse of the scan on clock signal SC_ON_CLK and a falling edge in response to each pulse of the scan off clock signal SC_OFF_CLK. During the high interval of the second carry clock signal CR_CLK2, it can generate a second scan clock signal SC_CLK2, which has a rising edge in response to each pulse of the scan on clock signal SC_ON_CLK and a falling edge in response to each pulse of the scan off clock signal SC_OFF_CLK. In this way, during the high interval of the eighth carry clock signal CR_CLK8, it can generate an eighth scan clock signal SC_CLK8, which has a rising edge in response to each pulse of the scan on clock signal SC_ON_CLK and a falling edge in response to each pulse of the scan off clock signal SC_OFF_CLK. Therefore, the switching number or the number of pulses for each scan clock signal SC_CLK1 to SC_CLK8 can be determined by the number of pulses of the scan on-clock signal SC_ON_CLK (or the number of pulses of the scan off-clock signal SC_OFF_CLK) in the high interval (i.e., the on-interval) of the corresponding carry clock signals CR_CLK1 to CR_CLK8. The controller can adjust the number of pulses for each scan clock signal SC_CLK1 to SC_CLK8 to any number (e.g., tens or hundreds) by adjusting the length of the on-interval of each carry clock signal CR_CLK1 to CR_CLK8. In addition, the scan pulse generator block 144 can repeat the sequential generation of the first to eighth scan clock signals SC_CLK1 to SC_CLK8 until the sensing signal SENSE becomes low.

[0096] The sensing pulse generator block 164 can generate a first sensing clock signal SS_CLK1 during the high interval of the first carry clock signal CR_CLK1, which has a rising edge in response to each pulse of the sensing on-clock signal SS_ON_CLK and a falling edge in response to each pulse of the sensing off-clock signal SS_OFF_CLK. During the high interval of the second carry clock signal CR_CLK2, it can generate a second sensing clock signal SS_CLK2, which has a rising edge in response to each pulse of the sensing on-clock signal SS_ON_CLK and a falling edge in response to each pulse of the sensing off-clock signal SS_OFF_CLK. In this way, during the high interval of the eighth carry clock signal CR_CLK8, it can generate an eighth sensing clock signal SS_CLK8, which has a rising edge in response to each pulse of the sensing on-clock signal SS_ON_CLK and a falling edge in response to each pulse of the sensing off-clock signal SS_OFF_CLK. Therefore, the switching number or the number of pulses of each sensing clock signal SS_CLK1 to SS_CLK8 can be determined by the number of pulses of the sensing on-clock signal SS_ON_CLK (or the number of pulses of the sensing off-clock signal SS_OFF_CLK) in the high interval (i.e., the conduction interval) of the corresponding carry clock signals CR_CLK1 to CR_CLK8. The controller can adjust the number of pulses of each sensing clock signal SS_CLK1 to SS_CLK8 to any number (e.g., tens or hundreds) by adjusting the length of the conduction interval of each carry clock signal CR_CLK1 to CR_CLK8. In addition, the sensing pulse generator block 164 can repeat the sequential generation of the first to eighth sensing clock signals SS_CLK1 to SS_CLK8 until the sensing signal SENSE becomes low.

[0097] Figure 4 This is a block diagram illustrating a gate clock generator according to another embodiment of the present invention.

[0098] Reference Figure 4 According to another embodiment of the present invention, the gate clock generator 200 of the display device may include a carry clock generator 220, a scan clock generator 240, and a sensing clock generator 260. Except that the carry clock generator 220 provides the multi-sensing enable signal MULTI_SEN_EN to the scan clock generator 240 and the sensing clock generator 260 in a multi-clock mode instead of N carry clock signals CR_CLKN, Figure 4 The gate clock generator 200 can have the same characteristics as... Figure 1 It has a similar structure and similar operation to the gate clock generator 100.

[0099] In the multi-clock mode, the carry clock generator 220 can sequentially generate N carry clock signals CR_CLKN based on the carry-on clock signal CR_ON_CLK and the carry-off clock signal CR_OFF_CLK. Whenever any one of the N carry clock signals CR_CLKN has an on interval (e.g., a high interval), a multi-sensor enable signal MULTI_SEN_EN with an on interval (e.g., a high interval) is generated. Additionally, the carry clock generator 220 can provide the multi-sensor enable signal MULTI_SEN_EN to both the scan clock generator 240 and the sensing clock generator 260. On the other hand, in operating modes different from the multi-clock mode (e.g., normal mode (or 1-clock mode), 2-clock mode, 3-clock mode, or 4-clock mode), the carry clock generator 220 may not provide the multi-sensor enable signal MULTI_SEN_EN to the scan clock generator 240 and the sensing clock generator 260.

[0100] In the multi-clock mode, the scan clock generator 240 can receive a multi-sensor enable signal MULTI_SEN_EN from the carry clock generator 220, and generate N scan clock signals SC_CLKN based on the multi-sensor enable signal MULTI_SEN_EN, the scan on-clock signal SC_ON_CLK, and the scan off-clock signal SC_OFF_CLK. The scan clock generator 240 can output the Kth scan clock signal, which has a number of pulses corresponding to the number of pulses of the scan on-clock signal SC_ON_CLK (or the number of pulses of the scan off-clock signal SC_OFF_CLK) in the N*M+K on-interval of the multi-sensor enable signal MULTI_SEN_EN (where K is an integer greater than or equal to 1 and less than or equal to N, and M is an integer greater than or equal to 0), as the Kth scan clock signal among the N scan clock signals SC_CLKN. For example, during the first conduction interval of the multi-sensor enable signal MULTI_SEN_EN, the scan clock generator 240 can change the first scan clock signal among the N scan clock signals SC_CLKN to the conduction level in response to each pulse of the scan conduction clock signal SC_ON_CLK, and change the first scan clock signal to the cutoff level in response to each pulse of the scan cutoff clock signal SC_OFF_CLK. Furthermore, during the second conduction interval of the multi-sensor enable signal MULTI_SEN_EN, the scan clock generator 240 can change the second scan clock signal among the N scan clock signals SC_CLKN to the conduction level in response to each pulse of the scan conduction clock signal SC_ON_CLK, and change the second scan clock signal to the cutoff level in response to each pulse of the scan cutoff clock signal SC_OFF_CLK. In this manner, during the Nth on-state interval of the multi-sensor enable signal MULTI_SEN_EN, the scan clock generator 240 can change the Nth scan clock signal among the N scan clock signals SC_CLKN to the on-state level in response to each pulse of the scan on-state clock signal SC_ON_CLK, and change the Nth scan clock signal to the off-state level in response to each pulse of the scan off-state clock signal SC_OFF_CLK. Subsequently, the scan clock generator 240 can repeat the sequential generation of the first to Nth scan clock signals SC_CLKN.

[0101] In the multi-clock mode, the sensing clock generator 260 can receive a multi-sensing enable signal MULTI_SEN_EN from the carry clock generator 220, and generate N sensing clock signals SS_CLKN based on the multi-sensing enable signal MULTI_SEN_EN, the sensing on-clock signal SS_ON_CLK, and the sensing off-clock signal SS_OFF_CLK. The sensing clock generator 260 can output the Kth sensing clock signal SS_CLKN as the Kth sensing clock signal among the N sensing clock signals SS_CLKN during the on-time (e.g., the high-time) of the N*M+K on-time interval of the multi-sensing enable signal MULTI_SEN_EN (where K is an integer greater than or equal to 1 and less than N, and M is an integer greater than or equal to 0). The Kth sensing clock signal has a number of pulses corresponding to the number of pulses of the sensing on-clock signal SS_ON_CLK (or the number of pulses of the sensing off-clock signal SS_OFF_CLK) in the N*M+K on-time interval. For example, during the first conduction interval of the multi-sensor enable signal MULTI_SEN_EN, the sensing clock generator 260 can change the first sensing clock signal among the N sensing clock signals SS_CLKN to the conduction level in response to each pulse of the sensing conduction clock signal SS_ON_CLK, and change the first sensing clock signal to the cutoff level in response to each pulse of the sensing cutoff clock signal SS_OFF_CLK, thereby generating the first sensing clock signal with a number of pulses corresponding to the number of pulses of the sensing conduction clock signal SS_ON_CLK (or the number of pulses of the sensing cutoff clock signal SS_OFF_CLK). Additionally, during the second conduction interval of the multi-sensor enable signal MULTI_SEN_EN, the sensing clock generator 260 can change the second sensing clock signal among the N sensing clock signals SS_CLKN to the conduction level in response to each pulse of the sensing conduction clock signal SS_ON_CLK, and change the second sensing clock signal to the cutoff level in response to each pulse of the sensing cutoff clock signal SS_OFF_CLK, thereby generating a second sensing clock signal having a number of pulses corresponding to the number of pulses of the sensing conduction clock signal SS_ON_CLK (or the number of pulses of the sensing cutoff clock signal SS_OFF_CLK).In this manner, during the Nth on-state interval of the multi-sensor enable signal MULTI_SEN_EN, the sensing clock generator 260 can change the Nth sensing clock signal among the N sensing clock signals SS_CLKN to the on-state level in response to each pulse of the sensing on-state clock signal SS_ON_CLK, and change the Nth sensing clock signal to the off-state level in response to each pulse of the sensing off-state clock signal SS_OFF_CLK, thereby generating the Nth sensing clock signal with a number of pulses corresponding to the number of pulses of the sensing on-state clock signal SS_ON_CLK (or the number of pulses of the sensing off-state clock signal SS_OFF_CLK). Next, the sensing clock generator 260 can repeat the sequential generation of the first to the Nth sensing clock signals SS_CLKN.

[0102] As described above, the gate clock generator 200 according to another embodiment of the present invention may have the multi-clock mode, in which the carry clock generator 220 generates a multi-sensor enable signal MULTI_SEN_EN, the scan clock generator 240 outputs a corresponding scan clock signal with an arbitrary number of pulses in each conduction interval of the multi-sensor enable signal MULTI_SEN_EN, and the sensing clock generator 260 outputs a corresponding sensing clock signal with an arbitrary number of pulses in each conduction interval of the multi-sensor enable signal MULTI_SEN_EN. Thus, the display device including the gate clock generator 200 according to another embodiment of the present invention can perform the multiple sensing operations for each pixel within a frame interval.

[0103] Figure 5 This is a block diagram illustrating an example of a gate clock generator according to another embodiment of the present invention. Figure 6 This is a timing diagram illustrating an example of the operation of a gate clock generator in a multi-clock mode according to another embodiment of the present invention.

[0104] Reference Figure 5The gate clock generator 200 of the display device may include a carry clock generator 220, a scan clock generator 240, and a sensing clock generator 260. The carry clock generator 220 may include a carry mode selection block 222, a carry pulse generator block 224, and a carry level shifter block 226. The scan clock generator 240 may include a scan mode selection block 242, a scan pulse generator block 244, and a scan level shifter block 246. The sensing clock generator 260 may include a sensing mode selection block 262, a sensing pulse generator block 264, and a sensing level shifter block 266. In one embodiment, the gate clock generator 200 may also include a mode register 280. In addition to the carry clock generator 220 providing the multi-sensing enable signal MULTI_SEN_EN to the scan clock generator 240 and the sensing clock generator 260 in multi-clock mode instead of the first to eighth carry clock signals CR_CLK1 to CR_CLK8, Figure 5 The gate clock generator 200 can have the same characteristics as... Figure 2 It has a similar structure and similar operation to the gate clock generator 100.

[0105] Carry pulse generator block 224 can selectively provide a multi-sensor enable signal MULTI_SEN_EN to scan clock generator 240 and sensing clock generator 260 in response to mode signal SMODE. For example, carry pulse generator block 224 can provide a multi-sensor enable signal MULTI_SEN_EN with a conduction interval to scan clock generator 240 and sensing clock generator 260 respectively in response to mode signal SMODE, which indicates a multi-clock mode, when at least one or any one of the first to eighth carry clock signals CR_CLK1 to CR_CLK8 has a conduction interval. On the other hand, when mode signal SMODE does not indicate the multi-clock mode, that is, when mode signal SMODE indicates a general mode (or 1-clock mode), 2-clock mode, 3-clock mode, or 4-clock mode, carry pulse generator block 224 may not provide the multi-sensor enable signal MULTI_SEN_EN to scan clock generator 240 and sensing clock generator 260.

[0106] The scan pulse generator block 244 can receive a mode signal SMODE from the scan mode selection block 242 and, in response to the mode signal SMODE representing the multi-clock mode, generate first to eighth scan clock signals SC_CLK1 to SC_CLK8 based on the multi-sensor enable signal MULTI_SEN_EN, the scan on-clock signal SC_ON_CLK, and the scan off-clock signal SC_OFF_CLK. For example, during the 8th*M+K on-interval (e.g., the high interval) of the multi-sensor enable signal MULTI_SEN_EN (K is an integer greater than or equal to 1 and less than or equal to 8, and M is an integer greater than or equal to 0), the scan pulse generator block 244 can output the Kth scan clock signal, which has a number of pulses corresponding to the number of pulses of the scan on-clock signal SC_ON_CLK (or the number of pulses of the scan off-clock signal SC_OFF_CLK) in the 8th*M+K on-interval. On the other hand, when the mode signal SMODE represents an operating mode different from the multi-clock mode, the scan pulse generator block 244 can generate the scan clock signal SC_CLKN sequentially based on the scan on clock signal SC_ON_CLK and the scan off clock signal SC_OFF_CLK, independent of the multi-sensor enable signal MULTI_SEN_EN.

[0107] The sensing pulse generator block 264 can receive a mode signal SMODE from the sensing mode selection block 262, and in response to the mode signal SMODE representing the multi-clock mode, generate first to eighth sensing clock signals SS_CLK1 to SS_CLK8 based on the multi-sensing enable signal MULTI_SEN_EN, the sensing on-clock signal SS_ON_CLK, and the sensing off-clock signal SS_OFF_CLK. For example, during the 8th*M+K on-interval (e.g., the high interval) of the multi-sensing enable signal MULTI_SEN_EN (K is an integer greater than or equal to 1 and less than or equal to 8, and M is an integer greater than or equal to 0), the sensing pulse generator block 264 can output the Kth sensing clock signal, which has a number of pulses corresponding to the number of pulses of the sensing on-clock signal SS_ON_CLK (or the number of pulses of the sensing off-clock signal SS_OFF_CLK) in the 8th*M+K on-interval. On the other hand, when the mode signal SMODE represents an operating mode different from the multi-clock mode, the sensing pulse generator block 264 can sequentially generate the first to eighth sensing clock signals SS_CLK1 to SS_CLK8 based on the sensing turn-on clock signal SS_ON_CLK and the sensing turn-off clock signal SS_OFF_CLK, independent of the multi-sensing enable signal MULTI_SEN_EN.

[0108] The following is for reference Figure 5 as well as Figure 6 The following describes an example of the operation of the gate clock generator 200 in the multi-clock mode. In addition to the scan clock generator 240 and the sense clock generator 260 operating in the multi-clock mode based on the multi-sensor enable signal MULTI_SEN_EN instead of the first to eighth carry clock signals CR_CLK1 to CR_CLK8, Figure 6 The gate clock generator 200 shown can operate with Figure 3 The gate clock generator 100 shown operates similarly.

[0109] Reference Figure 5 as well as Figure 6In multi-clock mode, when at least one or any one of the first to eighth carry clock signals CR_CLK1 to CR_CLK8 has a conduction interval, the carry pulse generator block 224 can generate a multi-sensor enable signal MULTI_SEN_EN with a conduction interval. For example, the multi-sensor enable signal MULTI_SEN_EN can sequentially have a first conduction interval OP1 corresponding to the conduction interval of the first carry clock signal CR_CLK1, a second conduction interval OP2 corresponding to the conduction interval of the second carry clock signal CR_CLK2, and a conduction interval corresponding to the conduction intervals of the third to eighth carry clock signals CR_CLK3 to CR_CLK8. Next, the multi-sensor enable signal MULTI_SEN_EN can again have a first conduction interval OP1 corresponding to the conduction interval of the first carry clock signal CR_CLK1. In addition, the carry pulse generator block 224 can provide the multi-sensor enable signal MULTI_SEN_EN to the scan clock generator 240 and the sensing clock generator 260 respectively.

[0110] The scan pulse generator block 244 can generate a first scan clock signal SC_CLK1 with a rising edge in response to each pulse of the scan turn-on clock signal SC_ON_CLK and a falling edge in response to each pulse of the scan turn-off clock signal SC_OFF_CLK during the first turn-on interval OP1 of the multi-sensor enable signal MULTI_SEN_EN, and generate a second scan clock signal SC_CLK2 with a rising edge in response to each pulse of the scan turn-on clock signal SC_ON_CLK and a falling edge in response to each pulse of the scan turn-off clock signal SC_OFF_CLK during the second turn-on interval OP2 of the multi-sensor enable signal MULTI_SEN_EN, and generate an eighth scan clock signal SC_CLK8 with a rising edge in response to each pulse of the scan turn-on clock signal SC_ON_CLK and a falling edge in response to each pulse of the scan turn-off clock signal SC_OFF_CLK during the eighth turn-on interval of the multi-sensor enable signal MULTI_SEN_EN. Therefore, the switching number or the number of pulses for each scan clock signal SC_CLK1 to SC_CLK8 can be determined by the number of pulses of the scan on-clock signal SC_ON_CLK (or the number of pulses of the scan off-clock signal SC_OFF_CLK) in each high interval (i.e., each on-interval) of the multi-sensor enable signal MULTI_SEN_EN. The number of pulses for each scan clock signal SC_CLK1 to SC_CLK8 can be adjusted to any number (e.g., tens or hundreds). In addition, the scan pulse generator block 244 can repeat the sequential generation of the first to eighth scan clock signals SC_CLK1 to SC_CLK8 until the sensing signal SENSE becomes low.

[0111] The sensing pulse generator block 264 can generate a first sensing clock signal SS_CLK1 with a rising edge in response to each pulse of the sensing turn-on clock signal SS_ON_CLK and a falling edge in response to each pulse of the sensing turn-off clock signal SS_OFF_CLK during the first turn-on interval OP1 of the multi-sensing enable signal MULTI_SEN_EN, and generate a second sensing clock signal SS_CLK2 with a rising edge in response to each pulse of the sensing turn-on clock signal SS_ON_CLK and a falling edge in response to each pulse of the sensing turn-off clock signal SS_OFF_CLK during the second turn-on interval OP2 of the multi-sensing enable signal MULTI_SEN_EN, and generate an eighth sensing clock signal SS_CLK8 with a rising edge in response to each pulse of the sensing turn-on clock signal SS_ON_CLK and a falling edge in response to each pulse of the sensing turn-off clock signal SS_OFF_CLK during the eighth turn-on interval of the multi-sensing enable signal MULTI_SEN_EN. Therefore, the switching number or the number of pulses for each sensing clock signal SS_CLK1 to SS_CLK8 can be determined by the number of pulses of the sensing on-clock signal SS_ON_CLK (or the number of pulses of the sensing off-clock signal SS_OFF_CLK) in each high interval (i.e., each on-interval) of the multi-sensing enable signal MULTI_SEN_EN. The number of pulses for each sensing clock signal SS_CLK1 to SS_CLK8 can be adjusted to any number (e.g., tens or hundreds). In addition, the sensing pulse generator block 264 can repeat the sequential generation of the first to eighth sensing clock signals SS_CLK1 to SS_CLK8 until the sensing signal SENSE becomes low.

[0112] Figure 7 This is a block diagram illustrating a gate clock generator according to yet another embodiment of the present invention. Figure 8 This is a block diagram illustrating an example of a gate clock generator according to yet another embodiment of the present invention.

[0113] Reference Figure 7 as well as Figure 8The gate clock generator 300 of the display device may include a carry clock generator 320, a scan clock generator 340, and a sensing clock generator 360. The carry clock generator 320 may include a carry mode selection block 322, a carry pulse generator block 324, and a carry level shifter block 326. The scan clock generator 340 may include a scan mode selection block 342, a scan pulse generator block 344, and a scan level shifter block 346. The sensing clock generator 360 may include a sensing mode selection block 362, a sensing pulse generator block 364, and a sensing level shifter block 366. In one embodiment, the gate clock generator 300 may also include a mode register 380. In addition to the scan clock generator 340 and the sensing clock generator 360 receiving a multi-sensor enable signal MULTI_SEN_EN from the controller of the display device instead of the carry clock generator 320, Figure 7 as well as Figure 8 The gate clock generator 300 can have the same characteristics as... Figure 4 as well as Figure 5 It has a similar structure and similar operation to the gate clock generator 200.

[0114] The carry clock generator 320 can receive a carry-on clock signal CR_ON_CLK and a carry-off clock signal CR_OFF_CLK from the controller, and sequentially generate N (N is an integer greater than 2) carry clock signals CR_CLKN based on the carry-on clock signal CR_ON_CLK and the carry-off clock signal CR_OFF_CLK. In one embodiment, the operation of the carry clock generator 320 in multi-clock mode can be substantially the same as the operation of the carry clock generator 320 in a different operating mode than the multi-clock mode, but is not limited thereto.

[0115] The scan clock generator 340 can receive a multi-sensor enable signal MULTI_SEN_EN, a scan on clock signal SC_ON_CLK, and a scan off clock signal SC_OFF_CLK from the controller. In the multi-clock mode, it sequentially generates N scan clock signals SC_CLKN based on the multi-sensor enable signal MULTI_SEN_EN, the scan on clock signal SC_ON_CLK, and the scan off clock signal SC_OFF_CLK. In a different operating mode than the multi-clock mode (e.g., a normal mode (or 1-clock mode), 2-clock mode, 3-clock mode, or 4-clock mode), it sequentially generates N scan clock signals SC_CLKN based on the scan on clock signal SC_ON_CLK and the scan off clock signal SC_OFF_CLK, regardless of the multi-sensor enable signal MULTI_SEN_EN. In one embodiment, the scan pulse generator block 344 may, in response to a mode signal SMODE representing the multi-clock mode, generate first to eighth scan clock signals SC_CLK1 to SC_CLK8 based on a multi-sensor enable signal MULTI_SEN_EN, a scan on clock signal SC_ON_CLK, and a scan off clock signal SC_OFF_CLK received from the controller, and in response to a mode signal SMODE representing an operating mode different from the multi-clock mode, generate first to eighth scan clock signals SC_CLK1 to SC_CLK8 based on a scan on clock signal SC_ON_CLK and a scan off clock signal SC_OFF_CLK. For example, in the multi-clock mode, the scan pulse generator block 344 can generate a first scan clock signal SC_CLK1 with a rising edge in response to each pulse of the scan on-clock signal SC_ON_CLK and a falling edge in response to each pulse of the scan off-clock signal SC_OFF_CLK during the first on-interval of the multi-sensor enable signal MULTI_SEN_EN, and generate a second scan clock signal SC_CLK2 with a rising edge in response to each pulse of the scan on-clock signal SC_ON_CLK and a falling edge in response to each pulse of the scan off-clock signal SC_OFF_CLK during the second on-interval of the multi-sensor enable signal MULTI_SEN_EN.

[0116] The sensing clock generator 360 can receive a multi-sensor enable signal MULTI_SEN_EN, a sensing on-clock signal SS_ON_CLK, and a sensing off-clock signal SS_OFF_CLK from the controller. In the multi-clock mode, it sequentially generates N sensing clock signals SS_CLKN based on the multi-sensor enable signal MULTI_SEN_EN, the sensing on-clock signal SS_ON_CLK, and the sensing off-clock signal SS_OFF_CLK. In a different operating mode than the multi-clock mode (e.g., a normal mode (or 1-clock mode), 2-clock mode, 3-clock mode, or 4-clock mode), it sequentially generates N sensing clock signals SS_CLKN based on the sensing on-clock signal SS_ON_CLK and the sensing off-clock signal SS_OFF_CLK, independent of the multi-sensor enable signal MULTI_SEN_EN. In one embodiment, the sensing pulse generator block 364 may, in response to a mode signal SMODE representing the multi-clock mode, generate first to eighth sensing clock signals SS_CLK1 to SS_CLK8 based on a multi-sensor enable signal MULTI_SEN_EN, a sensing on-clock signal SS_ON_CLK, and a sensing off-clock signal SS_OFF_CLK received from the controller, and in response to a mode signal SMODE representing an operating mode different from the multi-clock mode, generate first to eighth sensing clock signals SS_CLK1 to SS_CLK8 based on a sensing on-clock signal SS_ON_CLK and a sensing off-clock signal SS_OFF_CLK. For example, in the multi-clock mode, the sensing pulse generator block 364 can generate a first sensing clock signal SS_CLK1 with a rising edge in response to each pulse of the sensing turn-on clock signal SS_ON_CLK and a falling edge in response to each pulse of the sensing turn-off clock signal SS_OFF_CLK during the first turn-on interval of the multi-sensing enable signal MULTI_SEN_EN, and generate a second sensing clock signal SS_CLK2 with a rising edge in response to each pulse of the sensing turn-on clock signal SS_ON_CLK and a falling edge in response to each pulse of the sensing turn-off clock signal SS_OFF_CLK during the second turn-on interval of the multi-sensing enable signal MULTI_SEN_EN.

[0117] As described above, the gate clock generator 300 according to another embodiment of the present invention may have the multi-clock mode. In the multi-clock mode, the scan clock generator 340 and the sensing clock generator 360 receive a multi-sensing enable signal MULTI_SEN_EN from the controller. The scan clock generator 340 outputs a corresponding scan clock signal with an arbitrary number of pulses in each conduction interval of the multi-sensing enable signal MULTI_SEN_EN, and the sensing clock generator 360 outputs a corresponding sensing clock signal with an arbitrary number of pulses in each conduction interval of the multi-sensing enable signal MULTI_SEN_EN. Thus, the display device including the gate clock generator 300 according to another embodiment of the present invention can perform the multiple sensing operations for each pixel within a frame interval.

[0118] Figure 9 This is a block diagram illustrating a display device according to an embodiment of the present invention. Figure 10 This is a circuit diagram illustrating an example of pixels included in a display device according to an embodiment of the present invention.

[0119] Reference Figure 9 The display device 400 according to an embodiment of the present invention may include: a display panel 410 including a plurality of pixels PX; a data driver 420 connected to the plurality of pixels PX via a plurality of data lines DL; a sensing circuit 430 connected to the plurality of pixels PX via a plurality of sensing lines SL; a gate clock generator 440 generating N carry clock signals CR_CLKN, N scan clock signals SC_CLKN and N sensing clock signals SS_CLKN; a gate driver 450 providing the plurality of scan signals SC and the plurality of sensing signals SS to the plurality of pixels PX; and a controller 460 controlling the data driver 420, the sensing circuit 430, the gate clock generator 440 and the gate driver 450.

[0120] Display panel 410 may include multiple data lines DL, multiple sensing lines SL, and multiple pixels PX connected to the multiple data lines DL and multiple sensing lines SL. Additionally, display panel 410 may also include multiple scan signal lines for transmitting multiple scan signals SC and multiple sensing signal lines for transmitting multiple sensing signals SS. In one embodiment, each pixel PX may include at least one capacitor, at least two transistors, and an organic light-emitting diode (OLED), and display panel 410 may be an OLED display panel.

[0121] For example, such as Figure 10As shown, each pixel PX may include a driving transistor TDR, a first switching transistor TSW1, a second switching transistor TSW2, a storage capacitor CST, and an organic light-emitting diode EL.

[0122] The storage capacitor CST can store the data signal DS transmitted via the data line DL. In one embodiment, the storage capacitor CST may have: a first electrode connected to the gate of the driving transistor TDR; and a second electrode connected to the source of the driving transistor TDR.

[0123] The first switching transistor TSW1 can connect the data line DL to the first electrode of the storage capacitor CST in response to the scan signal SC. That is, the first switching transistor TSW1 can transmit the data signal DS of the data line DL to the first electrode of the storage capacitor CST in response to the scan signal SC. In one embodiment, the first switching transistor TSW1 may have: a gate for receiving the scan signal SC; a drain connected to the data line DL; and a source connected to the first electrode of the storage capacitor CST and the gate of the driving transistor TDR.

[0124] The second switching transistor TSW2 can connect the sensing line SL to the second electrode of the storage capacitor CST and the source of the driving transistor TDR in response to the sensing signal SS. In one embodiment, the second switching transistor TSW2 may have: a gate for receiving the sensing signal SS; a drain connected to the source of the driving transistor TDR; and a source connected to the sensing line SL.

[0125] The driving transistor TDR can generate a driving current based on the data signal DS stored in the storage capacitor CST. In one embodiment, the driving transistor TDR may have: a gate, connected to the first electrode of the storage capacitor CST; a drain, receiving a first power supply voltage (e.g., a high power supply voltage) ELVDD; and a source, connected to the second electrode of the storage capacitor CST and the drain of the second switching transistor TSW2.

[0126] An organic light-emitting diode (OLED) EL can emit light in response to the drive current generated by a drive transistor TDR. In one embodiment, the OLED EL may have: a positive terminal connected to the source of the drive transistor TDR; and a negative terminal receiving a second power supply voltage (e.g., a low power supply voltage) ELVSS.

[0127] On the other hand, despite Figure 10 An example of pixel PX is shown, but the pixel PX of the display device 400 according to an embodiment of the present invention is not limited to... Figure 10Examples are provided. Alternatively, in another embodiment, the display panel 410 may be a liquid crystal display (LCD) panel where each pixel PX includes a switching transistor and a liquid crystal capacitor connected to the switching transistor. However, the display panel 410 is not limited to the LCD panel and the OLED panel, and may be any display panel.

[0128] Data driver 420 can generate a data signal DS based on the output image data ODAT received from controller 460 and a data control signal DCTRL, and provide the data signal DS to multiple pixels PX through multiple data lines DL. In one embodiment, the data control signal DCTRL may include a data enable signal, a data clock signal, and / or a load signal, but is not limited thereto. In one embodiment, data driver 420 may be implemented as one or more integrated circuits. In another embodiment, data driver 420 and controller 460 may be implemented as a single integrated circuit, such integrated circuit may be called a timing controller embedded data driver (TED).

[0129] The sensing circuit 430 can perform sensing operations for multiple pixels PX via multiple sensing lines SL. For example, for each pixel PX, the data driver 420 provides a sensing data voltage as a data signal DS to the pixel PX, and the gate driver 450 provides a scan signal SC and a sensing signal SS to the pixel PX. The sensing circuit 430 measures the current or voltage of the generated pixel PX based on the sensing data voltage via the sensing lines SL. In one embodiment, in a multi-clock mode, within a frame interval, multiple pulses (e.g., tens or hundreds of pulses) of scan and sensing signals SC and SS are provided to each pixel PX, thereby allowing the sensing circuit 430 to perform the sensing operations for the pixel PX multiple times (e.g., tens or hundreds of times). In one embodiment, the sensing circuit 430 can be implemented as an integrated circuit separate from the integrated circuit of the data driver 420. In another embodiment, the sensing circuit 430 can be included in the data driver 420 or in the controller 460.

[0130] Alternatively, the gate clock generator 440 may generate a signal / voltage for the gate driver 450 based on a scan control signal received from the controller 460, and the gate driver 450 may apply multiple scan signals SC and multiple sensing signals SS sequentially to multiple pixels PX in row units based on the signal / voltage received from the gate clock generator 440. In one embodiment, the gate clock generator 440 can receive carry-on clock signal CR_ON_CLK, carry-off clock signal CR_OFF_CLK, scan-on clock signal SC_ON_CLK, scan-off clock signal SC_ON_CLK, sense-on clock signal SS_ON_CLK, and sense-off clock signal SS_OFF_CLK from the controller 460, and sequentially generate N carry clock signals CR_CLKN based on the carry-on clock signal CR_ON_CLK and carry-off clock signal CR_OFF_CLK, N scan clock signals SC_CLKN based on the scan-on clock signal SC_ON_CLK and scan-off clock signal SC_ON_CLK, and N sense clock signals SS_CLKN based on the sense-on clock signal SS_ON_CLK and sense-off clock signal SS_OFF_CLK. The gate driver 450 can sequentially generate multiple scan signals SC and multiple sensing signals SS based on N carry clock signals CR_CLKN, N scan clock signals SC_CLKN, and N sensing clock signals SS_CLKN. In one embodiment, the gate clock generator 440 may be included in the power management integrated circuit (PMIC) that supplies power to the display device 400, but is not limited thereto. In another embodiment, the gate driver 450 may be integrated or formed in the periphery of the display panel 410. In yet another embodiment, the gate driver 450 may be implemented as one or more integrated circuits.

[0131] Controller 460 (e.g., a timing controller) can receive input image data IDAT and control signals CTRL from an external host processor (e.g., an application processor (AP), a graphics processing unit (GPU), or a graphics card). In one embodiment, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Controller 460 can generate output image data ODAT, a data control signal DCTRL, and on / off clock signals CR_ON_CLK, CR_OFF_CLK, SC_ON_CLK, SC_OFF_CLK, SS_ON_CLK, and SS_OFF_CLK based on the input image data IDAT and the control signal CTRL. The controller 460 can provide the output image data ODAT and the data control signal DCTRL to the data driver 420 to control the operation of the data driver 420, and provide the on / off clock signals CR_ON_CLK, CR_OFF_CLK, SC_ON_CLK, SC_OFF_CLK, SS_ON_CLK, and SS_OFF_CLK to the gate clock generator 440 to control the operation of the gate clock generator 440 and the gate driver 450.

[0132] In the display device 400 according to an embodiment of the present invention, in the multi-clock mode, during the conduction interval of the Kth carry clock signal (K is an integer greater than or equal to 1 and less than N) among the N carry clock signals CR_CLKN, the gate clock generator 440 outputs the Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan-on clock signal SC_ON_CLK in the conduction interval of the Kth carry clock signal, and outputs the Kth sensing clock signal having a number of pulses corresponding to the number of pulses of the sensing-on clock signal SS_ON_CLK in the conduction interval of the N sensing clock signals SS_CLKN, as the Kth sensing clock signal. Thus, the display device 400 is capable of performing multiple sensing operations for each pixel within a frame interval. Furthermore, since the on / off clock signals CR_ON_CLK, CR_OFF_CLK, SC_ON_CLK, SC_OFF_CLK, SS_ON_CLK, and SS_OFF_CLK are transmitted between the controller 460 and the gate clock generator 440 instead of N carry clock signals CR_CLKN, N scan clock signals SC_CLKN, and N sense clock signals SS_CLKN, the number of output pins of the controller 460 and the number of input pins of the gate clock generator 440 can be reduced.

[0133] Figure 11 This is a block diagram illustrating an electronic device including a display device according to an embodiment of the present invention.

[0134] Reference Figure 11 Electronic device 1100 may include processor 1110, memory device 1120, storage device 1130, input / output device 1140, power supply 1150, and display device 1160. Electronic device 1100 may also include multiple ports capable of communicating with display cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0135] Processor 1110 can perform specific calculations or tasks. According to embodiments, processor 1110 can be a microprocessor, central processing unit (CPU), etc. Processor 1110 can be connected to other components via address bus, control bus, and data bus. According to embodiments, processor 1110 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0136] The memory device 1120 can store the data required for the operation of the electronic device 1100. For example, memory device 1120 may include non-volatile memory devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), Flash Memory, PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), FRAM (Ferroelectric Random Access Memory), and / or volatile memory devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and mobile DRAM.

[0137] Storage device 1130 may include a solid-state drive (SSD), a hard disk drive (HDD), an optical disc read-only memory (CD-ROM), etc. Input / output device 1140 may include input components such as a keyboard, keypad, touchpad, touch screen, mouse, etc., and output components such as speakers, printers, etc. Power supply 1150 can supply the power required for the operation of electronic device 1100. Display device 1160 can be connected to other components via the bus or other communication links.

[0138] In the display device 1160, a carry clock generator may generate N carry clock signals based on a carry-on clock signal and a carry-off clock signal, a scan clock generator may generate N scan clock signals based on a scan-on clock signal and a scan-off clock signal, and a sensing clock generator may generate N sensing clock signals based on a sensing-on clock signal and a sensing-off clock signal. This reduces the number of output pins of the controller and the number of input pins of the gate clock generator in the display device 1160. Furthermore, in the display device 1160, in a multi-clock mode, the scan clock generator may output a Kth scan clock signal with an arbitrary number of pulses during the conduction interval of the Kth carry clock signal, and in the same multi-clock mode, the sensing clock generator may output a Kth sensing clock signal with an arbitrary number of pulses during the conduction interval of the Kth carry clock signal. This allows the display device 1160 to perform multiple sensing operations for each pixel within a single frame interval.

[0139] According to an embodiment, the electronic device 1100 may be any electronic device including the display device 1160, such as a mobile phone, smartphone, tablet computer, virtual reality (VR) device, digital television, 3D television, personal computer (PC), home electronics, laptop computer, personal digital assistant (PDA), portable multimedia player (PMP), digital camera, music player, portable game console, navigation device, etc.

[0140] (Industry availability)

[0141] This invention can be applied to any display device and electronic device including it. For example, it can be applied to mobile phones, smartphones, tablet computers, virtual reality devices, digital televisions, 3D televisions, PCs, home electronics, laptop computers, PDAs, PMPs, digital cameras, music players, portable game consoles, navigators, etc.

[0142] The above description refers to embodiments of the present invention. However, those skilled in the art will understand that various modifications and alterations can be made to the present invention without departing from the concept and scope of the invention as set forth in the claims.

Claims

1. A gate clock generator, used in a display device to generate a gate clock signal for a gate driver, characterized in that, The gate clock generator includes: The carry clock generator generates N carry clock signals sequentially based on the carry on clock signal and the carry off clock signal, where N is an integer greater than 2. A scan clock generator generates N scan clock signals based on the scan on-clock signal and the scan off-clock signal; and A sensing clock generator generates N sensing clock signals based on a sensing on-clock signal and a sensing off-clock signal. In multi-clock mode, during the conduction interval of the Kth carry clock signal among the N carry clock signals, the scan clock generator, as the Kth scan clock signal among the N scan clock signals, outputs the Kth scan clock signal having a number of pulses corresponding to the number of pulses of the scan conduction clock signal in the conduction interval of the Kth carry clock signal; the sensing clock generator, as the Kth sensing clock signal among the N sensing clock signals, outputs the Kth sensing clock signal having a number of pulses corresponding to the number of pulses of the sensing conduction clock signal in the conduction interval of the Kth carry clock signal, where K is an integer greater than or equal to 1 and less than or equal to N.

2. The gate clock generator according to claim 1, characterized in that, In the multi-clock mode, the carry clock generator provides the N carry clock signals to the scan clock generator and the sensing clock generator.

3. The gate clock generator according to claim 2, characterized in that, In the multi-clock mode, during the conduction interval of the Kth carry clock signal, the scan clock generator changes the Kth scan clock signal to a conduction level in response to each pulse of the scan conduction clock signal, and changes the Kth scan clock signal to a cutoff level in response to each pulse of the scan cutoff clock signal. In the multi-clock mode, the sensing clock generator changes the Kth sensing clock signal to the on level in response to each pulse of the sensing on clock signal during the on interval of the Kth carry clock signal, and changes the Kth sensing clock signal to the off level in response to each pulse of the sensing off clock signal.

4. The gate clock generator according to claim 1, characterized in that, The carry clock generator includes: The carry mode selection block determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode. A carry pulse generator block sequentially generates the N carry clock signals based on the carry-on clock signal and the carry-off clock signal, and provides the N carry clock signals to the scan clock generator and the sensing clock generator in response to the mode signal representing the multi-clock mode; and The carry level shifter block adjusts the voltage level of the N carry clock signals to a voltage level suitable for the gate driver and provides the N carry clock signals to the gate driver.

5. The gate clock generator according to claim 1, characterized in that, The scan clock generator includes: The scan mode selection block determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode. A scan pulse generator block, in response to a mode signal representing the multi-clock mode, generates the N scan clock signals based on the N carry clock signals, the scan on clock signal, and the scan off clock signal; and in response to a mode signal representing an operating mode different from the multi-clock mode, generates the N scan clock signals based on the scan on clock signal and the scan off clock signal; and A scan level shifter block adjusts the voltage levels of the N scan clock signals to a voltage level suitable for the gate driver and provides the N scan clock signals to the gate driver.

6. The gate clock generator according to claim 1, characterized in that, The sensing clock generator includes: A sensing mode selection block determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode. A sensing pulse generator block, in response to a mode signal representing the multi-clock mode, generates N sensing clock signals based on the N carry clock signals, the sensing on clock signal, and the sensing off clock signal; and in response to a mode signal representing an operating mode different from the multi-clock mode, generates the N sensing clock signals based on the sensing on clock signal and the sensing off clock signal; and A sensing level shifter block adjusts the voltage levels of the N sensing clock signals to a voltage level suitable for the gate driver and provides the N sensing clock signals to the gate driver.

7. The gate clock generator according to claim 1, characterized in that, In the multi-clock mode, the carry clock generator provides a multi-sensor enable signal to the scan clock generator and the sense clock generator.

8. The gate clock generator according to claim 7, characterized in that, In the multi-clock mode, during the first conduction interval of the multi-sensor enable signal, the scan clock generator, in response to each pulse of the scan conduction clock signal, changes the first scan clock signal among the N scan clock signals to a conduction level, and in response to each pulse of the scan cutoff clock signal, changes the first scan clock signal to a cutoff level. During the second conduction interval of the multi-sensor enable signal, in response to each pulse of the scan conduction clock signal, the second scan clock signal among the N scan clock signals is changed to the conduction level, and in response to each pulse of the scan cutoff clock signal, the second scan clock signal is changed to the cutoff level. In the multi-clock mode, during the first conduction interval of the multi-sensor enable signal, the sensing clock generator changes the first sensing clock signal among the N sensing clock signals to the conduction level in response to each pulse of the sensing conduction clock signal, and changes the first sensing clock signal to the cutoff level in response to each pulse of the sensing cutoff clock signal. During the second conduction interval of the multi-sensor enable signal, the generator changes the second sensing clock signal among the N sensing clock signals to the conduction level in response to each pulse of the sensing conduction clock signal, and changes the second sensing clock signal to the cutoff level in response to each pulse of the sensing cutoff clock signal.

9. The gate clock generator according to claim 1, characterized in that, The carry clock generator includes: The carry mode selection block determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode. A carry pulse generator block sequentially generates the N carry clock signals based on the carry-on clock signal and the carry-off clock signal, and generates a multi-sensor enable signal with a conduction interval when at least one of the N carry clock signals has a conduction interval in response to the mode signal representing the multi-clock mode; and The carry level shifter block adjusts the voltage level of the N carry clock signals to a voltage level suitable for the gate driver and provides the N carry clock signals to the gate driver.

10. The gate clock generator according to claim 1, characterized in that, The scan clock generator includes: The scan mode selection block determines the operating mode of the gate clock generator and generates a mode signal representing the determined operating mode. A scan pulse generator block, in response to a mode signal representing the multi-clock mode, generates the N scan clock signals based on a multi-sensor enable signal received from the carry clock generator, the scan on clock signal, and the scan off clock signal; and in response to a mode signal representing an operating mode different from the multi-clock mode, generates the N scan clock signals based on the scan on clock signal and the scan off clock signal; and A scan level shifter block adjusts the voltage levels of the N scan clock signals to a voltage level suitable for the gate driver and provides the N scan clock signals to the gate driver.

Images