Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate including an active pattern; a first interlayer dielectric layer located on the substrate, the first interlayer dielectric layer including a groove in its upper portion; and a lower connecting line located in the first interlayer dielectric layer, the lower connecting line being electrically connected to the active pattern, and the lower connecting line including a conductive pattern and a barrier pattern. The groove of the first interlayer dielectric layer selectively exposes a top surface of the conductive pattern. The barrier pattern is located between the conductive pattern and the first interlayer dielectric layer, and the first interlayer dielectric layer covers a top surface of the barrier pattern.

Description

[0001] [Cross - reference to related applications]

[0002] Korean Patent Application No. 10 - 2018 - 0113152, filed on September 20, 2018 with the Korean Intellectual Property Office and entitled "Semiconductor Device and Method of Manufacturing the Same", is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device including connection lines on an integrated circuit of a substrate and a method of manufacturing the semiconductor device. Background Art

[0004] Semiconductor devices are widely used in the electronics industry due to their small size, versatility, and / or low manufacturing cost. Semiconductor devices can include memory devices for storing data, logic devices for processing data, and hybrid devices for operating various functions in parallel or simultaneously.

[0005] With the progress of the development of the electronics industry, the demand for semiconductor devices with high integration and high speed has been increasing. However, due to the reduction of process margins in the exposure process for defining fine patterns, it has become increasingly difficult to manufacture highly integrated devices and / or semiconductor devices. Various studies have been conducted to meet the requirements of high integration and / or high speed in semiconductor devices.

[0006] In addition, in the semiconductor industry, there has been a continuous need for high capacity, thinness, and small size in various semiconductor packaging technologies for semiconductor devices and electronic products using the semiconductor devices. One method of various packaging technologies is a packaging technology that vertically stacks multiple semiconductor chips to achieve high - density chip stacking. Compared with a semiconductor package composed of one semiconductor chip, this packaging technology has the advantage of being able to integrate semiconductor chips with various functions in a small area. Summary of the Invention

[0007] According to some exemplary embodiments, a semiconductor device may include: a substrate having an active pattern; a first interlayer dielectric layer located on the substrate, the first interlayer dielectric layer including a groove in its upper portion; and a lower connection line located in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line including a conductive pattern and a barrier pattern, the groove of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, the barrier pattern being located between the conductive pattern and the first interlayer dielectric layer, and the first interlayer dielectric layer covering a top surface of the barrier pattern.

[0008] According to some exemplary embodiments, a semiconductor device may include: a substrate; a first interlayer dielectric layer located on the substrate; and a lower connection line located in the first interlayer dielectric layer. The lower connection line may include: a conductive pattern; and a barrier pattern located between the conductive pattern and the first interlayer dielectric layer. The first interlayer dielectric layer may include: a groove exposing a top surface of the conductive pattern; and a portion adjacent to the groove located on a top surface of the barrier pattern.

[0009] According to some exemplary embodiments, a semiconductor device may include: a substrate having an active pattern; a first interlayer dielectric layer located on the substrate; a lower connection line located in the first interlayer dielectric layer and electrically connected to the active pattern; and a liner located between the first interlayer dielectric layer and the lower connection line. A top surface of the liner may be coplanar with a top surface of the first interlayer dielectric layer.

[0010] According to some exemplary embodiments, a method of manufacturing a semiconductor device may include: forming a sacrificial layer on a substrate; forming a lower connection line in the sacrificial layer; selectively forming a top cover pattern on a top surface of the lower connection line; replacing the sacrificial layer with a first interlayer dielectric layer; and selectively removing the top cover pattern to form a groove that exposes the top surface of the lower connection line. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] By describing the exemplary embodiments in detail with reference to the accompanying drawings, the features will become apparent to those skilled in the art, where:

[0012] Figure 1 A plan view of a semiconductor device according to some exemplary embodiments is shown.

[0013] Figure 2A And Figure 2B Respectively show cross-sectional views taken along Figure 1 the lines I-I' and II-II' shown.

[0014] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A and Figure 8A show a cross-sectional view along line I-I' shown in Figure 1 , which shows stages in a method of manufacturing a semiconductor device according to some exemplary embodiments.

[0015] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B and Figure 8B show a cross-sectional view along line II-II' shown in Figure 1 , which shows stages in a method of manufacturing a semiconductor device according to some exemplary embodiments.

[0016] Figure 9A and Figure 9B respectively show cross-sectional views of a semiconductor device according to some exemplary embodiments along line I-I' and line II-II' shown in Figure 1 .

[0017] Figure 10A and Figure 11A show a cross-sectional view along line I-I' shown in Figure 1 , which shows stages in a method of manufacturing a semiconductor device according to some exemplary embodiments.

[0018] Figure 10B and Figure 11B show a cross-sectional view along line II-II' shown in Figure 1 , which shows stages in a method of manufacturing a semiconductor device according to some exemplary embodiments.

[0019] Figure 12 show a cross-sectional view along line I-I' shown in Figure 1 , which shows a semiconductor device according to some exemplary embodiments.

[0020] Figure 13 and Figure 14 show a cross-sectional view along line I-I' shown in Figure 1 , which shows stages in a method of manufacturing a semiconductor device according to some exemplary embodiments.

[0021] Figure 15 show a cross-sectional view along line I-I' shown in Figure 1 , which shows a semiconductor device according to some exemplary embodiments.

[0022] Figure 16 show a cross-sectional view along line I-I' shown in Figure 1A cross-sectional view of the line I-I' is shown, which shows a method of manufacturing a semiconductor device according to some exemplary embodiments.

[0023] Figure 17 Shows along Figure 1 A cross-sectional view of the line I-I' is shown, which shows a semiconductor device according to some exemplary embodiments. Detailed Description

[0024] Figure 1 A plan view showing a semiconductor device according to some exemplary embodiments is shown. Figure 2A And Figure 2B Respectively show cross-sectional views taken along Figure 1 The lines I-I' and II-II' shown.

[0025] Referring to Figure 1 , Figure 2A And Figure 2B , the substrate 100 may include an active region AR. The active region AR may be defined by a second trench TR2 formed on an upper portion of the substrate 100. The substrate 100 may be, for example, a compound semiconductor substrate or a semiconductor substrate including silicon, germanium, silicon-germanium, etc. For example, the substrate 100 may be a silicon substrate.

[0026] The active region AR may be a logic unit region provided with logic transistors, and the logic transistors constitute a logic circuit of the semiconductor device. As another option, the active region AR may be a logic unit region for storing data.

[0027] As Figure 2A Shown in, a plurality of active patterns AP extending in a second direction D2 and spaced apart from each other in a first direction D1 may be provided on the active region AR. The active pattern AP may be a vertically protruding portion of the substrate 100. A first trench TR1 may be defined between adjacent active patterns AP.

[0028] The device isolation layer ST may fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a dielectric material, such as a silicon oxide layer. The upper portion of the active pattern AP may vertically protrude beyond (e.g., above) the device isolation layer ST. Each of the upper portions of the active pattern AP may have a fin shape. The device isolation layer ST may not cover the upper portion of the active pattern AP. The device isolation layer ST may cover the lower sidewalls of the active pattern AP.

[0029] The source / drain pattern SD may be provided on the upper portion of the active pattern AP. The source / drain pattern SD may be an impurity region having a first conductivity type (e.g., p-type) or a second conductivity type (e.g., n-type). As Figure 2B Shown in, the channel region CH may be sandwiched between a pair of source / drain patterns SD of the same active pattern AP.

[0030] The source / drain pattern SD can be an epitaxial pattern formed by a selective epitaxial growth process. For example, along the third direction D3, the top surface of the source / drain pattern SD can be at a higher level than the top surface of the channel region CH. For example, the source / drain pattern SD can include a semiconductor element (e.g., SiGe) having a lattice constant larger than that of the semiconductor element of the substrate 100. In another example, the source / drain pattern SD can include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., Si).

[0031] Each gate electrode GE can be arranged to extend in the first direction D1 while running across the active pattern AP. The gate electrodes GE can be spaced apart from each other in the second direction D2. The gate electrode GE can perpendicularly overlap the channel region CH. The gate electrode GE can include, for example, one or more of a conductive metal nitride (e.g., titanium nitride or tantalum nitride) and a metal (e.g., titanium, tantalum, tungsten, copper, or aluminum).

[0032] A pair of gate spacers GS can be located on two opposite sidewalls of each of the gate electrodes GE. The gate spacers GS can extend in the first direction D1 along the gate electrode GE. The gate spacers GS can include, for example, one or more of SiCN, SiCON, and SiN.

[0033] The gate dielectric pattern GI can be sandwiched between the corresponding gate electrode GE and the corresponding channel region CH. The gate dielectric pattern GI can include a high-k dielectric material. The gate cap pattern GP can be disposed on the corresponding gate electrode GE. For example, the gate cap pattern GP can include one or more of SiON, SiCN, SiCON, and SiN.

[0034] The first interlayer dielectric layer 110 can be disposed on the substrate 100. The first interlayer dielectric layer 110 can cover the source / drain pattern SD, the gate spacers GS, and the gate cap pattern GP. The first interlayer dielectric layer 110 can include, for example, a silicon oxide layer.

[0035] The active contact AC can penetrate the first interlayer dielectric layer 110 and be electrically connected to the source / drain pattern SD. The active contact AC can be located between a pair of gate electrodes GE.

[0036] The second interlayer dielectric layer 120, the third interlayer dielectric layer 130, and the fourth interlayer dielectric layer 140 can be sequentially stacked on the first interlayer dielectric layer 110 along the third direction D3. The second interlayer dielectric layer 120, the third interlayer dielectric layer 130, and the fourth interlayer dielectric layer 140 can include, for example, a silicon oxide layer.

[0037] The through-hole VI can be disposed in the second interlayer dielectric layer 120. For example, the thickness of the through-hole VI in the third direction D3 can be equal to the thickness of the second interlayer dielectric layer 120. The through-hole VI can penetrate the second interlayer dielectric layer 120 and be connected to the active contact AC. For example, the through-hole VI can have a polyhedral island shape that extends through the entire thickness of the second interlayer dielectric layer 120 to contact the top of the active contact AC. The through-hole VI can include a barrier pattern BM and a conductive pattern FM. The barrier pattern BM can cover the bottom surface and the sidewalls of the conductive pattern FM. The barrier pattern BM can not cover the top surface of the conductive pattern FM. The barrier pattern BM of the through-hole VI can be sandwiched between the conductive pattern FM and the active contact AC.

[0038] The barrier pattern BM can include a metal nitride layer, for example, one or more of a titanium nitride layer, a tungsten nitride layer, and a tantalum nitride layer. The conductive pattern FM can comprise a metallic material, for example, one or more of aluminum, copper, tungsten, molybdenum, and cobalt.

[0039] The lower connecting line M1 can be disposed in the third interlayer dielectric layer 130. Each of the lower connecting lines M1 can have a linear shape extending in the second direction D2. The lower connecting lines M1 can be arranged along the first direction D1 spaced apart from each other. Each of the lower connecting lines M1 can include a barrier pattern BM and a conductive pattern FM. The detailed description of the barrier pattern BM and the conductive pattern FM can be the same as the detailed description of the barrier pattern BM and the conductive pattern FM of the through-hole VI described above.

[0040] For example, as Figure 1 and Figure 2A shown, the lower connecting line M1 can include a first lower connecting line M11, a second lower connecting line M12, and a third lower connecting line M13 that are adjacent to each other along the first direction D1. The respective portions of the third interlayer dielectric layer 130 can be separated between the lower connecting lines M1. The second lower connecting line M12 can be disposed on the through-hole VI and connected to the through-hole VI. For example, the second lower connecting line M12 can overlap the entire top of the through-hole VI in the first direction D1 and the second direction D2. The second lower connecting line M12 can be electrically connected to the active contact AC through the through-hole VI.

[0041] The third interlayer dielectric layer 130 can include grooves RS on its upper portion. For example, each of the grooves RS can extend from the top surface of the third interlayer dielectric layer 130 to a predetermined depth along the third direction D3. The grooves RS can be formed on the corresponding lower connecting line M1. Each of the grooves RS can perpendicularly overlap the conductive pattern FM of the corresponding lower connecting line M1. When viewed in a plan view, each groove RS can extend along the entire lower connecting line M1 thereunder in the second direction D2.

[0042] The groove RS can expose the top surface FMt of the conductive pattern FM of the lower connecting line M1. The groove RS may not expose the top surface B Mt of the barrier pattern BM of the lower connecting line M1. For example, the third interlayer dielectric layer 130 can cover the top surface B Mt of the barrier pattern BM of the lower connecting line M1.

[0043] The third interlayer dielectric layer 130 can have a top surface 130t, for example, at a horizontal height higher than the horizontal height of the top surface FMt of the conductive pattern FM of the lower connecting line M1 along the third direction D3. The horizontal height of the top surface 130t of the third interlayer dielectric layer 130 can be higher than the horizontal height of the bottom of the groove RS.

[0044] For example, the third interlayer dielectric layer 130 can include a portion 130p that vertically protrudes between a pair of adjacent lower connecting lines M1. For example, each portion 130p can vertically protrude between adjacent grooves RS. The portion 130p of the third interlayer dielectric layer 130 can be located on the top surface B Mt of the barrier pattern BM of the lower connecting line M1. For example, the portion 130p of the third interlayer dielectric layer 130 can cover the top surface B Mt of the barrier pattern BM of the lower connecting line M1. For example, the portion 130p of the third interlayer dielectric layer 130 can continuously extend to cover the top surface B Mt of the opposing barrier patterns BM of adjacent lower connecting lines M1. The portion 130p of the third interlayer dielectric layer 130 can be positioned higher than the top surface FMt of the conductive pattern FM of the lower connecting line M1.

[0045] The etch stop layer EST can be sandwiched between the third interlayer dielectric layer 130 and the fourth interlayer dielectric layer 140. The etch stop layer EST can cover the top surface 130t of the third interlayer dielectric layer 130. The etch stop layer EST can locally fill the groove RS. The etch stop layer EST can cover the top surface FMt of the conductive pattern FM of the lower connecting line M1, which is exposed by the groove RS. The step difference between the groove RS and the top surface 130t of the third interlayer dielectric layer 130 can allow the etch stop layer EST to have a stepped structure on the groove RS. The etch stop layer EST can include, for example, one or more of SiN, SiON, SiCN, and SiCON.

[0046] The upper connecting line M2 can be disposed in the fourth interlayer dielectric layer 140. Each of the upper connecting lines M2 can have a linear shape extending in the first direction D1. The upper connecting lines M2 can be arranged to be spaced apart from each other along the second direction D2. Each of the upper connecting lines M2 can include a barrier pattern BM and a conductive pattern FM. The detailed description of the barrier pattern BM and the conductive pattern FM can be the same as the detailed description of the barrier pattern BM and the conductive pattern FM of the via VI described above.

[0047] For example, as Figure 1 and Figure 2B shown in, the upper connection line M2 may include a first upper connection line M21, a second upper connection line M22, and a third upper connection line M23 that are adjacent to each other along the second direction D2. Each part of the fourth interlayer dielectric layer 140 may be separated between the upper connection lines M2. The second upper connection line M22 may be disposed on the second lower connection line M12 and connected to the second lower connection line M12.

[0048] For example, the second upper connection line M22 may include a vertical extension portion VP that extends vertically toward the substrate 100 along the third direction D3. The vertical extension portion VP may penetrate the fourth interlayer dielectric layer 140 and the etch stop layer EST to be connected to the second lower connection line M12. For example, the second upper connection line M22 may be electrically connected to the second lower connection line M12 through the vertical extension portion VP.

[0049] The vertical extension portion VP may be a part of the second upper connection line M22. The upper connection line M2 may be formed by a dual damascene process. In contrast, the through hole VI and the lower connection line M1 may each be formed by a single damascene process. The barrier pattern BM of the second lower connection line M12 may be sandwiched between the through hole VI and the conductive pattern FM of the second lower connection line M12.

[0050] The vertical extension portion VP may fill at least a part of the groove RS above the second lower connection line M12. The vertical extension portion VP may include a first segment P1 that contacts the conductive pattern FM of the lower connection line M1 through the groove RS, and may also include, for example, a second segment P2 that covers a part of the top surface 130t of the third interlayer dielectric layer 130. The second segment P2 of the vertical extension portion VP may not fill the groove RS. The first segment P1 may protrude more toward the substrate 100 than the second segment P2. For example, the first segment P1 may have a bottom surface lower than the bottom surface of the second segment P2. The etch stop layer EST may cover the lower sidewall of the second segment P2. For example, as Figures 2A to 2B shown in, only the second lower connection line M12 and the second upper connection line M22 among the lower connection line M1 and the upper connection line M2 may contact each other above the through hole VI, and the bottom of the fourth interlayer dielectric layer 140 may separate the other lower connection line M1 and the upper connection line M2 from each other.

[0051] For example, as Figure 1 shown in, an additional through hole may be formed on the substrate 100 ( Figure 1), additional connections may be provided in different ones of the lower and upper connecting lines M1 and M2. For example, additional connecting lines may be provided on the upper connecting line M2. For example, multiple metal layers may be provided on the upper connecting line M2.

[0052] Figure 3A 、 Figure 4A 、 Figure 5A 、 Figure 6A 、 Figure 7A and Figure 8A Shown along Figure 1 The cross-sectional view taken along line II' shows a method of manufacturing a semiconductor device according to some exemplary embodiments. Figure 3B 、 Figure 4B 、 Figure 5B 、 Figure 6B 、 Figure 7B and Figure 8B Shown along Figure 1 The cross-sectional view taken along line II-II' shows a method of manufacturing a semiconductor device according to some exemplary embodiments.

[0053] Reference Figure 1 、 Figure 3A and Figure 3B , a transistor may be formed on the active region AR of the substrate 100. The transistor may include an active pattern AP having a source / drain pattern SD, and may further include a gate electrode GE crossing the active pattern AP.

[0054] A first interlayer dielectric layer 110 may be formed to cover the transistors. Active contacts AC may be formed to penetrate the first interlayer dielectric layer 110 and be connected to the source / drain patterns SD.

[0055] A second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. A through hole VI may be formed in the second interlayer dielectric layer 120. The through hole VI may be formed by a single damascene process. For example, the formation of the through hole VI may include forming a hole by patterning the second interlayer dielectric layer 120 and forming a barrier pattern BM and a conductive pattern FM filling the hole.

[0056] A sacrificial layer SL may be formed on the second interlayer dielectric layer 120. The sacrificial layer SL may include, for example, a silicon oxide layer or a carbon-containing silicon oxide layer. A lower connection line M1 may be formed in the sacrificial layer SL. The lower connection line M1 may include a first lower connection line M11, a second lower connection line M12, and a third lower connection line M13 adjacent to each other. The lower connection line M1 may be formed using a single damascene process. For example, forming the lower connection line M1 may include patterning the sacrificial layer SL to form a plurality of holes, and forming a blocking pattern BM and a conductive pattern FM to fill each of the holes.

[0057] Referring to Figure 1 、 Figure 4A and Figure 4B a top cover pattern CP can be formed on a corresponding lower connecting line M1. The top cover pattern CP can be formed to cover a top surface FMt of a conductive pattern FM of the lower connecting line M1. The top cover pattern CP may not cover a top surface B Mt of a barrier pattern BM of the lower connecting line M1.

[0058] The formation of the top cover pattern CP can use spin coating, atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). A metal (e.g., Ti, Mo, Ta, Mn, Al, Co, Ru, or a combination thereof) can be used to form the top cover pattern CP.

[0059] The top cover pattern CP can be selectively formed on the conductive pattern FM of the lower connecting line M1. For example, a metal that shows an affinity for the metal of the conductive pattern FM can be used to form the top cover pattern CP, so the top cover pattern CP can be self-alignedly formed on the conductive pattern FM, e.g., not on the barrier pattern BM.

[0060] Referring to Figure 1 、 Figure 5A and Figure 5B the sacrificial layer SL can be selectively removed. The removal of the sacrificial layer SL can include performing a wet etching process, an ashing process, a dry etching process, or a combination thereof. For example, when the sacrificial layer SL contains carbon, an ashing process can be performed to damage the sacrificial layer SL, and then a wet etching process or a dry etching process can be performed to selectively remove the damaged sacrificial layer SL. When the sacrificial layer SL is removed, the second interlayer dielectric layer 120 can be retained. The removal of the sacrificial layer SL can expose sidewalls of the top cover pattern CP and sidewalls of the lower connecting line M1.

[0061] Referring to Figure 1 、 Figure 6A and Figure 6B a third interlayer dielectric layer 130 can be formed to cover the exposed top cover pattern CP and the lower connecting line Ml. The third interlayer dielectric layer 130 can cover a top surface of the top cover pattern CP. The third interlayer dielectric layer 130 can have a top surface higher than the top surface of the top cover pattern CP. The third interlayer dielectric layer 130 can be formed by an ALD process showing superior gas filling characteristics or a flowable chemical vapor deposition (FCVD) process. The third interlayer dielectric layer 130 can include a silicon oxide layer with a low dielectric constant.

[0062] Referring to Figure 1 、 Figure 7A and Figure 7B, the third interlayer dielectric layer 130 may undergo a planarization process, which is performed until the top surface of the top cover pattern CP is exposed. Therefore, the third interlayer dielectric layer 130 may have a planarized top surface 130t, and the planarized top surface 130t is coplanar with the top surface of the top cover pattern CP. The top surface of the top cover pattern CP may be exposed.

[0063] The exposed top cover pattern CP may be selectively removed. The top cover pattern CP may be removed by a selective wet etching process. The removal of the top cover pattern CP may define a groove RS on the upper portion of the third interlayer dielectric layer 130. Each of the grooves RS may expose the top surface FMt of the conductive pattern FM of the lower connecting line M1. For example, the top surface FMt of the conductive pattern FM may define the bottom of the groove RS. The groove RS may extend in the second direction D2 along the lower connecting line M1 thereunder. The top surface 130t of the third interlayer dielectric layer 130 may be located at a horizontal height higher than the horizontal height of the top surface FMt of the conductive pattern FM of the lower connecting line M1.

[0064] Refer to Figure 1 , Figure 8A and Figure 8B , an etch stop layer EST may be formed on the third interlayer dielectric layer 130. The etch stop layer EST may be conformally formed to locally fill the groove RS. The etch stop layer EST may include, for example, one or more of SiN, SiON, SiCN, and SiCON.

[0065] A fourth interlayer dielectric layer 140 may be formed on the etch stop layer EST. The fourth interlayer dielectric layer 140 may be patterned to form a connection via HO. For example, the patterning process may be performed twice so that at least one connection via HO includes a vertically extending hole VHO. The vertically extending hole VHO may penetrate the etch stop layer EST and expose the top surface FMt of the conductive pattern FM of the second lower connecting line M12.

[0066] The vertically extending hole VHO may be formed in a self-aligned manner caused by the groove RS. The vertically extending hole VHO may not expose the top surface B Mt of the barrier pattern BM of the second lower connecting line M12. The groove RS may allow the vertically extending hole VHO to selectively expose the top surface FMt of the conductive pattern FM of the second lower connecting line M12.

[0067] Return to reference Figure 1 , Figure 2A and Figure 2B, an upper connection line M2 can be formed to fill the connection line hole HO. The upper connection line M2 can include a first upper connection line M21, a second upper connection line M22, and a third upper connection line M23 that are adjacent to each other. The upper connection line M2 can be formed by a dual damascene process. The formation of the upper connection line M2 can include forming a barrier pattern BM and a conductive pattern FM that fill each of the connection line holes HO.

[0068] The sacrificial layer SL may be damaged during the formation of the lower connection line M1. According to some exemplary embodiments, the damaged sacrificial layer SL can be replaced with the third interlayer dielectric layer 130. Since each of the lower connection lines M1 is provided with an undamaged dielectric layer having a low dielectric constant therebetween, the parasitic capacitance can be reduced and the electrical characteristics of the semiconductor device can be improved.

[0069] In addition, a vertical extension VP of the second upper connection line M22 can be formed on an upper portion of the third interlayer dielectric layer 130 in a self-aligned manner caused by the groove RS. Therefore, an electrical short circuit can be avoided between the vertical extension VP of the second upper connection line M22 and one of the first lower connection line M11 and the third lower connection line M13.

[0070] Figure 9A and Figure 9B respectively show cross-sectional views taken along Figure 1 the shown lines I-I' and II-II', which show a semiconductor device according to some exemplary embodiments. In the following embodiments, technical features that are repetitive with those of the semiconductor device described above with reference to Figure 1 , Figure 2A and Figure 2B will not be described in detail, and their differences will be discussed in detail.

[0071] Referring to Figure 1 , Figure 9A and Figure 9B , the lower connection line M1 can be formed by a dual damascene process. For example, the second lower connection line M12 can include a vertical extension VP that extends vertically toward the substrate 100. The vertical extension VP can penetrate the second interlayer dielectric layer 120 and be connected to the active contact AC. For example, the second lower connection line M12 can be electrically connected to the active contact AC through the vertical extension VP.

[0072] The second interlayer dielectric layer 120 can cover sidewalls of the vertical extension VP of the second lower connection line M12. Since the third interlayer dielectric layer 130 is provided on the second interlayer dielectric layer 120, the third interlayer dielectric layer 130 can be positioned higher than the vertical extension VP of the second lower connection line M12.

[0073] Figure 10A and Figure 11A show alongFigure 1 A cross-sectional view taken along line I-I' as shown, which shows a method of manufacturing a semiconductor device according to some exemplary embodiments. Figure 10B And Figure 11B Shows along Figure 1 A cross-sectional view taken along line II-II' as shown, which shows a method of manufacturing a semiconductor device according to some exemplary embodiments. In the following embodiments, technical features that are repetitive of those of the manufacturing method described above with reference to Figures 1 to 8B Will not be described in detail, and the differences will be discussed in detail.

[0074] Referring to Figure 1 , Figure 10A And Figure 10B , a lower connecting line M1 can be formed in the second interlayer dielectric layer 120. The lower connecting line M1 can be formed by a dual damascene process. For example, the formation of the lower connecting line M1 can be substantially the same as that of the upper connecting line M2 described above with reference to Figure 8A And Figure 8B . A cap pattern CP can be formed on the corresponding lower connecting line M1.

[0075] Referring to Figure 1 , Figure 11A And Figure 11B , a groove can be formed for the second interlayer dielectric layer 120. During the formation of the groove for the second interlayer dielectric layer 120, an upper portion of the second interlayer dielectric layer 120 can be removed, and a lower portion of the second interlayer dielectric layer 120 can be retained. The retained second interlayer dielectric layer 120 can cover a vertical extension portion VP of the second lower connecting line M12.

[0076] In the case where the second interlayer dielectric layer 120 is completely removed, the lower connecting line M1 may collapse. In this embodiment, since the upper portion of the second interlayer dielectric layer 120 is removed and the lower portion of the second interlayer dielectric layer 120 is retained, the lower connecting line M1 can be stably supported by the lower portion of the second interlayer dielectric layer 120.

[0077] Subsequent processes can be the same as those described above with reference to Figures 6A to 8B .

[0078] Figure 12 Shows along Figure 1 A cross-sectional view taken along line I-I' as shown, which shows a semiconductor device according to some exemplary embodiments. In the following embodiments, technical features that are repetitive of those of the semiconductor device described above with reference to Figure 1 , Figure 2A And Figure 2B Will not be described in detail, and the differences will be discussed in detail.

[0079] Referring toFigure 1 , Figure 2B and Figure 12 , one or more liners LIN may be sandwiched between the third interlayer dielectric layer 130 and the lower connecting line M1. The liner LIN may include a first segment that extends horizontally and covers the top surface of the second interlayer dielectric layer 120, and may also include a second segment that extends vertically and covers the sidewalls of the lower connecting line M1. For example, the liner LIN may include a silicon oxide layer or a silicon nitride layer.

[0080] The liner LIN adjacent to the groove RS may cover the top surface BMt of the barrier pattern BM of the lower connecting line M1. The liner LIN adjacent to the groove RS may define the side of the groove RS. The liner LIN adjacent to the groove RS may be sandwiched between the etch stop layer EST and the third interlayer dielectric layer 130. The liner LIN adjacent to the groove RS may have a top surface LINt that is coplanar with the top surface 130t of the third interlayer dielectric layer 130. The top surface LINt of the liner LIN may be at a horizontal height that is higher than the horizontal height of the top surface FMt of the conductive pattern FM of the lower connecting line M1.

[0081] Figure 13 and Figure 14 shows a cross-sectional view taken along the line I-I' shown in Figure 1 , which shows a method of manufacturing a semiconductor device according to some exemplary embodiments. In the following embodiments, technical features that are repeated from the manufacturing method described above with reference to Figures 1 to 8B will not be described in detail again, and their differences will be discussed in detail.

[0082] Referring to Figure 1 and [[ID=1 , the liner LIN may be formed conformally on the resulting structure shown in ​ and ​ . The liner LIN may cover the surface of the exposed lower connecting line M1 and the surface of the exposed top cap pattern CP. The liner LIN may protect the exposed lower connecting line M1.

[0083] Referring to ​ and ​ , the third interlayer dielectric layer 130 may be formed on the liner LIN. The third interlayer dielectric layer 130 may undergo a planarization process that is performed until the top surface of the top cap pattern CP is exposed. The exposed top cap pattern CP may be selectively removed. The removal of the top cap pattern CP may define a groove RS on the upper portion of the third interlayer dielectric layer 130. The upper portion of the liner LIN may define the side of the groove RS.

[0084] Subsequent processes may be the same as those described above with reference to ​ and ​ .

[0085] ​ shows a cross-sectional view taken along ​ the line I-I' shown, which shows a semiconductor device according to some exemplary embodiments. In the following embodiments, the technical features that are repeated with those of the semiconductor device ​ , ​ and ​ described above will not be described in detail, and their differences will be discussed in detail.

[0086] Referring to ​ , ​ and ​ , an air gap AG can be defined in the third interlayer dielectric layer 130. The air gap AG can be defined between the first lower connecting line M11 and the second lower connecting line M12 and between the second lower connecting line M12 and the third lower connecting line M13. Each of the air gaps AG can extend in the second direction D2 between a pair of adjacent lower connecting lines M1.

[0087] The width of the air gap AG in the first direction D1 can decrease as the distance from the substrate 100 increases. The air gap AG can be surrounded by the third interlayer dielectric layer 130 and the etch stop layer EST. The air gap AG can reduce the parasitic capacitance between adjacent lower connecting lines M1.

[0088] ​ shows a cross-sectional view taken along ​ the line I-I' shown, which shows a method of manufacturing a semiconductor device according to some exemplary embodiments. In the following embodiments, the technical features that are repeated with those of the manufacturing method ​ as well as ​ and ​ described above will not be described in detail, and their differences will be discussed in detail.

[0089] Referring to ​ and ​ , a third interlayer dielectric layer 130 can be formed on the ​ resultant structure shown. During the formation of the third interlayer dielectric layer 130, an air gap AG can be formed between a pair of adjacent lower connecting lines M1.

[0090] Subsequent processes can be the same as those ​ described above.

[0091] ​ shows a cross-sectional view taken along ​ the line I-I' shown, which shows a semiconductor device according to some exemplary embodiments. In the following embodiments, the technical features that are repeated with those of ​ , ​ and​ The technical features that are repeated in the semiconductor device described will be described in detail, and their differences will be discussed in detail.

[0092] Referring to ​ 、 ​ and ​ , the vertical extension portion VP of the second upper connection line M22 can be more offset in the first direction D1 than ​ the vertical extension portion VP shown. For example, the vertical extension portion VP may not be aligned with the center of the second lower connection line M12.

[0093] The second segment P2 of the vertical extension portion VP can be adjacent to the first lower connection line M11. The second segment P2 of the vertical extension portion VP can have a bottom surface that is higher than the top surface FMt of the conductive pattern FM of the first lower connection line M1, so that an electrical short circuit can be avoided between the vertical extension portion VP and the first lower connection line M11.

[0094] In this embodiment, even when the vertical extension portion VP of the second upper connection line M22 is not aligned with the center of the second lower connection line M12, the groove RS of the third interlayer dielectric layer 130 can also prevent process defects such as electrical short circuits.

[0095] As a summary and review, the exemplary embodiment provides a semiconductor device having improved electrical characteristics. The exemplary embodiment also provides a method of manufacturing a semiconductor device in which process defects are avoided.

[0096] That is, according to the exemplary embodiment, a non-damaged dielectric layer having a low dielectric constant is provided between each lower connection line, thereby reducing the parasitic capacitance between each lower connection line and improving the electrical characteristics of the semiconductor device. In addition, the vertical extension portion of the second upper connection line can be formed in a self-aligned manner caused by the groove on the upper portion of the third interlayer dielectric layer, thereby preventing or substantially minimizing an electrical short circuit between the vertical extension portion and the first lower connection line.

[0097] Exemplary embodiments have been disclosed herein, and although specific terms have been used, the terms should be used and interpreted only in a general and illustrative sense and not for purposes of limitation. In some cases, as will be apparent to those of ordinary skill in the art from the time of filing of this application, unless otherwise specifically indicated, the features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with the features, characteristics, and / or elements described in connection with other embodiments. Accordingly, those skilled in the art will understand that various changes may be made in form and detail without departing from the spirit and scope of the invention as set forth in the claims above.

Claims

1. A semiconductor device comprising: a substrate including an active pattern; a first interlayer dielectric layer located on the substrate, the first interlayer dielectric layer including a groove on an upper portion thereof; as well as a lower connection line located in the first interlayer dielectric layer, the lower connection line being electrically connected to the active pattern, and the lower connection line comprising: a conductive pattern, the groove of the first interlayer dielectric layer selectively exposing a top surface of the conductive pattern, and a blocking pattern located between the conductive pattern and the first interlayer dielectric layer, wherein the first interlayer dielectric layer covers a top surface of the blocking pattern; The barrier pattern covers sidewalls and a bottom surface of the conductive pattern except the top surface of the conductive pattern.

2. The semiconductor device according to claim 1, further comprising: a second interlayer dielectric layer located on the first interlayer dielectric layer; and An upper connection line is located in the second interlayer dielectric layer and is electrically connected to the lower connection line through a vertical extension, wherein the vertical extension contacts the top surface of the conductive pattern exposed by the groove. 3 . The semiconductor device according to claim 2 , wherein the vertical extension comprises a first segment located on the conductive pattern and a second segment located on the first interlayer dielectric layer, the first segment protruding more toward the substrate than the second segment. 4 . The semiconductor device according to claim 2 , wherein the lower connection line extends in a first direction, and the upper connection line extends in a second direction intersecting the first direction. 5 . The semiconductor device according to claim 1 , further comprising an etch stop layer on the first interlayer dielectric layer, wherein the etch stop layer partially fills the groove. 6 . The semiconductor device according to claim 1 , wherein a top surface of the first interlayer dielectric layer is at a higher level than a top surface of the lower connection line. 7 . The semiconductor device according to claim 1 , further comprising a liner between the first interlayer dielectric layer and the lower connection line, a top surface of the liner adjacent to the groove being at a higher level than a top surface of the lower connection line. 8 . The semiconductor device of claim 7 , wherein the top surface of the liner is coplanar with a top surface of the first interlayer dielectric layer. 9 . The semiconductor device of claim 1 , wherein the first interlayer dielectric layer further comprises an air gap adjacent to the lower connection line.

10. A semiconductor device comprising: substrate; a first interlayer dielectric layer located on the substrate, wherein the first interlayer dielectric layer comprises a groove and a protruding portion adjacent to the groove; as well as A lower connecting line is located in the first interlayer dielectric layer, and the lower connecting line includes: a conductive pattern, the groove in the first interlayer dielectric layer exposing a top surface of the conductive pattern, and a blocking pattern located between the conductive pattern and the first interlayer dielectric layer, the protruding portion of the first interlayer dielectric layer being located on a top surface of the blocking pattern, The barrier pattern covers sidewalls and a bottom surface of the conductive pattern except the top surface of the conductive pattern. 11 . The semiconductor device according to claim 10 , wherein a top surface of the protruding portion of the first interlayer dielectric layer is at a level higher than that of a top surface of the lower connection line.

12. The semiconductor device according to claim 10, further comprising: a second interlayer dielectric layer located on the first interlayer dielectric layer; and An upper connection line is located in the second interlayer dielectric layer and is electrically connected to the lower connection line through a vertical extension, the vertical extension contacting the top surface of the conductive pattern exposed in the groove. 13 . The semiconductor device according to claim 10 , further comprising an etch stop layer on the first interlayer dielectric layer, wherein the etch stop layer partially fills the groove. 14 . The semiconductor device according to claim 10 , further comprising a liner between the first interlayer dielectric layer and the lower connection line, the liner covering the top surface of the barrier pattern.

15. A semiconductor device comprising: a substrate including an active pattern; a first interlayer dielectric layer located on the substrate; a lower connecting line located in the first interlayer dielectric layer and electrically connected to the active pattern, the lower connecting line comprising a conductive pattern and a blocking pattern; as well as a liner located between the first interlayer dielectric layer and the barrier pattern of the lower connection line, a top surface of the liner being at a higher level than a top surface of the lower connection line, and the top surface of the liner being coplanar with a top surface of the first interlayer dielectric layer, The barrier pattern covers sidewalls and a bottom surface of the conductive pattern except a top surface of the conductive pattern. 16 . The semiconductor device of claim 15 , wherein the first interlayer dielectric layer includes a groove on an upper portion thereof, the top surface of the lower connecting line defines a bottom of the groove, and the liner defines a side of the groove. 17 . The semiconductor device according to claim 15 , wherein the liner covers a top surface of the barrier pattern.

18. The semiconductor device according to claim 15, further comprising: a second interlayer dielectric layer, located on the first interlayer dielectric layer; as well as The upper connecting line is located in the second interlayer dielectric layer and is electrically connected to the lower connecting line through a vertical extension portion. 19 . The semiconductor device according to claim 18 , further comprising an etch stop layer between the first interlayer dielectric layer and the second interlayer dielectric layer, the etch stop layer covering the top surface of the liner and the top surface of the first interlayer dielectric layer.

20. A method of manufacturing a semiconductor device, the method comprising: forming a sacrificial layer on the substrate; forming a lower connecting line in the sacrificial layer; selectively forming a capping pattern on a top surface of the lower connecting line; replacing the sacrificial layer with a first interlayer dielectric layer; as well as selectively removing the capping pattern to form a groove, wherein the groove exposes the top surface of the lower connecting line, The forming of the lower connecting line comprises: forming a blocking pattern; as well as forming a conductive pattern on the barrier pattern, The barrier pattern covers sidewalls and a bottom surface of the conductive pattern except a top surface of the conductive pattern.

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