Integrated circuit component design preparation method and system and semiconductor device

Abstract

The present disclosure provides a method for preparing an integrated circuit component design, the method comprising the following steps: analyzing a preliminary component layout to identify vertical adjacency between a first unit and a second unit, locations of internal metal cuts within the first unit and the second unit, and spacing between the internal metal cuts; positioning the second unit relative to the first unit through N contact polysilicon gaps to define one or more intermediate component layouts to define a modified component layout with improved internal metal cut spacing to suppress density gradient effects and landing effects.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor process technology. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth as technology advances in IC materials and designs have produced successive generations of ICs, with each new generation having smaller geometries and more complex circuitry than the previous generation. The complexity of the associated layout, device structure, and manufacturing processes used to produce each new generation of integrated circuits has correspondingly increased to achieve the designed functional density.

[0003] The performance of advanced patterning and etching processes associated with cutting metal layers is affected by density gradient effects (DGE) and / or landing effects (LE) associated with the specific integrated circuit device layout configuration being manufactured. Consideration and adjustment of the relative position and spacing of the cut metal patterns is used to mitigate some of the density gradient effects and / or landing effects and improve the uniformity and performance of the resulting integrated circuit. Summary of the invention

[0004] The present disclosure provides a method for preparing an integrated circuit device design, the method comprising the steps of analyzing a preliminary device layout to identify a vertical adjacency between a first cell and a second cell, determining a location of a first internal metal cut in the first cell and a location of a second internal metal cut in the second cell, determining a horizontal spacing between the first internal metal cut and the second internal metal cut, and evaluating the horizontal metal spacing and a target minimum horizontal metal cut spacing. If the horizontal metal cut spacing does not meet the target minimum horizontal metal spacing, the second cell is positioned relative to the first cell through a positioning step of N contacted polysilicon pitches (CPP) to define an intermediate device layout. The intermediate device layout is then evaluated for sufficient horizontal metal cut spacing, wherein the determining, evaluating, and positioning operations are repeated until the intermediate device layout passes the evaluation, wherein the passed device layout is saved as a modified device layout.

[0005] The present disclosure further provides a method for preparing an integrated circuit component design, comprising: identifying a vertical adjacency between a first standard cell and a second standard cell in the integrated circuit component design, identifying a first internal metal cutout on a first M0 metal conductor on the first standard cell, identifying a second internal metal cutout on the first M0 metal conductor on the second standard cell, determining a horizontal spacing between each pair of internal metal cutouts, determining whether the horizontal spacing satisfies a spacing threshold, and if the spacing threshold is not satisfied, horizontally shifting the second standard cell relative to the first standard cell by a predetermined distance to define a modified integrated circuit component design. Each of the first standard cell and the second standard cell has a plurality of M M0 horizontal metal conductors, and the plurality of M M0 horizontal metal conductors are arranged in parallel. Each pair of metal cutouts includes a first internal metal cutout and a second internal metal cutout. The predetermined distance is equal to N contact polysilicon spacings, where M and N are integers.

[0006] The present disclosure further provides a semiconductor device, including a first standard cell and a second standard cell. The first standard cell has a first gap, and the first gap is defined between adjacent portions of the first internal metal line cut. The second standard cell has a second gap, and the second gap is defined between adjacent portions of the second internal metal line cut, wherein the second standard cell is vertically adjacent to the first standard cell. The boundary of the first standard cell and the boundary of the second standard cell deviate from a predetermined distance of N contact polysilicon spacings in the horizontal direction, and the boundary of the second standard cell is closest to the boundary of the first standard cell, wherein N is an integer. The internal gap spacing between the first gap and the second gap is at least 1 contact polysilicon spacing. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure may be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1A is a top view of an initial integrated circuit layout unit according to some embodiments;

[0009] Figure 1B is a top view of an integrated circuit layout unit according to some embodiments;

[0010] Figure 2 is a top view of an integrated circuit layout according to some embodiments, wherein two integrated circuit layout cells are arranged in a vertically adjacent configuration;

[0011] Figure 3 is a top view of an integrated circuit layout according to some embodiments, wherein two integrated circuit layout cells having different inner cut metal zero (CM0) openings are arranged in a vertically adjacent configuration;

[0012] Figure 4 is a top view of an integrated circuit layout according to some embodiments, wherein two integrated circuit layout cells having different inner cut metal zero (CM0) openings are arranged in a vertically adjacent configuration;

[0013] Figure 5A is a top view of an integrated circuit layout according to some embodiments;

[0014] Figure 5B Based on Figure 5A Some embodiments of cells shown in FIG. 1 show a diagram of available metal zero (M0) locations for the cell;

[0015] FIG. 6A to FIG. 6B is a top view of an integrated circuit layout according to some embodiments;

[0016] FIG. 7A to FIG. 7B is a top view of an integrated circuit layout according to some embodiments;

[0017] FIG. 8A to FIG. 8B is a top view of an integrated circuit layout according to some embodiments;

[0018] Figure 8C is a diagram of available internal metal zero (M0) cut locations according to some embodiments;

[0019] Fig. 9 is a flow chart of a method for modifying an IC design layout to adjust spacing between internal metal cuts according to some embodiments;

[0020] Fig.10 is a schematic diagram of an electronic process control (EPC) system useful in IC design layout modification operations according to some embodiments;

[0021] Fig.11 is a flow chart of a manufacturing process for an integrated circuit according to some embodiments.

[0022]

Explanation of symbols

[0023] M0: Metal layer zero

[0024] MD: Source / Drain Conductor Layer

[0025] PO: Gate electrode layer

[0026] AA / OD: Active Area / Oxide Definition Layer

[0027] VIA: through hole

[0028] CM0B / PO: Alignment of boundary metal cuts and internal metal cuts of polysilicon / gate electrodes

[0029] CM0B / MD: Alignment of boundary metal cuts and internal metal cuts for source / drain conductors

[0030] 100A, 100B: Standard unit

[0031] 102, 102', 202, 302, 402, 502, 602, 702, 802: Active region / oxide defined region

[0032] 104, 204, 304, 404, 504, 604, 704, 804: Gate electrode

[0033] 106, 206, 306, 406, 506, 606, 706, 806: Source / drain conductors

[0034] 108, 208, 308, 408, 508, 608, 708, 808: Internal conductor

[0035] 110, 210, 310, 410, 510, 610, 710, 810: Shared power / ground conductor

[0036] 200, 300, 400, 500: Preliminary IC design layout

[0037] 210', 310', 410', 610', 710', 810': common conductor

[0038] 212: Through hole

[0039] 214, 314, 414, 514, 614, 714, 714': Boundary metal cutting area

[0040] 316, 316', 416', 516, 516', 616, 616', 716, 716', 816, 816': Internal metal cutouts

[0041] 600A, 700A, 800A: Preliminary IC Design Layout

[0042] 600B, 700B, 800B: Changed IC design layout

[0043] 518, 618, 718, 818, 818': Safe zone (or exclusion zone)

[0044] 620, 820, 820': Area

[0045] 824: Group

[0046] 900: Methods

[0047] 902-920: Operation

[0048] 1000: Electronic Design Automation (EDA) System

[0049] 1002: Processor

[0050] 1004: Storage Media

[0051] 1006: Computer program code (or instructions)

[0052] 1008: Process control data

[0053] 1010: User Interface

[0054] 1012: I / O interface

[0055] 1014: Network interface

[0056] 1016: Network

[0057] 1018: Bus

[0058] 1100: Integrated Circuit (IC) Manufacturing System

[0059] 1120: Design Factory

[0060] 1122: IC Design Layout

[0061] 1130: Mask Factory

[0062] 1132: Mask data preparation

[0063] 1144: Mask manufacturing

[0064] 1145: Mask

[0065] 1150: IC Manufacturer / Fabricator

[0066] 1153: Semiconductor wafer

[0067] 1160: IC components DETAILED DESCRIPTION

[0068] The description of this exemplary embodiment is intended to be read in conjunction with the accompanying drawings, and the accompanying drawings should be considered as part of the entire written description. The following disclosure provides many different embodiments or examples to achieve the different features of each embodiment. The following describes specific examples of components, values, operations, materials, arrangements, or the like to simplify the present disclosure. Of course, these examples are only examples and are not intended to be restrictive. Consider other components, values, operations, materials, arrangements, or the like. For example, the formation of the first feature above or on the second feature in the subsequent description may include an embodiment in which the first and second features are formed as direct contacts, and may also include an additional feature that may be formed between the first and second features so that the first and second features may not be directly contacted. In addition, the present disclosure may repeat component symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the discussed embodiments and / or configurations.

[0069] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature(s) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted similarly accordingly.

[0070] A method for simplifying wafer-level wiring and manufacturing of semiconductor IC layout designs generated using electronic design automation (EDA) tools, the method comprising the steps of forming a conventional metal pattern, such as a reference plane metal interconnect pattern (metal zero (M0)), and then selectively cutting (removing) portions of the metal pattern according to appropriate design rules. Metal cuts (CM0) (boundary metal cuts) on the reference plane metal interconnect pattern at the cell boundaries of a standard cell layout are used to separate / disconnect adjacent standard cells so that each separated cell can independently perform a designated function.

[0071] In addition to the boundary metal cuts, in some embodiments additional internal metal cuts are used to further adapt the standard cell for its designated function and / or reduce parasitic capacitance associated with redundant or unused portions of the reference plane metal interconnect pattern. In the following embodiments, the relationship of both the boundary metal cut and the internal metal cut to the polysilicon / gate electrode will be represented by "(CM0B / PO)", and the relationship of both the boundary metal cut and the internal metal cut to the source / drain conductor will be represented by "(CM0B / MD)". Some embodiments of the present disclosure describe metal cutting methods that are used to reduce density gradient effects and / or landing effects and / or parasitic capacitance without requiring additional mask layers and without modifying the internal configuration of individual standard cells. Some embodiments of the metal cutting method use a modified metal cutting mask layer (e.g., a mask layer that exposes those areas of the reference plane metal interconnect pattern to be removed and protects those areas of the reference plane metal interconnect pattern to be retained in the final IC component). The conductive layer from which the gate electrode and source / drain conductors are patterned includes one or more conductive materials applied to the substrate individually, in series, and / or in combination, including aluminum, copper, cobalt, tungsten, titanium, nickel, gold, platinum, graphene, silicide, silicide, and mixtures and alloys thereof. The conductive layer deposition process includes a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a plasma vapor deposition (PVD) process, an electroplating process, an electroless plating process, and any other suitable application process or one or more of the above combinations.

[0072] According to some embodiments, the standard cell structure includes one or more standard cells from a standard cell library. The standard cell is selected from a group including AND, OR, XOR, XNOR, NAND, inverter, and other appropriate logic elements. In some embodiments, metal cuts (e.g., boundary metal cuts and internal metal cuts) are located on the reference plane metal interconnect pattern by using a modified metal cutting mask layer. As used herein, the term "boundary metal cut" refers to a metal cut placed along the cell boundary of a standard cell and the term "internal metal cut" refers to a metal cut other than the boundary metal cut performed on the standard cell. The terms "boundary metal cut" and "internal metal cut" are relative terms only and do not indicate any difference in patterning, developing, and / or etching of a given metal cut.

[0073] With respect to the internal metal cuts on the standard cells specified for vertical adjoining, the internal metal cuts exhibit a horizontal spacing equal to or greater than the contacted polysilicon pitch (CPP) exhibited by the standard cells. The value of CPP will be determined by the applicable design rules and generally corresponds to the gate electrode pitch or gate pitch (GP), i.e., the center-to-center spacing of adjacent gate electrodes in the active region utilized within a standard cell that has been configured to comply with the design rules.

[0074] Figure 1A A top view of a modified preliminary IC design layout of a standard cell 100A according to some embodiments, in which portions of some structural elements have been removed to expose more of the underlying structure and to more clearly illustrate the spatial relationship between different merged structures. The standard cell 100A includes active areas / oxide defined (AA / OD) regions 102 / 102' and source / drain conductors 106 (MD), with alternating gate electrodes 104 (PO) formed above the regions 102 / 102', which define the contacted polysilicon pitch (CPP) of the standard cell. A metal level zero (M0) pattern is formed on the gate electrodes 104 and the source / drain conductors 106, which includes both an inner conductor 108 and a common power / ground conductor 110. The standard cell 100A includes five inner conductors 108 and has a total width of 8 CPPs.

[0075] Figure 1B 1 is a top view of a preliminary IC design layout of a standard cell 100B according to some embodiments. The standard cell 100B has a total width of 8 CPPs and includes an active area / oxide definition (AA / OD) region 102, over which are formed alternating gate electrodes 104 (PO) that define the contact poly pitch (CPP) of the standard cell and alternate with source / drain conductors 106 (MD). A metal layer zero (M0) pattern is formed over the gate electrodes 104 and the source / drain conductors 106, the pattern including five parallel horizontal inner conductors 108 and both upper and lower parallel horizontal common power / ground conductors 110. The standard cell 100B includes five inner conductors 108 and has a total width of 8 CPPs.

[0076] Figure 21 is a top view of a preliminary IC design layout 200 according to some embodiments, including two standard cells (cell A, cell B) arranged in a vertically adjacent configuration. Both cell A and cell B include active region / oxide definition areas 202 and source / drain conductors 206, over which alternating gate electrodes 204 are formed. An M0 pattern is formed over the gate electrodes 204 and the source / drain conductors 206, the pattern including both inner conductors 208 and common power / ground conductors 210. For convenience, the inner conductors 208 are ordered / numbered relative to the common conductors 210' formed along the adjacent edges of the standard cells A and B. The preliminary IC design layout 200 also includes a boundary metal cut area 214 aligned with the gate electrodes 204 (CM0B / PO) for disconnecting the standard cells A and B from the horizontally adjacent standard cells; and a via 212 arranged to contact the second M0 line of the standard cell B with the underlying gate electrode.

[0077] Figure 3 1 is a top view of a preliminary IC design layout 300 according to some embodiments, including two standard cells A and B arranged in a vertically adjacent configuration. Both cells A and B include active / oxide defined regions 302 and source / drain conductors 306, over which alternating gate electrodes 304 are formed. A M0 pattern is formed over the gate electrodes 304 and the source / drain conductors 306, the pattern including both inner conductors 308 and common power / ground conductors 310 / 310'. For convenience, the inner conductors 308 are ordered / numbered relative to the common conductors 310' formed along the adjacent edges of the standard cells A and B. The preliminary IC design layout 300 also includes a boundary metal cut region 314 (CM0B / PO) aligned with the gate electrodes 304 for disconnecting the standard cells A and B from horizontally adjacent standard cells (not shown). In addition to the border metal cut regions, the preliminary IC design layout 300 includes both inner metal cuts 316 aligned with the gate electrode 304 (CM0B / PO) and inner metal cuts 316 ′ aligned with the source / drain conductors 306 (CM0B / MD).

[0078] Figure 44 is a top view of a preliminary IC design layout 400 according to some embodiments, including two standard cells A and B arranged in a vertically adjacent configuration. Both cells A and B include active / oxide defined regions 402 and source / drain conductors 406, over which alternating gate electrodes 404 are formed. An M0 pattern is formed over the gate electrodes 404 and the source / drain conductors 406, the pattern including both inner conductors 408 and common power / ground conductors 410 / 410'. For convenience, the inner conductors 408 are ordered / numbered relative to the common conductors 410' formed along the adjacent edges of the standard cells A and B. The preliminary IC design layout 400 also includes a boundary metal cut region 414 (CM0B / MD) aligned with the source / drain conductors 406 for disconnecting the standard cells A and B from horizontally adjacent standard cells (not shown). In addition to the border metal cut regions, the preliminary IC design layout 400 includes inner metal cuts 416 ′ aligned with the source / drain conductors 406 .

[0079] Figure 5A 1 is a top view of a preliminary IC design layout 500 according to some embodiments, the layout 500 includes a standard cell and a source / drain conductor 506, the standard cell including an active region / oxide defined area 502, an alternating gate electrode 504 formed above the area 502. An M0 pattern is formed on the gate electrode 504 and the source / drain conductor 506, the pattern including both an inner conductor 508 and a common power / ground conductor 510. The preliminary IC design layout 500 also includes a boundary metal cut region 514 (CM0B / PO) aligned with the gate electrode 504, which is used to disconnect the standard cell from a horizontally adjacent standard cell (not shown). In addition to the boundary metal cut region, the preliminary IC design layout 500 includes both an inner metal cut 516 aligned with the gate electrode 504 (CM0B / PO) and an inner metal cut 516' (CM0B / MD) aligned with the source / drain conductor 506.

[0080] The preliminary IC design layout 500 also includes a safe area (or keep-out area) 518 in which no internal metal cutouts 516 / 516' are allowed. The size and positioning of the safe area 518 in the preliminary IC design layout 500 are configured so that the predetermined horizontal shift of the N CPPs between adjacent standard cells will address the horizontal spacing problem between the internal metal cutouts 516, 516' of adjacent standard cells. Figure 5BThe available locations on the preliminary IC design layout 500 for the boundary metal cut 514, the inner metal cut 516 (CM0B / PO) aligned with the gate electrode 504, and the inner metal cut 516' (CM0B / MD) aligned with the source / drain conductor 506 are marked. Due to the alignment with the gate conductor, the inner metal cut 516 (CM0B / PO) aligned with the gate conductor will necessarily be separated by at least 1 CPP. However, the inner metal cut 516' (CM0B / MD) aligned with the source / drain conductor 506 is located in the middle of the gate conductor and therefore will have a horizontal spacing of less than 1 CPP relative to the inner metal cut 516 on any of the adjacent gate conductors on the adjacent standard cell. When such an inner cut spacing conflict is detected, horizontally shifting (or positioning or relocating) the lower standard cell by a predetermined N CPPs will relocate the inner metal cut 516' (CM0B / MD) below the safe area 518 of the upper standard cell, thereby resolving the inner cut spacing conflict.

[0081] Fig. 6A 6 is a top view of a preliminary IC design layout 600A according to some embodiments, including two standard cells A and B arranged in a vertically adjacent configuration. Both cells A and B include active / oxide defined regions 602 and source / drain conductors 606, with alternating gate electrodes 604 formed above the regions 602. An M0 pattern is formed over the gate electrodes 604 and the source / drain conductors 606, including both inner conductors 608 and common power / ground conductors 610 / 610'. For convenience, the inner conductors 608 are ordered / numbered relative to the common conductors 610' formed along the adjacent edges of the standard cells A and B.

[0082] The preliminary IC design layout 600A also includes a boundary metal cut region 614 (CM0B / PO) aligned with the gate electrode 604 for disconnecting the standard cell A and the standard cell B from the horizontally adjacent standard cell (not shown). In addition to the boundary metal cut region, the preliminary IC design layout 600A includes both an inner metal cut 616 aligned with the gate electrode 604 (CM0B / PO) and an inner metal cut 616′ (CM0B / MD) aligned with the source / drain conductor 606.

[0083] The preliminary IC design layout 600A also includes a safety zone (or exclusion zone) 618 in at least one of the standard cells A and B, in which the internal metal cutouts 616 / 616' are not allowed to exist. The safety zone 618 has a vertical dimension and a horizontal dimension, wherein the vertical dimension includes each internal conductor 608, and the horizontal dimension includes at least two gate electrodes 604 and at least one source / drain conductor 606 located between the gate electrodes 604. Fig. 6AAs shown, region 620 includes both an internal metal cut 616 (CM0B / PO) aligned with the third gate electrode 604 on standard cell A and an internal metal cut 616' (CM0B / MD) aligned with the third source / drain conductor 606 on standard cell B. Because the third source / drain conductor 606 is located between the third gate electrode and the fourth gate electrode, the horizontal spacing between the two internal metal cuts 616, 616' is less than 1 CPP and greater than about 0.5 CPP, or less. Because the horizontal spacing of the internal metal cuts less than about 1 CPP is associated with the generation of DGE / LE, it in turn tends to reduce manufacturing yield and IC device reliability. Therefore, addressing the insufficient spacing between the internal metal cuts 616, 616' shown in region 620 will improve the manufacturability and reliability of the resulting IC device.

[0084] The principle of the horizontal spacing of the metal cuts in the cut metal zero boundary (CM0B) is to maintain the horizontal spacing between the metal cuts on adjacent inner conductors 608 to be no less than 0.5 CPP, and usually at least 1.0 CPP to suppress DGE / LE. Fig. 6A As shown, the CM0B notch in region 620 violates this principle and, if not corrected, will tend to degrade the performance of the resulting IC device.

[0085] Figure 6B 6 is a top view of a modified IC design layout 600B according to some embodiments, including two standard cells A and B arranged in a vertically adjacent configuration. Both cells A and B include active / oxide defined regions 602 and source / drain conductors 606, with alternating gate electrodes 604 formed above the regions 602. An M0 pattern is formed on the gate electrodes 604 and the source / drain conductors 606, and the pattern includes both inner conductors 608 and common power / ground conductors 610 / 610'. For convenience, the inner conductors 608 are ordered / numbered relative to the common conductors 610' formed along the adjacent edges of the standard cells A and B.

[0086] The modified IC design layout 600B also includes a boundary metal cutting region 614 (CM0B / PO) aligned with the gate electrode 604 for disconnecting the standard cell A and the standard cell B from the horizontally adjacent standard cell (not shown). In addition to the boundary metal cutting region, the modified IC design layout 600B includes an inner metal cut 616 aligned with the gate electrode 604 (CM0B / PO) and an inner metal cut 616′ (CM0B / MD) aligned with the source / drain conductor 606.

[0087] The modified IC design layout 600B also includes a safety zone (or exclusion zone) 618 provided in the standard cell A, in which the internal metal cutouts 616 / 616' are not allowed to exist. Figure 6B As shown, the horizontal position of the standard cell B has been changed from 4 CPP to 4 CPP by shifting the standard cell B to the right. Fig. 6A Due to this realignment of standard cell B with respect to standard cell A, Fig. 6A 6, wherein the inner metal cut 616' (CM0B / MD) of standard cell B is relocated below the safe area of ​​standard cell A. The spacing between the inner metal cut 616 (CM0B / PO) on standard cell A aligned with the third gate electrode 604 and the inner metal cut 616' (CM0B / MD) on standard cell B aligned with the third source / drain conductor 606 has increased from about 0.5 CPP to about 4.5 CPP.

[0088] In addition, the width of the safety zone is set to ensure that the new spacing between the internal metal cutout 616' (CM0B / MD) of cell B and other internal metal cutouts 616 (CM0B / PO) on standard cell A, which are aligned with the fourth or fifth gate electrode 604, meets or exceeds 1 CPP minimum spacing. Fig. 6A and Figure 6B As shown, the original spacing between the inner metal cut 616' in region 620 and the second inner metal cut 616 (CM0B / PO) aligned with the fifth gate electrode 604 on the standard cell A is about 1.5 CPP, which is acceptable. After the standard cell B is horizontally shifted, the modified spacing is about 2.5 CPP, thereby ensuring that the horizontal shift does not create a new horizontal spacing problem.

[0089] Although, if Fig. 6A and Figure 6B As shown in FIG. 1 , some versions of the standard cell may be configured to have a width of 8 CPPs and a specified safety zone, whereby a horizontal shift of 4 CPPs resolves any initial horizontal spacing issues between the internal metal cutouts 616 / 616' of adjacent standard cells, but the method is not limited thereto. In some embodiments, standard cells having a width of 10 CPPs or more are used with an appropriate combination of constraints on the placement of the internal metal cutouts 616' (CM0B / MD) and the corresponding placement of one or more safety zones, whereby a predetermined horizontal shift of N CPPs resolves any internal metal cutout spacing issues between adjacent standard cells.

[0090] Fig. 7AFIG. 7 is a top view of a preliminary IC design layout 700A according to some embodiments, including two standard cells A and B arranged in a vertically adjacent configuration. Both cells A and B include active / oxide defined regions 702 and source / drain conductors 706, with alternating gate electrodes 704 formed above the regions 702. An M0 pattern is formed over the gate electrodes 704 and the source / drain conductors 706, including both inner conductors 708 and common power / ground conductors 710 / 710'. For convenience, the inner conductors 708 are ordered / numbered relative to the common conductors 710' formed along the adjacent edges of the standard cells A and B.

[0091] The preliminary IC design layout 700A also includes standard cell A and standard cell B. Standard cell A includes a boundary metal cut region 714′ (CM0B / MD) aligned with the source / drain conductor 606 for disconnecting the standard cell A and the standard cell B from horizontally adjacent standard cells (not shown). Standard cell B includes a boundary metal cut region 714 (CM0B / PO) aligned with the gate electrode 704 for disconnecting the standard cell A and the standard cell B from horizontally adjacent standard cells (not shown). In addition to the boundary metal cut region, the preliminary IC design layout 700A includes both an inner metal cut 716 aligned with the gate electrode 704 (CM0B / PO) and an inner metal cut 716′ (CM0B / MD) aligned with the source / drain conductor 706.

[0092] The preliminary IC design layout 700A also includes a safety zone (or exclusion zone) 718 in at least one of the standard cell A and the standard cell B, in which the internal metal cutouts 716 / 716' are not allowed to exist. The safety zone 718 has a vertical dimension and a horizontal dimension, wherein the vertical dimension includes each internal conductor 708, and the horizontal dimension includes at least two gate electrodes 704 and at least one source / drain conductor 706 located between the gate electrodes 704. Fig. 7A As shown, in region 620, internal metal cutout 716 (CM0B / PO) on standard cell A and internal metal cutout 716' (CM0B / MD) on standard cell B are located within a horizontal interval of about 0.5 CPP from each other, which is associated with the generation of DGE / LE.

[0093] According to some embodiments, the principle of horizontal spacing of CM0B metal cutouts is to maintain the horizontal spacing between metal cutouts on adjacent inner conductors 708 to be no less than 0.5 CPP, and generally at least 1.0 CPP to suppress DGE / LE. Fig. 7A As shown, the CM0B notch in region 720 violates this principle and, if not corrected, will tend to degrade the performance of the resulting IC device.

[0094] Figure 7B FIG. 7 is a top view of a modified IC design layout 700B according to some embodiments, including two standard cells A and B arranged in a vertically adjacent configuration. Fig. 7A , both cell A and cell B include active / oxide defined regions 702 and source / drain conductors 706, over which alternating gate electrodes 704 are formed. An M0 pattern is formed over the gate electrodes 704 and the source / drain conductors 706, which pattern includes both inner conductors 708 and common power / ground conductors 710 / 710'. For convenience, the inner conductors 708 are sequenced / numbered relative to the common conductors 710' formed along the adjacent edges of the standard cells A and B.

[0095] The modified IC design layout 700B also includes a boundary metal cut region 714′ (CM0B / MD) aligned with the source / drain conductor 706 for disconnecting the standard cell A from the horizontally adjacent standard cell (not shown); and a boundary metal cut region 714 (CM0B / PO) aligned with the source / drain conductor 706 for disconnecting the standard cell A from the horizontally adjacent standard cell (not shown). In addition to the boundary metal cut region, the modified IC design layout 700B includes an inner metal cut 716 aligned with the gate electrode 704 (CM0B / PO) and an inner metal cut 716′ (CM0B / MD) aligned with the source / drain conductor 706.

[0096] The modified IC design layout 700B also includes a safety zone (or exclusion zone) 718 provided on the standard cell A, in which the internal metal cutouts 716 / 716' are not allowed to exist. Figure 7B As shown, the horizontal position of the standard cell B has been changed from 4 CPP to 4 CPP by shifting the standard cell B to the right. Fig. 7A Due to the realignment of standard cell B relative to standard cell A, the Fig. 7A 7, wherein the inner metal cutout 716′ (CM0B / MD) of standard cell B is relocated below the safe area 718 of standard cell A.

[0097] Fig. 8AFIG. 8 is a top view of a preliminary IC design layout 800A according to some embodiments, including two standard cells A and B arranged in a vertically adjacent configuration with a nominal width of 20 CPPs between the two cells. Both cells A and B include active / oxide defined regions 802 and source / drain conductors 806, over which alternating gate electrodes 804 are formed. An M0 pattern is formed over the gate electrodes 804 and the source / drain conductors 806, and includes both inner conductors 808 and common power / ground conductors 810 / 810'. For convenience, the inner conductors 808 are ordered / numbered relative to the common conductors 810' formed along the adjacent edges of the standard cells A and B.

[0098] The preliminary IC design layout 800A also includes standard cells A and B, which include a boundary metal cut region 814 (CM0B / PO) aligned with the gate electrode 804 for disconnecting the standard cells A and B from horizontally adjacent standard cells (not shown). In addition to the boundary metal cut region, the preliminary IC design layout 800A includes both an inner metal cut 816 aligned with the gate electrode 804 (CM0B / PO) and an inner metal cut 816′ (CM0B / MD) aligned with the source / drain conductor 806.

[0099] The preliminary IC design layout 800A also includes a pair of safety zones (or exclusion zones) 818, 818' in at least one of the standard cells A and B, in which the internal metal cutouts 816 / 816' are not allowed to exist. The safety zones 818, 818' have a vertical dimension and a horizontal dimension, wherein the vertical dimension includes each internal conductor 808, and the horizontal dimension includes at least two gate electrodes 804 and at least one source / drain conductor 806 located between the gate electrodes 804. Fig. 8A As shown, in region 820, the internal metal cutout 816 (CM0B / PO) on standard cell A and the internal metal cutout 816' (CM0B / MD) on standard cell B are placed within a horizontal interval of about 0.5 CPP from each other, which is associated with the generation of DGE / LE. Fig. 8A In region 820', internal metal cutout 816'A (CM0B / PO) on standard cell A and internal metal cutout 816'B (CM0B / MD) on standard cell B are placed within a horizontal interval of about 0.5 CPP from each other, which is associated with the generation of DGE / LE.

[0100] The principle of horizontal spacing of CM0B metal cutouts is to maintain the horizontal spacing between metal cutouts on adjacent inner conductors 808 to be no less than 0.5 CPP, and usually at least 1.0 CPP to suppress DGE / LE. Fig. 8AAs shown, the CM0B cuts in regions 820, 820' violate this principle and, if not corrected, will tend to degrade the performance of the resulting IC device.

[0101] Figure 8B FIG. 8 is a top view of a modified IC design layout 800B according to some embodiments, including two standard cells A and B arranged in a vertically adjacent configuration. Fig. 8A , both cell A and cell B include active / oxide defined regions 802 and source / drain conductors 806, over which alternating gate electrodes 804 are formed. An M0 pattern is formed over the gate electrodes 804 and the source / drain conductors 806, and includes both inner conductors 808 and common power / ground conductors 810 / 810'. For convenience, the inner conductors 808 are sequenced / numbered relative to the common conductors 810' formed along the adjacent edges of the standard cells A and B.

[0102] The modified IC design layout 800B also includes a boundary metal cut region 814 (CM0B / PO) aligned with the source / drain conductor 806 for disconnecting the standard cell A from the horizontally adjacent standard cell (not shown). In addition to the boundary metal cut region, the modified IC design layout 800B includes both an inner metal cut 816 (CM0B / PO) and inner metal cuts 816', 816'B (CM0B / MD). Figure 8B As shown, the horizontal position of the standard cell B has been changed from 4 CPP by shifting the standard cell B to the right to achieve a deviation of 4 CPP from the original position. Fig. 8A Due to the relocation / realignment of standard cell B relative to standard cell A, the Fig. 8A The previously indicated problem intervals are shown in regions 820, 820' of FIG. 1 , where the internal metal cutouts 816' (CM0B / MD) of standard cell B are relocated below the safety regions 818, 818' of standard cell A.

[0103] FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B ,and FIG. 8A to FIG. 8BIn one embodiment, the method of using a standard cell in combination is improved by predetermining certain aspects of the internal metal cuts, especially those aspects of the internal metal cuts (CM0B / MD) aligned with the source / drain conductors. According to some embodiments, the standard cell has a majority of the internal metal cuts aligned with the gate electrode (CM0B / PO) and includes at least one safe area without internal metal cuts. According to some embodiments, the standard cell will limit the placement of the internal metal cuts (CM0B / MD) aligned with the source / drain conductors to the first or last internal conductor, and / or limit the number of such internal metal cuts to a minimum portion of the internal metal cuts, such as no more than one or two internal metal cuts on the standard cell.

[0104] In some embodiments, when the internal cutouts in the circuit layout are limited by the specification of the positioning position, adding a standard offset (e.g., 4 CPP) between multiple standard cells will be sufficient to solve the spacing problem that may be caused when multiple standard cells are completely vertically aligned and butted against each other in the traditional case. Figure 8C In some embodiments, the standard cell developed by the IC designer will comply with the design rules for placing the internal metal cutouts, and a position is selected from both the fixed cutout position 816 of (CM0B / PO) and the group 824 to place the internal metal cutouts. The group 824 is composed of the cutout positions 816, 816' of (CM0B / PO) and (CM0B / MD), and a position is selected and placed, which means that the cutout position 816 of (CM0B / PO) or the cutout position 816' of (CM0B / MD) in the center can be selected. According to some embodiments, the standard cell developed according to these principles will have a predetermined offset, such as N CPPs, where N is an integer, and when the second standard cell is positioned by the predetermined offset, the internal metal cutout placement problem of the standard cell configured according to the same principle will be solved.

[0105] Fig. 9 A flow chart illustrating a method 900 for modifying an IC design layout to adjust the spacing between internal metal cuts according to some embodiments. Fig. 9In some embodiments of method 900, in operation 902, a preliminary IC design file is captured for evaluation. The source from which the preliminary IC design file is captured includes a dedicated design file memory element and a preliminary IC design file that has been stored or uploaded by one or more designers or design groups. In operation 904, the preliminary IC design file is evaluated to identify vertical adjacencies between standard cells. Operation 906 includes an inquiry as to the degree of success in identifying vertical adjacencies. If less than all empty areas have been identified, method 900 branches from operation 906 to operation 908 to identify the next vertical adjacency. When all vertical adjacencies have been identified, method 900 branches to operation 910 for identifying internal metal cuts in adjacent standard cells; then proceeds to operation 912 for evaluating the horizontal spacing between internal metal cuts on the first cell and the second cell.

[0106] Operation 914 includes an inquiry as to whether the identified horizontal spacing between the internal metal cutouts on the first cell and the second cell meets a target offset threshold (e.g., at least one CPP). If the spacing fails to meet the target offset threshold, the method 900 branches to operation 915 during which a predetermined horizontal shift of the N CPPs of the first cell relative to the second cell is performed to generate a modified IC design file. The modified IC design file is then evaluated again in operation 914. Once all identified spacings meet or exceed the target offset threshold, the method 900 proceeds to operation 916 to save the modified IC design file.

[0107] For those modified IC design layouts that pass the interval evaluation of operation 914, method 900 includes an optional operation 918, during which, in some embodiments, a tape out data file corresponding to the passed modified IC design layout is generated. For those modified IC design layouts for which the tape out data file is generated, the tape out data file will be used to manufacture semiconductor devices based on the passed modified IC design layout in optional operation 920.

[0108] Fig.101 is a block diagram of an electronic process control (EPC) system 1000 according to some embodiments. For example, using the EPC system 1000 according to some embodiments, the method described herein for generating a cell layout diagram according to one or more embodiments can be implemented. In some embodiments, the EPC system 1000 is a general-purpose computing device, including a processor 1002 and a non-transitory computer-readable storage medium 1004. In addition, the storage medium 1004 is encoded with computer program code (or instructions) 1006, that is, stores computer program code (or instructions), which is an executable instruction group. The processor 1002 executes the computer program code 1006 to represent (at least in part) an EPC tool, which implements, for example, part or all of the method described herein according to one or more (hereinafter, the processes and / or methods mentioned).

[0109] The processor 1002 is electrically coupled to the computer readable storage medium 1004 via a bus 1018. The processor 1002 is also electrically coupled to the I / O interface 1012 via the bus 1018. The network interface 1014 is also electrically connected to the processor 1002 via the bus 1018. The network interface 1014 is connected to a network 1016 so that the processor 1002 and the computer readable storage medium 1004 can be connected to external components via the network 1016. The processor 1002 is used to execute computer program code 1006 encoded in the computer readable storage medium 1004 so that the EPC system 1000 is useful for performing part or all of the processes and / or methods described. In one or more embodiments, the processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0110] In one or more embodiments, the computer readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer readable storage medium 1004 includes compact disk read only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disc (DVD).

[0111] In one or more embodiments, the storage medium 1004 stores computer program code 1006 for causing the EPC system 1000 (where such execution represents (at least in part) an EPC tool) to be useful for executing part or all of the processes and / or methods. In one or more embodiments, the storage medium 1004 also stores information that facilitates executing part or all of the processes and / or methods. In one or more embodiments, the storage medium 1004 stores process control data 1008, which in some embodiments includes control algorithms, active region data, transition unit data, uniform algorithms, layout data and constants, ranges, set points, and code for implementing various process controls based on statistical process control (SPC) and / or model predictive control (MPC).

[0112] The EPC system 1000 includes an I / O interface 1012. The I / O interface 1012 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1012 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for exchanging information and commands with the processor 1002.

[0113] The EPC system 1000 also includes a network interface 1014 coupled to the processor 1002. The network interface 1014 allows the EPC system 1000 to communicate with a network 1016 to which one or more other computer systems are connected. The network interface 1014 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more EPC systems 1000.

[0114] The EPC system 1000 is configured to receive information via an I / O interface 1012. The information received via the I / O interface 1012 includes one or more of instructions, data, design rules, process execution history, target distance, set points, and / or other parameters for processing by the processor 1002. The information is transmitted to the processor 1002 via a bus 1018. The EPC system 1000 is configured to receive information related to a user interface (UI) via the I / O interface 1012. The information is stored in a storage medium 1004 as the user interface 1010.

[0115] In some embodiments, part or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, part or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, part or all of the processes and / or methods are implemented as a plug-in to a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EPC tool. In some embodiments, part or all of the processes and / or methods are implemented as a software application used by the EPC system 1000.

[0116] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, for example, one or more of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as a ROM, RAM, a memory card, etc.

[0117] Fig.11 FIG. 1 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1100 is used to manufacture at least one of one or more semiconductor masks (A) or at least one component (B) in a semiconductor integrated circuit layer.

[0118] exist Fig.11 In the present invention, the IC manufacturing system 1100 includes entities such as a design factory 1120, a mask factory 1130, and an IC manufacturer / wafer factory (fab) 1150, which interact with each other in the design, development and manufacturing cycles and / or services related to manufacturing IC components 1160. The entities in the system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an internal network and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design factory 1120, the mask factory 1130, and the wafer factory 1150 are owned by a single larger company. In some embodiments, two or more of the design factory 1120, the mask factory 1130, and the wafer factory 1150 coexist in a public facility and use common resources.

[0119] The design house (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric patterns designed for the IC element 1160. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers that make up the various components of the IC element 1160 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC design layout 1122 includes various IC features, such as active regions, gate electrodes, source and drain, metal lines or vias for interlayer interconnection, and openings for bonding pads, which are to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers (disposed on this semiconductor substrate). The design house 1120 implements a suitable design program to form the IC design layout 1122. The design program includes one or more of a logical design, a physical design and / or placement and routing. The IC design layout 1122 is presented in one or more data files with geometric pattern information. For example, the IC design layout 1122 is represented in a GDSII file format or a DFII file format according to some embodiments.

[0120] The mask factory 1130 includes data preparation 1132 and mask manufacturing 1144. The mask factory 1130 uses the IC design layout drawing 1122 to manufacture one or more masks 1145, which are to be used to manufacture various layers of the IC component 1160 according to the IC design layout drawing 1122. The mask factory 1130 performs mask data preparation 1132, in which the IC design layout drawing 1122 is converted into a representative data file (RDF). The mask data preparation 1132 provides the RDF to the mask manufacturing 1144. The mask manufacturing 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 1145 or a semiconductor wafer 1153. The design layout drawing 1122 is manipulated by the mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the necessary conditions of the wafer factory 1150. In Fig.11 In FIG. 1 , mask data preparation 1132 and mask manufacturing 1144 are illustrated as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 are collectively referred to as mask data preparation.

[0121] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for aberrations, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 1122. In some embodiments, mask data preparation 1132 includes additional resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase change masks, other suitable techniques, etc., or combinations thereof. In some embodiments, inverse lithography technology (ILT) may also be used, which treats OPC as an inverse image problem.

[0122] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks the IC design layout 1122 that has been processed in OPC using a set of mask generation rules, which include certain geometric and / or connectivity constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for the constraints during mask generation 1144, which may undo portions of the modifications performed by the OPC to satisfy the mask generation rules.

[0123] In some embodiments, mask data preparation 1132 includes lithography process checking (LPC), which simulates the process to be performed by wafer fab 1150 to manufacture IC device 1160. LPC simulates this process based on IC design layout 1122 to generate simulated manufacturing devices, such as IC device 1160. In some embodiments, the processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as spatial imaging contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, etc. or combinations thereof. In some embodiments, after the simulated manufactured device has been generated by LPC, if the simulated device is not close enough to the shape to meet the design rules, OPC and / or MRC are repeated to further improve IC design layout 1122.

[0124] Those skilled in the art will appreciate that the above description of mask data preparation 1132 has been simplified for the purpose of brevity. In some embodiments, data preparation 1132 includes additional features such as logic operations (LOP) to modify IC design layout 1122 according to manufacturing rules. In addition, according to some embodiments, the processes applied to IC design layout 1122 during data preparation 1132 may be performed in a variety of different orders.

[0125] After the mask data preparation 1132 and during the mask manufacturing 1144, a mask 1145 or a mask group 1145 is manufactured based on the modified IC design layout 1122. In some embodiments, the mask manufacturing 1144 includes performing one or more lithography exposures based on the IC design layout 1122. In some embodiments, an electron-beam (e-beam) or a plurality of electron-beam mechanisms are used to form a pattern on a mask (mask or shrink mask) 1145 based on the modified IC design layout 1122. In some embodiments, the mask 1145 is formed using various techniques. In some embodiments, the mask 1145 is formed using a binary technique. In some embodiments, the mask pattern includes dark areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) that has been coated on a wafer is blocked by the dark areas and transmitted through the transparent areas. In one example, a binary mask version of mask 1145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the dark areas of the binary mask. In another example, mask 1145 is formed using a phase transfer technique. In a phase shift mask (PSM) version of mask 1145, various features in the pattern formed on the phase shift mask are used to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by mask manufacturing 1144 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in semiconductor wafer 1153, in an etching process to form various etched regions in semiconductor wafer 1153, and / or in other appropriate processes.

[0126] Wafer fab 1150 includes wafer fabrication 1152. Wafer fab 1150 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, wafer fab 1150 is a semiconductor manufacturing plant. For example, according to some embodiments, there is a manufacturing facility for the front-end-of-line (FEOL) of a plurality of IC products, while a second manufacturing facility provides back-end-of-line (BEOL) for interconnection and packaging of IC products, and a third manufacturing facility provides other services for the manufacturing company.

[0127] In some embodiments of the present disclosure, the step of fin size adjustment includes operations associated with making a fin array across the entire fin-containing functional area of ​​the integrated circuit, and then modifying the fin size in at least one fin-containing functional area of ​​the integrated circuit. In embodiments of the present disclosure, fins of functional areas containing different fins are formed to a final fin shape, or are formed to a fin size profile separately in a single fin formation manufacturing process for each fin-containing functional area of ​​the IC. In some embodiments, the fin size adjustment step is achieved by the following steps: forming fins in a fin material layer or a fin substrate, applying a mask layer to the top surface of the fin material, patterning the mask layer with a pattern corresponding to the fin position in one or more of the fin-containing functional areas, exposing the top surface of the fin material through the mask layer, and etching the fin material to form fins on the fin substrate. In some embodiments, the fin is formed in a single functional area of ​​the IC having a final fin size, and the selected fin size (or, fin height) is as described above in operation 1150.

[0128] The patterned mask material layer formed on the semiconductor substrate is composed of a mask material, and the mask material includes one or more layers of photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si3N4), SiON, SiC, SiOC, or a combination thereof. In some embodiments, the mask includes a single mask material layer. In some embodiments, the mask includes multiple mask material layers.

[0129] In some embodiments, the mask material is patterned by exposure to an illumination source. In some embodiments, the illumination source is an electron beam source. In some embodiments, the illumination source is a light that emits light. In some embodiments, the light is ultraviolet light. In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the illumination source emits a combination of different (UV, visible, and / or infrared) light.

[0130] After the mask patterning operation, the fin areas not covered by the mask, or the fins in the pattern open areas, are etched to change the size of the fins. In some embodiments, etching is performed on the top surface of the fin having fin sides that are completely covered by adjacent dielectric support materials deposited between the fins in a previous manufacturing step. According to some embodiments, the etching of the top surface of the fin is performed using plasma etching, or using a liquid chemical etching solution. The chemical agent of the liquid chemical etching solution includes one or more etchants, such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F), potassium hydroxide (KOH), 2-ethylenediamine pyrocatechol (EDP), TMAH (tetramethylammonium hydroxide), or a combination thereof. In some embodiments, the step of etching the fins is achieved by exposing an upper portion of the fin material, the portion extending above the top surface of the dielectric support material, which was deposited between the fins and recessed below the top surface of the fin height in a previous manufacturing step, to a liquid chemical etching solution, the etching solution comprising one or more of the above-mentioned liquid chemical etchants. The upper portion of the fin material includes the top surface and side surfaces of the fin material.

[0131] In some embodiments, the etching process is a dry etching or plasma etching process. Plasma etching of substrate materials is performed using a halogen-containing reactive gas that is excited by an electromagnetic field to be ionized. Reactive or etchant gases include CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, or a combination thereof, but other semiconductor material etchant gases are also expected to fall within the scope of the present disclosure. According to plasma etching methods known in the art, ions are accelerated by an alternating electromagnetic field or a fixed bias to impact the exposed fin material.

[0132] In some embodiments, the etching process includes exposing the exposed portions of the fins of the functional areas to an oxygen-containing atmosphere to oxidize the outer portions of the fin material, followed by a chemical trimming process, such as plasma etching or liquid chemical etching, as described above, to remove the oxidized semiconductor fin material and leave the modified fins. In some embodiments, the fin oxidation prior to chemical trimming is performed to provide greater selectivity to the fin material and reduce the possibility of accidental fin material removal during the manufacturing process. In some embodiments, the exposed portions of the fins of the functional areas are the top surfaces of the fins, which are embedded in a dielectric support medium covering the sides of the fins. In some embodiments, the exposed portions of the fins of the functional areas are the sides and top surfaces of the fins located above the top surface of the dielectric support medium, wherein the top surface of the dielectric support medium has been recessed to a level below the top surface of the fins, but still covers the lower portions of the sides of the fins.

[0133] Fab 1150 manufactures IC element 1160 using mask 1145 manufactured by mask factory 1130. Thus, fab 1150 manufactures IC element 1160 at least indirectly using IC design layout 1122. In some embodiments, semiconductor wafer 1153 is manufactured by fab 1150 forming IC element 1160 using mask 1145. In some embodiments, IC manufacturing includes performing one or more lithography exposures based at least indirectly on IC design layout 1122. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1153 further includes one or more of various doped regions, dielectric features, multi-level interconnects formed in subsequent manufacturing steps, and the like.

[0134] With respect to integrated circuit (IC) manufacturing systems (e.g., Fig.11 Details of the system 1100 and the IC manufacturing process associated therewith are found in, for example, U.S. Patent No. 9,256,709, issued on February 9, 2016; U.S. Pregrant Publication No. 20150278429, published on October 1, 2015; U.S. Pregrant Publication No. 20140040838, published on February 6, 2014; and U.S. Patent No. 7,260,442, issued on August 21, 2007, the contents of each of which are incorporated herein by reference in their entirety.

[0135] According to some embodiments, a method for preparing an integrated circuit device design is provided, the method comprising the following steps: analyzing a preliminary device layout to identify a vertical adjacency between a first cell and a second cell, determining a location of a first internal metal cut in the first cell and a location of a second internal metal cut in the second cell, determining a horizontal spacing between the first internal metal cut and the second internal metal cut, and evaluating the horizontal metal spacing and a target minimum horizontal metal cut spacing. If the horizontal metal cut spacing does not meet the target minimum horizontal metal spacing, the second cell is positioned relative to the first cell through a positioning step of N CPPs to define an intermediate device layout. The intermediate device layout is then evaluated for sufficient horizontal metal cut spacing, wherein the determination, evaluation, and positioning operations are repeated until the intermediate device layout passes the evaluation, wherein the passed device layout is saved as a modified device layout.

[0136] In some embodiments, the value N is an integer greater than 1, and in some embodiments, the value N is at least 4. In some embodiments, the method will include retrieving the preliminary device layout from a designated memory or receiving the preliminary device layout from an electronic design automation (EDA) tool. In some embodiments, the method includes generating a production file corresponding to the modified device layout, and in some embodiments, manufacturing an IC device corresponding to the production file.

[0137] In some embodiments, the first unit includes a designated safety zone with internal metal cutting locations, the locations are configured whereby the positioning step of the N CPP locations is applied to the second unit location, the second internal metal cut is below the designated safety zone of the first unit. In some embodiments, the first unit includes at least 2 designated safety zones with the first unit and the second unit, the units are configured whereby the positioning step of the N CPP locations is applied to the second unit location, the second internal metal cut is below one of the designated safety zones.

[0138] In some embodiments, the first cell comprises a plurality of internal metal cuts, wherein only a single internal metal cut is aligned with the source / drain conductor. In some embodiments, the second cell comprises a plurality of internal metal cuts, wherein no more than two internal metal cuts are aligned with the source / drain conductor.

[0139] In some embodiments, a method for preparing an integrated circuit component design includes the following steps: analyzing a preliminary component layout to identify a vertical adjacency between a first standard cell and a second standard cell, each of the first standard cell and the second standard cell having a plurality of M (e.g., 5) M0 internal metal conductors arranged in parallel; determining a position of each first internal metal cut on a first M0 metal conductor on the first standard cell; determining a position of each second internal metal cut on a first M0 metal conductor on the second standard cell; determining a horizontal spacing between each pair of first internal metal cuts and second internal metal cuts; evaluating the horizontal metal cut spacing and a target minimum horizontal metal cut spacing to identify a failed pair having a horizontal spacing of less than 1 CPP; and positioning the second standard cell and the horizontal direction relative to the first standard cell through a positioning step of N CPPs to increase the horizontal spacing between the failed pairs.

[0140] In some embodiments, M is 5 and N is 4. In some embodiments, the positioning step of applying N CPPs increases the horizontal spacing between the internal cutouts of the failed pair without reducing the spacing of any other pair of internal cutouts to less than 1 CPP. In some embodiments, the positioning step of applying N CPPs places the second metal cutout of the internal cutouts of the failed pair below the safe area provided on the first standard cell.

[0141] In some embodiments, a semiconductor device design is prepared and / or manufactured, the semiconductor device design comprising a first standard cell having a first internal metal cutout and a second standard cell having a second internal metal cutout, the second standard cell being arranged in a vertically adjacent configuration relative to the first standard cell; wherein the first cell and the second cell are offset in a horizontal direction by a horizontal offset distance N CPPs, where N is an integer; and wherein the internal cutout spacing between each pair of the first internal metal cutout and the second internal metal cutout is at least 1 CPP.

[0142] In some embodiments, the semiconductor device will include a first standard cell having a safety zone, and a second standard cell, wherein the first internal metal cut does not exist in the safety zone, and the second standard cell has at least one second internal metal cut vertically aligned with the safety zone. In some embodiments, the horizontal offset distance is at least 4 CPPs. In some embodiments, the internal metal cut pattern of the first standard cell includes both a fixed first metal cut aligned with the gate electrode and a second metal cut position, the second metal cut position being selected from a group consisting of three adjacent metal cut positions, wherein at least one adjacent metal cut position is aligned with the source / drain conductor. In some embodiments, the first cell includes a plurality of first internal metal cuts, wherein no more than one internal metal cut is aligned with the source / drain conductor, and / or the second cell includes a plurality of second internal metal cuts, wherein no more than two internal metal cuts are aligned with the source / drain conductor.

[0143] In some embodiments, a semiconductor device design will be prepared and / or manufactured using embodiments of the disclosed method, wherein the semiconductor device design will include a first standard cell having a first gap defined between adjacent portions of a first internal metal line cut; a second standard cell having a second gap defined between adjacent portions of a second internal metal line cut, wherein the second standard cell is vertically adjacent to and offset from the first standard cell; and wherein the internal gap spacing of at least 1 CPP between the first gap and the second gap is determined by being offset in the horizontal direction by a predetermined distance (i.e., an integer N times a contact polysilicon pitch (CPP)).

[0144] In some embodiments, a semiconductor device includes a first standard cell having a safe zone, and a second standard cell, in which no gaps exist in those portions of the internal metal lines (falling within the safe zone), and the second standard cell has at least one second gap vertically aligned with the safe zone of the first standard cell. In some embodiments, the predetermined offset distance between the first standard cell and the second standard cell is at least 4 CPPs. In some embodiments, the first standard cell includes a fixed first gap in the first internal metal line aligned with a predetermined gate electrode, and a fixed second gap in the second internal metal line, a fixed second gap located in one of three adjacent predetermined second gap positions, wherein at least one of the predetermined second gap positions is aligned with a source / drain conductor, and at least one of the predetermined second gap positions is aligned with a gate electrode adjacent to the source / drain conductor. In some embodiments, the first cell includes at least two first gaps, wherein only a single first gap is aligned with the source / drain conductor, and some embodiments have a second cell, the second cell includes at least two second gaps, wherein at most two second gaps are aligned with the source / drain conductor.

[0145] Some of the embodiments detailed above are applicable to IC devices fabricated using a range of photolithography processes (e.g., 20 nm to 3 nm). References to specific values ​​of photolithography processes (e.g., 10 nm, 7 nm, or 5 nm) used herein are simply industry terms that one of ordinary skill in the art would associate with a particular method of producing an IC device and are not intended to be used at any particular size. Table 1 below provides some representative structural and spatial measurements associated with the above processes.

[0146]

[0147] Table 1

[0148] The above detailed method is applicable to manufacturing IC devices with representative dimensions within a range, such as fin pitch of 20 to 50 nanometers, fin width of 5 to 15 nanometers, gate length of 3 to 16 nanometers, contact polysilicon pitch of 40 to 90 nanometers, and minimum metal pitch of 28 to 50 nanometers. In some embodiments, the relative sizes of various specific dimensions will result in certain ratios, for example, a ratio of polysilicon gap to metal one gap of 2 to 3, a ratio of metal zero gap to metal zero width of 2 to 1, a ratio of metal zero signal width to metal zero power width of 1 to 4, and a ratio of via gap to polysilicon gap and a ratio of CM0B to contact polysilicon pitch of 1 to 1.

[0149] The features or examples of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that the present disclosure can be easily used as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments or examples introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications herein can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for preparing an integrated circuit component design, characterized in that: The following steps are involved: identifying a vertical adjacency between a first cell and a second cell in a device layout; identifying a first internal metal cutout in the first unit; identifying a second internal metal cutout in the second unit; Determining a horizontal interval between the first inner metal cutout and the second inner metal cutout in the device layout; determining whether the horizontal interval satisfies an interval threshold; as well as If the spacing threshold is not met, horizontally shifting the second cell relative to the first cell by a distance equal to N contact polysilicon pitches, where N is an integer, to define a modified device layout; The determination and shifting operations are repeated until the modified device layout satisfies the spacing threshold.

2. The method for preparing an integrated circuit component design according to claim 1, characterized in that: Further including: The component layout passed is saved as a modified component layout.

3. The method for preparing an integrated circuit component design according to claim 2, characterized in that: in: N is at least 4.

4. The method for preparing an integrated circuit component design according to claim 1, wherein: Further including: Retrieve the component layout from a specified memory.

5. The method for preparing an integrated circuit component design according to claim 1, wherein: Further including: The component layout is received from an electronic design automation tool.

6. The method for preparing an integrated circuit component design according to claim 1, wherein: Further including: A down-line production file is generated, which corresponds to the changed component layout.

7. The method for preparing an integrated circuit component design according to claim 1, wherein: in: The first unit includes a designated safety zone; and Shifting the second unit includes placing the second internal metal cutout below the designated safety zone.

8. The method for preparing an integrated circuit component design according to claim 1, wherein: in: The first unit includes at least two designated safety zones; and Shifting the second cell by N contact polysilicon pitches places the second inner metal cut of the second cell below one of the designated safe areas.

9. The method for preparing an integrated circuit component design according to claim 1, wherein: in: The first unit includes a plurality of inner metal cuts, only one of the plurality of inner metal cuts being aligned with a source / drain conductor.

10. The method for preparing an integrated circuit component design according to claim 9, wherein: in: The second unit includes a plurality of internal metal cuts, at most two of the plurality of internal metal cuts being aligned with a source / drain conductor.

11. A method for preparing an integrated circuit component design, characterized in that: include: Identifying a vertical adjacency between a first standard cell and a second standard cell in an integrated circuit device design, each of the first standard cell and the second standard cell having a plurality of M M0 horizontal metal conductors arranged in parallel; identifying a first internal metal cutout on a first M0 metal conductor on the first standard cell; identifying a second internal metal cutout on a first M0 metal conductor on the second standard cell; Determining a horizontal spacing between each pair of internal metal cutouts, each pair of metal cutouts comprising a first internal metal cutout and a second internal metal cutout; determining whether the horizontal interval satisfies an interval threshold; and If the spacing threshold is not met, the second standard cell is horizontally shifted relative to the first standard cell by a predetermined distance to define a modified integrated circuit device design, the predetermined distance being equal to N contact polysilicon pitches, where M and N are integers.

12. The method for preparing an integrated circuit component design according to claim 11, wherein: in: M is 5; and N is 4.

13. The method for preparing an integrated circuit component design according to claim 11, wherein: in: Horizontally shifting the second standard cell by the predetermined distance of N contact polysilicon pitches increases the horizontal spacing between an inner notch failure pair without reducing the spacing of any other inner notch pairs to a horizontal spacing less than 1 contact polysilicon pitch.

14. The method for preparing an integrated circuit component design according to claim 11, wherein: in: A second metal notch of an inner notch failure pair is placed below a safety region provided on the first standard cell.

15. A semiconductor device, characterized in that: include: a first standard cell having a first gap defined between adjacent portions of a first inner metal line cut; as well as a second standard cell having a second gap defined between adjacent portions of a cut second inner metal line, wherein the second standard cell is vertically adjacent to the first standard cell; wherein a boundary of the first standard cell and a boundary of the second standard cell deviate from each other in the horizontal direction by a predetermined distance of N contact polysilicon pitches, and the boundary of the second standard cell is closest to the boundary of the first standard cell, wherein N is an integer; as well as An inner gap spacing between the first gap and the second gap is at least one contact polysilicon spacing.

16. The semiconductor device according to claim 15, wherein: in: The first standard cell has a safety zone, and the first gap does not exist in the inner metal line portion of the safety zone; and The second standard cell has at least one second gap, and the at least one second gap is vertically aligned with the safety area.

17. The semiconductor device according to claim 15, wherein: in: The predetermined distance is at least 4 contact polysilicon pitches.

18. The semiconductor device according to claim 17, wherein: in: An internal metal cut pattern is applied to the first internal metal line of the first standard cell, the internal metal cut pattern producing: a fixed first gap in the first inner metal line, the fixed first gap being aligned with a predetermined gate electrode; as well as A fixed second slot is in the second inner metal line, the fixed second slot being located in one of three adjacent predetermined second slot locations, wherein at least one of the predetermined second slot locations is aligned with a source / drain conductor.

19. The semiconductor device according to claim 15, wherein: in: The first standard cell includes a plurality of first slots, and only one of the plurality of first slots is aligned with a source / drain conductor.

20. The semiconductor device according to claim 15, wherein in: The second standard cell includes a plurality of second slots, and at most two second slots of the plurality of second slots are aligned with a source / drain conductor.

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