Chip inner moat structure and manufacturing method thereof

Abstract

The present invention provides a moat structure in a chip and a manufacturing method thereof, the manufacturing method comprising the following steps: providing a substrate, the substrate surface having a diffusion barrier layer; forming a dielectric layer on the diffusion barrier layer, and forming a metal interconnection structure and a bonding pad in the dielectric layer, the metal interconnection structure being located in the chip main body area; forming a passivation protection layer on the dielectric layer; forming an opening in the chip main body area to expose the bonding pad, and simultaneously forming a moat groove structure in the chip peripheral area, the moat groove structure comprising at least two discretely arranged groove rings, the groove rings extending downward into the dielectric layer, but not penetrating the diffusion barrier layer. The present invention arranges groove rings in the chip peripheral area, the groove rings surround the chip main body area, can effectively block the wafer cutting stress from being transmitted to the chip main body area, thereby preventing the generation of cracks in the chip. The present invention reduces the use of metal materials, can not only reduce the process complexity, improve the yield, but also help to reduce production costs.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor integrated circuits and relates to a moat structure within a chip and a manufacturing method thereof. Background Art

[0002] In the semiconductor manufacturing process, a wafer with integrated circuits is usually cut into individual chips, and then these chips are made into semiconductor packaging structures with different functions. Figure 1 As shown, it is a partial top view of a wafer, which contains multiple chips 101, and two adjacent chips are separated by a scribe line 102. Each chip includes a device structure, an interconnection structure, and a pad formed on a substrate through processes such as deposition, photolithography, etching, doping, and heat treatment. Afterwards, the wafer is cut into multiple independent chips along the scribe line.

[0003] When the wafer is cut, mechanical stress is applied to the wafer, so cracks are easily caused in the cut chips. In the prior art, in order to prevent the semiconductor chip from being damaged by the cutting process, a guard ring 103 is formed between the device area of ​​each chip and the cutting path to surround the chip.

[0004] like Figure 2 As shown, it is shown as Figure 1 From the A-A' cross-sectional view, it can be seen that the protection ring in the prior art includes contact plug 104, first metal ring 105, first plug 106, second metal ring 107, second plug 108, third metal ring 109 and passivation protection layer 110 from bottom to top, wherein the contact plug and the first metal ring are surrounded by dielectric layer 111, the first plug, the second metal ring, the second plug and the third metal ring are surrounded by dielectric layer 112, there is a SiCN diffusion barrier layer 113 between dielectric layer 111 and dielectric layer 112, the passivation protection layer includes oxide layer 1101, silicon nitride layer 1102 and polyimide layer 1103 from bottom to top, the contact plug and the first plug can be made of W, the first metal ring can be made of Cu, the second metal ring, the second plug and the third metal ring can be made of aluminum. In order to strengthen the connection between the metal and the dielectric, there is also an adhesive layer 114 between each contact plug, plug and the second and third metal rings and the dielectric layer.

[0005] Since the existing chip protection ring structure contains multiple metal layers, the manufacturing process is relatively complicated and the cost is relatively high. Therefore, how to provide a new protection structure and its manufacturing method to reduce the process complexity and cost while providing good chip protection effect has become an important technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a chip inner moat structure and a manufacturing method thereof, so as to solve the problem of complex manufacturing process and high cost of the chip protection ring structure in the prior art.

[0007] To achieve the above-mentioned and other related purposes, the present invention provides a method for manufacturing a moat structure in a chip, which comprises the following steps:

[0008] A substrate is provided, wherein a diffusion barrier layer is provided on the surface of the substrate, and a chip main body area and a chip peripheral area surrounding the chip main body area are defined on the substrate, and a moat ring structure is embedded in the substrate, located in the chip peripheral area and covered under the diffusion barrier layer;

[0009] Forming a dielectric layer on the diffusion barrier layer, and forming a metal interconnect structure and a bonding pad in the dielectric layer, wherein the conductive metal layer of the metal interconnect structure and the bonding pad are located in the chip main body region;

[0010] forming a passivation protection layer on the dielectric layer;

[0011] An opening is formed in the chip main body area to expose the bonding pad, and a moat groove structure is simultaneously formed in the chip peripheral area to block the wafer cutting stress from being transmitted to the chip main body area, the moat groove structure is aligned with the moat ring structure and includes at least two discretely arranged groove rings, wherein the groove ring extends downward into the dielectric layer but does not penetrate the diffusion barrier layer, and the opening extends downward to the surface of the bonding pad.

[0012] Optionally, the moat ring structure includes at least two discretely arranged first metal rings and a plurality of first conductive plugs, the diffusion barrier layer covers the first metal rings, the conductive plugs are connected under the metal rings, and the groove ring is longitudinally aligned with the first metal rings.

[0013] Optionally, the metal interconnect structure includes at least two conductive metal layers, the dielectric layer includes an upper diffusion barrier layer, the upper diffusion barrier layer is located above one of the conductive metal layers to prevent diffusion of this conductive metal layer, and the bottom surface of the slot ring is relatively located on the top surface of the upper diffusion barrier layer and includes a non-penetrating surface of the dielectric layer.

[0014] Optionally, the metal interconnect structure further includes at least two discretely arranged second metal rings aligned on the moat ring structure and a plurality of second metal plugs in the dielectric layer in the peripheral area of ​​the chip, the second metal ring is located below the upper diffusion barrier layer, and the second metal plug is connected below the second metal ring.

[0015] Optionally, the metal interconnect structure includes at least two conductive metal layers, the dielectric layer includes an upper diffusion barrier layer, the upper diffusion barrier layer is located above one of the conductive metal layers to prevent diffusion of this conductive metal layer, and the bottom surface of the slot ring includes the exposed surface of the upper diffusion barrier layer.

[0016] Optionally, the metal interconnect structure further includes at least two discretely arranged second metal rings aligned on the moat ring structure and a plurality of second metal plugs in the dielectric layer in the peripheral area of ​​the chip, the second metal ring is located below the upper diffusion barrier layer, and the second metal plug is connected below the second metal ring.

[0017] Optionally, a bottom surface of the slot ring is located opposite to a top surface of the diffusion barrier layer and includes a non-penetrating surface of the dielectric layer.

[0018] Optionally, the slot ring penetrates the dielectric layer, and a bottom surface of the slot ring includes an exposed surface of the diffusion barrier layer.

[0019] Optionally, the width of the groove ring is in the range of 1 to 3 μm, the height of the groove ring is in the range of 2 to 10 μm, and the spacing between adjacent groove rings is in the range of 4 to 90 μm.

[0020] Optionally, the metal interconnect structure includes at least two conductive metal layers, two adjacent conductive metal layers are connected via conductive pillars, and a bottom conductive pillar is connected below the conductive metal layer located at the bottom layer.

[0021] Optionally, a conductive metal layer and a plurality of conductive plugs are formed in the substrate in the chip main body area, which are located on the same layer structure as the moat ring structure. The conductive plugs are connected below the conductive metal layer, and the metal interconnection structure passes through the diffusion barrier layer and is connected above the conductive metal layer.

[0022] Optionally, the passivation protection layer includes, from bottom to top, a first oxide layer, a silicon nitride layer and a second oxide layer.

[0023] Optionally, the method further includes forming a polymer layer on the passivation protection layer, wherein the groove ring opens from a top surface of the polymer layer, and the opening opens from a top surface of the polymer layer.

[0024] The present invention also provides a chip inner moat structure, comprising:

[0025] A substrate, on which a chip main body area and a chip peripheral area surrounding the chip main body area are defined;

[0026] A diffusion barrier layer is located on the surface of the substrate, and a moat ring structure is embedded in the substrate, located in the peripheral area of ​​the chip and covered under the diffusion barrier layer;

[0027] A dielectric layer, located on the surface of the diffusion barrier layer;

[0028] A metal interconnect structure and a bonding pad are located in the dielectric layer, and the conductive metal layer of the metal interconnect structure and the bonding pad are located in the chip body area;

[0029] A passivation protection layer, located on the surface of the dielectric layer;

[0030] Among them, the moat structure inside the chip has an opening formed in the chip main body area to expose the bonding pad; the moat structure inside the chip also has a moat groove structure, which is formed in the chip peripheral area and aligned with the moat ring structure to block the wafer cutting stress from being transmitted to the chip main body area; the moat groove structure includes at least two separately arranged groove rings, wherein the groove rings extend downward into the dielectric layer but do not penetrate the diffusion barrier layer, and the opening extends downward to the surface of the bonding pad.

[0031] Optionally, the moat ring structure includes at least two discretely arranged first metal rings and a plurality of first conductive plugs, the diffusion barrier layer covers the first metal rings, the conductive plugs are connected under the metal rings, and the groove ring is longitudinally aligned with the first metal rings.

[0032] Optionally, the metal interconnect structure includes at least two conductive metal layers, the dielectric layer includes an upper diffusion barrier layer, the upper diffusion barrier layer is located above one of the conductive metal layers to prevent diffusion of this conductive metal layer, and the bottom surface of the slot ring is relatively located on the top surface of the upper diffusion barrier layer and includes a non-penetrating surface of the dielectric layer.

[0033] Optionally, the metal interconnect structure further includes at least two discretely arranged second metal rings aligned on the moat ring structure and a plurality of second metal plugs in the dielectric layer in the peripheral area of ​​the chip, the second metal ring is located below the upper diffusion barrier layer, and the second metal plug is connected below the second metal ring.

[0034] Optionally, the metal interconnect structure includes at least two conductive metal layers, the dielectric layer includes an upper diffusion barrier layer, the upper diffusion barrier layer is located above one of the conductive metal layers to prevent diffusion of this conductive metal layer, and the bottom surface of the slot ring includes the exposed surface of the upper diffusion barrier layer.

[0035] Optionally, the metal interconnect structure further includes at least two discretely arranged second metal rings aligned on the moat ring structure and a plurality of second metal plugs in the dielectric layer in the peripheral area of ​​the chip, the second metal ring is located below the upper diffusion barrier layer, and the second metal plug is connected below the second metal ring.

[0036] Optionally, a bottom surface of the slot ring is located opposite to a top surface of the diffusion barrier layer and includes a non-penetrating surface of the dielectric layer.

[0037] Optionally, the slot ring penetrates the dielectric layer, and a bottom surface of the slot ring includes an exposed surface of the diffusion barrier layer.

[0038] Optionally, the width of the groove ring is in the range of 1 to 3 μm, the height of the groove ring is in the range of 2 to 10 μm, and the spacing between adjacent groove rings is in the range of 4 to 90 μm.

[0039] Optionally, the metal interconnect structure includes at least two conductive metal layers, two adjacent conductive metal layers are connected via conductive pillars, and a bottom conductive pillar is connected below the conductive metal layer located at the bottom layer.

[0040] Optionally, a conductive metal layer and a plurality of conductive plugs are formed in the substrate in the chip main body area, which are located on the same layer structure as the moat ring structure. The conductive plugs are connected below the conductive metal layer, and the metal interconnection structure passes through the diffusion barrier layer and is connected above the conductive metal layer.

[0041] Optionally, the passivation protection layer includes, from bottom to top, a first oxide layer, a silicon nitride layer and a second oxide layer.

[0042] Optionally, the moat structure within the chip further includes a polymer layer located on the passivation protection layer, the groove ring opens from the top surface of the polymer layer, and the opening opens from the top surface of the polymer layer.

[0043] As described above, the chip inner moat structure and the manufacturing method thereof of the present invention have the following beneficial effects: the chip inner moat structure and the manufacturing method thereof of the present invention arrange a groove ring in the chip peripheral area, and the groove ring surrounds the chip main body area, which can effectively block the wafer cutting stress from being transmitted to the chip main body area, thereby preventing the generation of cracks in the chip. The present invention reduces the use of metal materials, which can not only reduce the process complexity and improve the yield, but also help reduce production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Shown is a partial top view of a wafer in the prior art.

[0045] Figure 2 Display as Figure 1 A-A' cross-sectional view.

[0046] Figure 3 Shown is a partial top view of the wafer in the first embodiment of the present invention.

[0047] Figure 4 Display as Figure 3 B-B' cross-sectional view.

[0048] Figure 5-Figure 13 It is a schematic diagram of the cross-sectional structure presented in each step of the manufacturing method of the moat structure in the chip of the present invention in the first embodiment.

[0049] Fig.14 It is a cross-sectional structural diagram of the moat structure within a chip of the present invention in the second embodiment.

[0050] Fig.15 It is a cross-sectional structural diagram of the moat structure within a chip of the present invention in the third embodiment.

[0051] Fig.16 It is a cross-sectional structural diagram of the moat structure within a chip of the present invention in the fourth embodiment.

[0052] Fig.17 It is a cross-sectional structural diagram of the moat structure within a chip of the present invention in the fifth embodiment.

[0053] Fig.18 It is a cross-sectional structural diagram of the moat structure within the chip of the present invention in the sixth embodiment.

[0054] Component number description

[0055] 101 Chip

[0056] 102 Cutting Road

[0057] 103 protection ring

[0058] 104 contact pin

[0059] 105 First Metal Ring

[0060] 106 First Plug

[0061] 107 Second Metal Ring

[0062] 108 Second Plug

[0063] 109 Third Metal Ring

[0064] 110 Passivation protective layer

[0065] 1101 Oxide layer

[0066] 1102 Silicon nitride layer

[0067] 1103 Polyimide layer

[0068] 111,112 Dielectric layer

[0069] 113 SiCN diffusion barrier layer

[0070] 114 Adhesive layer

[0071] 200 cutting lanes

[0072] I Chip body area

[0073] II Chip surrounding area

[0074] 201 substrate

[0075] 202 conductive metal layer

[0076] 203 Conductive plug

[0077] 204 Adhesive layer

[0078] 205 First Metal Ring

[0079] 206 first conductive plug

[0080] 207 Adhesive layer

[0081] 208 Diffusion Barrier

[0082] 209 Dielectric layer

[0083] 209a first dielectric layer

[0084] 209b Second dielectric layer

[0085] 210 Metal Interconnect Structure

[0086] 210a, 210b conductive metal layer

[0087] 210c Conductive column

[0088] 210c' conductive column through hole

[0089] 210d Bottom conductive column

[0090] 211 Bonding pad

[0091] 212 Passivation protective layer

[0092] 212a First oxide layer

[0093] 212b Silicon nitride layer

[0094] 212c Second oxide layer

[0095] 213 Polymer layer

[0096] 213a First polymer layer opening

[0097] 213b Second polymer layer opening

[0098] 214 Groove Ring

[0099] 215 Opening

[0100] 216 Upper diffusion barrier

[0101] 217 Second Metal Ring

[0102] 218 Second metal plug

[0103] W Width of groove ring

[0104] H Groove ring height

[0105] D groove ring spacing DETAILED DESCRIPTION

[0106] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0107] See also Figures 3 to 18 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0108] Embodiment 1

[0109] In this embodiment, the moat structure in the chip is manufactured on a wafer. Figure 3 , which is a partial top view of the wafer, wherein a plurality of intra-chip moat structures are arranged in the wafer, and adjacent intra-chip moat structures are separated by cutting paths 200 .

[0110] like Figure 3As shown, the chip inner moat structure is defined as a chip main body area I and a chip peripheral area II surrounding the chip main body area I. The chip peripheral area II is provided with a moat groove structure, and the moat groove structure includes at least two discretely arranged groove rings 214. The groove rings 214 surround the chip main body area I to block the wafer cutting stress from being transmitted to the chip main body area I. In this embodiment, the groove ring 214 is a rectangular ring ( Figure 3 Only two sides of the rectangular ring are shown), and the number of the groove rings 214 is 3. However, in other embodiments, the shape of the groove ring 214 can also be adjusted according to the actual outline of the chip and the device layout, and the number of the groove rings 214 can also be adjusted as needed, for example, 2 to 10, and the scope of protection of the present invention should not be excessively limited here.

[0111] See also Figure 4 , displayed as Figure 3 From the BB' cross-sectional view, it can be seen that in addition to the moat groove structure, the moat structure in the chip further includes a substrate 201, a diffusion barrier layer 208, a dielectric layer 209, a metal interconnect structure 210, a bonding pad 211, a passivation protection layer 212, a polymer layer 213 and an opening 215, wherein the diffusion barrier layer 208 is located on the surface of the substrate 201, a moat ring structure is buried in the substrate 201, the moat ring structure is located in the chip peripheral area II and covered under the diffusion barrier layer 208, the moat ring structure includes at least two discretely arranged first metal rings 205 and a plurality of first conductive plugs 206, the interface between the first conductive plugs 206 and the substrate 201 has an adhesion layer 207, the diffusion barrier layer 208 covers the first metal ring 205, and the conductive plug 206 is connected to the bottom of the first metal ring 205. In this embodiment, the moat groove structure is aligned with the moat ring structure, and the groove ring 214 is longitudinally aligned with the first metal ring 205. The dielectric layer 209 is located on the surface of the diffusion barrier layer 208, the metal interconnect structure 210 and the bonding pad 211 are located in the dielectric layer 209, the conductive metal layer of the metal interconnect structure 210 and the bonding pad 211 are located in the chip main body region I, and in this embodiment, the bonding pad 211 is close to the edge of the chip main body region I. The passivation protection layer 212 is located on the surface of the dielectric layer 209, the polymer layer 213 is located on the surface of the passivation protection layer, the groove ring 214 opens from the top surface of the polymer layer 213 and extends downward to the dielectric layer 209, but does not penetrate the diffusion barrier layer 208, and the opening 215 opens from the top surface of the polymer layer 213 and extends downward to the surface of the bonding pad 211 to expose the bonding pad 211.

[0112] Specifically, the width W of the groove ring is in the range of 1 to 3 μm, the height H of the groove ring is in the range of 2 to 10 μm, and the spacing D between adjacent groove rings is in the range of 4 to 90 μm. In this embodiment, the bottom surface of the groove ring 214 is located on the top surface of the diffusion barrier layer 208 and includes a non-penetrating surface of the dielectric layer 209 .

[0113] Specifically, the metal interconnect structure 210 includes at least two conductive metal layers. In this embodiment, the metal interconnect structure 210 includes two conductive metal layers 210a and 210b, and the two adjacent conductive metal layers are connected by a conductive column 210c, and the conductive column 210d is connected to the bottom of the conductive metal layer 210b. The materials of the conductive metal layers 210a, 210b and the conductive column 210c include but are not limited to tungsten, copper, aluminum, etc.

[0114] Specifically, the substrate in the chip main body region I further forms a conductive metal layer 202 and a plurality of conductive plugs 203 located in the same layer structure as the moat ring structure, the conductive plugs 203 are connected below the conductive metal layer 202, and the metal interconnect structure 210 penetrates the diffusion barrier layer 208 and is connected above the conductive metal layer 202. The conductive metal layer 202 and the conductive plugs 203 are made of materials including, but not limited to, tungsten, copper, aluminum, etc.

[0115] Specifically, the passivation protection layer 212 includes a first oxide layer 212a, a silicon nitride layer 212b and a second oxide layer 212c from bottom to top. The materials of the first oxide layer 212a and the second oxide layer 212c include but are not limited to silicon dioxide, the material of the polymer layer 213 includes but is not limited to polyimide, and the material of the diffusion barrier layer 208 includes but is not limited to silicon carbonitride.

[0116] As an example, manufacturing the moat structure in the chip includes the following steps:

[0117] See also Figure 5 and Figure 6, performing step S201: providing a substrate 201, the surface of the substrate having a diffusion barrier layer 208, and the substrate defining a chip main body region I and a chip peripheral region II surrounding the chip main body region, the substrate being embedded with a moat ring structure, located in the chip peripheral region II and covered under the diffusion barrier layer 208. The moat ring structure comprises at least two first metal rings 205 and a plurality of first conductive plugs 206 disposed separately, the interface between the first conductive plugs 206 and the substrate 201 having an adhesive layer 207, the diffusion barrier layer 208 covering the first metal rings 205, and the conductive plugs 206 connected to the bottom of the first metal rings 205. In this embodiment, the moat groove structure is aligned with the moat ring structure, and the groove ring 214 is longitudinally aligned with the first metal ring 205. The substrate in the chip main body region I further includes a conductive metal layer 202 and a plurality of conductive plugs 203 located in the same layer structure as the moat ring structure, wherein the conductive plugs 203 are connected below the conductive metal layer 202. As an example, Figure 5 As shown, a plurality of conductive plugs 203 and a plurality of first conductive plugs 206 are first formed in the substrate 201, wherein the conductive plugs 203 are located in the substrate in the chip main body region I, and the first conductive plugs 206 are located in the substrate in the chip peripheral region II. Figure 6 As shown, a conductive metal layer 202 is then formed on the conductive plug 203 , a first metal ring 205 is formed on the first conductive plug 206 , and a diffusion barrier layer 208 is formed on the substrate.

[0118] Specifically, a conductive plug groove is first formed in the substrate by photolithography and etching processes, and then a conductive plug material (such as W) is deposited in the conductive plug groove, and excess conductive plug material outside the conductive plug groove is removed by chemical etching or chemical mechanical polishing. In order to enhance the bonding between the conductive plug 203 and the first conductive plug 206 and the substrate 201, and reduce the diffusion of the conductive plug material, an adhesive layer 204, 207 can be deposited on the bottom surface and sidewall of the conductive plug groove before depositing the conductive plug. The diffusion barrier layer 208 is used to prevent the diffusion of the conductive metal layer 202 and the first metal ring 205. The material of the diffusion barrier layer 208 includes but is not limited to silicon carbonitride.

[0119] See also Figures 7 to 10, execute step S202: form a dielectric layer 209 on the diffusion barrier layer, and form a metal interconnect structure 210 and a bonding pad 211 in the dielectric layer 209, the conductive metal layer of the metal interconnect structure 210 and the bonding pad 211 are located in the chip main body area I, and the bonding pad 211 is close to the edge of the chip main body area I.

[0120] Specifically, the metal interconnect structure 210 includes at least two conductive metal layers. In this embodiment, the metal interconnect structure 210 includes two conductive metal layers 210a and 210b, and the two adjacent conductive metal layers are connected by a conductive column 210c, and the conductive column 210d is connected to the bottom of the conductive metal layer 210b. The materials of the conductive metal layers 210a, 210b and the conductive column 210c include but are not limited to tungsten, copper, aluminum, etc.

[0121] As an example, Figure 7 As shown, a first dielectric layer 209a is first formed on the diffusion barrier layer 208, and a bottom conductive column 210d is formed in the first dielectric layer 209a of the chip main body region I. The material of the bottom conductive column 210d can be tungsten. Figure 7 The structure of the bottom conductive column 210d after chemical mechanical polishing is shown. Figure 8 As shown, a conductive metal layer 210b is then formed on the bottom conductive column 210d. Figure 8 The structure shown is that of the conductive metal layer 210b after being etched and patterned. Fig. 9 As shown, a second dielectric layer 209b is then formed on the first dielectric layer 209a, and a conductive column through hole 210c' is formed in the second dielectric layer 209b. Fig.10 As shown, a conductive column 210c and a conductive metal layer 210a are formed in the second dielectric layer 209b. Fig.10 The structure shown is that of the conductive metal layer 210a after being etched and patterned. The material of the first dielectric layer 209a can be silicon dioxide or low-k dielectric. The material of the second dielectric layer 209b can be silicon dioxide or low-k dielectric.

[0122] In this embodiment, a bonding pad 211 is further formed in the second dielectric layer 209 b . The bonding pad 211 is close to the edge of the chip main body region I for packaging testing.

[0123] See also Fig.11 , perform step 203 : forming a passivation protection layer 212 on the dielectric layer 209 .

[0124] Specifically, a first oxide layer 212a, a silicon nitride layer 212b and a second oxide layer 212c are sequentially deposited from bottom to top as the passivation protection layer 212, and the material of the first oxide layer 212a and the second oxide layer 212c can be silicon dioxide.

[0125] See also Fig.12 , perform step 204 : forming a polymer layer 213 on the passivation protection layer 212 .

[0126] Specifically, the material of the polymer layer 213 includes but is not limited to polyimide. In this embodiment, the polymer layer 213 is further patterned to obtain a first polymer layer opening 213a and a second polymer layer opening 213b, wherein the first polymer layer opening 213a corresponds to the position of the bonding pad 211, and the second polymer layer opening 213b is annular and located in the chip peripheral area II. The first polymer layer opening 213a and the second polymer layer opening 213b can be formed by photolithography or laser drilling.

[0127] See also Fig.13 , execute step S205: form an opening 215 in the chip main body area I to expose the bonding pad 211, and simultaneously form a moat groove structure in the chip peripheral area II to block the wafer cutting stress from being transmitted to the chip main body area I, the moat groove structure is aligned with the moat ring structure and includes at least two discretely arranged groove rings 214, wherein the groove ring 214 opens from the top surface of the polymer layer 213 and extends downward to the dielectric layer 209, but does not penetrate the diffusion barrier layer 208, and the opening 215 opens from the top surface of the polymer layer 213 and extends downward to the surface of the bonding pad 211.

[0128] Specifically, the first polymer layer opening 213a is extended downward to the surface of the bonding pad 211 by etching, and the second polymer layer opening 213b is extended downward to the dielectric layer 209. In this embodiment, the bottom surface of the slot ring 214 is relatively located on the top surface of the diffusion barrier layer 208 and includes a non-penetrating surface of the dielectric layer 209a.

[0129] It should be noted that in other embodiments, the metal interconnect structure 210 may also have more layers of metal, and its manufacturing process is not limited to the above process flow, for example, a single damascene process or a dual damascene process may be selected as needed, and the protection scope of the present invention should not be excessively limited here.

[0130] The chip inner moat structure and manufacturing method of the present invention arranges a groove ring in the chip peripheral area, and the groove ring surrounds the chip main area, which can effectively block the wafer cutting stress from being transmitted to the chip main area, thereby preventing the generation of cracks in the chip. Since there is no metal filling in the groove ring, the use of metal materials can be reduced, which can not only reduce the process complexity and improve the yield, but also help reduce production costs.

[0131] Embodiment 2

[0132] This embodiment adopts the same technical solution as the first embodiment, except that in the first embodiment, the groove ring 214 opens from the top surface of the polymer layer 213 and extends downward into the dielectric layer 209, and the bottom surface of the groove ring 214 is located relatively on the top surface of the diffusion barrier layer 208 and includes the non-penetrating surface of the dielectric layer 209a. In this embodiment, the groove ring 214 penetrates the dielectric layer 209, and the bottom surface of the groove ring 214 includes the exposed surface of the diffusion barrier layer 208, as shown in FIG. Fig.14 shown.

[0133] Embodiment 3

[0134] This embodiment adopts the same technical solution as the first embodiment, except that in this embodiment, the dielectric layer 209 has an upper diffusion barrier layer 216, and the upper diffusion barrier layer 216 is located above one of the conductive metal layers to prevent the diffusion of the conductive metal layer. Fig.15 , which is a schematic diagram of the cross-sectional structure of the moat structure in the chip in this embodiment, as an example, the upper diffusion barrier layer 216 is located above the conductive metal layer 210b, and the bottom surface of the groove ring 214 is located on the top surface of the upper diffusion barrier layer 216 and includes the non-penetrating surface of the dielectric layer 209b. The material of the upper diffusion barrier layer 216 includes but is not limited to silicon carbonitride.

[0135] This embodiment is applicable to the case where the conductive metal layer 210 b is made of Cu or other easily diffusible materials.

[0136] Embodiment 4

[0137] This embodiment and the third embodiment adopt the same technical solution, except that the groove ring 214 in the third embodiment opens from the top surface of the polymer layer 213 and extends downward into the dielectric layer 209, and the bottom surface of the groove ring 214 is located relatively on the top surface of the upper diffusion barrier layer 216 and includes the non-penetrating surface of the dielectric layer 209b. In this embodiment, the bottom surface of the groove ring 214 includes the exposed surface of the upper diffusion barrier layer 216, such as Fig.16 shown.

[0138] Embodiment 5

[0139] This embodiment and the third embodiment adopt a substantially same technical solution, except that the metal interconnect structure 210 in this embodiment further comprises at least two discretely arranged second metal rings 217 aligned on the moat structure and a plurality of second metal plugs 218 in the dielectric layer 209 in the chip peripheral region, the second metal ring 217 being located below the upper diffusion barrier layer 216, and the second metal plugs 218 being connected below the second metal ring 217, as shown in FIG. Fig.17 shown.

[0140] In this embodiment, the chip peripheral area II has both a groove ring 214 and a metal ring 217, taking into account the advantages of both and reducing the use of metal materials, which can not only reduce process complexity and improve yield, but also help reduce production costs.

[0141] Embodiment 6

[0142] This embodiment and the fifth embodiment adopt the same technical solution, except that the groove ring 214 in the fifth embodiment opens from the top surface of the polymer layer 213 and extends downward into the dielectric layer 209, and the bottom surface of the groove ring 214 is located relatively on the top surface of the upper diffusion barrier layer 216 and includes the non-penetrating surface of the dielectric layer 209b. In this embodiment, the bottom surface of the groove ring 214 includes the exposed surface of the upper diffusion barrier layer 216, such as Fig.18 shown.

[0143] In summary, the chip moat structure and manufacturing method of the present invention can effectively block the wafer cutting stress from being transmitted to the inside of the chip by arranging a groove ring in the peripheral area of ​​the chip main body layer, and the groove ring surrounds the middle area of ​​the chip main body layer, thereby preventing the generation of cracks in the chip. Since there is no metal filling in the groove ring, the use of metal materials can be reduced, which can not only reduce the process complexity and improve the yield, but also help to reduce production costs. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0144] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a moat structure in a chip, characterized in that: The following steps are involved: A substrate is provided, wherein a diffusion barrier layer is provided on the surface of the substrate, and a chip main body area and a chip peripheral area surrounding the chip main body area are defined on the substrate, and a moat ring structure is embedded in the substrate, located in the chip peripheral area and covered under the diffusion barrier layer; Forming a dielectric layer on the diffusion barrier layer, and forming a metal interconnect structure and a bonding pad in the dielectric layer, wherein the conductive metal layer of the metal interconnect structure and the bonding pad are located in the chip main body region; forming a passivation protection layer on the dielectric layer; An opening is formed in the chip main body area to expose the bonding pad, and a moat groove structure is simultaneously formed in the chip peripheral area to block the wafer cutting stress from being transmitted to the chip main body area, the moat groove structure is aligned with the moat ring structure and includes at least two discretely arranged groove rings, wherein the groove ring extends downward into the dielectric layer but does not penetrate the diffusion barrier layer, and the opening extends downward to the surface of the bonding pad.

2. The method for manufacturing a moat structure in a chip according to claim 1, characterized in that: The moat ring structure includes at least two first metal rings and a plurality of first conductive plugs which are separately arranged. The diffusion barrier layer covers the first metal rings. The conductive plugs are connected under the metal rings. The groove rings are longitudinally aligned with the first metal rings.

3. The method for manufacturing a moat structure in a chip according to claim 2, characterized in that: The metal interconnect structure includes at least two conductive metal layers, the dielectric layer includes an upper diffusion barrier layer, the upper diffusion barrier layer is located above one of the conductive metal layers to prevent the diffusion of this conductive metal layer, and the bottom surface of the slot ring is relatively located on the top surface of the upper diffusion barrier layer and includes a non-penetrating surface of the dielectric layer.

4. The method for manufacturing a moat structure in a chip according to claim 3, characterized in that: The metal interconnect structure further includes at least two discretely arranged second metal rings aligned on the moat ring structure and a plurality of second metal plugs in the dielectric layer in the chip peripheral area, the second metal ring is located below the upper diffusion barrier layer, and the second metal plug is connected below the second metal ring.

5. The method for manufacturing a moat structure in a chip according to claim 2, characterized in that: The metal interconnect structure includes at least two conductive metal layers, the dielectric layer includes an upper diffusion barrier layer, the upper diffusion barrier layer is located above one of the conductive metal layers to prevent the diffusion of this conductive metal layer, and the bottom surface of the groove ring includes the exposed surface of the upper diffusion barrier layer.

6. The method for manufacturing a moat structure in a chip according to claim 5, characterized in that: The metal interconnect structure further includes at least two discretely arranged second metal rings aligned on the moat ring structure and a plurality of second metal plugs in the dielectric layer in the chip peripheral area, the second metal ring is located below the upper diffusion barrier layer, and the second metal plug is connected below the second metal ring.

7. The method for manufacturing a moat structure in a chip according to claim 1, characterized in that: A bottom surface of the groove ring is located opposite to a top surface of the diffusion barrier layer and includes a non-penetrating surface of the dielectric layer.

8. The method for manufacturing a moat structure in a chip according to claim 1, characterized in that: The slot ring penetrates the dielectric layer, and a bottom surface of the slot ring includes an exposed surface of the diffusion barrier layer.

9. The method for manufacturing a moat structure in a chip according to claim 1, characterized in that: The width of the groove ring is in the range of 1 to 3 μm, the height of the groove ring is in the range of 2 to 10 μm, and the spacing between adjacent groove rings is in the range of 4 to 90 μm.

10. The method for manufacturing a moat structure in a chip according to claim 1, characterized in that: The metal interconnect structure includes at least two conductive metal layers, two adjacent conductive metal layers are connected by conductive pillars, and a bottom conductive pillar is connected below the conductive metal layer located at the bottom.

11. The method for manufacturing a moat structure in a chip according to claim 1, characterized in that: The substrate in the chip main area further forms a conductive metal layer and a plurality of conductive plugs located on the same layer structure as the moat ring structure. The conductive plugs are connected below the conductive metal layer, and the metal interconnection structure penetrates the diffusion barrier layer and is connected above the conductive metal layer.

12. The method for manufacturing a moat structure in a chip according to claim 1, characterized in that: The passivation protection layer includes a first oxide layer, a silicon nitride layer and a second oxide layer in order from bottom to top.

13. The method for manufacturing a moat structure in a chip according to claim 1, characterized in that: The method further comprises the step of forming a polymer layer on the passivation protection layer, wherein the groove ring opens from the top surface of the polymer layer, and the opening opens from the top surface of the polymer layer.

14. A moat structure in a chip, characterized in that: include: A substrate, on which a chip main body area and a chip peripheral area surrounding the chip main body area are defined; A diffusion barrier layer is located on the surface of the substrate, and a moat ring structure is embedded in the substrate, located in the peripheral area of ​​the chip and covered under the diffusion barrier layer; A dielectric layer, located on the surface of the diffusion barrier layer; A metal interconnect structure and a bonding pad are located in the dielectric layer, and the conductive metal layer of the metal interconnect structure and the bonding pad are located in the chip body area; A passivation protection layer, located on the surface of the dielectric layer; Among them, the moat structure inside the chip has an opening formed in the chip main body area to expose the bonding pad; the moat structure inside the chip also has a moat groove structure, which is formed in the chip peripheral area and aligned with the moat ring structure to block the wafer cutting stress from being transmitted to the chip main body area; the moat groove structure includes at least two separately arranged groove rings, wherein the groove ring extends downward into the dielectric layer but does not penetrate the diffusion barrier layer, the opening extends downward to the surface of the bonding pad, and the groove ring surrounds the chip main body area.

15. The chip inner moat structure according to claim 14, characterized in that: The moat ring structure includes at least two first metal rings and a plurality of first conductive plugs which are separately arranged. The diffusion barrier layer covers the first metal rings. The conductive plugs are connected under the metal rings. The groove rings are longitudinally aligned with the first metal rings.

16. The chip inner moat structure according to claim 15, characterized in that: The metal interconnect structure includes at least two conductive metal layers, the dielectric layer includes an upper diffusion barrier layer, the upper diffusion barrier layer is located above one of the conductive metal layers to prevent the diffusion of this conductive metal layer, and the bottom surface of the slot ring is relatively located on the top surface of the upper diffusion barrier layer and includes a non-penetrating surface of the dielectric layer.

17. The chip inner moat structure according to claim 16, characterized in that: The metal interconnect structure further includes at least two discretely arranged second metal rings aligned on the moat ring structure and a plurality of second metal plugs in the dielectric layer in the chip peripheral area, the second metal ring is located below the upper diffusion barrier layer, and the second metal plug is connected below the second metal ring.

18. The chip inner moat structure according to claim 15, characterized in that: The metal interconnect structure includes at least two conductive metal layers, the dielectric layer includes an upper diffusion barrier layer, the upper diffusion barrier layer is located above one of the conductive metal layers to prevent the diffusion of this conductive metal layer, and the bottom surface of the groove ring includes the exposed surface of the upper diffusion barrier layer.

19. The chip inner moat structure according to claim 18, characterized in that: The metal interconnect structure further includes at least two discretely arranged second metal rings aligned on the moat ring structure and a plurality of second metal plugs in the dielectric layer in the chip peripheral area, the second metal ring is located below the upper diffusion barrier layer, and the second metal plug is connected below the second metal ring.

20. The chip inner moat structure according to claim 14, characterized in that: A bottom surface of the groove ring is located opposite to a top surface of the diffusion barrier layer and includes a non-penetrating surface of the dielectric layer.

21. The chip inner moat structure according to claim 14, characterized in that: The slot ring penetrates the dielectric layer, and a bottom surface of the slot ring includes an exposed surface of the diffusion barrier layer.

22. The chip inner moat structure according to claim 14, characterized in that: The width of the groove ring is in the range of 1 to 3 μm, the height of the groove ring is in the range of 2 to 10 μm, and the spacing between adjacent groove rings is in the range of 4 to 90 μm.

23. The chip inner moat structure according to claim 14, characterized in that: The metal interconnect structure includes at least two conductive metal layers, two adjacent conductive metal layers are connected by conductive pillars, and a bottom conductive pillar is connected below the conductive metal layer located at the bottom.

24. The chip inner moat structure according to claim 14, characterized in that: The substrate in the chip main area further forms a conductive metal layer and a plurality of conductive plugs located on the same layer structure as the moat ring structure. The conductive plugs are connected below the conductive metal layer, and the metal interconnection structure penetrates the diffusion barrier layer and is connected above the conductive metal layer.

25. The chip inner moat structure according to claim 14, characterized in that: The passivation protection layer includes a first oxide layer, a silicon nitride layer and a second oxide layer in order from bottom to top.

26. The chip inner moat structure according to claim 14, characterized in that: The chip inner moat structure further includes a polymer layer located on the passivation protection layer, the groove ring opens from the top surface of the polymer layer, and the opening opens from the top surface of the polymer layer.

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