Semiconductor structure and method for forming the same

Abstract

The present invention provides a semiconductor structure and a method for forming the same. A stress buffer layer is inserted into the insulating dielectric layer of the semiconductor structure to counterbalance the stress of the insulating dielectric layer and avoid the problem of warping of the substrate under the stress of the insulating dielectric layer. In addition, the stress buffer layer can effectively block the intrusion of water vapor, which can improve the accuracy of the passivation layer pattern on the one hand, and avoid the problem of water vapor erosion of the film layer below the stress buffer layer on the other hand.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the post-process of semiconductor manufacturing, it is usually necessary to package the substrate formed with the device structure and form a semiconductor structure.

[0003] At present, when encapsulating a substrate, a thick insulating dielectric layer is generally covered on the substrate to seal the device structure below and insulate the device structure. However, the thick insulating dielectric layer often causes the entire substrate to warp due to the stress of the material itself, which can easily lead to the film layer on the substrate breaking. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor structure to solve the problem that the existing semiconductor structure is prone to warping.

[0005] In order to solve the above technical problems, the present invention provides a semiconductor structure, which includes a substrate and a passivation layer formed on the substrate, the passivation layer includes an insulating dielectric layer and a stress buffer layer, the stress buffer layer is interspersed in the insulating dielectric layer along the direction of the substrate surface, and the stress of the stress buffer layer is opposite to the stress of the insulating dielectric layer.

[0006] Optionally, a contact pad is further formed on the substrate, an opening is formed in the passivation layer, the passivation layer covers the substrate and exposes at least a portion of the contact pad through the opening.

[0007] Optionally, a portion of the insulating dielectric layer located below the stress buffer layer constitutes a first dielectric layer, and a portion of the insulating dielectric layer located above the stress buffer layer constitutes a second dielectric layer; wherein the side walls of the first dielectric layer, the stress buffer layer and the second dielectric layer close to the contact pad are all exposed in the opening to jointly constitute the side walls of the opening.

[0008] Optionally, a portion of the insulating dielectric layer located below the stress buffer layer constitutes a first dielectric layer, and a portion of the insulating dielectric layer located above the stress buffer layer constitutes a second dielectric layer; wherein the stress buffer layer is formed on the first dielectric layer and also covers the side wall of the first dielectric layer close to the contact pad so that the stress buffer layer is connected to the contact pad.

[0009] Optionally, an interconnection structure is further formed in the substrate, a top interconnection layer of the interconnection structure protrudes from the surface of the substrate and is located in the same structural layer as the contact pad, and the passivation layer covers the interconnection structure.

[0010] Optionally, an interconnection structure is further formed in the substrate, a top interconnection layer of the interconnection structure protrudes from the surface of the substrate and is located in the same structural layer as the contact pad, and the passivation layer covers the interconnection structure.

[0011] Optionally, the thickness of the stress buffer layer is between 10 nm and 120 nm.

[0012] Optionally, the passivation layer further includes a polyimide protective layer, and the polyimide protective layer covers the insulating dielectric layer.

[0013] Optionally, the passivation layer further includes an isolation dielectric layer, and the isolation dielectric layer is located between the insulating dielectric layer and the polyimide protective layer.

[0014] Another object of the present invention is to provide a method for forming a semiconductor structure, comprising:

[0015] providing a substrate; and,

[0016] A passivation layer is formed on the substrate, the passivation layer includes an insulating dielectric layer and a stress buffer layer, the stress buffer layer is interspersed in the insulating dielectric layer along the substrate surface, and the stress of the stress buffer layer is opposite to the stress of the insulating dielectric layer.

[0017] Optionally, a contact pad is further formed on the substrate, an opening is formed in the passivation layer, the passivation layer covers the substrate and exposes at least a portion of the contact pad through the opening.

[0018] Optionally, the method for forming the passivation layer includes:

[0019] sequentially forming a first dielectric material layer, a buffer material layer, and a second dielectric material layer on the substrate;

[0020] forming a polyimide protection layer on the second dielectric material layer, wherein a mask opening is formed in the polyimide protection layer, and the mask opening is located above the contact pad; and,

[0021] An etching process is performed using the polyimide protective layer as a mask to sequentially etch the second dielectric material layer, the buffer material layer and the first dielectric material layer to respectively form a second dielectric layer, a stress buffer layer and a first dielectric layer, and the second dielectric layer, the stress buffer layer and the first dielectric layer are used to surround the opening near the side wall of the contact pad, and the first dielectric layer and the second dielectric layer constitute the insulating dielectric layer, and the polyimide layer is retained to jointly constitute the passivation layer.

[0022] Optionally, the method for forming the passivation layer includes:

[0023] forming a first dielectric layer on the substrate, wherein a groove is formed in the first dielectric layer to expose at least a portion of the contact pad;

[0024] forming a buffer material layer on the substrate, wherein the buffer material layer covers the first dielectric layer and covers the sidewall of the groove;

[0025] forming a second dielectric material layer on the buffer material layer, and forming a polyimide protective layer on the buffer material layer, wherein the polyimide protective layer also covers a portion of the buffer material layer that covers the sidewall of the groove, and a through hole is formed in the polyimide protective layer, wherein the through hole is located above the contact pad; and,

[0026] An etching process is performed using the polyimide protective layer as a mask to sequentially etch the second dielectric material layer and the buffer material layer to respectively form a second dielectric layer and a stress buffer layer, wherein the side wall of the second dielectric layer close to the contact pad is connected to the contact pad, and the side wall of the second dielectric layer close to the contact pad is used to surround the opening, and the first dielectric layer and the second dielectric layer constitute the insulating dielectric layer, and the polyimide layer is retained to jointly constitute the passivation layer.

[0027] Optionally, before forming the polyimide protective layer, an isolation dielectric material layer is formed on the second dielectric material layer; and during the etching process, the isolation dielectric material layer is also etched to form an isolation dielectric layer between the second dielectric layer and the polyimide protective layer.

[0028] In the semiconductor structure provided by the present invention, a stress buffer layer with opposite stress in the insulating dielectric layer is provided to counterbalance the stress of the insulating dielectric layer, thereby effectively improving the problem of substrate warping caused by the stress of the insulating dielectric layer.

[0029] Furthermore, the stress buffer layer also has a barrier effect. For example, when a polyimide coating is used to define a passivation layer pattern, the stress buffer layer can be used to block residual water vapor underneath it, thereby preventing the polyimide coating above the stress buffer layer from absorbing water and deforming, thereby ensuring the accuracy of the passivation layer pattern; and, after the preparation of the semiconductor structure is completed, the stress buffer layer can also be used to block the intrusion of water vapor in the external environment, thereby avoiding adverse effects on the film layer below the stress buffer layer (for example, the problem of water vapor erosion of the metal film layer below the stress buffer layer can be avoided). BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1a The layout structure of the interconnection structure and contact pad of the semiconductor structure in the first embodiment of the present invention;

[0031] Figure 1b The semiconductor structure in the first embodiment of the present invention corresponds to Figure 1a Schematic diagram of the cross section in the AA' and BB' directions;

[0032] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure in Embodiment 2 of the present invention;

[0033] Figure 3 is a schematic flow chart of a method for forming a semiconductor structure in Embodiment 3 of the present invention;

[0034] Figure 4a to Figure 4d A schematic structural diagram of a method for forming a semiconductor structure in a third embodiment of the present invention during its preparation process;

[0035] Figure 5 is a schematic flow chart of a method for forming a semiconductor structure in a fourth embodiment of the present invention;

[0036] Figure 6a to Figure 6c It is a structural schematic diagram of the method for forming a semiconductor structure in the fourth embodiment of the present invention during its preparation process.

[0037] The reference numerals are as follows:

[0038] 100-substrate;

[0039] 110- contact pad;

[0040] 111-bottom metal diffusion barrier layer; 112-metal material layer;

[0041] 113-top metal diffusion barrier layer;

[0042] 120-interconnection structure;

[0043] 121 - lower layer interconnection line; 122 - conductive plug;

[0044] 123-upper interconnection line;

[0045] 200-passivation layer; 200a-opening;

[0046] 210-first dielectric layer; 210a-first dielectric material layer;

[0047] 211-groove;

[0048] 220-stress buffer layer; 220a-buffer material layer;

[0049] 230-a second dielectric layer; 230a-a second dielectric material layer;

[0050] 240-polyimide protective layer; 241-mask opening;

[0051] 250-isolation dielectric layer; 250a-isolation dielectric material layer. DETAILED DESCRIPTION

[0052] The semiconductor structure and the method for forming the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0053] Embodiment 1

[0054] Figure 1a The layout structure of the interconnection structure and the contact pad of the semiconductor structure in the first embodiment of the present invention is as follows: Figure 1b The semiconductor structure in the first embodiment of the present invention corresponds to Figure 1a Schematic diagram of the cross section in the AA' and BB' directions.

[0055] Combination Figure 1a and Figure 1b As shown, the semiconductor structure includes a substrate 100 and a passivation layer 200 formed on the substrate 100 .

[0056] In this embodiment, an interconnection structure 120 is further formed in the substrate 100. The interconnection structure 120 has a plurality of interconnection lines stacked on each other, and the interconnection lines in different structural layers can be electrically connected by conductive plugs.

[0057] It should be appreciated that the drawings of the present embodiment only schematically show three lower interconnection lines 121, three upper interconnection lines 123, and conductive plugs 122 connecting the lower interconnection lines 121 and the upper interconnection lines 123. Further, the upper interconnection lines 123 are formed on the substrate 100 and protrude from the top surface of the substrate 100, and the passivation layer 200 covers the upper interconnection lines 123 and fills the gaps between adjacent upper interconnection lines 123.

[0058] Further, a contact pad 110 is formed on the substrate 100. The contact pad 110 is located in the same structural layer as the top interconnection line of the interconnection structure 120 (i.e., the upper interconnection line 123 in this embodiment) and can be electrically connected to the upper interconnection line 123. In addition, an opening 200a is formed in the passivation layer 200. The passivation layer 200 covers the substrate 100 and exposes at least a portion of the contact pad 110 through the opening 200a. In this embodiment, the opening 200a of the passivation layer 200 covers the edge area of ​​the contact pad 110.

[0059] Further, the contact pad 110 includes a bottom metal diffusion barrier layer 111, a metal material layer 112, and a top metal diffusion barrier layer 113 stacked sequentially from bottom to top. Optionally, the top metal diffusion barrier layer 113 of the portion of the contact pad 110 exposed from the opening 200a is removed so that the metal material layer 112 is exposed in the opening 200a.

[0060] Key References Figure 1b As shown, the passivation layer 200 includes an insulating dielectric layer and a stress buffer layer 220. The stress buffer layer 220 is interspersed in the insulating dielectric layer along the direction of the substrate surface, and the stress of the stress buffer layer 220 is opposite to the stress of the insulating dielectric layer.

[0061] For example, when the insulating dielectric layer is tensile stress, a stress buffer layer 220 with compressive stress may be used; or, when the insulating dielectric layer has compressive stress, a stress buffer layer 220 with tensile stress may be used. In this embodiment, the material of the insulating dielectric layer includes silicon oxide, and the material of the stress buffer layer 220 includes silicon nitride.

[0062] That is, by forming a stress buffer layer 220 with a stress opposite to that of the insulating dielectric layer, the stress buffer layer 220 is used to balance the stress of the insulating dielectric layer, thereby alleviating the problem of warping of the insulating dielectric layer with a relatively large thickness under stress, so that the substrate is maintained on a flat horizontal plane. Specifically, the thickness of the stress buffer layer is, for example, between 10 nm and 120 nm. Obviously, the thickness of the insulating dielectric layer is greater than the thickness of the stress buffer layer.

[0063] In this embodiment, the substrate 100 is provided with an upper interconnection line 123 and a contact pad 110 protruding from the top surface of the substrate, so that the surface of the substrate below the passivation layer presents an uneven morphology. At this time, the stress buffer layer 220 presents an uneven morphology along the surface of the substrate. For example, the stress buffer layer 220 is protruding corresponding to the position of the upper interconnection line 123, and the stress buffer layer 220 is concave corresponding to the position between the upper interconnections.

[0064] like Figure 1b As shown, it can be considered that the insulating dielectric layer is divided into a first dielectric layer and a second dielectric layer by the stress buffer layer 220. The portion of the insulating dielectric layer located below the stress buffer layer 220 constitutes the first dielectric layer 210, and the portion of the insulating dielectric layer located above the stress buffer layer 220 constitutes the second dielectric layer 230.

[0065] In this embodiment, the side walls of the first dielectric layer 210 , the stress buffer layer 220 , and the second dielectric layer 230 close to the contact pad 110 are all exposed in the opening 200 a to jointly form the side walls of the opening 200 a .

[0066] Continue to refer Figure 1b As shown, the passivation layer 200 further includes a polyimide protection layer 240 , which covers the insulating dielectric layer and is used to isolate and protect the film layer and device structure thereunder, and correspondingly exposes the contact pad 110 .

[0067] Specifically, the polyimide protective layer 240 can effectively block electron migration, resist moisture, and increase the mechanical properties of the device. The polyimide protective layer 240 also has a buffering function, which can effectively improve the problem of circuit cracking and breaking caused by thermal stress and reduce damage to components during subsequent processing, packaging and post-processing.

[0068] It should be noted that the polyimide protective layer 240 not only plays a protective role, but also in the process of preparing the passivation layer 200, since the polyimide protective layer 240 is a photosensitive material, it can be used to determine the pattern of the passivation layer, and based on the patterned polyimide protective layer 240, the exposed film layer underneath is etched to further pattern the film layer underneath the polyimide protective layer 240, and then the polyimide protective layer 240 can be retained to constitute the passivation layer 200.

[0069] In a preferred solution, the passivation layer 200 further includes an isolation dielectric layer 250 , and the isolation dielectric layer 250 is located between the insulating dielectric layer and the polyimide protection layer 240 .

[0070] As described above, the polyimide protective layer 240 can be combined with the photolithography process to define the pattern of the passivation layer. However, the polyimide material has obvious characteristics of water absorption and expansion. Therefore, when there is residual water vapor on the substrate and it is not processed in time, during the process of polyimide coating, photolithography, and heating and baking, the water vapor will be absorbed by the polyimide material, and the polyimide coating will easily cause abnormality in the final photolithography shape after water absorption and expansion.

[0071] In this embodiment, an isolation dielectric layer 250 is disposed on the insulating dielectric layer, and the isolation dielectric layer 250 separates the polyimide protective layer 240 and the substrate 100. Therefore, before the polyimide protective layer 240 is formed, based on the isolation effect of the isolation dielectric layer 250, it is possible to prevent the water vapor under the isolation dielectric layer 250 from being absorbed by the polyimide protective layer 240. The material of the isolation dielectric layer 250 includes, for example, silicon nitride.

[0072] Of course, the stress buffer layer 220 is further provided in this embodiment, and the stress buffer layer 220 can correspondingly block the water vapor thereunder from diffusing upward to the polyimide protective layer 240 .

[0073] Embodiment 2

[0074] The difference from the first embodiment is that the stress buffer layer in this embodiment also covers the side wall of the first dielectric layer close to the contact pad, so that the stress buffer layer is connected to the contact pad. In this way, the stress buffer layer can be used to block the intrusion of external water vapor from the side wall position of the passivation layer opening, so as to prevent the interconnection structure in the semiconductor structure or the metal in the device structure from being corroded.

[0075] Figure 2 FIG. 1 is a cross-sectional schematic diagram of a semiconductor structure in Embodiment 2 of the present invention. Figure 2As shown, in this embodiment, the sidewalls of the first dielectric layer 210 are covered by the stress buffer layer 220 , so the stress buffer layer 220 can not only block the intrusion of external water vapor from the top of the interconnect structure 120 , but also block the intrusion of external water vapor from the side of the interconnect structure 120 .

[0076] Similar to the first embodiment, the top metal diffusion barrier layer 113 of the portion of the contact pad 110 exposed in the opening 200a is removed, and the top metal diffusion barrier layer 113 of the portion of the contact pad 110 covered by the passivation layer 200 is still retained, so that the stress buffer layer 220 extends to the edge of the contact pad 110 and is connected to the top metal diffusion barrier layer 113.

[0077] In this embodiment, the second dielectric layer 230 further covers the stress buffer layer 220 so that the stress buffer layer 220 is not exposed in the opening 200a, that is, in this embodiment, the bottom of the side wall of the second dielectric layer 230 is connected to the contact pad 110, and the side wall of the opening 200a is formed by the side wall of the second dielectric layer 230.

[0078] Embodiment 3

[0079] This embodiment provides a method for forming the semiconductor structure as described above. Figure 3 is a schematic flow chart of a method for forming a semiconductor structure in Embodiment 3 of the present invention, Figure 4a to Figure 4d It is a structural schematic diagram of the method for forming a semiconductor structure in the third embodiment of the present invention during its preparation process.

[0080] In step S100, refer to Figure 4a As shown, a substrate 100 is provided. The substrate 100 generally has a device structure (not shown in the figure) formed therein.

[0081] Furthermore, an interconnection structure is formed in the substrate 100, and the interconnection structure can be electrically connected to the device structure below it to lead out the device structure. The interconnection structure usually has a plurality of interconnection lines stacked on each other, and the interconnection lines in different structural layers can be electrically connected using conductive plugs.

[0082] Continue to refer Figure 4a As shown, a contact pad 110 is also formed on the substrate 100. The contact pad 110 is located in the same structural layer as the top interconnection line of the interconnection structure, and can be further electrically connected to the upper interconnection line. The upper interconnection line in the interconnection structure and the contact pad 110 both protrude from the top surface of the substrate 100.

[0083] In this embodiment, the contact pad 110 includes a bottom metal diffusion barrier layer 111 , a metal material layer 112 , and a top metal diffusion barrier layer 113 which are sequentially stacked from bottom to top.

[0084] In step S200, refer to Figure 4b to Figure 4d As shown, a passivation layer 200 is formed on the substrate 100, and the passivation layer 200 includes an insulating dielectric layer and a stress buffer layer 220. The stress buffer layer 220 is interspersed in the insulating dielectric layer along the direction of the substrate surface, and the stress of the stress buffer layer 220 is opposite to the stress of the insulating dielectric layer.

[0085] As described above, the contact pad 110 is formed on the substrate 100, and the passivation layer 200 is formed with an opening 200a, the passivation layer 200 covers the substrate 100 and uses the opening 200a to expose at least a portion of the contact pad 110. In this embodiment, the opening 200a of the passivation layer 200 covers the edge region of the contact pad 110.

[0086] Specifically, the method for forming the passivation layer 200 includes, for example, the following steps.

[0087] Step S210, see Figure 4b As shown, a first dielectric material layer 210 a , a buffer material layer 220 a , and a second dielectric material layer 230 a are sequentially formed on the substrate 100 and cover the interconnect structure and the contact pad 110 .

[0088] In a preferred embodiment, an isolation dielectric material layer 250a is also formed on the second dielectric material layer 230a. On the one hand, the isolation dielectric material layer 250a can isolate the water vapor in the film layer below it to avoid the water vapor in the film layer below affecting the polyimide material when the polyimide material is subsequently used to perform a photolithography process; on the other hand, after the semiconductor structure is prepared, the isolation dielectric material layer can also be used to isolate external water vapor from entering the film layer and structure below it.

[0089] Step S220, see Figure 4c As shown, a polyimide protection layer 240 is formed on the second dielectric material layer 230 a , and a mask opening 241 is formed in the polyimide protection layer 240 . The mask opening 241 is located above the contact pad 110 .

[0090] In this embodiment, the polyimide protection layer 240 is correspondingly formed on the isolation dielectric material layer 250 a , so that the isolation dielectric material layer 250 a can be used to isolate the water vapor thereunder to ensure the pattern accuracy in the polyimide protection layer 240 .

[0091] In step S230, refer to Figure 4d As shown, the polyimide protective layer 240 is used as a mask to perform an etching process to sequentially etch the isolation dielectric material layer 250a, the second dielectric material layer 230a, the buffer material layer 220a and the first dielectric material layer 210a, thereby forming an isolation dielectric layer 250, a second dielectric layer 230, a stress buffer layer 220 and a first dielectric layer 210 respectively, and the sidewalls of the isolation dielectric layer 250, the second dielectric layer 230, the stress buffer layer 220 and the first dielectric layer 210 close to the contact pad 110 are used to surround the opening 200a. The etching process may be dry etching or wet etching.

[0092] In this embodiment, after etching to the first dielectric material layer using the polyimide protection layer 240 as a mask, the top metal diffusion barrier layer 113 of the exposed contact pad 110 is further etched to further expose the metal material layer 112 of the contact pad 110 .

[0093] Furthermore, after the etching process is performed, the polyimide protective layer 240 is retained to form the passivation layer 200. Specifically, the first dielectric layer 210 and the second dielectric layer 230 form an insulating dielectric layer, and together with the stress buffer layer 220, the isolation dielectric layer 250 and the polyimide protective layer 240, form the passivation layer 200.

[0094] Embodiment 4

[0095] Figure 5 FIG6a is a schematic diagram of a process of forming a semiconductor structure in a fourth embodiment of the present invention, FIG6a- Figure 6c It is a structural schematic diagram of the method for forming a semiconductor structure in the fourth embodiment of the present invention during its preparation process.

[0096] The difference from the third embodiment is that in step S200 of the third embodiment, the side walls of the first dielectric layer, the stress buffer layer and the second dielectric layer of the formed passivation layer are all exposed in the opening; while in step S200' of the present embodiment, the formed passivation layer can have a stress buffer layer that further covers the side wall of the first dielectric layer close to the opening, so that the stress buffer layer can be used to block the intrusion of external water vapor from the side wall of the opening. Therefore, only step S200 of the present embodiment is described in detail below.

[0097] In step S200 ′, the method for forming the passivation layer specifically includes the following steps.

[0098] Step S210', for details, refer to Figure 6aAs shown, a first dielectric layer 210 is formed on the substrate 100 , and a groove 211 is formed in the first dielectric layer 210 to expose at least a portion of the contact pad 110 .

[0099] Step S220', for details, refer to Figure 6b As shown, a buffer material layer 220 a is formed on the substrate 100 , and the buffer material layer 220 a covers the first dielectric layer 210 and the sidewall of the groove. Meanwhile, the buffer material layer 220 a further extends to cover the contact pad 110 .

[0100] Step S230', continue to refer to Figure 6b As shown, a second dielectric material layer 230a is formed on the buffer material layer 220a, and a polyimide protective layer 240 is formed on the buffer material layer 220a, the polyimide protective layer 240 also covers the portion of the buffer material layer 220a covering the side wall of the groove, and a through opening 241 is formed in the polyimide protective layer 240, and the through opening 241 is located above the contact pad 110.

[0101] It can be considered that the opening size of the through hole 241 is smaller than the opening size of the groove, so as to ensure that the projection of the polyimide protective layer 240 in the height direction can correspondingly cover the portion of the buffer material layer 220a covering the side wall of the groove.

[0102] In an optional solution, an isolation dielectric material layer 250a may be formed on the second dielectric material layer 230a, and a polyimide protection layer 240 may be formed on the isolation dielectric material layer 250a.

[0103] Step S240', for details, refer to Figure 6c As shown, the etching process is performed using the polyimide protective layer 240 as a mask to sequentially etch the second dielectric material layer and the buffer material layer to respectively form a second dielectric layer 230 and a stress buffer layer 220. In this embodiment, the etching process also etches the isolation dielectric material layer to form an isolation dielectric layer 250.

[0104] Furthermore, in this embodiment, the sidewall of the second dielectric layer 230 close to the contact pad 110 is connected to the contact pad 110, and the sidewall of the second dielectric layer 230 close to the contact pad 110 is used to surround the opening 200a, so as to expose the contact pad 110 through the opening 200a. Similar to the third embodiment, after the contact pad 110 is exposed, part of the top metal diffusion barrier layer of the contact pad can also be removed.

[0105] At this point, the first dielectric layer 210 , the second dielectric layer 230 , the stress buffer layer 220 , the isolation dielectric layer 250 and the polyimide protection layer 240 may be used together to form the passivation layer 200 , thereby forming the semiconductor structure as described above.

[0106] In summary, in the semiconductor structure provided by the present invention, a stress buffer layer is inserted into the isolation dielectric layer to relieve the stress of the isolation dielectric layer by using the directional stress of the stress buffer layer, thereby avoiding the problem of warping of the substrate under the stress of the stress buffer layer. In addition, the stress buffer layer can also be used as a barrier layer. On the one hand, when the passivation layer pattern of the semiconductor structure is defined by using polyimide material, the residual water vapor under the stress buffer layer can be blocked from diffusing into the polyimide coating, thereby avoiding the problem of abnormal pattern caused by the polyimide coating due to water absorption and expansion; on the other hand, after the preparation of the semiconductor structure is completed, the stress buffer layer can also be used to block the intrusion of water vapor in the external environment, thereby preventing the film layer under the stress buffer layer from being eroded by water vapor.

[0107] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0108] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure includes a substrate and a passivation layer formed on the substrate, the passivation layer includes an insulating dielectric layer and a stress buffer layer, the stress buffer layer is interspersed in the insulating dielectric layer along the direction of the substrate surface, and the stress of the stress buffer layer is opposite to the stress of the insulating dielectric layer, the stress buffer layer presents an uneven morphology along the substrate surface, and the thickness of the insulating dielectric layer is greater than the thickness of the stress buffer layer.

2. The semiconductor structure according to claim 1, wherein: A contact pad is also formed on the substrate, and an opening is formed in the passivation layer. The passivation layer covers the substrate and exposes at least a portion of the contact pad through the opening.

3. The semiconductor structure according to claim 2, wherein: The portion of the insulating dielectric layer located below the stress buffer layer constitutes a first dielectric layer, and the portion of the insulating dielectric layer located above the stress buffer layer constitutes a second dielectric layer; wherein the side walls of the first dielectric layer, the stress buffer layer and the second dielectric layer close to the contact pad are all exposed in the opening to jointly constitute the side walls of the opening.

4. The semiconductor structure according to claim 2, characterized in that The portion of the insulating dielectric layer located below the stress buffer layer constitutes a first dielectric layer, and the portion of the insulating dielectric layer located above the stress buffer layer constitutes a second dielectric layer; wherein the stress buffer layer is formed on the first dielectric layer and also covers the side wall of the first dielectric layer close to the contact pad, so that the stress buffer layer is connected to the contact pad.

5. The semiconductor structure according to claim 2, wherein: An interconnection structure is also formed in the substrate. The top interconnection layer of the interconnection structure protrudes from the surface of the substrate and is located in the same structural layer as the contact pad. The passivation layer covers the interconnection structure.

6. The semiconductor structure according to claim 1, wherein: The thickness of the stress buffer layer is between 10 nm and 120 nm.

7. The semiconductor structure according to any one of claims 1 to 6, characterized in that: The passivation layer further includes a polyimide protection layer, and the polyimide protection layer covers the insulating dielectric layer.

8. The semiconductor structure according to claim 7, wherein: The passivation layer further includes an isolation dielectric layer, and the isolation dielectric layer is located between the insulating dielectric layer and the polyimide protection layer.

9. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; as well as, A passivation layer is formed on the substrate, the passivation layer includes an insulating dielectric layer and a stress buffer layer, the thickness of the insulating dielectric layer is greater than the thickness of the stress buffer layer; the stress buffer layer is interspersed in the insulating dielectric layer along the direction of the substrate surface, the stress buffer layer presents an uneven morphology along the substrate surface, and the stress of the stress buffer layer is opposite to the stress of the insulating dielectric layer.

10. The semiconductor structure according to claim 9, wherein: A contact pad is also formed on the substrate, and an opening is formed in the passivation layer. The passivation layer covers the substrate and exposes at least a portion of the contact pad through the opening.

11. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the passivation layer comprises: sequentially forming a first dielectric material layer, a buffer material layer, and a second dielectric material layer on the substrate; forming a polyimide protection layer on the second dielectric material layer, wherein a mask opening is formed in the polyimide protection layer, and the mask opening is located above the contact pad; and, An etching process is performed using the polyimide protective layer as a mask to sequentially etch the second dielectric material layer, the buffer material layer and the first dielectric material layer to respectively form a second dielectric layer, a stress buffer layer and a first dielectric layer, and the second dielectric layer, the stress buffer layer and the first dielectric layer are used to surround the opening near the side wall of the contact pad, and the first dielectric layer and the second dielectric layer constitute the insulating dielectric layer, and the polyimide layer is retained to jointly constitute the passivation layer.

12. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming the passivation layer comprises: forming a first dielectric layer on the substrate, wherein a groove is formed in the first dielectric layer to expose at least a portion of the contact pad; forming a buffer material layer on the substrate, wherein the buffer material layer covers the first dielectric layer and covers the sidewall of the groove; forming a second dielectric material layer on the buffer material layer, and forming a polyimide protective layer on the buffer material layer, wherein the polyimide protective layer also covers a portion of the buffer material layer that covers the sidewall of the groove, and a through hole is formed in the polyimide protective layer, wherein the through hole is located above the contact pad; and, An etching process is performed using the polyimide protective layer as a mask to sequentially etch the second dielectric material layer and the buffer material layer to respectively form a second dielectric layer and a stress buffer layer, wherein the side wall of the second dielectric layer close to the contact pad is connected to the contact pad, and the side wall of the second dielectric layer close to the contact pad is used to surround the opening, and the first dielectric layer and the second dielectric layer constitute the insulating dielectric layer, and the polyimide layer is retained to jointly constitute the passivation layer.

13. The semiconductor structure according to claim 11 or 12, characterized in that: Before forming the polyimide protective layer, the method further includes forming an isolation dielectric material layer on the second dielectric material layer; and during the etching process, the isolation dielectric material layer is further etched to form an isolation dielectric layer between the second dielectric layer and the polyimide protective layer.

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