Switching Converter with Output Current Estimator Circuit

Abstract

The present disclosure relates to a switching converter having an output current estimator circuit. A system (100) includes a switching converter circuit (102) and a monitoring circuit (130) coupled to the switching converter circuit (102). The monitoring circuit (130) includes a current estimation circuit (132) configured to estimate an output current of the switching converter circuit (102). The monitoring circuit (132) further includes a comparison circuit (134) configured to compare the estimated average output current with a threshold, wherein the comparison circuit (134) is configured to output an alarm signal in response to the estimated output current being greater than the threshold.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application No. 62 / 736,583, filed Sep. 26, 2018, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to circuits, and more particularly, to a switching converter having an output current estimator circuit. Background Art

[0004] Power supplies and power converters are used in various electronic systems. Electric power is typically transmitted long distances as an alternating current (AC) signal. The AC signal is divided and metered as needed for individual commercial or residential locations and is often converted to direct current (DC) for individual electronic devices or components. Modern electronic systems often employ devices or components designed to operate using different DC voltages. Thus, such systems require different DC-DC converters or DC-DC converters that support a wide range of output voltages.

[0005] There are many different DC-DC converter topologies. The available topologies differ in the components used, the amount of power processed, the input voltage, the output voltage, the efficiency, the reliability, the size, and / or other characteristics. One example DC-DC converter topology is a single-input multi-output (SIMO) converter that provides multiple outputs by charging a single inductor and selectively discharging it to different nodes. In some SIMO converter scenarios, low efficiency and output oscillation may occur due to the components used and control issues. Summary of the Invention

[0006] According to at least one example of the present disclosure, a system includes a switching converter circuit and a monitoring circuit coupled to the switching converter circuit. The monitoring circuit includes a current estimation circuit configured to estimate an output current of the switching converter circuit. The monitoring circuit also includes a comparison circuit configured to compare the estimated average output current with a threshold, wherein the comparison circuit is configured to output an alarm signal in response to the estimated output current being greater than the threshold.

[0007] According to at least one example of the present disclosure, a converter circuit includes a first switch coupled between a first inductor node and a voltage supply node. The converter circuit further includes a second switch coupled between the first inductor node and a negative power output node. The converter circuit further includes a third switch coupled between a second inductor node and a positive power output node. The converter further includes a fourth switch coupled between the second inductor node and a ground node. The converter circuit further includes a controller coupled to the first, second, third, and fourth switches. The converter circuit further includes a monitoring circuit coupled to at least one of the negative power output node and the positive power output node, wherein the monitoring circuit includes a current estimation circuit and a comparison circuit coupled to the current estimation circuit.

[0008] According to at least one example of the present disclosure, a converter device includes a first switch coupled between a first inductor node and a voltage supply node. The converter device further includes a second switch coupled between the first inductor node and a negative power output node. The converter device further includes a third switch coupled between a second inductor node and a positive power output node. The converter device further includes a fourth switch coupled between the second inductor node and a ground node. The converter device further includes a monitoring circuit coupled to at least one of the negative power output node and the positive power output node. The monitoring circuit is configured to estimate an output current and provide an alarm signal in response to the estimated output current being greater than a threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To describe various examples in detail, reference is now made to the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing a switched converter system according to various examples;

[0011] Figure 2 is a set of schematic diagrams showing a boost iteration scenario according to various examples;

[0012] Figures 3 to 5 is a block diagram showing a current monitoring circuit according to various examples;

[0013] Figure 6 and 7 is a block diagram showing a current monitoring circuit according to various examples;

[0014] Figure 8 is a schematic diagram of a part of a current monitoring circuit according to various examples; and

[0015] Figure 9 is a timing diagram showing a current waveform and an estimated current waveform over time according to various examples. Detailed Implementation Modes

[0016] This disclosure relates to a switched - converter topology for a current monitor circuit, which is configured to estimate the output current of a switched converter. The estimated output current is used, for example, to detect an over - current condition (e.g., the current is above a threshold for a predetermined interval). In some examples, the current monitor circuit includes a switch "on" (conducting) detection stage, a current estimation stage, and a comparison stage. The conduction detection stage detects a high - side switch "on" condition or a low - side switch "on" condition. The current estimation stage provides a scaled estimate of the current associated with the detected switch "on" condition. In some examples, an integration stage is used to integrate the estimated current over a time interval. The comparison stage compares the current estimate from the current estimation stage or the integration stage with a reference value. If the current estimate is greater than the reference value, the comparison stage outputs an over - current signal or alarm. If the current estimate is not greater than the reference value, the comparison stage does not output an over - current signal or alarm. Alternatively, the comparison stage can output an under - current signal in response to the current estimate being equal to or less than the reference value. In some examples, the comparison stage avoids outputting a signal in response to the current estimate being equal to or less than the reference value (i.e., the comparison stage only outputs a signal in response to an over - current condition).

[0017] In some examples, the switched converter has a single - input multiple - output (SIMO) converter topology. An example SIMO converter includes an inductor, a first switch between the first end of the inductor and a power supply node, a second switch between the first end of the inductor and a negative power output node, a third switch coupled between the second end of the inductor and a positive power output node, and a fourth switch coupled between the second end of the inductor and a ground node. The SIMO converter also includes a controller coupled to the first, second, third, and fourth switches, where the controller instructs the operation of the first, second, third, and fourth switches to transition from a quiescent state to at least one boost iteration and then return to the quiescent state. In some examples, each boost iteration involves performing an inductor charge mode, followed by a positive or negative boost mode. As needed, multiple boost iterations are performed before transitioning back to the quiescent state. In some examples, the current monitor circuit is used to detect and respond to over - current conditions in the SIMO converter, where the detection occurs during a switch "on" or forward - biased diode condition associated with one or more boost iterations. In other examples, the current monitor circuit is used to detect and respond to over - current conditions in another switched converter during a switch "on" or forward - biased diode condition. For better understanding, the following figures are used to describe various switched - converter options and current - monitor - circuit options.

[0018] Figure 1 is a block diagram showing a switched - converter system 100 according to various examples. In Figure 1In this case, system 100 represents a consumer product, an integrated circuit or chip, a printed circuit board (PCB) with integrated circuits and / or discrete components, and / or another electrical device. As shown, system 100 includes a SIMO converter circuit 102 coupled to a controller 104. System 100 also includes a sensing circuit 108 coupled to the SIMO converter circuit 102 and the controller 104. System 100 also includes a first load 126 coupled to the positive power output node 116 of the SIMO converter circuit 102. System 100 also includes a second load 128 coupled to the negative power output node 114 of the SIMO converter circuit 102.

[0019] In Figure 1 an example, the SIMO converter circuit 102 includes a first switch (S1) coupled between a power supply (VIN) node 112 and a first inductor node (labeled "LY") 122. The SIMO converter circuit 102 also includes a second switch (S2) coupled between the first inductor node 122 and the negative power output node 114. The SIMO converter circuit 102 also includes a third switch (S3) coupled between a second inductor node (labeled "LX") 124 and the positive power output node 116. The SIMO converter circuit 102 also includes a fourth switch (S4) coupled between the second inductor node 124 and a ground node 118.

[0020] In Figure 1 this case, an inductor 120 is coupled between the first inductor node 122 and the second inductor node 124. In some examples, the inductor 120 is a discrete component added to the SIMO converter circuit 102 by coupling the respective terminals of the inductor 120 to the first inductor node 122 and the second inductor node 124. In contrast, other components of the SIMO converter circuit 102 can be part of an integrated circuit. In some examples, the integrated circuit also includes the controller 102 and the sensing circuit 108. In other examples, the controller 102 and / or the sensing circuit 108 are part of an integrated circuit separate from the SIMO converter circuit 102. Additionally, in some examples, the first load 126 and the second load 128 are separate components or circuits relative to the SIMO converter circuit 102, the controller 104, and the sensing circuit 108.

[0021] In Figure 1In an example, the controller 104 supports various modes of the SIMO converter circuit 102 and at least one quiescent state. More specifically, the controller 104 is configured to provide an inductor charging mode, a positive boost mode, a negative boost mode, and at least one quiescent state. For the inductor charging mode, the controller 104 is configured to close S1 and S4 and open S2 and S3. For the positive boost mode, the controller 104 is configured to close S1 and S3 and open S2 and S4. For the negative boost mode, the controller 104 is configured to close S2 and S4 and open S1 and S3. In one example quiescent state, the controller 104 is configured to close S1 and open S2, S3, and S4. In another example quiescent state, the controller 104 is configured to close S4 and open S1, S2, and S3.

[0022] In some examples, the controller 104 includes an asynchronous state machine that is configured to adjust the control signals (CS1 to CS4) of S1 to S4 of the SIMO converter circuit 102 to implement the various modes or quiescent states described herein without a clock signal. More specifically, in Figure 1 an example, the controller 104 receives various input signals from the sensing circuit 108 and adjusts the operation of S1 to S4 to implement the various modes or quiescent states described herein.

[0023] In some examples, the controller 104 executes a state machine loop that begins at one of the first or second quiescent states. The state machine loop also includes performing at least one boost iteration that includes an inductor charging mode and a positive or negative boost mode. The state machine loop also includes returning to one of the first or second quiescent states. In some examples, the controller 104 includes arbitration logic (see, for example, Figure 2 the arbitration logic 240 in) that is configured to determine whether to use the positive boost mode or the negative boost mode in a given boost iteration. In some examples, the arbitration logic uses sensing signals from the sensing circuit 108 to determine whether to use the positive boost mode or the negative boost mode in a given boost iteration.

[0024] Once a boost iteration is triggered, the controller 104 performs the inductor charging mode by closing S1 and S4 while S2 and S3 are open. In some examples, the inductor charging mode continues until the inductor charge is higher than a programmable threshold. After the inductor charging mode is complete, the controller 104 transitions to the positive boost mode or the negative boost mode based on the arbitration result (e.g., which output supply voltage is farthest from the corresponding target and / or other criteria). After the positive or negative boost mode is complete, the controller 104 transitions to another boost iteration or one of the quiescent states based on the input signals to the controller 104.

[0025] In Figure 1In an example, system 100 includes a current monitor circuit 130 coupled to LY node 122 and / or LX node 124. As shown, current monitor circuit 130 includes an "on" detection circuit 131, a current estimation circuit 132, and a comparison circuit 134. In operation, the "on" detection circuit 131 detects the switch "on" state. In some examples, when the SIMO converter circuit 102 transitions from the inductor charging mode to the negative boost mode, the "on" detection circuit 131 detects that S2 is closed. On the other hand, when the SIMO converter circuit 102 transitions from the inductor charging mode to the positive boost mode, the "on" detection circuit 131 detects that S3 is closed.

[0026] The current estimation circuit 132 determines an estimated value of the current to the positive power supply output node 116 during the positive boost mode and / or an estimated value of the current to the negative power supply output node 114 during the negative boost mode. In some examples, the estimated current corresponds to a voltage value. As shown, the current monitor circuit 132 also includes a comparison circuit 134. The comparison circuit 134 compares the current estimate 133 output from the current estimation circuit 132 with a programmable threshold 138. If the current estimate 133 is greater than the programmable threshold 138, the comparison circuit 134 outputs an overcurrent signal or alarm signal 136. In other examples, the comparator 134 outputs an undercurrent signal in response to the current estimate 133 being equal to or less than the programmable threshold 138. In some examples, the comparator 134 avoids outputting a signal in response to the current estimate being equal to or less than a reference value (i.e., the comparator only outputs a signal in response to an overcurrent condition).

[0027] Figure 2 is a set of schematic diagrams showing a boost iteration scenario 200 according to various examples. In scenario 200, the boost iteration is initiated by transitioning from a stationary state (not shown) to the inductor charging mode arrangement 210 of the SIMO converter circuit 102. As Figure 2 shown, the inductor charging mode arrangement 210 corresponds to S1 and S4 closed and S2 and S3 open. After the inductor charging mode is completed, the arbitration logic 240 determines whether a positive boost or a negative boost will be performed.

[0028] In scenario 200, positive boosting is performed by transitioning from the inductor charging mode arrangement 210 of the SIMO converter circuit 102 to the positive boost arrangement 220 of the SIMO converter circuit 102. As shown, the positive boost mode arrangement 220 corresponds to S1 and S3 being closed and S2 and S4 being open. After the positive boost mode is completed, the arbitration logic 240 determines whether another boost iteration is needed. If so, scenario 200 returns to the inductor charging mode arrangement 210 of the SIMO converter circuit 102, and then another positive or negative boost follows. Otherwise, if another boost iteration is not needed, the boost iteration scenario 200 is completed and the SIMO converter circuit 102 is placed in the quiescent state as described herein. In some instances, the use of different quiescent states depends on the enable signals (e.g., VPOS_enabled and / or S1_IDLE) as described herein.

[0029] In scenario 200, negative boosting is performed by transitioning from the inductor charging mode arrangement 210 of the SIMO converter circuit 102 to the negative boost arrangement 230 of the SIMO converter circuit 102. As shown, the negative boost mode arrangement 230 corresponds to S2 and S4 being closed and S1 and S3 being open. After the negative boost mode is completed, the arbitration logic 240 determines whether another boost iteration is needed. If so, scenario 200 returns to the inductor charging mode arrangement 210 of the SIMO converter circuit 102, and then another positive or negative boost is performed. Otherwise, if another boost iteration is not needed, the boost iteration scenario 200 is completed and the SIMO converter circuit 102 is placed in the quiescent state.

[0030] In some scenarios, the current monitor circuit (e.g., Figure 1 the current monitor circuit 130) performs its operation during the positive boost mode (when the SIMO converter circuit 102 is in the positive boost arrangement 220). In other scenarios, the current monitor circuit (e.g., Figure 1 the current monitor circuit 130) performs its operation during the negative boost mode (when the SIMO converter circuit 102 is in the negative boost arrangement 220).

[0031] Figures 3 to 5 is a block diagram showing a current monitoring circuit according to various examples. In Figure 3 a current monitoring circuit 300 for low-side monitoring (e.g., negative boost mode monitoring) is presented. As shown, the current monitoring circuit 300 includes a power stage 302, a low-side "on" detection stage 312, an integration stage 322, and a comparison stage 332. Figure 3 The power stage 302 of Figure 3is presented as using a power supply voltage node 112, an open S1 (where S1 corresponds to a transistor having a diode on its current terminals), a LY node 122, an inductor 120, a ground node 118, a closed S2 (where S2 corresponds to a diode (D1) when closed), a closed S4, and a negative power supply output node 114. There may also be other components described for the SIMO converter circuit 102 (e.g., S3, a LX node 124, and a positive power supply output node 116), but are not presented in Figure 3 the negative boost arrangement 230A of

[0032] In Figure 3 the example of, the low-side "on" detection stage 312 includes a detection circuit 314 coupled to the LY node 122. As shown, the detection circuit 314 includes a Schmitt trigger 316. During the inductor charging mode, S1 is on and the current flowing through the inductor 120 (from the VIN node 112 to the ground node 118) begins to increase. When sufficient current is established across the inductor 120, S1 is turned off, causing the current to divert from the transistor of S1 to the diode D1. When this occurs, the voltage at the LY node 122 rapidly drops below the voltage at the VNEG node 114, which turns on D1. Due to the rapid drop in the voltage at the LY node 122, a capacitor (e.g., Figure 7 the capacitor 704 in Figure 7 causes the input of the Schmitt trigger 316 to switch. As the discharge cycle ends and the inductor current reverses, the voltage at the LY node 122 increases at a slower rate above the voltage at the VNEG node 114. When this occurs, the capacitor (e.g., Figure 7 the capacitor 704 in applies a charge to the input of the Schmitt trigger 316 and switches its state even immediately before the voltage at the LY node 122 has increased all the way to the input supply voltage (VIN) provided at the node 112. In some examples, the low-side "on" detection stage 312 can detect the switch "on" time with a very short duration (e.g., 20 to 100 ns).

[0033] As shown, the integrator stage 322 includes an integrating circuit 324 that has a peak current value (e.g., the same value as the inductor charging phase threshold) and a current threshold (Ith_sel). In some instances, whenever the low-side diode / switch (S2) is turned on, the integrating circuit 324 pushes a segmented form of the estimated peak current into C1. In some instances, the peak inductor charging current can be programmed using a signal (Ipk_sel). Additionally, the integrating circuit 324 calculates the average output current minus the threshold current. In this case, when the average output current exceeds the threshold current, the voltage of C1 increases. In another instance, the integrating circuit 324 calculates the average output current to the node voltage by charging C1 in parallel with an optional resistor. In some instances, the integrating circuit 324 uses a known fraction of the peak inductor current setting (e.g., α = 1 / 10000). Since this current is programmable, a scaling factor is applied to match the programmed value. This arrangement effectively estimates the average output current of the converter by leveraging the peak inductor current setting and the S2 “on” time information. The reason for estimating the current instead of measuring it is to avoid a very high bandwidth, high quiescent current (Iq), and a large area sense amplifier to accurately measure the current.

[0034] The comparator stage 332 includes a comparison circuit 334 that has a comparator 336. The inputs to the comparator 336 are the C1 voltage from the integrator stage 322 and a reference voltage (VREF). In response to the output of the integrator being higher than VREF, the comparison circuit 334 outputs an overcurrent signal (IAVG_TH_EXCEEDED). In some instances, as Figure 3 shown, the overcurrent signal is an indication that the average current estimate provided by the integrator stage 322 exceeds the threshold. In some instances, the comparator 336 is used to detect when the current exceeds a selected average current threshold, where the detection and filtering time can be selected by the value of C1.

[0035] In Figure 4 a, a current monitoring circuit 400 for high-side monitoring (e.g., positive boost mode monitoring) is presented. As shown, the current monitoring circuit 400 includes a power stage 402, a high-side “on” detection stage 412, an integrator stage 422, and a comparator stage 432. Figure 4 The power stage 402 of Figure 4is presented as using a power supply voltage node 112, a closed S1 (or replaced by a short circuit) (e.g., S1 corresponds to a transistor having a diode on its current terminals), an LX node 124, an inductor 120, a ground node 118, a closed S3 (in the form of a transistor having a diode on its current terminals), an open S4 (in the form of a transistor having a diode on its current terminals). There may also be other components described for the SIMO converter circuit 102 (e.g., S2, an LY node 122, and a negative power supply output node 114), but are not presented in Figure 4 the positive boost arrangement 220A of

[0036] In Figure 4 the example of, the high-side "on" detection stage 412 includes a detection circuit 414 coupled to the LX node 124. As shown, the detection circuit 414 includes a Schmitt trigger 416. During the inductor charging mode, S4 is on and the current flowing through the inductor 120 (from the VIN node 112 to the ground node 118) begins to increase. When sufficient current is established across the inductor 120, S4 is turned off and S3 is closed, causing the current to flow to the positive power supply output node 116. When this occurs, the inductor 120 discharges and the voltage at the LX node 124 rapidly increases. Since the voltage at the LX node 124 increases rapidly, Figure 4 C2 in Figure 7 causes the input of the Schmitt trigger 416 to switch. As the discharge cycle ends, the inductor current reverses and the voltage at the LX node 124 drops at a slower rate. When this occurs, a capacitor (e.g., Figure 7 the capacitor 704 in

[0037] ) applies a charge to the input of the Schmitt trigger 416 and immediately switches its state. In some examples, the high-side "on" detection stage 412 can detect the switch "on" time with a very short duration (e.g., 20 to 100 ns).As shown, the integration stage 422 includes an integration circuit 424 that has a peak current value (e.g., the same value as the inductor charging phase threshold) and a current threshold (Ith_sel). In some instances, whenever the high-side diode (a part of S1) turns on, the integration circuit 424 pushes the estimated peak current in a segmented form into C2. In some instances, the peak current can be programmed using a signal (Ipk_sel). Additionally, the integration circuit 424 calculates the average output current minus the threshold current. In this case, when the average output current exceeds the threshold current, the voltage of C2 increases. In another instance, the integration circuit 424 calculates the average output current to the node voltage by charging C2 in parallel with an optional resistor. In some instances, the integration circuit 424 uses a known fraction of the estimated peak inductor current (e.g., α = 1 / 10000). Since this current is programmable, a scaling factor is applied to match the programmed value. The reason for estimating the current instead of measuring it is to avoid a very high bandwidth, high quiescent current (Iq), and a large-area sense amplifier to accurately measure the current.

[0038] The comparator stage 432 includes a comparison circuit 434 having a comparator 436. The inputs to the comparator 436 are the current estimate output from the integration stage 422 and a reference voltage (VREF). In response to the current estimate being higher than VREF, the comparison circuit 434 outputs an over-current signal (IAVG_TH_EXCEEDED). In some instances, as Figure 4 shown, the over-current signal is an indication that the average current estimate provided by the integration stage 422 exceeds the threshold. In some instances, the comparator 436 is used to detect when the current exceeds a selected average current threshold, where the detection and filtering time can be selected by the value of C2.

[0039] In Figure 5 shown, a current monitoring circuit 500 for high-side monitoring or low-side monitoring (e.g., positive boost mode monitoring and negative boost mode monitoring) is presented. As shown, the current monitoring circuit 500 includes a power stage 502, a "turn-on" detection stage 512, an integration stage 522, and a comparator stage 532. Figure 5 The power stage 502 of includes SIMO converter circuit components. In the positive boost mode, S1 and S3 are closed while S2 and S4 are open. In the negative boost mode, S2 and S4 are closed while S1 and S3 are open. An inductor 120, an LY node 122, an LX node 124, a power supply node 112, D1, a negative output power supply node 114, a positive output power supply node 116, and a ground node 118 are also presented in the power stage 502. In other instances, the components included in the power stage 502 can vary.

[0040] In Figure 5In an example, the "ON" detection stage 512 includes a first detection circuit 514 coupled to the LY node 122. As shown, the first detection circuit 514 includes a Schmitt trigger 515. The first detection circuit 514 operates in a manner substantially the same as the detection circuit 314 described for Figure 3 The "ON" detection stage 512 also includes a second detection circuit 516 coupled to the LX node 122. As shown, the second detection circuit 516 includes a Schmitt trigger 518. The second detection circuit 514 operates in a manner substantially the same as the detection circuit 414 described for Figure 4

[0041] As shown, the integration stage 522 includes an integration circuit 524 having a peak current value and a current threshold (Ith_sel). In some examples, the integration circuit 524 pushes the estimated peak current in a segmented form into C1 or C2. In some examples, the peak current can be programmed using a signal (Ipk_sel).

[0042] The comparison stage 532 includes a comparison circuit 534 having a first comparator 536 and a second comparator 538. The input of the first comparator 536 (when used) is the estimated current value output from the integration stage 522 to C2 and a first reference voltage (VREF1). In response to the estimated current value from the integration stage 522 being higher than VREF1, the comparison circuit 534 outputs an overcurrent signal (IAVG_TH_EXCEEDED). The input of the second comparator 538 (when used) is the estimated current value output from the integration stage 522 to C1 and a second reference voltage (VREF2). In response to the estimated current value from the integration stage 522 being higher than VREF2, the comparison circuit 534 outputs IAVG_TH_EXCEEDED. In some examples, as Figure 5 shown, the overcurrent signal is an indication that the average current estimate provided by the integration stage 522 exceeds a threshold.

[0043] Figure 6 and 7 are schematic diagrams showing current monitoring circuits 600 and 700 according to various examples. In Figure 6 , the current monitoring circuit 600 includes a detector circuit 602, an integrator circuit 604, and a comparator 606. More specifically, the integrator circuit 604 includes a first current digital-to-analog converter (DAC) 612, a second current DAC 608, and a reset device 610. When the peak current changes, the first current DAC 612 modulates a copy of the current. The second current DAC 608 sets an average current target threshold. The reset device 610 clears the integrator circuit 604.

[0044] In Figure 7 ​In FIG. 7, the current monitoring circuit 700 includes a transistor 702, a capacitor 704, and a Schmitt trigger 710. The current monitoring circuit 700 also includes circuits 706 and 708. In the current monitoring circuit 700, the transistor 702 and the capacitor 704 are part of a "turn-on" detection circuit (see, for example, Figure 3 the "turn-on" detection circuit 314 in FIG. 3), where the input of the detector circuit is the LY node 122. Meanwhile, the circuit 706 is a "fine-tuning" circuit configured to align the rising and falling edge delays. In some instances, the characteristic delay differences are found by characterization, and the best-fit numbers are used for all parts. Additionally, the circuit 708 is a level converter configured to convert a signal to the integrator voltage domain.

[0045] The switch S1 (see, for example, Figure 2 ) is turned on for the inductor charging mode, and the inductor current flowing from the power supply node (e.g., Figure 1 the power supply node 112 in FIG. 3) to the ground node (e.g., Figure 1 the ground node 118 in FIG. 3) starts to increase. When sufficient current is established in the inductor, S1 is turned off, which causes the current to flow from the transistor of S1 to the parasitic capacitance at the LY node 122. When this occurs, the voltage of the LY node 122 rapidly drops below the voltage of the negative power supply output node (e.g., Figure 1 the negative power supply output node 114 in FIG. 3), and turns on the diode of S2 (see, for example, Figure 3 D1 in FIG. 3). Since the voltage of the LY node 122 drops rapidly, the capacitor 704 below causes the input of the Schmitt trigger 710 to switch. In the instance of Figure 7 FIG. 4, the low-voltage NMOS device adjacent to the Schmitt trigger 710 keeps the input of the Schmitt trigger 710 much lower than the ground. As the discharge cycle ends and the inductor current reverses, the LY node 122 increases at a slower rate to a voltage higher than the voltage at the negative power supply output node 114. When this occurs, the capacitor 704 applies charge to the input of the Schmitt trigger 710, causing its input voltage to increase from close to 0V to Vin, and immediately switching its state even before the voltage at the LY node 122 has increased all the way to the voltage at the power supply node 112.

[0046] Figure 8FIG. 800 is a schematic diagram of a part of a current monitoring circuit 802 according to various examples. As shown, the current monitoring circuit 802 includes an integrating circuit 803 and a comparator 804. More specifically, the integrating circuit 803 includes a plurality of transistors Q1 to Q6, each transistor having a first current terminal, a second current terminal, and a control terminal. The first current terminals of Q1 and Q2 are coupled to a power supply node 806. The control terminals of Q1 and Q2 are coupled to each other. The second current terminal of Q1 is coupled to the control terminal of Q1 and to a first current source 807A, where the first current source 807A is located between the second current terminal of Q1 and a ground node 808. In Figure 8 an example, the current through Q2 corresponds to the peak current setting divided by 20000 (I_peak_setting / 20000). In different examples, the peak current setting and / or the scaling factor of the peak current setting may vary. The second current terminal of Q2 is coupled to the first current terminals of Q3 and Q4. The control terminal of Q3 is gated by a clock signal (CS2), and the control terminal of Q4 is gated by another clock signal (CS2_Z, where CS2_Z is the inverse of CS2). In some examples, CS2 also gates S2 (e.g., a switch to Figure 1 the negative power supply output node 114 in Figure 3 ). In other examples, a detector (e.g.,

[0047] the detection circuit 314 in Figure 8 ) can be used to drive CS2 and CS2_Z. The second current terminal of Q4 is coupled to the ground node 808. replica_avg ) The second current terminal of Q3 is coupled to the first current terminal of Q6 and to one of the inputs of the comparator 804. In some examples, as Figure 8 shown, the current at the second current terminal of Q3 is the average estimated current (I limit ). As shown, the second current terminal of Q6 is coupled to the ground node 808. At the same time, the control terminal of Q6 is coupled to the control terminal of Q5 and a current source 807B. More specifically, the current source 807B is located between the power supply node 806 and the control terminals of Q5 and Q6. As shown, the control terminal of Q5 is also coupled to the first current terminal of Q5. Finally, the second current terminal of Q5 is coupled to the ground node 808. In limit an example, the current through Q6 is a threshold current (Ith), where Ith = 2*I

[0048] In Figure 8 an example, the second current terminal of Q3 is also coupled to the top plate of a variable capacitor C3. The bottom plate of C3 is coupled to the ground node 808. In Figure 8 , C3 has a value of 50 pF. In operation, I replica_avgThe difference from Ith causes charge to accumulate at C3 to provide a voltage value to comparator 804, where the increased voltage indicates that the average output current exceeds the desired converter output threshold. Another input to comparator 804 is a reference voltage (VREF), which does not need to be precise. The output of comparator 804 is a value I limit_det , where I limit_det corresponds to Figures 3 to 5 IAVG_TH_EXCEEDED in

[0049] Figure 9 is a timing diagram 900 showing the current waveform 912 varying with time and the estimated current waveform 922 according to various examples. As shown, the current waveform 912 includes pulses 914A and 914B, where the average current of the current waveform 912 is I limit 916. In Figure 9 the example of limit I pk = I lim D pk / 2, where I pk is the peak current and D lim is the duty cycle (or the mathematical expression t S2 / (t S2 + t S1,S4 ), where ts2 is the amount of time when only S2 is on). In Figure 9 the example of pk the estimated current waveform 922 has pulses 924A and 924B, where the average current of the estimated current waveform 922 is used as the threshold current, i.e., Ith926. In different examples, selecting a pulse of I pk / 20000 results in Ith = I lim / 20000 * D limit or I limit / 10000. Example values of I limit and Ith are: ILIM = 5 mA; and Ith = 500 nA. Note: In the examples of the current estimator described herein, the estimator assumes an output current having a triangular shape. This is for the case of a switching converter because the inductor behavior follows the equation: V = L * di / dt. For constant V and L, di / dt is constant (e.g., the inductor current decreases linearly). At the same time, the estimated current waveform includes a square because the switch can easily switch a constant current in a circuit implementation.

[0050] In this description, the term "coupled" means a direct or indirect wired or wireless connection. Thus, if a first device is coupled to a second device, that connection may be through a direct connection, or through an indirect connection via other devices and connections. Additionally, in this description, the recitation of "based on" means "at least in part based on". Thus, if X is based on Y, X may depend on Y and any number of other factors.

[0051] Modifications may be made to the described embodiments, and other embodiments are possible within the scope of the claims.

Claims

1. An electronic system, comprising: A switching converter circuit having a power input, a power output, and an inductor terminal; And A monitoring circuit coupled to the inductor terminal of the switching converter circuit, the monitoring circuit comprising: A current estimation circuit configured to estimate an output current at the inductor terminal of the switching converter circuit in response to a voltage at the inductor terminal; and A comparison circuit configured to: compare the estimated output current with a threshold; And output an alarm signal in response to the estimated output current being greater than the threshold.

2. The system according to claim 1, wherein the threshold is adjustable.

3. The system according to claim 2, wherein the threshold can be adjusted between 3 mA and 13 mA.

4. The system according to claim 1, wherein the current estimation circuit includes an integrator.

5. The system according to claim 4, wherein the integrator includes a current digital-to-analog converter (DAC), the DAC being configured to modulate a current replica based on peak current.

6. The system according to claim 5, wherein the current DAC is a first current DAC, and the integrator includes a second current DAC configured to set an average current target threshold.

7. The system according to claim 4, wherein the integrator includes a reset device configured to zero the integrator.

8. The system according to claim 1, wherein the switching converter circuit includes a first switch coupled between the power input and the inductor terminal and a second switch coupled between the inductor terminal and the power output, the current estimation circuit being configured to detect a turn-on time of one of the first switch or the second switch between 20 nanoseconds and 100 nanoseconds.

9. The system according to claim 4, wherein the integrator is configured to apply a scaling factor to the estimated peak inductor current, and the scaling factor is less than 1 / 10000.

10. The system according to claim 1, wherein the power input is coupled to a positive voltage, the power output is a negative power output, and the current estimation circuit is configured to estimate the output current by estimating an average output current at the negative power output.

11. The system according to claim 1, wherein the power input is coupled to ground, the power output is a positive power output, and the current estimation circuit is configured to estimate the output current by estimating an average output current at the positive power output.

12. A converter circuit, comprising: A first switch coupled between a first inductor terminal and a voltage supply terminal; A second switch coupled between the first inductor terminal and a negative power output; A third switch coupled between a second inductor terminal and a positive power output; A fourth switch coupled between the second inductor terminal and a ground terminal; A controller, the controller being coupled to the first switch, the second switch, the third switch, and the fourth switch; and A monitoring circuit, the monitoring circuit being coupled to at least one of the first inductor terminal or the second inductor terminal, the monitoring circuit comprising: A current estimation circuit, the current estimation circuit being configured to estimate an output current at at least one of the first inductor terminal or the second inductor terminal in response to a voltage at at least one of the first inductor terminal or the second inductor terminal; and A comparison circuit, the comparison circuit being coupled to the current estimation circuit.

13. The converter circuit according to claim 12, wherein the current estimation circuit is configured to estimate an output current of the converter circuit, and the comparison circuit is configured to: compare the estimated output current with a threshold; and output an alarm signal in response to the estimated output current being greater than the threshold.

14. The converter circuit according to claim 13, wherein the threshold is adjustable between 3 mA and 13 mA.

15. The converter circuit according to claim 12, wherein the current estimation circuit includes an integrator, and the integrator includes: A first current digital-to-analog converter (DAC), the DAC being configured to modulate a current replica based on a peak current; and A second current DAC, the second current DAC being configured to set an average current target threshold.

16. The converter circuit according to claim 12, wherein the current estimation circuit is configured to detect a high-side switch on-time between 20 nanoseconds and 100 nanoseconds.

17. The converter circuit according to claim 15, wherein the integrator is configured to apply a scaling factor to the estimated peak inductor current, and the scaling factor is less than 1 / 10000.

18. A converter device, comprising: A first switch, the first switch being coupled between a first inductor terminal and a voltage supply terminal; A second switch, the second switch being coupled between the first inductor terminal and a negative power output; A third switch, the third switch being coupled between a second inductor terminal and a positive power output; A fourth switch, the fourth switch being coupled between the second inductor terminal and a ground terminal; and A monitoring circuit, the monitoring circuit being coupled to at least one of the first inductor terminal or the second inductor terminal, wherein the monitoring circuit is configured to estimate an output current at at least one of the first inductor terminal or the second inductor terminal in response to a voltage at at least one of the first inductor terminal or the second inductor terminal and provide an alarm signal in response to the estimated output current being greater than a threshold.

19. The converter device according to claim 18, wherein the monitoring circuit includes: A current estimation circuit, the current estimation circuit being configured to estimate an average output current at the negative power output; and A comparison circuit configured to compare the estimated average output current with the threshold, wherein the comparison circuit is configured to output an alarm signal in response to the estimated average output current being greater than the threshold.

20. The converter device according to claim 18, wherein the monitoring circuit comprises: A current estimation circuit configured to estimate the average output current at the positive power supply output; And A comparison circuit configured to compare the estimated average output current with the threshold, wherein the comparison circuit is configured to output an alarm signal in response to the estimated average output current being greater than the threshold.

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