Semiconductor device and its design, definition method and conductive pattern layout method

Abstract

Some embodiments of the present disclosure disclose methods for designing semiconductor elements, conductive layer patterns, and interconnect layer patterns, the method comprising the following steps: analyzing an initial semiconductor design layout to identify excessive open space between adjacent conductive elements or lines within an interconnect layer pattern; selecting or generating a dummy pattern to fill a portion of the open space; and generating an improved semiconductor design layout that incorporates the dummy pattern into the first interconnect layer pattern to reduce the open space.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to a method for designing a semiconductor device, a method for defining a conductive pattern layout of a semiconductor device design, and a semiconductor device. Background Art

[0002] The semiconductor integrated circuit (IC) industry continues to experience rapid growth, and technological advances in IC materials and design have produced successive generations of ICs, each with smaller geometries and more complex circuits than the previous generation. The complexity of the associated layout, device structure, and manufacturing process used to produce each new generation of ICs has increased accordingly to achieve the designed functional density.

[0003] The performance of advanced patterning and etching processes associated with metal patterning is impacted by density gradient effects (DGE) associated with the particular IC device layout configuration being manufactured. Using dummy conductive patterns (lines or portions of conductive patterns that will not carry signals and / or power in the completed IC device) to account for and adjust the relative positions and spacing of main conductive lines or primary conductive patterns (lines or portions of lines that carry signals and / or power in the completed IC device) mitigates some of the DGE and improves the uniformity and performance of the resulting IC. Summary of the invention

[0004] In some embodiments, a method for designing a semiconductor device includes the following steps: analyzing an initial semiconductor design layout to identify an open space within a first interconnect layer pattern, selecting a first dummy pattern to fill a portion of the open space, and generating a modified semiconductor design layout by incorporating the first dummy pattern into the first interconnect layer pattern.

[0005] In some embodiments, a method for defining a conductive pattern layout for a semiconductor device design includes the following steps: setting a first design rule for an end-to-end spacing requirement for an open area between adjacent first and second conductive elements; identifying a first open area in an initial conductive pattern layout that is outside the first design rule; selecting a first dummy pattern to cover a first portion of the first open area so that the remaining second open area is within the first design rule; and placing the first dummy pattern within the first open area to generate a revised conductive pattern layout.

[0006] In some embodiments, a semiconductor device includes an interconnect pattern. The interconnect pattern includes a plurality of parallel tracks, a first conductor and a second conductor aligned with the first track, and a first dummy pattern. The first conductor and the second conductor are separated by an open space. The first dummy pattern is aligned with the first track and disposed in the open space. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, aspects of some embodiments of the present disclosure will be best understood from the detailed description below. It should be noted that, in accordance with standard practice in the industry, the features are not drawn to scale. In fact, the size of the features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figures 1A to 1E is a top view of an integrated circuit layout cell including a pattern of horizontal parallel conductive lines arranged along five evenly spaced traces and including a series of iterative line-end-extension (LEE) adjustments according to some embodiments;

[0009] FIG. 2A to FIG. 2B is a top view of an integrated circuit layout cell including a pattern of horizontal parallel conductive lines arranged along two evenly spaced traces and including line density adjustment using dummy patterns according to some embodiments;

[0010] Figure 3 is a top view of an integrated circuit layout cell including a pattern of horizontal parallel conductive lines arranged along five evenly spaced traces and including line density adjustment using dummy patterns according to some embodiments;

[0011] FIG. 4A to FIG. 4B is a top view of an integrated circuit layout cell including horizontal conductive lines arranged along a single trace and illustrating line density adjustment using a dummy pattern according to some embodiments;

[0012] FIG. 5A to FIG. 5C is a top view of an integrated circuit layout cell including horizontal conductive lines arranged along a single trace and illustrating line density adjustment using a dummy pattern according to some embodiments;

[0013] Fig. 6A is a top view of an integrated circuit layout cell including horizontal conductive lines arranged along a single trace adjacent to spaced traces and including line density adjustment using a dummy pattern according to some embodiments;

[0014] Figure 6B is a top view of an integrated circuit layout cell including a series of horizontal conductive lines and spaced traces arranged along four parallel traces and including line density adjustment using dummy patterns according to some embodiments;

[0015] Figure 6Cis a top view of an integrated circuit layout cell including a series of horizontal conductive lines arranged along two parallel traces and including line density adjustment using a dummy pattern according to some embodiments;

[0016] Fig.6D is a top view of an integrated circuit layout cell including a series of horizontal conductive lines and spaced traces arranged along three parallel traces and including line density adjustment using dummy patterns according to some embodiments;

[0017] Figure 7 is a flow chart of a method for improving an IC design layout to include dummy patterns according to some embodiments;

[0018] Figure 8 is a block diagram of an integrated circuit manufacturing system and an IC manufacturing process associated therewith according to some embodiments;

[0019] Fig. 9 is a schematic diagram of an electronic process control (EPC) system in operation for IC design layout improvement according to some embodiments.

[0020]

Explanation of symbols

[0021] 100A: IC layout unit / conductive pattern layout

[0022] 100B: IC layout unit / conductive pattern layout

[0023] 100C: IC layout unit / conductive pattern layout

[0024] 100D: IC layout unit / conductive pattern layout

[0025] 100E: IC layout unit / conductive pattern layout

[0026] 102: Conductive elements

[0027] 104: Conductive element

[0028] 106: Conductive pattern

[0029] 108A: Conductive element

[0030] 108B: Conductive element

[0031] 108C: Conductive element

[0032] 108D: Conductive element

[0033] 108E: Conductive element

[0034] 110: Conductive element

[0035] 112: Conductive element

[0036] 114A: Area

[0037] 114B: Area

[0038] 114C: Area

[0039] 114D: Area

[0040] 116A: Interval

[0041] 116B: Interval

[0042] 116C: Interval

[0043] 116D: Interval

[0044] 200A: IC Layout Unit

[0045] 200B: Integrated Circuit Layout Unit

[0046] 202A: Conductive components

[0047] 202B: Conductive components

[0048] 204A: Conductive element

[0049] 204B: Conductive components

[0050] 206: Fake pattern

[0051] 208: Fake pattern

[0052] 300: Integrated Circuit Layout Unit

[0053] 302: Conductive element

[0054] 304: Conductive element

[0055] 306A: Fake pattern

[0056] 310: Track

[0057] 310': Interval track

[0058] 400A: Integrated Circuit Layout Unit

[0059] 400B: Integrated Circuit Layout Unit

[0060] 402A: First conductive element

[0061] 402B: Second conductive element

[0062] 406A: Fake pattern

[0063] 406B: Fake pattern

[0064] 500A: IC Layout Unit

[0065] 500B: Integrated Circuit Layout Unit

[0066] 500C: Integrated Circuit Layout Unit

[0067] 502A: First conductive element

[0068] 502B: Second conductive element

[0069] 506A: Fake pattern

[0070] 506B: dummy pattern

[0071] 506C': dummy pattern

[0072] 506C": dummy pattern

[0073] 600A: Integrated Circuit Layout Unit

[0074] 600B: Integrated Circuit Layout Unit

[0075] 600C: Integrated Circuit Layout Unit

[0076] 602: Conductive element

[0077] 602A: Conductive element

[0078] 602B: Conductive components

[0079] 606: Fake pattern

[0080] 606': Fake pattern

[0081] 606A': dummy pattern

[0082] 606A": dummy pattern

[0083] 606C': dummy pattern

[0084] 606C": dummy pattern

[0085] 606D: dummy pattern

[0086] 610: Track

[0087] 610': Interval track

[0088] 700: Methods

[0089] 702: Steps

[0090] 704: Steps

[0091] 706: Steps

[0092] 708: Steps

[0093] 710: Steps

[0094] 712: Steps

[0095] 714: Steps

[0096] 716: Steps

[0097] 718: Steps

[0098] 720: Steps

[0099] 800: Integrated Circuit (IC) Manufacturing System

[0100] 820: Design Studio

[0101] 822: IC Design Layout

[0102] 830: Masking Room

[0103] 832: Mask Data Preparation

[0104] 844: Mask Manufacturing

[0105] 850: IC fab

[0106] 852: Wafer Manufacturing

[0107] 860: IC components

[0108] 900: Electronic Process Control (EPC) System

[0109] 902: Hardware Processor

[0110] 904: Computer readable storage media

[0111] 906: Computer Program Code

[0112] 908: Process Control Data

[0113] 910: User Interface (UI)

[0114] 912: I / O interface

[0115] 914: Network interface

[0116] 916: Network

[0117] 918: Bus

[0118] EE: Distance

[0119] EE D :distance

[0120] EE i :distance

[0121] FF: Fill DETAILED DESCRIPTION

[0122] The description of the exemplary embodiments is to be read in conjunction with the accompanying drawings, and the accompanying drawings are considered to be part of the entire written description. The following disclosure provides many different embodiments or examples to implement the different features of the subject matter provided. The following describes specific examples of components, values, operations, materials, arrangements or the like to simplify some embodiments of the present disclosure. Of course, these are only examples and are not intended to be restrictive. Other components, values, operations, materials, arrangements or the like are included. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, some embodiments of the present disclosure may repeat component symbols and / or letters in each example. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0123] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0124] In some embodiments, the initial layout of conductive patterns used to fabricate integrated circuit components includes large open areas between functional conductive lines and / or patterns (i.e., dominant conductive lines and / or patterns). In some embodiments, depending on the size, number, and layout, the open areas result in degradation in the patterning and / or etching of the dominant conductive lines. Since the dominant conductive lines are used to implement the designed functions and / or operations of the integrated circuit components fabricated using such layouts, any degradation in the formation of such structures is detrimental to the operation and reliability of the resulting components. According to some embodiments, the possibility of such degradation effects caused by excessive gaps in the conductive patterns is mitigated by adding dummy metal patterns during an automatic placement and routing (APR) process.

[0125] In some embodiments, an initial termination portion of a main conductor is extended (using a track-based fill (TBF) process) under a dummy pattern and / or an adjacent isolated dummy pattern (a dummy pattern that is not in direct electrical contact with the main conductor) that is used to reduce the end-to-end spacing between the main conductor and a second main conductor. In some embodiments, the open space between two main conductors and / or components is reduced by laying out one or more dummy patterns (using a track-based fill (TBF) process). In some embodiments, an array of smaller dummy patterns is used to reduce parasitic capacitance to a level below that associated with a single dummy pattern of similar total length. In some embodiments, dummy patterns selected from a dummy pattern library and / or generated during a routing process in response to layout analysis according to certain formulas and structural criteria reduce design iterations used in some methods to obtain an acceptable IC design layout, thereby simplifying and / or shortening the design layout process.

[0126] Figure 1A is a top view of an integrated circuit layout cell 100A including a pattern of horizontal parallel conductive lines arranged along five evenly spaced traces. The conductive pattern layout 100A includes conductive elements 102, 104, 105, 108A, 110, 112 arranged along a series of horizontal parallel traces. Depending on the IC design layout in the level of the conductive pattern, the conductive elements are connected to source / drain regions, gate electrodes, bulk contacts and / or other conductive patterns (not shown) to form a portion of an interconnect on the IC component. In accordance with applicable design rules, the ends of the individual conductive elements are separated by a minimum end-to-end distance (also referred to as EE or E2E) to improve patterning operations and / or reduce the possibility of shorting between closely placed conductive elements after the manufacturing process. With respect to the conductive pattern 100A, the spacing 116A between the ends of the conductive elements 108A and 110 in the region 114A has an initial spacing 116A that is less than a target EE. For the conductive pattern 100A according to FIG. 1 , the spacing 116A between the ends of the conductive elements 108A and 110 in the region 114A has an initial spacing 116A that is less than a target EE. For the conductive pattern 100A according to FIG. 1 , the spacing 116A between the ends of the conductive elements 108A and 110 in the region 114A has an initial spacing 116A that is less than a target EE. Figure 1A In some embodiments, spacings such as 116A that are below the minimum EE spacing are corrected by extending one of the conductive patterns in a process known as line end extension (LEE), where additional sections of conductive material are added to create overlap between opposing ends of the conductive element.

[0127] Figure 1B 1 is a top view of an integrated circuit layout cell 100B, including a pattern of horizontal parallel conductive lines arranged along five evenly spaced traces. The conductive pattern layout 100B includes conductive elements 102, 104, 105, 108A, 110, 112 arranged along a series of horizontal parallel traces, wherein an additional segment 108B is added to the original segment 108A to sufficiently resolve Figure 1AHowever, with respect to the conductive pattern 100B, the spacing 116B between the ends of the conductive elements 108A+108B and 102 in the region 114B has a currently improved end-to-end spacing 116B that is less than the target EE. Figure 1B In some embodiments, spacings such as 116B that are below the minimum EE spacing are corrected by extending one of the conductive patterns 102 or 108A+108B through the LEE, where additional sections of conductive material are added to create overlap between opposing ends of the conductive elements that are below the target EE.

[0128] Figure 1C 1 is a top view of an integrated circuit layout cell 100C, including a pattern of horizontal parallel conductive lines arranged along five evenly spaced traces. The conductive pattern layout 100C includes conductive elements 102, 104, 105, 108A+108B, 110, 112 arranged along a series of horizontal parallel traces, wherein an additional segment 108C is added to the above segments 108A+108B to sufficiently address Figure 1B However, with respect to the conductive pattern 100C, the spacing 116C between the ends of the conductive elements 108A+108B+108C and 112 in the region 114C has the currently improved end-to-end spacing 116C that is smaller than the target EE. Figure 1C In some embodiments, spacings such as 116C that are below the minimum EE spacing are corrected by extending conductive pattern 112 or one of 108A+108B+108C through LEEs, where additional sections of conductive material are added to create overlap between opposing ends of the conductive elements.

[0129] Figure 1D 1 is a top view of an integrated circuit layout unit 100D, including a pattern of horizontal parallel conductive lines arranged along five evenly spaced traces. The conductive pattern layout 100D includes conductive elements 102, 104, 105, 108A+108B+108C, 110, 112 arranged along a series of horizontal parallel traces, wherein an additional segment 108D is added to the modified conductive element 108A+108B+108C to sufficiently address Figure 1C However, with respect to the conductive pattern 100D, the spacing 116D between the ends of the conductive elements 108A+108B+108C+108D and 106 in the region 114C has a currently improved end-to-end spacing 116D that is smaller than the target EE. Figure 1DIn some embodiments, spacings such as 116D that are below the minimum EE spacing are corrected by extending conductive pattern 106 or one of 108A+108B+108C+108D through LEEs, where additional sections of conductive material are added to create overlap between opposing ends of the conductive elements.

[0130] Figure 1E 1 is a top view of an integrated circuit layout unit 100E, including a pattern of horizontal parallel metal lines arranged along five evenly spaced traces. The conductive pattern layout 100E includes conductive elements 102, 104, 105, 108A+108B+108C+108D, 110, 112 arranged along a series of horizontal parallel traces, wherein an additional segment 108E is added to the modified conductive element 108A+108B+108C+108D to sufficiently address Figure 1D Regarding the conductive pattern 100E, this fifth additional section is sufficient to solve all EE spacing problems within the conductive pattern 100E without creating new EE spacing problems.

[0131] like Figures 1A to 1E , using line end extension techniques to solve spacing problems, however, in some cases, new EE spacing problems are created while the initial EE spacing problem is solved. Therefore, the iterative and unpredictable nature of LEEs applied in this manner is both slow and difficult to optimize, particularly because the extension of conductive elements 102, 104, 105, 108A, 110, 112, even if no new EE spacing problems are created, will tend to increase parasitic resistance and capacitance due to the increased length of the conductive elements.

[0132] Figure 2A 2 is a top view of an integrated circuit layout cell 200A including a pattern of horizontally parallel conductive elements 202A, 202B, 204A, 204B arranged along two evenly spaced horizontally parallel traces in accordance with some embodiments. Figure 2A , dummy pattern 206 has been used to extend the line end of conductive element 202B so as to reduce the end-to-end spacing with conductive element 202A to the minimum allowed EE spacing. Similarly, dummy pattern 208 has been used to extend the line end of conductive element 204A so as to reduce the end-to-end spacing with conductive element 204B to the minimum allowed EE spacing. Extending the length of one or more conductive elements 202A, 202B, 204A, 204B including one or more main conductive lines using dummy patterns to reduce the included end-to-end spacing is characterized as a trace-fill based method operating in an extension mode.

[0133] Figure 2B2 is a top view of an integrated circuit layout cell 200B according to some embodiments, including a pattern of horizontally parallel conductive elements 202A, 202B, 204A, 204B arranged along two evenly spaced horizontally parallel traces. Figure 2B In the embodiment, the dummy pattern 206 has been inserted between and separated from the line ends of the conductive elements 202A, 202B so as to fill a portion of the open area existing between the two conductive elements and reduce the end-to-end spacing between the conductive elements 202A, 202B and the dummy pattern 206 to the minimum allowed EE spacing. Similarly, the dummy pattern 208 has been inserted between and separated from the line ends of the conductive elements 204A, 204B so as to fill a portion of the gap existing between the two conductive elements and reduce the end-to-end spacing between the conductive elements 204A, 204B and the dummy pattern 208 to the minimum allowed EE spacing. Filling a portion of the open area of ​​two conductive elements 202A, 202B, 204A, 204B including one or more main conductive lines using one or more dummy patterns to increase the local conductor density and reduce the included end-to-end spacing to the minimum allowed EE spacing is characterized as a trace-fill based method operating in a fill, segment, or insert mode.

[0134] Figure 3 3 is a top view of an integrated circuit layout cell 300 according to some embodiments, including a pattern of horizontally parallel conductive elements 302, 304 arranged along at least some of a plurality of evenly spaced traces 310. The integrated circuit layout cell 300 also includes spacer traces 310' over which no conductive elements are patterned or etched to provide additional spacing between the conductive elements 302, 304 forming the main conductive lines.

[0135] Many dummy patterns 306A are arranged on the portion of the trace 310 that is not covered by the conductive element forming the main signal line. The dummy patterns 306A are arranged at an end-to-end distance (EE D ) are separated. In some embodiments, EE D is less than the minimum EE distance allowed between conductive elements including the main conductors, and in some embodiments, the EE D The distance between the conductive elements 306A and 306B is equal to or greater than the minimum EE distance allowed between the conductive elements including the main wires. In some embodiments, the dummy patterns 306A of adjacent columns may be horizontally offset to provide staggered fill-to-fill (also referred to as FF, EE, etc.) F and / or F2F) (or dummy to dummy (also known as DD and / or D2D)) arrangements to increase local conductor density without a corresponding increase in dummy to dummy (or dummy to main (also known as DM, EE DM and / or D2M)) parasitic capacitance and / or parasitic resistance.

[0136] In some embodiments, each of the dummy patterns 306A is characterized by a predetermined minimum area and a predetermined end-to-end distance EE D In some embodiments, each of the spatial criteria regarding the size, spacing and / or relative positioning of the conductive elements including the main conductive lines and any dummy patterns used to extend the end length of at least one of the conductive elements and / or to serve as one or more separate fill elements between two conductive elements are incorporated into the design rules to allow generation and placement of appropriate dummy patterns during an automatic place and route (APR) process.

[0137] In some embodiments, each of the spatial criteria regarding the size, spacing and / or relative positioning of the conductive elements comprising the main conductive lines and any dummy patterns used to extend the end length of at least one of the conductive elements and / or serve as one or more separate fill elements between two conductive elements are used to generate a dummy pattern library from which a designer or APR function is able to retrieve suitable dummy patterns to correct excessive spacing between the main conductive lines and / or increase the overall conductive layer density.

[0138] Figure 4A is a top view of an integrated circuit layout cell 400A according to some embodiments, including a first conductive element 402A and a second conductive element 402B separated by an initial open space corresponding to a relatively large end-to-end spacing EE i . Figure 4B is a top view of an integrated circuit layout cell 400B including horizontal metal lines arranged along a single trace and including a first conductive element 402A and a second conductive element 402B separated by an initial open space corresponding to an end-to-end spacing EE i In some embodiments, the initial open space is of sufficient size so that the two dummy patterns 406A, 406B can be inserted between the first conductive element 402A and the second conductive element 402B while still maintaining the target EE spacing between the dummy patterns and the conductive elements and the EE spacing between the two dummy patterns. D interval.

[0139] Figure 5A is a top view of an integrated circuit layout unit 500A according to some embodiments, including a first conductive element 502A and a second conductive element 502B separated by a single dummy pattern 506A, the single dummy pattern satisfying at least a minimum size criterion DL of a dummy pattern. min (a value set in the process design rules corresponding to a specific manufacturing process that will be used to manufacture IC devices according to the integrated circuit layout). As long as the initial open interval EE i If formula 1 is satisfied, it can be used Figure 5A Fill pattern in .

[0140] EE i ≥DL min +2x(EE)[Formula 1]

[0141] Figure 5B is a top view of an integrated circuit layout cell 500B according to some embodiments, including a first conductive element 502A and a second conductive element 502B separated by a single dummy pattern 506B, the single dummy pattern exceeding a minimum size criterion DL of a dummy pattern. min Without exceeding the maximum length DL of the dummy pattern max (a value set in the process design rules corresponding to a specific manufacturing process that will be used to manufacture IC devices according to the integrated circuit layout). As long as the initial open interval EE i If both equations 2 and 3 are satisfied, it can be used Figure 5B Fill pattern in .

[0142] EE i >DL min +2x(EE) [Formula 2]

[0143] EE i ≤DL max +2x(EE) [Formula 3]

[0144] Figure 5C 5 is a top view of an integrated circuit layout unit 500C according to some embodiments, including a first conductive element 502A and a second conductive element 502B separated by a pair of dummy patterns 506C′, 506C″, the pair of dummy patterns satisfying a minimum size criterion DL of the dummy patterns. min Without exceeding the maximum length DL of the dummy pattern max . As long as the initial opening interval EE i If both equations 4 and 5 are satisfied, it can be used Figure 5C Fill pattern in .

[0145] EE i >DL max +2x(EE)+EE D [Formula 4]

[0146] EE i ≥2DL min +2x(EE)+EE D [Formula 5]

[0147] Fig. 6A 6 is a top view of an integrated circuit layout unit 600A, which includes a first conductive element 602A and a second conductive element 602B separated by a pair of dummy patterns 606A′, 606A″, which meet the minimum size requirement DL of the dummy pattern.min Without exceeding the maximum length DL of the dummy pattern max Can be used in conjunction with interval track 610' Fig. 6A In the fill pattern shown in FIG. 1 , no conductive element or dummy pattern is formed on the spaced track 610'. The spaced track 610' is separated from the conductive elements 602A and 602B by the track offset interval TO. Fig. 6A In some embodiments, a combination of a trace-fill based approach using both extend mode (not shown) and fill mode operations is used to fill the open space.

[0148] Figure 6B 6 is a top view of an integrated circuit layout cell 600B according to some embodiments, including horizontal conductive elements 602A and 602B arranged along a single track 610 adjacent to a spaced track 610'. A first conductive element 602A and a second conductive element 602B are separated by a pair of dummy patterns 606C', 606C". According to some embodiments, the track including the conductive elements may be flanked by a first array of spaced tracks 610' and dummy patterns 606A and a second array of dummy patterns 606D. The array of spaced tracks 610' and dummy patterns 606D may be separated from the conductive elements 602A, 602B by a track offset spacing TO. In accordance with Figure 6B In some embodiments, a combination of a trace-fill based approach using both extend mode and fill mode operations (not shown) is used to fill the open space.

[0149] Figure 6C is a top view of an integrated circuit layout cell 600C according to some embodiments, including horizontal conductive elements arranged along a single trace 610, including a first conductive element 602A and a second conductive element 602B separated by a dummy pattern 606', the dummy pattern meeting the minimum size requirement DL of the dummy pattern. min .like Figure 6C As shown, the dummy pattern 606' may be used in the following situations: although the maximum allowable length DL of the dummy pattern is met max , but the larger dummy pattern 606 is too large to be used between the conductive elements 602A, 602B.

[0150] Fig.6D 6 is a top view of an integrated circuit layout cell 600D according to some embodiments, including a horizontal conductive element 602 arranged along a single trace 610. The conductive element 602 is flanked on a first side by an array of dummy patterns 606' and on a second side by a single dummy pattern 606. The array of dummy patterns 606' and the larger dummy pattern 606 cover substantially the same length of the conductive element 602. Fig.6DAs indicated in FIG. 1 , each of the array of dummy patterns 606′ will have a characteristic parasitic capacitance PC1 relative to the conductive element 602. Similarly, the larger dummy pattern 606 will have a characteristic parasitic capacitance PC2 relative to the conductive element 602. Due to the inclusion of dummy to dummy spacings EE within the array of dummy patterns 606′, D , thus establishing that PC2>3(PC1), thereby reducing parasitic capacitance while maintaining an increased conductive element density relative to embodiments that do not include dummy patterns.

[0151] Figure 7 is a flow chart of a method 700 for improving uniformity of conductive (typically metal) patterning in conjunction with integrated circuit design by adding dummy metal patterns during an automatic place and route (APR) process to compensate for the degrading effects of density gradient effect (DGE) induced by gaps in the metal pattern.

[0152] In step 702, a preliminary IC metal design layout including a preliminary conductive pattern is obtained, such as retrieved from memory or input by a designer, for evaluation. In step 704, the preliminary IC design file or at least one preliminary conductive pattern is evaluated to identify open areas (OA) in the conductive (e.g., metal) pattern arranged along one or more specified tracks. Step 706 involves a query about the degree of successful identification of open areas. If less than all open areas have been identified, the method 700 branches from step 706 to step 708 to identify the next open area for evaluation. When all open areas have been identified, the method 700 branches to step 710 to select a dummy pattern or multiple patterns for each of the identified open areas. Selecting a suitable dummy pattern in step 710 involves evaluating the length of the open area, and in some embodiments, classifying the conductive elements that define the open area, such as the main conductor and / or the dummy pattern, followed by selecting or generating a dummy pattern for layout in the open area. The selection and / or generation operations involve applying criteria and / or formulas associated with the particular manufacturing process and the specific conductive patterns (eg, M0, M1, . . . , Mx) being formed during production of the IC device.

[0153] In some embodiments, a library of dummy patterns is available for selection and / or modification by a designer for use in IC layout design. In some embodiments, dummy patterns can be automatically generated during execution of a placement and routing process based on a set of specific design rules corresponding to a desired IC manufacturing process, particularly with respect to one or more parameters, including, for example, minimum length, minimum length, minimum area, maximum area, and minimum spacing. Each of the dummy patterns available in the library has passed the relevant technical rule check (DRC) and can be used to handle at least one of the open area configuration types found in IC layout design.

[0154] Because embodiments of dummy patterns do not have specific design rules for specific types of development areas, DRC update revisions and node-to-node propagation are simplified and can be efficiently implemented across families or libraries of transitional cell designs. In some embodiments, the dummy pattern design library includes dummy patterns suitable for placement in open areas that are found for each of the various levels of conductive / metal patterns incorporated within an IC layout design. For example, some embodiments include IC layout designs that incorporate standard threshold voltage (SVT), low threshold voltage (LVT), and / or ultralow threshold voltage (ULVT). The configuration of dummy patterns according to some embodiments is improved whereby the dummy patterns can be used for each of the various conductive / metal patterns found within active areas using different operating voltages.

[0155] Some embodiments include a method comprising the steps of: receiving a preliminary device layout including a plurality of conductive / metal patterns; analyzing the preliminary device layout to identify open areas found between segments of the conductive / metal patterns; determining a configuration of one or more suitable dummy patterns from a dummy pattern library. These steps of analyzing the open areas while selecting suitable dummy patterns continue until each of the open areas has been filled with a dummy pattern to generate an improved IC design layout having an improved conductive pattern. In some embodiments, the improved IC design layout will be used to generate a tapeout, which can then be used to manufacture IC devices according to the improved IC design layout.

[0156] Step 712 involves a query as to the extent to which selection of a suitable dummy pattern has been completed for each of the identified open areas. If selection of a suitable dummy pattern has not been completed, step 712 branches back to step 710 to continue selecting a suitable dummy pattern for each of the identified open areas.

[0157] Once a suitable dummy pattern has been selected for each of the open areas, step 714 involves generating a modified conductive pattern, wherein the selected dummy pattern is incorporated into the preliminary conductive pattern design layout and / or the preliminary IC design layout.

[0158] In optional step 716, the improved conductive pattern produced in step 714 may be evaluated with respect to one or more parameters or performance values, including, for example, conductor / metal density, parasitic capacitance, parasitic resistance, electromigration performance, self-heating, expected device lifetime, timing performance, core utilization, or other structural and / or operational values ​​of interest to designers and / or customers. In some embodiments, the success of this evaluation or multiple evaluations is judged based on one or more target values, such as a metal density of at least 50%, and / or with respect to the degree of improvement observed relative to a corresponding evaluation or multiple evaluations of the original and unmodified preliminary conductive pattern.

[0159] For those improved conductive patterns that pass the evaluation, method 700 includes an optional step 718, during which, in some embodiments, a tape output data file is generated, the tape output data file corresponding to the passed improved IC design layout, the IC design layout having the improved conductive pattern. For those improved IC design layouts for which the tape output data file is generated, the tape output data file is used in optional step 720 to manufacture semiconductor devices based on the passed improved IC design layout.

[0160] Figure 8 8 is a block diagram of an integrated circuit (IC) manufacturing system 800 and an IC manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 800 is used to manufacture at least one of the following: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0161] exist Figure 8 In the embodiment, IC manufacturing system 800 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC components 860, such as design studio 820, mask room 830 and IC manufacturer / fabricator ("fab") 850. The entities in system 800 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an internal network and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of design studio 820, mask room 830 and IC fab 850 are owned by a single larger company. In some embodiments, two or more of design studio 820, mask room 830 and IC fab 850 coexist in a common facility and use common resources.

[0162] The design office (or design team) 820 generates an IC design layout 822. The IC design layout 822 includes various geometric patterns designed for the IC element 860. The geometric patterns correspond to patterns of metal, oxide or semiconductor layers, which constitute various components of the IC element 860 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 822 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnection, and openings for bonding pads, as well as various material layers disposed on the semiconductor substrate. The design office 820 implements a suitable design program to form the IC design layout 822. The design program includes one or more of a logical design, a physical design, or a layout and routing. The IC design layout 822 is presented in one or more data files having information of the geometric patterns. For example, according to some embodiments, the IC design layout 822 can be represented in a GDSII file format or a DFII file format.

[0163] Although the pattern of the modified IC design layout is adjusted by a method such as method 800 to reduce the parasitic capacitance of the integrated circuit as compared to an unmodified IC design layout, the modified IC design layout reflects the results of changing the positions of conductive lines in the layout and, in some embodiments, inserting features associated with capacitor isolation structures into the IC design layout to further reduce parasitic capacitance as compared to an IC structure having the modified IC design layout but without features for forming capacitor isolation structures disposed therein.

[0164] The mask chamber 830 includes data preparation 832 and mask manufacturing 844. The mask chamber 830 uses the IC design layout 822 to manufacture one or more masks 845 for manufacturing various layers of the IC component 860 according to the IC design layout 822. The mask chamber 830 performs mask data preparation 832, in which the IC design layout 822 is converted into a representative data file (RDF). The mask data preparation 832 provides the RDF to the mask manufacturing 844. The mask manufacturing 844 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 845 or a semiconductor wafer 853. The design layout 822 is manipulated by the mask data preparation 832 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 850. In Figure 8 , mask data preparation 832 and mask manufacturing 844 are illustrated as separate elements. In some embodiments, mask data preparation 832 and mask manufacturing 844 are collectively referred to as mask data preparation.

[0165] In some embodiments, mask data preparation 832 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, crosstalk, other process effects, and the like. OPC adjusts IC design layout 822. In some embodiments, mask data preparation 832 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0166] In some embodiments, mask data preparation 832 includes a mask rule checker (MRC) that checks the IC design layout 822 that is processed in the OPC using a set of mask generation rules that include certain geometric and / or connection constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 822 to compensate for the constraints during mask generation 844, which may override a portion of the modifications performed by the OPC to satisfy the mask generation rules.

[0167] In some embodiments, mask data preparation 832 includes lithography process checking (LPC), which simulates the process to be performed by IC fab 850 to manufacture IC component 860. LPC simulates this process based on IC design layout 822 to produce simulated manufacturing components, such as IC component 860. In some embodiments, the process parameters in the LPC simulation include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, and the like, or combinations thereof. In some embodiments, after LPC has produced simulated manufacturing components, if the simulated components are not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine IC design layout 822.

[0168] Those skilled in the art will appreciate that the above description of mask data preparation 832 has been simplified for clarity purposes. In some embodiments, data preparation 832 includes additional features, such as logic operations (LOPs) to improve IC design layout 822 according to manufacturing rules. In addition, according to some embodiments, the processes applied to IC design layout 822 during data preparation 832 may be performed in a variety of different orders.

[0169] After mask data preparation 832 and during mask fabrication 844, a mask 845 or a set of masks 845 are fabricated based on the modified IC design layout 822. In some embodiments, mask fabrication 844 includes performing one or more lithographic exposures based on the IC design layout 822. In some embodiments, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on a mask (mask or master mask) 845 based on the modified IC design layout 822. In some embodiments, the mask 845 is formed using various techniques. In some embodiments, the mask 845 is formed using a binary technique.

[0170] In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (such as an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and transmitted through the transparent areas. In one example, a binary mask version of mask 845 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In another example, mask 845 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 845, each feature in the pattern formed on the phase shift mask is configured to have a suitable phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask is an attenuated PSM or an alternating PSM. The mask produced by mask manufacturing 844 is used in various processes. For example, such masks are used in an ion implantation process to form various doped regions in the semiconductor wafer 853, in an etching process to form various etched regions in the semiconductor wafer 853, and / or in other suitable processes.

[0171] IC fab 850 includes wafer fabrication 852. IC fab 850 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC Fab 850 is a semiconductor factory. For example, according to some embodiments, a manufacturing facility is provided for front-end manufacturing of multiple IC products (front-end-of-line; FEOL) manufacturing), while a second manufacturing facility is provided for back-end manufacturing of interconnection and packaging of IC products (back-end-of-line; BEOL) manufacturing, and a third manufacturing facility is provided for other services of the factory business. In some embodiments of the present disclosure, fin size adjustment includes operations associated with forming a fin array across a functional area of ​​the integrated circuit that includes fins, followed by improving the fin size in at least one functional area of ​​the integrated circuit that includes fins.

[0172] In some embodiments of the present disclosure, in a single fin formation manufacturing flow for each functional region of the IC containing fins, fins of different functional regions containing fins are individually formed into final fin shapes or fin size profiles. In some embodiments, fin sizing occurs by forming fins in a layer of fin material or a fin substrate, by applying a mask layer to a top surface of the fin material, patterning the mask layer with a pattern corresponding to the location of the fins in one or more of the functional regions containing fins, exposing the top surface of the fin material through the mask layer, and etching the fin material to form the fins in the fin substrate. In some embodiments, fins are formed in a single functional region of the IC at a final fin size, which is the selected fin size (or fin height) described above in step 850.

[0173] The patterned layer of mask material formed on the semiconductor substrate is made of a mask material, including one or more layers of photoresist, polyimide, silicon oxide, silicon nitride (e.g., Si3N4), SiON, SiC, SiOC, or a combination thereof. In some embodiments, the mask includes a single layer of mask material. In some embodiments, the mask includes multiple layers of mask material.

[0174] In some embodiments, the mask material is patterned by exposure to an illumination source. In some embodiments, the illumination source is an electron beam source. In some embodiments, the illumination source is a lamp that emits light. In some embodiments, the light is ultraviolet light. In some embodiments, the light is visible light. In some embodiments, the light is infrared light. In some embodiments, the illumination source emits a combination of different (UV, visible and / or infrared) light.

[0175] After the mask patterning operation, the fins in the areas not covered by the mask or the fins in the open areas of the pattern are etched to improve the fin size. In some embodiments, etching is performed on the top surface of the fin, wherein the side of the fin is completely covered by the adjacent dielectric support material deposited between the fins in the previous manufacturing step. According to some embodiments, the etching of the top surface of the fin is performed using plasma etching or using a liquid chemical etching solution. The chemical composition of the liquid chemical etching solution includes one or more etchants, such as citric acid (C6H8O7), hydrogen peroxide (H2O2), nitric acid (HNO3), sulfuric acid (H2SO4), hydrochloric acid (HCl), acetic acid (CH3CO2H), hydrofluoric acid (HF), buffered hydrofluoric acid (BHF), phosphoric acid (H3PO4), ammonium fluoride (NH4F) potassium hydroxide (KOH), ethylenediamine catechol (EDP), TMAH (tetramethylammonium hydroxide) or a combination of the above. In some embodiments, etching the fins is performed by exposing an upper portion of the fin material that extends above a top surface of a dielectric support medium that was deposited between the fins in a previous manufacturing step and is recessed below the top surface at the height of the fins to a liquid chemical etching solution that includes one or more of the liquid chemical etchants described above. The upper portion of the fin material includes the top surface and sides of the fin material.

[0176] In some embodiments, the etching process is a dry etching or plasma etching process. Plasma etching of the substrate material is performed using a halogen-containing reactive gas excited by an electromagnetic field to dissociate into ions. Reactive or etchant gases include CF4, SF6, NF3, Cl2, CCl2F2, SiCl4, BCl2, or a combination thereof, but other semiconductor material etchant gases are also contemplated within the scope of some embodiments of the present disclosure. According to methods of plasma etching known in the art, ions are accelerated by alternating electromagnetic fields or by a fixed bias to impact the exposed fin material. In some embodiments, the etching process includes an exposed portion of the fin presenting a functional area in an oxygen-containing atmosphere to oxidize the outer portion of the fin material, followed by a chemical trimming process, such as plasma etching or liquid chemical etching, as described above, to remove the oxidized semiconductor fin material and leave a modified fin. In some embodiments, fin oxidation is performed, followed by chemical trimming, to provide greater selectivity for the fin material and reduce the possibility of accidental removal of the fin material during the manufacturing process. In some embodiments, the exposed portion of the fin in the functional area is the top surface of the fin, and the fin is embedded in the dielectric support medium covering the side surfaces of the fin. In some embodiments, the exposed portion of the fin in the functional area is the top surface and side surfaces of the fin, which are located above the top surface of the dielectric support medium, wherein the top surface of the dielectric support medium has been recessed to a level lower than the top surface of the fin, but still covers the lower portion of the side surfaces of the fin.

[0177] IC fab 850 uses mask 845 manufactured by mask chamber 830 to manufacture IC component 860. Therefore, IC fab 850 at least indirectly uses IC design layout 822 to manufacture IC component 860. In some embodiments, semiconductor wafer 853 is manufactured by ICfab 850 using mask 845 to form IC component 860. In some embodiments, IC manufacturing includes performing one or more lithography exposures based at least indirectly on IC design layout 822. Semiconductor wafer 853 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 853 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent manufacturing steps).

[0178] With respect to integrated circuit (IC) manufacturing systems (e.g., Figure 8 Details of the system 800 and the IC manufacturing process associated therewith can be found, for example, in U.S. Patent No. 9,256,709 issued on February 9, 2016, U.S. Pre-Grant Publication No. 20150278429 published on October 1, 2015, U.S. Pre-Grant Publication No. 20140040838 published on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, each of which is incorporated herein by reference in its entirety.

[0179] Fig. 9 900 according to some embodiments. The method of generating a cell layout diagram described herein according to one or more embodiments can be implemented, for example, using the EPC system 900 according to some embodiments. In some embodiments, the EPC system 900 is a general-purpose computing device, including a hardware processor 902 and a non-transitory computer-readable storage medium 904. Therein, the storage medium 904 is encoded with computer program code (or instructions) 906 (i.e., a set of executable instructions), i.e., the storage medium stores the computer program code (or instructions). The execution of the computer program code 906 by the hardware processor 902 (at least in part) represents an EPC tool that implements a portion or all of the method described herein according to one or more (hereinafter, the process and / or method).

[0180] The hardware processor 902 is electrically coupled to the computer readable storage medium 904 via the bus 918. The hardware processor 902 is also electrically coupled to the I / O interface 912 via the bus 918. The network interface 914 is also electrically coupled to the hardware processor 902 via the bus 918. The network interface 914 is connected to the network 916 so that the hardware processor 902 and the computer readable storage medium 904 can be connected to external components via the network 916. The hardware processor 902 is configured to execute computer program code 906 encoded in the computer readable storage medium 904 to cause the EPC system 900 to be used to perform part or all of the processes and / or methods described. In one or more embodiments, the hardware processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0181] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 904 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0182] In one or more embodiments, the storage medium 904 stores computer program code 906 configured to cause the EPC system 900 (where such execution (at least in part) represents an EPC tool) to be used to perform some or all of the processes and / or methods. In one or more embodiments, the storage medium 904 also stores information that facilitates the performance of some or all of the processes and / or methods. In one or more embodiments, the storage medium 904 stores process control data 908, which in some embodiments includes control algorithms, active region data, transition cell data, uniformity algorithms, layout data, and constants, target ranges, set points, and code for enabling statistical process control (SPC) and / or model predictive control (MPC) based control of various processes.

[0183] The EPC system 900 includes an I / O interface 912. The I / O interface 912 is coupled to an external circuit system. In one or more embodiments, the I / O interface 912 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a screen and / or cursor arrow keys to transmit information and commands to the hardware processor 902.

[0184] The EPC system 900 also includes a network interface 914 coupled to the hardware processor 902. The network interface 914 allows the EPC system 900 to communicate with a network 916 to which one or more other computer systems are connected. The network interface 914 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more EPC systems 900.

[0185] The EPC system 900 is configured to receive information via an I / O interface 912. The information received via the I / O interface 912 includes one or more of the following: instructions, data, design rules, process execution history, target ranges, set points, and / or other parameters processed by the hardware processor 902. The information is transmitted to the hardware processor 902 via a bus 918. The EPC system 900 is configured to receive information related to a user interface (UI) via the I / O interface 912. The information is stored in the computer readable medium 904 as a user interface (UI) 910.

[0186] In some embodiments, some or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods are implemented as a plug-in in a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an EPC tool. In some embodiments, some or all of the processes and / or methods are implemented as a software application used by the EPC system 900.

[0187] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical disks, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROM, RAM, memory cards, and the like.

[0188] According to some embodiments, a method for designing a semiconductor device is provided, the method comprising the steps of: analyzing an initial semiconductor design layout to identify a first open space between a first segment and a second segment within a first interconnect layer pattern, the first open space having an open space length exceeding an end-to-end spacing; selecting a first dummy pattern for placement in the first open space; and generating an improved semiconductor design layout by incorporating the first dummy pattern into the first interconnect layer pattern. According to some embodiments, the method for designing a semiconductor device includes outputting an improved semiconductor design layout. According to some embodiments, the method for designing a semiconductor device includes placing the first dummy pattern in the open space to be in direct electrical contact with a portion of the first interconnect layer pattern. According to some embodiments, the method for designing a semiconductor device includes placing the first dummy pattern in the open space to be electrically separated from the first interconnect layer pattern, wherein the first dummy pattern generates a first reduced open space length between the first segments within the end-to-end spacing limit, and a second reduced open space length within the end-to-end spacing limit. According to some embodiments, the first dummy pattern includes both a first portion and a second portion, the first portion being in direct electrical contact with the first interconnect layer pattern, and the second portion being electrically separated from the first interconnect layer pattern. According to other embodiments, the first dummy pattern includes a first portion and a second portion, the first portion is electrically separated from the first interconnect layer pattern, and the second portion is electrically separated from the first interconnect layer pattern. According to some embodiments, the first interconnect layer pattern includes a main conductive element aligned along a first track, a first dummy pattern aligned along the first track, and a second dummy pattern aligned along a second track, the second track being parallel to the first track. According to some embodiments, the first interconnect layer pattern includes a spacer track parallel to the first track and the second track, wherein the spacer track does not include any conductive element and / or dummy pattern. According to some embodiments, the spacer track is arranged between the first track and the second track.

[0189] According to some embodiments, a method for defining a conductive pattern layout for a semiconductor device design includes the following steps: setting a first design rule for an end-to-end spacing requirement for an open area between adjacent first and second conductive elements; identifying a first open area in an initial conductive pattern layout that is outside the first design rule; selecting a first dummy pattern for covering a first portion of the first open area, whereby a remaining second open area is within the first design rule; and placing the first dummy pattern within the first open area to produce a revised conductive pattern layout. In some embodiments, a method for revising a conductive pattern layout for a semiconductor device design includes additional steps, which include: setting a second design rule for a maximum area requirement for the first dummy pattern; identifying a first dummy pattern in a revised conductive pattern layout that is outside the second design rule; selecting a second dummy pattern to replace the first dummy pattern, wherein the second dummy pattern includes at least two dummy pattern elements, each of which is within the second design rule; replacing the first dummy pattern with the second dummy pattern to produce a revised conductive pattern layout. In some embodiments, a method for defining a conductive pattern layout for a semiconductor device design includes additional steps, which include: identifying a third open area having an end-to-end spacing length L3 outside a first design rule; generating a third dummy pattern according to a second design rule, such that the third dummy pattern is placed in the third open area leaving a remaining fourth open area, and the remaining fourth open area is within the first design rule; storing the generated third dummy pattern in a memory device for subsequent retrieval for layout in an interconnect layer pattern, wherein the interconnect layer pattern has one or more open spaces, and these open spaces have an end-to-end spacing length of L3.

[0190] According to some embodiments, a semiconductor component has an interconnect pattern, the interconnect pattern having at least two parallel tracks, a first conductor and a second conductor aligned with the first track, the first conductor and the second conductor being separated by an open space; and a first dummy pattern aligned with the first track and disposed within the open space. According to some embodiments, the first dummy pattern is in direct electrical contact with the first conductor, and the first dummy pattern is electrically isolated from the second conductor. According to some embodiments, the first dummy pattern is electrically isolated from both the first main conductor and the second main conductor. According to some embodiments, the semiconductor component includes a second dummy pattern aligned with the second track, wherein the second dummy pattern includes at least two conductive elements. According to some embodiments, the semiconductor component includes a spaced track parallel to the first track and the second track and arranged between the first track and the second track. According to some embodiments, the semiconductor component includes a third dummy pattern including at least two conductive elements aligned with the third track, the third track being arranged adjacent to the first track. According to some embodiments, the semiconductor component includes conductive elements of the second dummy pattern defining a first array, a plurality of conductive elements including the third dummy pattern defining a second array, and the first array and the second array are arranged in a staggered offset configuration.

[0191] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of some embodiments of the present disclosure. Those skilled in the art will appreciate that some embodiments of the present disclosure may be readily used as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent structures do not depart from the spirit and scope of some embodiments of the present disclosure, and that various changes, substitutions, and modifications may be implemented herein without departing from the spirit and scope of some embodiments of the present disclosure.

Claims

1. A method for designing a semiconductor device, characterized in that: The method comprises the following steps: Analyzing an initial semiconductor design layout to identify a first end-to-end spacing between a first end of a first conductive element and a second end of a parallel second conductive element within a first interconnect layer pattern, wherein the first end-to-end spacing is less than a minimum end-to-end spacing rule for the semiconductor element; Selecting a first dummy pattern extending from the first end of the first conductive element by a first extension length, the first extension length being sufficient to make the first end-to-end spacing comply with the minimum end-to-end spacing rule; as well as A first improved semiconductor design layout is generated by incorporating the first dummy pattern into the first interconnect layer pattern to form a second interconnect layer pattern.

2. The method for designing a semiconductor device according to claim 1, wherein: Also includes: The first improved semiconductor design layout is output.

3. The method for designing a semiconductor device according to claim 1, wherein: Also includes: Analyzing the first improved semiconductor design layout to identify a second end-to-end spacing between a first end of the first dummy pattern and a first end of a parallel third conductive element, wherein the second end-to-end spacing is less than the minimum end-to-end spacing rule of the semiconductor element; Selecting a second dummy pattern extending from the first end of the first dummy pattern by a second extension length, the second extension length being sufficient to make the second end-to-end spacing comply with the minimum end-to-end spacing rule; as well as A second improved semiconductor design layout is generated by incorporating the second dummy pattern into the second interconnect layer pattern to form a third interconnect layer pattern.

4. The method for designing a semiconductor device according to claim 1, wherein: Also includes: Analyzing the initial semiconductor design layout to identify a second end-to-end spacing between another first end of the first conductive element and a second end of a coaxial second conductive element within the first interconnect layer pattern, wherein the second end-to-end spacing is at least twice greater than a maximum end-to-end spacing rule of the semiconductor element; Selecting a coaxial second dummy pattern having a second dummy pattern length for placement within the second end-to-end spacing, the coaxial second dummy pattern length being sufficient to make the first end-to-end spacing comply with the minimum end-to-end spacing rule; as well as A second improved semiconductor design layout is generated by incorporating the coaxial second dummy pattern into the first interconnect layer pattern to form the second interconnect layer pattern.

5. The method for designing a semiconductor device according to claim 4, wherein: The second interconnection layer pattern comprises: a first dummy pattern portion in direct electrical contact with the first interconnect layer pattern; and A second dummy pattern portion is electrically separated from the first interconnection layer pattern.

6. The method for designing a semiconductor device according to claim 1, wherein: Also includes: Analyzing the initial semiconductor design layout to identify a second end-to-end spacing between another first end of the first conductive element and a second end of a coaxial second conductive element within the first interconnect layer pattern, wherein the second end-to-end spacing is greater than a maximum end-to-end spacing rule of the semiconductor element; Selecting a coaxial second dummy pattern having a second dummy pattern length to extend from the other first end of the first conductive element to a second extension length sufficient to make the second end-to-end spacing comply with the maximum end-to-end spacing rule; as well as A second improved semiconductor design layout is generated by incorporating the coaxial second dummy pattern into the second interconnect layer pattern to form a third interconnect layer pattern.

7. The method for designing a semiconductor device according to claim 3, wherein: The first interconnection layer pattern comprises: The first conductive element aligned along a first track and the first dummy pattern aligned along the first track; as well as The second conductive element is aligned along a second track and the second dummy pattern is aligned along the second track, and the second track is parallel to the first track.

8. The method for designing a semiconductor device according to claim 7, wherein: The first interconnection layer pattern further comprises: A spaced track is parallel to the first conductive element and the second conductive element, and the spaced track does not include both the conductive element and the dummy pattern.

9. The method for designing a semiconductor device according to claim 8, wherein: The spaced trace is disposed between the first conductive element and the second conductive element.

10. A method for defining a conductive pattern layout of a semiconductor device design, characterized in that: The method comprises the following steps: A first design rule is set for an end-to-end spacing requirement of an open area between adjacent first conductive elements and second conductive elements; identifying a first open area in an initial conductive pattern layout that does not comply with the first design rule; selecting a first dummy pattern for covering a first portion of the first open area so that a remaining second open area complies with the first design rule; and The first dummy pattern is disposed in the first open area to generate a modified conductive pattern layout.

11. The method for defining a conductive pattern layout of a semiconductor device design as claimed in claim 10, wherein: Also includes: Setting a second design rule according to a maximum area requirement of the first dummy pattern; identifying a first dummy pattern in a revised conductive pattern layout that does not comply with the second design rule; selecting a second dummy pattern to replace the first dummy pattern, the second dummy pattern comprising a plurality of dummy pattern elements, wherein each of the plurality of dummy pattern elements complies with the second design rule; and The first dummy pattern is replaced with the second dummy pattern to generate the revised conductive pattern layout.

12. The method for defining a conductive pattern layout of a semiconductor device design as claimed in claim 11, wherein: Also includes: identifying a third open region having an end-to-end spacing length L3 that does not comply with the first design rule; and A third dummy pattern conforming to the second design rule is generated, whereby the third dummy pattern is placed in the third open area leaving a remaining fourth open area, the remaining fourth open area conforming to the first design rule.

13. The method for defining a conductive pattern layout of a semiconductor device design as claimed in claim 12, wherein: Also includes: The generated third dummy pattern is stored in a memory device so as to be subsequently retrieved and laid out in a second initial interconnection layer pattern, wherein the second initial interconnection layer pattern has an open space having an end-to-end spacing length of L3.

14. A semiconductor element, characterized in that: Include: An interconnect pattern, the pattern comprising: Multiple parallel tracks; a first conductor and a second conductor aligned with a first trace, the first conductor and the second conductor separated by an open space; and A first dummy pattern is aligned with the first trace and disposed in the open space, wherein the first dummy pattern establishes an end-to-end spacing distance between the first conductor and the second conductor within an end-to-end spacing requirement of the semiconductor device.

15. The semiconductor device according to claim 14, wherein: The first dummy pattern is in direct electrical contact with the first conductor, and The first dummy pattern is electrically isolated from the second conductor.

16. The semiconductor device according to claim 14, wherein: The first dummy pattern is electrically isolated from both the first conductor and the second conductor.

17. The semiconductor device according to claim 14, wherein: Also includes: A second dummy pattern is aligned with a second track, the second dummy pattern comprising a plurality of adjacent conductive elements.

18. The semiconductor device according to claim 17, wherein: Also includes: A spaced track is parallel to the first track and the second track and is arranged between the first track and the second track.

19. The semiconductor device according to claim 17, wherein: Also includes: A third dummy pattern includes a plurality of conductive elements aligned with a third track, and the third track is arranged adjacent to the first track.

20. The semiconductor device according to claim 19, wherein: The plurality of conductive elements including the second dummy pattern define a first array; and The plurality of conductive elements including the third dummy pattern define a second array, wherein the first array and the second array are arranged in a staggered offset configuration.

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