Semiconductor device

Abstract

A semiconductor device includes: a substrate; a first insulating interlayer located on the substrate; a first wiring located in the first insulating interlayer on the substrate; an insulating pattern located on a portion of the first insulating interlayer adjacent to the first wiring, the insulating pattern having vertical sidewalls and comprising a low dielectric material; an etch stop structure located on the first wiring and the insulating pattern; a second insulating interlayer located on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] Korean Patent Application No. 10-2018-0116855, filed on October 1, 2018, in the Korean Intellectual Property Office (KIPO), entitled “Semiconductor Devices and Methods of Manufacturing the Same,” is hereby incorporated by reference in its entirety. Technical Field

[0003] Embodiments relate to semiconductor devices and methods of manufacturing the same. Background Art

[0004] A via may be formed below the wiring located at the upper level to contact an upper surface of one of the wirings located at the lower level. Summary of the Invention

[0005] An embodiment can be implemented by providing a semiconductor device, comprising: a substrate; a first insulating interlayer located on the substrate; a first wiring located in the first insulating interlayer on the substrate; an insulating pattern located on a portion of the first insulating interlayer adjacent to the first wiring, the insulating pattern having vertical sidewalls and comprising a low dielectric material; an etch stop structure located on the first wiring and the insulating pattern; a second insulating interlayer located on the etch stop structure; and a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring.

[0006] An embodiment can be implemented by providing a semiconductor device, which includes: a substrate; a wiring located on the substrate; a first insulating interlayer located on the substrate, the first insulating interlayer covering at least a portion of a side wall of the wiring, and an upper portion of the first insulating interlayer having a higher carbon concentration than the carbon concentration of other portions of the first insulating interlayer; an insulating pattern located on the first insulating interlayer, the insulating pattern comprising a low dielectric material; an etch stop layer located on the wiring and the insulating pattern; a second insulating interlayer located on the etch stop layer; and a via extending through the second insulating interlayer and the etch stop layer to contact the upper surface of the wiring.

[0007] An embodiment can be implemented by providing a semiconductor device, which includes: a substrate, including a first region and a second region; a first insulating interlayer, located on the substrate; a first wiring, located in the first insulating interlayer on the first region of the substrate; a second wiring, located in the first insulating interlayer on the second region of the substrate; an insulating pattern, located on a portion of the first insulating interlayer adjacent to the first wiring on the first region of the substrate; an etch stop structure, located on the first insulating interlayer, the first wiring, the second wiring and the insulating pattern; a second insulating interlayer, located on the etch stop structure; and a via, extending through the second insulating interlayer and the etch stop structure on the first region of the substrate to contact the upper surface of the first wiring, wherein the insulating pattern is not formed on the second region of the substrate.

[0008] An embodiment can be implemented by providing a method for manufacturing a semiconductor device, the method comprising: forming a wiring in a first insulating interlayer on a substrate; forming a direct self-assembly (DSA) layer comprising a first pattern and a second pattern, the first pattern being arranged on the wiring and the second pattern being arranged on the first insulating interlayer; removing the second pattern to form a first opening, thereby exposing an upper surface of the first insulating interlayer; forming an insulating pattern to fill the first opening, the insulating pattern comprising a low dielectric material; removing the first pattern to form a second opening, thereby exposing the upper surface of the wiring; forming an etch stop structure on the exposed upper surface of the wiring and on the sidewalls and lower surface of the insulating pattern; forming a second insulating interlayer on the etch stop structure to fill the second opening; and forming a via through the second insulating interlayer and the etch stop structure, the via contacting the upper surface of the wiring.

[0009] An embodiment can be implemented by providing a method for manufacturing a semiconductor device, the method comprising: forming a first insulating interlayer on a substrate including a first region and a second region, so that the first insulating interlayer contains a first wiring located on the first region of the substrate and a second wiring located on the second region of the substrate; forming a mask on the first insulating interlayer and the second wiring to cover the second region of the substrate; forming an insulating pattern on a portion of the first insulating interlayer located on the first region of the substrate; removing the mask; forming an etch stop structure on the upper surface of the first insulating interlayer, the upper surface of the first wiring, the upper surface of the second wiring, and the sidewalls and upper surface of the insulating pattern; forming a second insulating interlayer on the etch stop structure; and forming a path through the second insulating interlayer and the etch stop structure so that the path contacts the upper surface of the first wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0011] Figures 1 to 10 Cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0012] Figure 11 A cross-sectional view of a semiconductor device according to an exemplary embodiment is shown.

[0013] Figures 12 to 14 Cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0014] Figures 15 to 20 Cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0015] Figures 21 to 24 Cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0016] [Explanation of Symbols]

[0017] 100: substrate

[0018] 110: First insulation interlayer

[0019] 115: First groove

[0020] 120: First barrier layer

[0021] 125: First barrier pattern

[0022] 130: First lining layer

[0023] 135: First lining

[0024] 140: First metal layer

[0025] 145: First Metal Pattern

[0026] 155: First wiring

[0027] 160: High carbon concentration area / carbon-containing layer

[0028] 170: First Pattern

[0029] 180: Second pattern

[0030] 190: Direct Self-Assembly (DSA) Layer

[0031] 200: First opening

[0032] 210: First insulation pattern

[0033] 220: Second opening

[0034] 230: Etch stop structure

[0035] 232: First etch stop layer

[0036] 234: Second etch stop layer

[0037] 240: Second insulation interlayer

[0038] 250: Second barrier pattern

[0039] 260: Second lining

[0040] 270: Second metal pattern

[0041] 280: Passage

[0042] 290: Third Barrier Pattern

[0043] 300: Third lining

[0044] 310: Third metal pattern

[0045] 320: Second wiring

[0046] 400: First mask

[0047] 410: Second mask

[0048] 430: Second insulation pattern

[0049] D1: First distance

[0050] D2: Second distance

[0051] DH1: First horizontal direction / horizontal direction

[0052] DH2: horizontal direction

[0053] DV: vertical direction

[0054] I: District 1

[0055] II: Second District DETAILED DESCRIPTION

[0056] Figures 1 to 10 Cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to an exemplary embodiment.

[0057] Reference Figure 1, a first insulating interlayer 110 may be formed on the substrate 100 , an upper portion of the first insulating interlayer 110 may be removed to form a first trench 115 , and a wiring layer structure may be formed on the first insulating interlayer 110 to fill the first trench 115 .

[0058] The substrate 100 may include a semiconductor material (e.g., silicon, germanium, silicon-germanium, etc.) or a Group III-V compound (e.g., gallium phosphide (GaP), gallium arsenide (GaAs), gallium antimonide (GaSb), etc.). In one embodiment, the substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0059] In an embodiment, various elements (eg, gate structures, source / drain layers, contact plugs, etc.) may be formed on the substrate 100 and may be covered by an insulating layer between the substrate 100 and the first insulating interlayer 110 .

[0060] In an embodiment, the first insulating interlayer 110 may include a low dielectric material (e.g., having a dielectric constant of 4.2 or less). The low dielectric material may include, for example, fluorine-doped silicon oxide (e.g., SiOF), carbon-doped silicon oxide (e.g., SiOCH), an inorganic polymer (e.g., porous silicon oxide), hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc., or a spin-on organic polymer.

[0061] The first trench 115 may be formed at least at an upper portion of the first insulating interlayer 110. In an embodiment, the first trench 115 may extend (e.g., completely) through the first insulating interlayer 110. For example, the first trench 115 may expose the upper surface of the element below the first insulating interlayer 110, and the wiring layer structure filling the first trench 115 may contact and be electrically connected to the element.

[0062] The wiring layer structure may include a first barrier layer 120, a first liner layer 130, and a first metal layer 140 (for example, stacked sequentially along the vertical direction DV in the order described). In an embodiment, the first barrier layer 120 may be conformally formed on the inner wall of the first trench 115 and the upper surface of the first insulating interlayer 110, the first liner layer 130 may be conformally formed on the first barrier layer 120, and the first metal layer 140 may be formed on the first liner layer 130 to fill the first trench 115.

[0063] The first barrier layer 120 may include metal nitride, such as titanium nitride, tantalum nitride, etc., the first liner layer 130 may include metal, such as cobalt, ruthenium, etc., and the first metal layer 140 may include low-resistance metal, such as copper, aluminum, tungsten, etc.

[0064] Reference Figure 2 The wiring layer structure may be planarized until the upper surface of the first insulating interlayer 110 is exposed, and thus the first wiring 155 may be formed in the first trench 115. For example, the upper surface of the first insulating interlayer 110 may be coplanar with the upper surface of the first wiring 155.

[0065] The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch-back process.

[0066] The first wiring 155 may include a first metal pattern 145 , a first liner 135 covering a lower (eg, substrate-facing) surface and sidewalls of the first metal pattern 145 , and a first barrier pattern 125 covering a lower surface and sidewalls of the first liner 135 .

[0067] When the first liner layer 130 includes cobalt, more of the first liner layer 130 can be removed during the planarization process than the first barrier layer 120. For example, the height of the uppermost surface of the first liner 135 can be lower than the height of the uppermost surface of the first barrier pattern 125 (e.g., closer to the substrate 100 along the vertical direction DV). In one embodiment, the upper surface of the first metal pattern 145 adjacent to one or more edges of the first liner 135 can be lower than the upper surface of the central portion of the first metal pattern 145. For example, the upper surface of the central portion of the first metal pattern 145 and the uppermost surface of the first barrier pattern 125 can be higher than the upper surface of the edge of the first metal pattern 145 (e.g., farther away from the substrate 100 along the vertical direction DV) and higher than the uppermost surface of the first liner 135.

[0068] Reference Figure 3 , a first surface treatment process and a second surface treatment process may be performed on the upper surface of the first wiring 155 and the upper portion of the first insulating interlayer 110, respectively. For example, the first surface treatment process may be performed on the upper surface of the first wiring 155, and the second surface treatment process may be performed on the upper portion of the first insulating interlayer 110.

[0069] In an embodiment, the first surface treatment process may include reducing or removing metal oxide on or at the upper surface of the first wiring 155 .

[0070] In an embodiment, the second surface treatment process may include doping carbon into the upper portion of the first insulating interlayer 110. In an embodiment, when the first insulating interlayer 110 already contains carbon (e.g., SiOCH), the carbon concentration of the upper portion of the first insulating interlayer 110 may be higher than the carbon concentration of the other portions of the first insulating interlayer 110. For example, a high carbon concentration region may be formed. In an embodiment, when the first insulating interlayer 110 does not already contain carbon, for example, when the first insulating interlayer 110 contains SiOF, a carbon-containing layer may be formed at the upper portion of the first insulating interlayer 110. Hereinafter, both the high carbon concentration region or the carbon-containing layer may be represented by reference numeral 160. In an embodiment, the high carbon concentration region 160 or the carbon-containing layer 160 may be hydrophobic, i.e., not sufficiently coupled with water.

[0071] Reference Figure 4 A direct self-assembly process may be performed to form a direct self-assembly (DSA) layer 190 on the first wiring 155 and the first insulating interlayer 110. In an embodiment, the direct self-assembly layer 190 may be formed by applying a composition including a block copolymer (BCP) on the first wiring 155 and the first insulating interlayer 110 using a spin coating process.

[0072] The block copolymer may be a copolymer composed of two polymer units having different chemical properties. For example, the block copolymer may be synthesized by copolymerizing a first polymer unit with a second polymer unit using, for example, anionic polymerization or cationic polymerization. In an embodiment, the first polymer unit may have a higher hydrophilicity than the second polymer unit.

[0073] In an embodiment, the first polymer unit may include, for example, polymethylmethacrylate (PMMA), polydimethylsiloxane (PDMS), polyvinylpyrrolidone (PVP), polyethylene oxide (PEO), polylactic acid (PLA), or polyimide (PI). In an embodiment, the second polymer unit may include, for example, polystyrene (PS).

[0074] In an embodiment, the block copolymer may be represented by PS-b-PMMA, PS-b-PDMS, PS-b-PVP, PS-b-PEO, PS-b-PLA, or PS-b-PI. Hereinafter, an example in which the first polymer unit and the second polymer unit are PMMA and PS, respectively, and the block copolymer is PS-b-PMMA is described. In this case, the block copolymer may include a first pattern 170 comprising PMMA and a second pattern 180 comprising PS.

[0075] In an embodiment, the first pattern 170 and the second pattern 180 can be self-aligned on the upper surface of the first wiring 155 and the upper surface of the first insulating interlayer 110, respectively. The metal oxide on the upper surface of the first wiring 155 can be removed by the first surface treatment process, and the first pattern 170 can be easily arranged on the first wiring 155. In addition, the high carbon concentration region 160 or the carbon-containing layer 160 (having hydrophobicity) can be formed on the upper portion of the first insulating interlayer 110 by the second surface treatment process, and the second pattern 180 can be easily arranged on the first insulating interlayer 110.

[0076] Reference Figure 5 , the second pattern 180 of the direct self-assembly layer 190 may be removed, and a first opening 200 may be formed to expose the upper surface of the first insulating interlayer 110, for example, the upper surface of the high carbon concentration region 160 or the carbon-containing layer 160. In an embodiment, the second pattern 180 may be removed by a stripping process.

[0077] Reference Figure 6 , a first insulating pattern 210 may be formed on the exposed upper surface of the first insulating interlayer 110 to fill the first opening 200. In an embodiment, the first insulating pattern 210 may be formed by forming a first insulating layer on the exposed upper surface of the first insulating interlayer 110 and the upper surface of the first pattern 170 of the direct self-assembled layer 190 to fill the first opening 200, and planarizing the first insulating layer until the upper surface of the first pattern 170 is exposed.

[0078] In one embodiment, the first insulating layer can be formed by a flowable chemical vapor deposition (FCVD) process and can include a low-dielectric material having a dielectric constant of 4.2 or less. In one embodiment, the first insulating pattern 210 can include, for example, fluorine-doped silicon oxide (e.g., SiOF), carbon-doped silicon oxide (e.g., SiOCH), an inorganic polymer (e.g., porous silicon oxide), hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), a spin-on organic polymer, etc. In one embodiment, the first insulating pattern 210 can include a material substantially the same as that of the underlying first insulating interlayer 110. In one embodiment, the material of the first insulating pattern 210 can be distinguished from the material of the first insulating interlayer by the high carbon concentration region 160 or the carbon-containing layer 160.

[0079] Reference Figure 7 , the first pattern 170 of the direct self-assembly layer 190 may be removed, and the second opening 220 may be formed to expose the upper surface of the first wiring 155. In an embodiment, the first pattern 170 may be removed by a curing process using ultraviolet rays.

[0080] Reference Figure 8 After forming an etch stop structure 230 on the exposed upper surface of the first wiring 155, the sidewall of the second opening 220 and the upper surface of the first insulating pattern 210, a second insulating interlayer 240 (filling the remaining portion of the second opening 220) can be formed on the etch stop structure 230 to reach a sufficient height.

[0081] In one embodiment, the etch stop structure 230 may include a first etch stop layer 232 and a second etch stop layer 234 stacked in sequence. The first etch stop layer 232 may include, for example, aluminum oxide, aluminum nitride, etc., and the second etch stop layer 234 may include, for example, silicon carbide, silicon nitride, silicon carbonitride, etc. In one embodiment, the stacking order of the first etch stop layer 232 and the second etch stop layer 234 in the etch stop structure 230 may be reversed (for example, the second etch stop layer 234 may be located between the substrate 100 and the first etch stop layer 232).

[0082] The second insulating interlayer 240 may include a low dielectric material having a dielectric constant of 4.2 or less. In embodiments, the second insulating interlayer 240 may include, for example, fluorine-doped silicon oxide (e.g., SiOF), carbon-doped silicon oxide (e.g., SiOCH), an inorganic polymer (e.g., porous silicon oxide), hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), a spin-on organic polymer, etc.

[0083] Reference Figure 9A via 280 may be formed (extending along the vertical direction DV through the lower portion of the second insulating interlayer 240 to contact the upper surface of the first wiring 155). A second wiring 320 may also be formed (extending through the upper portion of the second insulating interlayer 240 to contact the upper surface of the via 280) to complete the fabrication of the semiconductor device.

[0084] In an embodiment, the via 280 and the second wiring 320 can be formed simultaneously by a dual damascene process and can be integrally formed with each other. For example, the via 280 and the second wiring 320 can be formed by forming a via hole extending through the lower portion of the second insulating interlayer 240 and the etch stop structure 230 to expose the upper surface of the first wiring 155, and a second trench extending through the upper portion of the second insulating interlayer 240 (to connect to the via hole), sequentially forming a second barrier layer and a second liner layer on the inner walls of the via hole and the second trench, the exposed upper surface of the first wiring 155, and the upper surface of the second insulating interlayer 240, forming a second metal layer on the second liner layer to fill the via hole and the second trench, and planarizing the second metal layer, the second liner layer, and the second barrier layer until the upper surface of the second insulating interlayer 240 is exposed.

[0085] For example, the via 280 may include a second metal pattern 270, a second liner 260 (covering the lower surface and sidewalls of the second metal pattern 270), and a second barrier rib pattern 250 (covering the lower surface and sidewalls of the second liner 260 and contacting the upper surface of the first wiring 155). In one embodiment, the second wiring 320 may include a third metal pattern 310 (contacting the upper surface of the second metal pattern 270), a third liner 300 (covering a portion of the lower surface and sidewalls of the third metal pattern 310), and a third barrier rib pattern 290 (covering the lower surface and sidewalls of the third liner 300 along a vertical direction DV). In one embodiment, the second metal pattern 270 and the third metal pattern 310, the second liner 260 and the third liner 300, and the second barrier rib pattern 250 and the third barrier rib pattern 290 may each be integrally formed to contact each other and include the same material. The lower surface of the via 280 may, for example, contact (e.g., directly contact) the upper surface of the wiring 155 along the vertical direction DV.

[0086] The second barrier layer may include metal nitride, such as titanium nitride, tantalum nitride, etc., the second liner layer may include metal, such as cobalt, ruthenium, etc., and the second metal layer may include low-resistance metal, such as copper, aluminum, tungsten, etc.

[0087] Figure 10Misalignment between the via 280 and the first wiring 155 is shown, wherein the via 280 is not fully aligned with the upper surface of the first wiring 155. For example, the via 280 may contact not only the upper surface of the first wiring 155, but also the sidewalls and upper surface of the first insulation pattern 210 adjacent to the via 280.

[0088] If first insulating pattern 210 is not formed, via 280 may contact the upper surface of first insulating interlayer 110, and the minimum distance between via 280 and one of the first wirings 155 that is not in contact with via 280 but adjacent to via 280 will be a first distance D1 along first horizontal direction DH1. According to embodiments, first insulating pattern 210 may be formed, and the minimum distance between via 280 and one of the first wirings 155 that is not in contact with via 280 but adjacent to via 280 may be a second distance D2 along a diagonal line between first horizontal direction DH1 and vertical direction DV. Second distance D2 may be greater than first distance D1. Consequently, the electrical short circuit margin between via 280 and adjacent first wirings 155 may be advantageously increased, thereby maintaining an acceptable misaligned structure.

[0089] exist Figure 9 and Figure 10 The semiconductor device described in the foregoing may have the following characteristics.

[0090] For example, a first insulating pattern 210 may be formed on the first insulating interlayer 110 adjacent to the first wiring 155. The first insulating pattern 210 may be formed by performing a direct self-assembly process, and the first insulating pattern 210 may have substantially vertical sidewalls (e.g., sidewalls perpendicular to the surface of the substrate 100). For example, the sidewalls may be vertical within manufacturing tolerances. In embodiments, a first surface treatment process and a second surface treatment process may be performed before the direct self-assembly process, and a high carbon concentration region 160 or a carbon-containing layer 160 may be formed at an upper portion of the first insulating interlayer 110.

[0091] A first insulating pattern 210 and a second insulating interlayer 240 may be formed on the first insulating interlayer 110. Both the first insulating pattern 210 and the second insulating interlayer 240 may include a low-dielectric material having a dielectric constant of 4.2 or less. For example, when a plurality of first wirings 155 are formed in one direction, an undesirable increase in parasitic capacitance between the first wirings 155 in the horizontal directions DH1 and DH2 and in parasitic capacitance between the first wirings 155 and the second wirings 320 in the vertical direction DV may be prevented.

[0092] Figure 11 1 shows a cross-sectional view of a semiconductor device according to an exemplary embodiment. Figure 9The semiconductor devices described in the accompanying drawings are substantially the same or similar. Therefore, the same reference numerals refer to the same elements, and the same elements may not be described in detail herein.

[0093] Reference Figure 11 The top surface of the first insulating interlayer 110 may be lower than the top surface of the first wiring 155 (e.g., closer to the substrate 100). For example, the bottom surface of the first insulating pattern 210 on the first insulating interlayer 110 may also be lower than the top surface of the first wiring 155.

[0094] This can be done by Figure 1 and Figure 2 The process described in the above is then performed by removing the upper portion of the first insulating interlayer 110 .

[0095] Since the height of the upper surface of the first insulating interlayer 110 is reduced, the height of the upper surface of the high carbon concentration region 160 or the carbon containing layer 160 may also be reduced to be lower than that of the upper surface of the first wiring 155 .

[0096] Figures 12 to 14 A cross-sectional view showing various stages in a method of manufacturing a semiconductor device according to an exemplary embodiment. The method of manufacturing a semiconductor device includes: Figures 1 to 10 The processes described in are substantially the same or similar processes, and the substantially the same or similar processes may not be described in detail herein.

[0097] Reference Figure 12 , executable with Figure 1 and Figure 2 The process described in is substantially the same or similar process.

[0098] According to the present embodiment, the first liner layer 130 may include ruthenium instead of cobalt. After performing a planarization process, the height of the uppermost surface of the first liner 135 and the height of the upper surface of the first metal pattern 145 may be lower than the height of the uppermost surface of the first barrier rib pattern 125. In one embodiment, the upper surface of the edge of the first metal pattern 145 (adjacent to the first liner 135) may be higher than the upper surface of the central portion of the first metal pattern 145. For example, the upper surface of the central portion of the first metal pattern 145 may be lower (e.g., closer to the substrate 100) than the upper surface of the edge of the first metal pattern 145 and the uppermost surface of the first barrier pattern 125.

[0099] Reference Figure 13 , executable with Figures 3 to 9 The processes described in are substantially the same or similar processes to complete the manufacture of semiconductor devices.

[0100] Similar to Figure 10 , Figure 14A misalignment between the via 280 and the first wiring 155 is shown, wherein the via 280 is not fully aligned with the upper surface of the first wiring 155 .

[0101] Figures 15 to 20 A cross-sectional view showing various stages in a method of manufacturing a semiconductor device according to an exemplary embodiment. The method of manufacturing a semiconductor device includes: Figures 1 to 10 The processes described in the foregoing are substantially the same or similar processes, and thus the same reference numerals refer to the same elements, and the same elements may not be described in detail herein.

[0102] Reference Figure 15 , executable with Figure 1 and Figure 2 The process described in is substantially the same or similar process.

[0103] According to the present embodiment, the substrate 100 may include a first region I and a second region II. A mask structure may be formed on the first wiring 155 and the first insulating interlayer 110 , the mask structure covering the second region II of the substrate 100 .

[0104] In an embodiment, the mask structure may include a first mask 400 and a second mask 410 stacked sequentially. In an embodiment, the first mask 400 may include, for example, aluminum nitride, and the second mask 410 may include, for example, silicon nitride.

[0105] Executable Figure 3 The first surface treatment process and the second surface treatment process described in the embodiment are used to remove the metal oxide on the upper surface of the first wiring 155 on the first region I of the substrate 100, and a high carbon concentration region 160 or a carbon-containing layer 160 can be formed at the upper portion of the first insulating interlayer 110 (also on the first region I of the substrate 100).

[0106] Reference Figure 16 , executable with Figures 4 to 7 The process described in is substantially the same or similar process.

[0107] Therefore, a first insulating pattern 210 can be formed on the upper surface of the first insulating interlayer 110 (for example, the upper surface of the high carbon concentration region 160 or the carbon-containing layer 160 on the first region I of the substrate 100), and a second opening 220 can be formed to expose the upper surface of the first wiring 155 on the first region I of the substrate 100.

[0108] Reference Figure 17 , the mask structure on the second region II of the substrate 100 may be removed, and portions of the first wiring 155 and the first insulating interlayer 110 on the second region II of the substrate 100 may be exposed.

[0109] Reference Figure 18 , executable with Figure 8 The process described in is substantially the same or similar process.

[0110] For example, an etch stop structure 230 may be formed on the upper surface of the first wiring 155, the sidewalls of the second opening 220, and the upper surface of the first insulating pattern 210 in the first region I of the substrate 100, and on the upper surface of the first wiring 155 and the upper surface of the first insulating interlayer 110 in the second region II of the substrate 100. A second insulating interlayer 240 may be formed on the etch stop structure 230.

[0111] Reference Figure 19 , executable with Figure 9 The processes described in are substantially the same or similar processes to complete the manufacture of semiconductor devices.

[0112] According to the present embodiment, the via 280 may be formed only on the first region I of the substrate 100 , and may contact only the first wiring 155 on the first region I of the substrate 100 .

[0113] Similar to Figure 10 , Figure 20 A misalignment between the via 280 and the first wiring 155 is shown, wherein the via 280 is not fully aligned with the upper surface of the first wiring 155 .

[0114] exist Figure 19 and Figure 20 In the semiconductor device shown in FIG, the first insulating pattern 210 may not be formed on the second region II of the substrate 100 where the via 280 is not formed. For example, the first insulating pattern 210 may be formed to increase the electrical short-circuit margin between the via 280 and the adjacent first wiring 155, and may not be formed on the second region II of the substrate 100 where the via 280 is not formed.

[0115] Figures 21 to 24 A cross-sectional view showing various stages in a method of manufacturing a semiconductor device according to an exemplary embodiment. The method of manufacturing a semiconductor device includes: Figures 15 to 20 The processes described in are substantially the same or similar processes, and the substantially the same or similar processes may not be described in detail herein.

[0116] Reference Figure 21 , executable with Figure 15 The process described in is substantially the same or similar process.

[0117] In an embodiment, the first surface treatment process and the second surface treatment process may not be performed.

[0118] Reference Figure 21, the second insulating pattern 430 may be formed by a selective deposition process only on a portion of the first insulating interlayer 110 on the first region I of the substrate 100. In an embodiment, the second insulating pattern 430 may have a rounded or inclined sidewall.

[0119] In an embodiment, the second insulating pattern 430 may include a high dielectric material, such as aluminum oxide, aluminum nitride, or the like.

[0120] Reference Figures 22 to 24 , executable with Figures 18 to 20 The processes described in are substantially the same or similar processes to complete the manufacture of semiconductor devices.

[0121] exist Figure 23 and Figure 24 In the semiconductor device shown in FIG, the second insulating pattern 430 may not be formed on the second region II of the substrate 100 on which the via 280 is not formed. Figure 9 and Figure 10 The semiconductor device shown includes first and second insulating patterns 210 and 430, which may include a high-dielectric material. For example, if the second insulating pattern 430 is also formed on the second region II of the substrate 100, the resistor-capacitor (RC) delay characteristics may be degraded due to an increase in parasitic capacitance. According to this embodiment, the second insulating pattern 430 including a high-dielectric material can be formed only on the first region I of the substrate 100, where the via 280 is formed, so that the increase in parasitic capacitance can be completely suppressed.

[0122] The semiconductor device can be applied to various types of memory devices and systems including wiring structures. For example, the semiconductor device can be applied to a logic device including a wiring structure, such as a central processing unit (CPU), a main processing unit (MPU), or an application processor (AP). In addition, the semiconductor device can be applied to a volatile memory device including a wiring structure (such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device) or a non-volatile memory device (such as a flash memory device, a phase change random access memory (PRAM) device, a magnetic random access memory (MRAM) device, a resistive random access memory (RRAM) device, etc.).

[0123] To summarize and review, a plurality of wirings can be formed at minute intervals, and an electrical short circuit may not occur between a via and another wiring located at a lower level among the wirings.

[0124] One or more embodiments may provide semiconductor devices including wirings and vias having improved characteristics.

[0125] One or more embodiments may provide a method of manufacturing a semiconductor device including wirings and vias having improved characteristics.

[0126] In a semiconductor device according to an exemplary embodiment, an insulating pattern may be formed on an insulating interlayer, and the distance between a via connected to an upper wiring and a lower wiring adjacent to the via may be increased, thereby increasing the electrical short circuit margin. For example, the upper surface of the insulating pattern may be higher than the upper surface of the wiring, thereby increasing the distance between a via associated with a wiring and a wiring adjacent to the wiring (for example, even if the vias are misaligned) and reducing or preventing electrical short circuits. In addition, the insulating pattern may include a low-dielectric material, thereby preventing an increase in parasitic capacitance between lower wirings and between upper and lower wirings.

[0127] One or more embodiments may provide a semiconductor device including a wiring and a via and a method of manufacturing the same.

[0128] Although the corresponding plan views and / or stereograms for a particular cross-sectional view(s) may not be shown, the cross-sectional views of the device structures shown herein provide support for multiple device structures extending in two different directions as would be shown in the plan views and / or extending in three different directions as would be shown in the stereograms. The two different directions may or may not be orthogonal to each other. The three different directions may include a third direction that may be orthogonal to the two different directions. The multiple device structures may be integrated into the same electronic device. For example, when a device structure (e.g., a memory cell structure or a transistor structure) is shown in a cross-sectional view, the electronic device may include multiple such device structures (e.g., a memory cell structure or a transistor structure), as would be shown by a plan view of the electronic device. The multiple device structures may be arranged in an array and / or a two-dimensional pattern.

[0129] Exemplary embodiments have been disclosed herein, and although specific terms are employed, such terms are to be used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art as of the time of filing this application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise indicated. Accordingly, various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device comprising: substrate; a first insulating interlayer, located on the substrate; a first wiring, located in the first insulating interlayer on the substrate; an insulating pattern located on a portion of the first insulating interlayer adjacent to the first wiring, the insulating pattern having vertical sidewalls and comprising a low dielectric material; an etch stop structure, located on the first wiring and the insulating pattern; a second insulating interlayer, located on the etch stop structure; as well as a via extending through the second insulating interlayer and the etch stop structure to contact an upper surface of the first wiring, The first wiring includes a first metal pattern, the first metal pattern has a curved top surface, and an edge area of the curved top surface is located below or above an interface between the first insulating interlayer and the insulating pattern, and The etch stop structure covers the sidewall of the insulation pattern. 2 . The semiconductor device according to claim 1 , wherein a portion of the first insulating interlayer adjacent to the insulating pattern has a higher carbon concentration than a carbon concentration of other portions of the first insulating interlayer. 3 . The semiconductor device according to claim 1 , wherein the insulating pattern comprises SiOF, SiOCH, porous silicon oxide, hydrogen silsesquioxane, methyl silsesquioxane, or a spin-on organic polymer. 4 . The semiconductor device according to claim 1 , wherein the first insulating interlayer and the second insulating interlayer each comprise a low dielectric material. 5 . The semiconductor device according to claim 1 , wherein the etch stop structure comprises a first etch stop layer and a second etch stop layer stacked in sequence.

6. The semiconductor device according to claim 5, wherein: The first etch stop layer comprises aluminum oxide or aluminum nitride, and The second etch stop layer includes silicon carbide, silicon nitride or silicon carbonitride. 7 . The semiconductor device according to claim 1 , wherein an upper surface of the first insulating interlayer is coplanar with the upper surface of the first wiring. 8 . The semiconductor device according to claim 1 , wherein an upper surface of the first insulating interlayer is closer to the substrate than the upper surface of the first wiring. 9 . The semiconductor device according to claim 1 , wherein the first insulating interlayer has a flat upper surface.

10. The semiconductor device according to claim 1, wherein the first wiring comprises: the first metal pattern; as well as The first barrier rib pattern covers the lower surface and sidewalls of the first metal pattern.

11. The semiconductor device according to claim 10, wherein: The first wiring further includes a first liner located between the first metal pattern and the first barrier rib pattern, the first liner containing cobalt, and An upper surface of a central portion of the first metal pattern and an uppermost surface of the first barrier rib pattern are farther away from the substrate than an upper surface of an edge region of the first metal pattern and an uppermost surface of the first liner.

12. The semiconductor device according to claim 10, wherein: The first wiring further includes a first liner located between the first metal pattern and the first barrier rib pattern, the first liner containing ruthenium, and An upper surface of a central portion of the first metal pattern is closer to the substrate than an upper surface of an edge region of the first metal pattern and an uppermost surface of the first barrier rib pattern. 13 . The semiconductor device according to claim 1 , wherein the via contacts the upper surface of the first wiring, and a sidewall and an upper surface of a portion of the insulating pattern adjacent to the first wiring. 14 . The semiconductor device according to claim 1 , further comprising a second wiring located on the via, the second wiring contacting the via.

15. The semiconductor device according to claim 1, wherein: The first wiring includes a plurality of first wirings spaced apart from each other in one direction, and The insulating pattern is located on a portion of the first insulating interlayer between the first wirings.

16. A semiconductor device comprising: substrate; wiring, located on the substrate; a first insulating interlayer located on the substrate, the first insulating interlayer covering at least a portion of a sidewall of the wiring, and an upper portion of the first insulating interlayer having a higher carbon concentration than a carbon concentration of other portions of the first insulating interlayer; an insulating pattern, located on the first insulating interlayer, wherein the insulating pattern comprises a low dielectric material; an etch stop layer, located on the wiring and the insulation pattern; a second insulating interlayer, located on the etch stop layer; as well as a via extending through the second insulating interlayer and the etch stop layer to contact the upper surface of the wiring, wherein the wiring comprises a metal pattern having a curved top surface, an edge region of the curved top surface being located below or above an interface between the first insulating interlayer and the insulating pattern, and The etch stop layer covers the sidewalls of the insulation pattern. 17 . The semiconductor device according to claim 16 , wherein the insulating pattern has a sidewall perpendicular to an upper surface of the substrate. 18 . The semiconductor device according to claim 16 , wherein the insulating pattern comprises SiOF, SiOCH, porous silicon oxide, hydrogen silsesquioxane, methyl silsesquioxane, or a spin-on organic polymer. 19 . The semiconductor device according to claim 16 , wherein an upper surface of the first insulating interlayer is closer to the substrate than the upper surface of the wiring. 20 . The semiconductor device according to claim 16 , wherein the via contacts the upper surface of the wiring, and a sidewall and an upper surface of a portion of the insulation pattern adjacent to the wiring.

21. A semiconductor device comprising: a substrate comprising a first region and a second region; a first insulating interlayer, located on the substrate; a first wiring located in the first insulating interlayer on the first region of the substrate; a second wiring located in the first insulating interlayer on the second region of the substrate; an insulating pattern located on a portion of the first insulating interlayer on the first region of the substrate adjacent to the first wiring, the insulating pattern comprising a low dielectric material; an etch stop structure, located on the first insulating interlayer, the first wiring, the second wiring, and the insulating pattern; a second insulating interlayer, located on the etch stop structure; as well as a via extending through the second insulating interlayer and the etch stop structure on the first region of the substrate to contact an upper surface of the first wiring, wherein the insulating pattern is not formed on the second region of the substrate, wherein the insulating pattern has a sidewall perpendicular to the upper surface of the substrate, The first wiring includes a first metal pattern, the first metal pattern has a curved top surface, and an edge area of the curved top surface is located below or above an interface between the first insulating interlayer and the insulating pattern, and The etch stop structure covers the sidewall of the insulation pattern.

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