Capacitor array structure, semiconductor device and method for manufacturing the same

Abstract

The present invention provides a capacitor array structure, a semiconductor device and a manufacturing method thereof. A boundary protection layer formed of an insulating material is added on the basis of the boundary of the original capacitor array structure, which can separate the cracks generated due to the uneven boundary of the capacitor array structure in the manufacturing process of the conductive contact plug from the boundary of the capacitor array structure, thereby avoiding the problem of short circuit between the conductive contact plug and the boundary of the capacitor array structure caused by the cracks and improving the reliability of the capacitor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a capacitor array structure, a semiconductor device and a method for manufacturing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in a computer, which is composed of many repeated memory cells. Each memory cell usually includes a capacitor and a transistor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage. With the continuous evolution of the DRAM manufacturing process, the integration degree is continuously improved, the device size is continuously miniaturized, and the lateral area of the memory array formed by the memory cells on the substrate is also getting smaller and smaller. In order to enable the capacitor in the DRAM to increase or maintain a sufficiently high capacitance value, the height of the bottom electrode in the capacitor is usually increased to increase the contact area between the bottom electrode and the capacitor dielectric layer. However, with the increase in the height of the bottom electrode, the aspect ratio of the bottom electrode also increases accordingly, which is very likely to cause problems such as bending deformation or collapse of the bottom electrode, affecting the reliability of the device area.

[0003] Please refer to Figure 1, currently, during the formation process of the existing DRAM capacitor array structure, the stability is generally increased by adding a lateral continuous support layer for the electrode (including the bottom support layer 111, the middle support layer 112, and the top support layer 113). However, this will cause the boundary of the capacitor array structure in the device area 100A to be uneven, which will further cause an adverse impact on the capacitor array structure in the subsequent process, and thus affect the reliability of the DRAM. For example, in the subsequent process of forming the conductive contact plug 102 (CT), an interlayer dielectric layer will be deposited above and around the capacitor array structure for fabricating a contact hole for accommodating the conductive contact plug 102, and the interlayer dielectric layer deposited above and around the capacitor array structure will be etched to form the contact hole. Then, a metal conductive material will be filled in the contact hole to form the conductive contact plug 102. However, as the device size shrinks, the distance between the conductive contact plugs 102 above and around the capacitor array structure also becomes very small. This makes the thickness of the interlayer dielectric layer between the part of the contact hole protruding towards the periphery of the capacitor array structure in the uneven boundary of the capacitor array structure and the side wall of the contact hole very thin. During the process of etching the interlayer dielectric layer to form these peripheral contact holes, the interlayer dielectric layer around the uneven boundary of the capacitor array structure is unevenly stressed, which easily causes cracks (cracks) in the side wall of the contact hole. Then, when filling the metal conductive material corresponding to the conductive contact plug 102, on the one hand, it will exacerbate the increase of the crack and directly crack to the uneven boundary of the capacitor array structure. On the other hand, the filled metal conductive material will also fill into the crack, thereby causing a direct short circuit between the formed conductive contact plug 102 and the capacitor array boundary or between the conductive contact plugs 102, which affects the reliability of the DRAM. Therefore, it is necessary to protect the capacitance array boundary. Summary of the Invention

[0004] The purpose of the present invention is to provide a capacitor array structure, a preparation method thereof, a semiconductor device, and a preparation method thereof, which can insulate and protect the boundary of the capacitance array structure, block the short circuit problem between the plug and the capacitance array structure boundary caused by the cracks formed in the subsequent conductive contact plug process, and thus improve the device reliability.

[0005] To solve the above technical problems, the present invention provides a capacitor array structure, including:

[0006] A substrate having a device area for forming a capacitor array;

[0007] A lower electrode layer disposed on the device area of the substrate, and the lower electrode layer has a plurality of cylindrical structures arranged in an array;

[0008] A capacitor dielectric layer covering the inner and outer surfaces of the lower electrode layer;

[0009] An upper electrode layer, covering the surface of the capacitive dielectric layer;

[0010] An upper electrode filling layer; covering the surface of the upper electrode layer and filling the gaps in the upper electrode layer, the outer sidewall of the upper electrode filling layer having an uneven topography; and,

[0011] A boundary protection layer, the boundary protection layer covering at least the outer sidewall of the upper electrode filling layer, and the boundary protection layer being an insulating material.

[0012] Optionally, the capacitor array structure further includes an upper electrode covering layer, the upper electrode covering layer covering the surface of the upper electrode filling layer and having an uneven outer sidewall corresponding to the outer sidewall of the upper electrode filling layer; and the capacitive dielectric layer, the upper electrode layer, the upper electrode filling layer, and the upper electrode covering layer sequentially extend to cover the surface of the entire device area; the boundary protection layer covers at least the uneven outer sidewall of the upper electrode covering layer.

[0013] Optionally, the boundary protection layer covers the upper surface and the uneven outer sidewall of the upper electrode covering layer.

[0014] Optionally, the substrate further has a peripheral area located outside the device area, a conductive structure being formed in the peripheral area; the capacitor array structure further includes an interlayer dielectric layer, the interlayer dielectric layer not only covering the surface of the device area having the boundary protection layer, but also extending to cover the peripheral area; a conductive contact plug located in the device area and a conductive contact plug located in the peripheral area are formed in the interlayer dielectric layer, the conductive contact plug in the device area being in electrical contact with the upper electrode filling layer in the device area, and the conductive contact plug in the peripheral area being in electrical contact with the conductive structure in the peripheral area.

[0015] Optionally, the boundary protection layer extends to cover the surface of the peripheral area.

[0016] Optionally, the capacitor array structure further includes a lateral support layer, the lateral support layer being located on the substrate of the device area and laterally connecting the plurality of cylindrical structures of the lower electrode layer, wherein the uneven topography of the outer sidewall of the upper electrode filling layer corresponds to the lateral support layer outside the cylindrical structures of the lower electrode.

[0017] Optionally, the lateral support layer includes a top support layer, at least one intermediate support layer, and a bottom support layer, the top support layer being located at the outer periphery of the top of the cylindrical structure of the lower electrode layer, the intermediate support layer being located at the middle part of the cylindrical structure of the lower electrode layer, and the bottom support layer being located at the outer periphery of the bottom of the cylindrical structure of the lower electrode layer.

[0018] Optionally, a plurality of capacitive contact nodes are further formed in the substrate, and the lower electrode layer is connected to the corresponding contact nodes at the bottom of each of the cylindrical structures.

[0019] The present invention also provides a semiconductor device including the capacitor array structure of the present invention.

[0020] The present invention also provides a method for manufacturing a capacitor array structure, including:

[0021] Providing a substrate having a device region, and forming an alternately stacked sacrificial layer and a support layer on the substrate;

[0022] Etching the support layer and the sacrificial layer to form a plurality of capacitive holes in the device region, and the capacitive holes sequentially penetrate the support layer and the sacrificial layer to expose the surface of the substrate;

[0023] Forming a lower electrode layer on the side walls and bottom walls of the capacitive holes to form a plurality of cylindrical structures;

[0024] Removing the sacrificial layer and retaining the support layer, and the support layer connects the plurality of cylindrical structures of the lower electrode layer;

[0025] Sequentially forming a capacitive dielectric layer and an upper electrode layer on the inner and outer surfaces of the lower electrode layer;

[0026] Forming an upper electrode filling layer on the surface of the upper electrode layer, the upper electrode filling layer fills the gaps in the upper electrode layer, and the outer side wall of the upper electrode filling layer has an uneven morphology; and,

[0027] Forming a boundary protection layer on the upper electrode filling layer, the boundary protection layer at least covers the outer side wall of the upper electrode filling layer, and the boundary protection layer is an insulating material.

[0028] Optionally, before forming the boundary protection layer, first form an upper electrode covering layer on the surface of the upper electrode filling layer, the upper electrode covering layer has an uneven outer side wall corresponding to the outer side wall of the upper electrode filling layer, and the boundary protection layer at least covers the uneven outer side wall of the upper electrode covering layer.

[0029] Optionally, the substrate further has a peripheral region located outside the device region. Before forming the boundary protection layer, the capacitive dielectric layer, the upper electrode layer, the upper electrode filling layer, and the upper electrode covering layer sequentially extend and cover the surfaces of the entire device region and the peripheral region.

[0030] Optionally, the step of forming the boundary protection layer includes:

[0031] Deposit a boundary protection layer on the sidewalls and upper surface of the upper electrode covering layer;

[0032] Etch away the boundary protection layer located on the peripheral region and the boundary protection layer located in the device region and covering the upper surface of the upper electrode covering layer, so that the remaining boundary protection layer serves as a boundary sidewall, covering the uneven outer sidewalls of the upper electrode covering layer in the device region; and,

[0033] Etch away the upper electrode covering layer, the upper electrode filling layer, the upper electrode layer, and the capacitive dielectric layer on the peripheral region; or,

[0034] The steps of forming the boundary protection layer include:

[0035] Deposit a boundary protection layer on the sidewalls and upper surface of the upper electrode covering layer; and,

[0036] Etch away the boundary protection layer, the upper electrode covering layer, the upper electrode filling layer, the upper electrode layer, and the capacitive dielectric layer on the peripheral region, and the remaining boundary protection layer covers the upper surface and the uneven outer sidewalls of the upper electrode covering layer in the device region;

[0037] Or, the steps of forming the boundary protection layer include:

[0038] Etch away the upper electrode covering layer, the upper electrode filling layer, the upper electrode layer, and the capacitive dielectric layer on the peripheral region; and,

[0039] Deposit the boundary protection layer on the upper electrode covering layer and the peripheral region.

[0040] Optionally, the method for manufacturing the capacitor array structure further includes:

[0041] Form an interlayer dielectric layer on the device region having the boundary protection layer, and the interlayer dielectric layer also extends to cover the peripheral region; and,

[0042] Form conductive contact plugs in the interlayer dielectric layer on the device region and the peripheral region, the conductive contact plugs in the device region are in electrical contact with the upper electrode filling layer in the device region, and the conductive contact plugs in the peripheral region are in electrical contact with the conductive structure in the peripheral region.

[0043] The present invention also provides a method for manufacturing a semiconductor device, including: manufacturing a capacitor array structure by using the method for manufacturing the capacitor array structure of the present invention.

[0044] Compared with the prior art, the capacitor array structure, semiconductor device and their manufacturing method provided by the present invention add a boundary protection layer formed of an insulating material on the basis of the boundary of the original capacitor array structure, which can separate the cracks generated due to the uneven boundary of the capacitor array structure in the manufacturing process of the conductive contact plug from the boundary of the capacitor array structure, thereby avoiding the problem of short circuit between the conductive contact plug and the boundary of the capacitor array structure caused by the cracks and improving the reliability of the capacitor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 FIG. 6 is a schematic cross-sectional view of a capacitor array structure in the prior art.

[0046] Figure 2 FIG. 10 is a schematic flow chart of the manufacturing method of the capacitor array structure according to an embodiment of the present invention.

[0047] Figure 3a FIG. 14 is a top view structural schematic diagram of an embodiment of the present invention after performing step S1 in the manufacturing method shown in Figure 2 FIG. 16.

[0048] Figure 3b FIG. 20 is a schematic cross-sectional structure diagram along the AA' line in Figure 3a FIG. 22.

[0049] Figure 4a FIG. 26 is a top view structural schematic diagram of an embodiment of the present invention after performing step S2 in the manufacturing method shown in Figure 2 FIG. 28.

[0050] Figure 4b FIG. 32 is a schematic cross-sectional structure diagram along the AA' line in Figure 4a FIG. 34.

[0051] Figure 5 FIG. 38 is a schematic cross-sectional structure diagram of an embodiment of the present invention after performing step S3 in the manufacturing method shown in Figure 2 FIG. 40.

[0052] Figure 6 FIG. 44 is a schematic cross-sectional structure diagram of an embodiment of the present invention after performing step S4 in the manufacturing method shown in Figure 2 FIG. 46.

[0053] Figure 7 FIG. 50 is a schematic cross-sectional structure diagram of an embodiment of the present invention after performing step S5 in the manufacturing method shown in Figure 2 FIG. 52.

[0054] Figure 8 FIG. 56 is a schematic cross-sectional structure diagram of an embodiment of the present invention after performing step S6 in the manufacturing method shown in Figure 2 FIG. 58.

[0055] Figure 9 FIG. 62 is a schematic cross-sectional structure diagram of an embodiment of the present invention after performingFigure 2 Schematic cross-sectional structure diagram after depositing the boundary protection layer in step S7 of the preparation method shown.

[0056] Figure 10a This is an embodiment of the present invention when performing Figure 2 Schematic top-down structure diagram after etching the boundary protection layer to form sidewalls in step S7 of the preparation method shown.

[0057] Figure 10b This is an embodiment of the present invention when performing Figure 2 Schematic cross-sectional structure diagram after etching the boundary protection layer to form sidewalls in step S7 of the preparation method shown.

[0058] Figure 11a This is an embodiment of the present invention when performing Figure 2 Schematic top-down structure diagram after etching the upper electrode covering layer to the capacitor dielectric layer in step S7 of the preparation method shown.

[0059] Figure 11b This is an embodiment of the present invention when performing Figure 2 Schematic cross-sectional structure diagram after etching the upper electrode covering layer to the capacitor dielectric layer in step S7 of the preparation method shown.

[0060] Figure 12 This is an embodiment of the present invention when performing Figure 2 Schematic cross-sectional structure diagram after step S8 of the preparation method shown.

[0061] Figure 13a This is another embodiment of the present invention when performing Figure 2 Schematic top-down structure diagram after etching the boundary protection layer in step S7 of the preparation method shown.

[0062] Figure 13b This is another embodiment of the present invention when performing Figure 2 Schematic cross-sectional structure diagram after step S7 of the preparation method shown.

[0063] Figure 14 This is another embodiment of the present invention when performing Figure 2 Schematic cross-sectional structure diagram after step S8 of the preparation method shown.

[0064] Figure 15 This is yet another embodiment of the present invention when performing Figure 2 Schematic cross-sectional structure diagram after step S6 of the preparation method shown.

[0065] Figure 16a This is yet another embodiment of the present invention when performing Figure 2 Schematic top-down structure diagram after step S7 of the preparation method shown.

[0066] Figure 16b This is a schematic cross-sectional view after step S7 in the preparation method shown in Figure 2 another embodiment of the present invention.

[0067] Figure 17 This is a schematic cross-sectional view after step S7 in the preparation method shown in Figure 2 another embodiment of the present invention.

[0068] Among them, the reference numerals are as follows:

[0069] 100 - Substrate;

[0070] 100A - Device area;

[0071] 100B - Peripheral area;

[0072] 103 - Crack;

[0073] 102, 170 - Conductive contact plug;

[0074] 101 - Capacitor contact node;

[0075] 111 - Bottom support layer;

[0076] 112 - Intermediate support layer;

[0077] 113 - Top support layer;

[0078] 121 - First sacrificial layer;

[0079] 122 - Second sacrificial layer;

[0080] 110 - Capacitor via;

[0081] 130 - Lower electrode;

[0082] 131 - Capacitor dielectric layer;

[0083] 132 - Upper electrode layer;

[0084] 133 - Upper electrode filling layer;

[0085] 140 - Upper electrode covering layer;

[0086] 150 - Boundary protection layer;

[0087] 160 - Interlayer dielectric layer;

[0088] E1 - Boundary of capacitor array;

[0089] E2 - Boundary of device area. Detailed implementation manners

[0090] To make the objectives and features of the present invention more obvious and understandable, the technical solutions of the present invention will be described in detail below with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be limited only to the described embodiments. It should be noted that the accompanying drawings are in very simplified forms and use non-precise scales, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present invention.

[0091] Please refer to Figure 2 , an embodiment of the present invention provides a method for preparing a capacitor array structure, including the following steps:

[0092] S1. Provide a substrate with a device region, and form an alternately stacked sacrificial layer and a support layer on the substrate;

[0093] S2. Etch the support layer and the sacrificial layer to form a plurality of capacitor holes in the device region, and the capacitor holes sequentially penetrate the support layer and the sacrificial layer to expose the surface of the substrate;

[0094] S3. Form a lower electrode layer on the sidewalls and bottom walls of the capacitor holes to form a plurality of cylindrical structures;

[0095] S4. Remove the sacrificial layer and retain the support layer, and the support layer connects the plurality of cylindrical structures of the lower electrode layer;

[0096] S5. Sequentially form a capacitor dielectric layer and an upper electrode layer on the inner and outer surfaces of the lower electrode layer;

[0097] S6. Form an upper electrode filling layer on the surface of the upper electrode layer, the upper electrode filling layer fills the gaps in the upper electrode layer, and the outer sidewall of the upper electrode filling layer has an uneven morphology;

[0098] S7. Form a boundary protection layer on the upper electrode filling layer, the boundary protection layer at least covers the outer sidewall of the upper electrode filling layer, and the boundary protection layer is an insulating material;

[0099] S8. Form an interlayer dielectric layer on the substrate having the boundary protection layer, and form a conductive contact plug in the interlayer dielectric layer, and the conductive contact plug in the device region is in electrical contact with the upper electrode filling layer in the device region.

[0100] The method for preparing the capacitor array structure in this embodiment will be further explained below with reference to the corresponding structural schematic diagrams of each step.

[0101] Please refer to Figure 3a and Figure 3b, in step S1, a substrate 100 is provided. The substrate 100 includes a device region 100A for forming a capacitor array and a peripheral region 100B located outside the device region 100A. The device region 100A and the peripheral region 100B can be isolated by a shallow trench isolation structure (not shown). The material of the substrate 100 can be single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon on insulator (SOI), etc., or other materials known to those skilled in the art. In the substrate 100 of the device region 100A, a plurality of capacitor contact nodes 101 are further formed, and the capacitor contact nodes 101 are electrically connected to the lower electrode layer of the capacitor formed subsequently; in the substrate 100 of the peripheral region 100B, a conductive structure (which can be a transistor, etc., not shown) is further formed for electrical contact with the subsequent conductive contact plug. Of course, other device structures such as shallow trench isolation structures and transistors can also be formed in the substrate 100, and the present invention does not limit this. The bottom support layer 111, the first sacrificial layer 121, the intermediate support layer 112, the second sacrificial layer 122, and the top support layer 113 can be sequentially formed on the surface of the substrate 100 through processes such as chemical vapor deposition and spin coating, that is, the sacrificial layer and the support layer are alternately stacked on the substrate 100. The bottom support layer 111 is used to support the lower electrode layer formed subsequently at the bottom, and on the other hand, it is also used to isolate the internal components of the substrate 100 from the components such as capacitors above. The formation process of the bottom support layer 111 can also be a thermal oxidation process. The materials of the bottom support layer 111, the intermediate support layer 112, and the top support layer 113 include but are not limited to silicon nitride, and the materials of the first sacrificial layer 121 and the second sacrificial layer 122 include but are not limited to silicon oxide. The thickness of the first sacrificial layer 121 defines the height of the intermediate support layer 112 formed subsequently. Therefore, the thickness of the first sacrificial layer 121 can be adjusted according to the height position of the intermediate support layer 112 to be formed. When the thicknesses of the first sacrificial layer 121 and the intermediate support layer 112 are determined, the thickness of the second sacrificial layer 122 defines the height of the top support layer 113 formed subsequently. Therefore, the thickness of the second sacrificial layer 122 can be adjusted according to the height position of the top support layer 113 to be formed. In other embodiments of the present invention, in order to better support the lower electrode layer, more than two intermediate support layers 112 can be stacked between the bottom support layer 111 and the top support layer 113, and the adjacent intermediate support layers are isolated by a sacrificial layer.

[0102] Please refer to Figure 4a and Figure 4bAs shown, in step S2, a plurality of capacitor holes 110 are formed in the sacrificial layer and the support layer on the device region 100A. The capacitor holes 110 expose the surface of the substrate 100 of the device region 100A for forming a capacitor. The plurality of capacitor holes 110 are arranged in an array. Specifically, a mask layer (not shown) is formed on the top support layer 113, the mask layer is patterned to expose the region where the capacitor holes 110 are to be formed, and then, using the patterned mask layer as a mask, the top support layer 113, the second sacrificial layer 122, the intermediate support layer 112, the first sacrificial layer 121, and the bottom support layer 111 are etched in sequence to remove the support layer and the sacrificial layer on the peripheral region 100B and the edge region of the device region 100A, and a plurality of capacitor holes 110 are formed in the device region 100A, and then the patterned mask layer is removed. The capacitor holes 110 sequentially penetrate the top support layer 113, the second sacrificial layer 122, the intermediate support layer 112, the first sacrificial layer 121, and the bottom support layer 111 to expose the surface of the capacitor contact node 101 in the substrate 100 of the device region 100A. Optionally, all the capacitor holes 110 are arranged in a hexagonal close-packed pattern. In addition, the capacitor holes 110 can be trapezoidal holes, rectangular holes, etc., and their side walls can have irregular morphologies, such as having curved side walls, etc., which are not specifically limited herein. In addition, in this embodiment, the bottom support layer 111 is still retained on the peripheral region 100B to protect the surface of the substrate 100 of the peripheral region 100B in the subsequent capacitor formation process.

[0103] It can be understood that since the capacitor holes 110 need to be formed in the alternately stacked support layer and sacrificial layer, and then a lower electrode (i.e., the lower electrode layer 130) having a cylindrical structure can be formed on the bottom wall and side wall of the capacitor holes 110 subsequently. It can be seen that the total height of the stack for forming the capacitor holes 110 can define the height of each cylindrical structure in the lower electrode layer 130 formed subsequently. Therefore, by increasing the thickness of the first sacrificial layer 121 and the second sacrificial layer 122, the height of the lower electrode of the capacitor formed subsequently can be increased, thereby increasing the surface area of the lower electrode of the capacitor, and further increasing the capacitance value of the formed capacitor.

[0104] Please refer to Figure 5As shown, in step S3, a lower electrode layer 130 is formed to cover the sidewalls and the bottom wall of the capacitor hole 110. The portion of the lower electrode layer 130 located in the capacitor hole 110 has the same morphology as that of the capacitor hole 110, so that the lower electrode layer 130 located in the capacitor hole 110 forms a cylindrical structure. Specifically, the lower electrode layer 130 can be formed by combining a planarization process on the basis of a deposition process. For example, first, a patterned protective layer (not shown), such as a photoresist, can be used to protect the peripheral region 100B and expose the top surface of the top support layer 113 in the device region 100A and the surface of the capacitor hole 110. Then, a physical vapor deposition or chemical vapor deposition process is used to form an electrode material layer on the patterned protective layer and the exposed surfaces of the device region 100A. The electrode material layer covers the bottom and sidewalls of the capacitor hole 110, as well as the top support layer 113 in the device region 100A and the top surface of the patterned protective layer in the peripheral region 100B. Then, a planarization process (e.g., chemical mechanical polishing process CMP) is performed to remove the portion of the electrode material layer located above the top support layer 113, so that the remaining electrode material layer is only formed in the capacitor hole 110 to form a lower electrode layer 130 having a plurality of cylindrical structures 110a, and then the patterned protective layer is removed. In addition, in this embodiment, the capacitor contact node 101 is exposed through the capacitor hole 110, so that the bottom of the cylindrical structure 110a of the formed lower electrode layer 130 can be electrically connected to the capacitor contact node 101. Further, the lower electrode layer 130 can be a polysilicon electrode or a metal electrode. When the lower electrode layer 130 is a metal electrode, a titanium nitride (TiN) and Ti stacked structure can also be used. When the lower electrode layer 130 is a polysilicon electrode, a zero-doped and / or doped polysilicon material can be used to form it.

[0105] Please refer to Figure 5 and 6As shown, in step S4, each of the sacrificial layers is removed and each of the support layers is retained. All of the support layers form a lateral support layer to laterally connect the outer walls of the plurality of cylindrical structures of the lower electrode layer 130, so as to support the lower electrode layer 130 on the side walls of each of the cylindrical structures. Specifically, the top support layer 113 is located at the top periphery of the plurality of cylindrical structures of the lower electrode layer 130, the middle support layer 112 is located at the middle part of the plurality of cylindrical structures of the lower electrode layer 130, and the bottom support layer 111 is located at the bottom periphery of the plurality of cylindrical structures of the lower electrode layer 130. Among them, the specific process of step S4 includes: forming a first opening (not shown) in the top support layer 113 to expose the second sacrificial layer 122; the second sacrificial layer 122 can be etched away by a wet etching process; forming a second opening in the middle support layer 112 to expose the first sacrificial layer 121; etching away the first sacrificial layer 121 by a wet etching process; wherein, one of the first openings overlaps only one of the capacitor holes 110, or one of the first openings overlaps a plurality of the capacitor holes 110 at the same time; one of the second openings overlaps only one of the capacitor holes 110, or one of the second openings overlaps a plurality of the capacitor holes 110 at the same time. In addition, the second opening can be completely aligned with the first opening.

[0106] Please refer to Figure 7As shown, in step S5, first, a capacitor dielectric layer 131 is formed on the inner and outer surfaces of the lower electrode layer 130 and the exposed surfaces of each of the support layers by using a chemical vapor deposition process or an atomic layer deposition process, etc.; then, an upper electrode layer 132 is formed on the inner and outer surfaces of the capacitor dielectric layer 131. Among them, the capacitor dielectric layer 131 covers the inner and outer surfaces of the cylindrical structure 110a of the lower electrode layer 130 to make full use of the two opposite surfaces of the lower electrode layer 130 to form a capacitor with a larger electrode surface area. Preferably, the capacitor dielectric layer 131 can be a high-k dielectric layer such as a metal oxide. Further, the capacitor dielectric layer 131 is a multi-layer structure, for example, a two-layer structure of hafnium oxide-zirconium oxide. The upper electrode layer 132 can be a single-layer structure or a multi-layer structure. When the upper electrode layer 132 is a single-layer structure, for example, it can be a polysilicon electrode or a metal electrode. When the upper electrode layer 132 is a metal electrode, for example, titanium nitride (TiN) can be used to form it. The upper electrode layer 132 can form a capacitor with the capacitor dielectric layer 131 and the lower electrode layer 130 both inside and outside the corresponding cylindrical structure. In addition, in the edge region of the device area 100A (i.e., the boundary region of the capacitor hole array), due to the presence of the lateral support layers (i.e., the middle support layer 112 and the top support layer 113), the capacitor dielectric layer 131 and the upper electrode layer 132 both have a sidewall structure with an uneven morphology, and the sidewall structure with the uneven morphology corresponds to the middle support layer 112 and the top support layer 113 outside the cylindrical structure of the lower electrode layer 130. As a result, the part of the upper electrode layer 132 in the edge region of the device area 100A (i.e., the boundary region of the capacitor hole array) protrudes away from the lower electrode layer 130 corresponding to the middle support layer 112 and the top support layer 113, making the boundary of the capacitor array in the device area 100A uneven. In addition, in this embodiment, the capacitor dielectric layer 131 and the upper electrode layer 132 also sequentially extend to cover the surface of the bottom support layer 111 remaining on the peripheral area 100B.

[0107] Please refer to Figure 8As shown, in step S6, a chemical vapor deposition process may be first used to form an upper electrode filling layer 133 on the surface of the upper electrode layer 132. The upper electrode filling layer 133 fills the gaps between the upper electrode layers 132. That is to say, the upper electrode filling layer 133 fills the gaps between adjacent cylindrical structures and covers the formed structure. Preferably, the material of the upper electrode filling layer 133 includes undoped or boron-doped polysilicon. Then, a physical vapor deposition process or the like is used to form an upper electrode covering layer 140 on the upper electrode filling layer 133. The upper electrode covering layer 160 is preferably a laminated structure, including a conductive metal layer (the material thereof includes but is not limited to tungsten) for connecting the surface of the upper electrode filling layer 132 and an oxide layer (the material thereof includes but is not limited to silicon oxide) for preventing oxidation of the conductive metal layer. Similarly, both the upper electrode filling layer 133 and the upper electrode covering layer 140 have sidewall structures with uneven morphologies, and the sidewall structures with uneven morphologies correspond to the intermediate support layer 112 and the top support layer 113. Thus, the fabrication of the capacitor array is completed.

[0108] Since a lateral support layer (i.e., the bottom support layer 111, the intermediate support layer 112, and the top support layer 113) is added between the lower electrode layers, the stability of the above capacitor array is improved. However, the presence of the lateral support layer makes the boundary of the capacitor array have an uneven morphology. During the subsequent conductive plug process for depositing and filling a conductive metal material into the contact holes, cracks are formed at the uneven places (concave and convex sides) of the boundary of the capacitor array, resulting in a short circuit between the formed conductive contact plug and the capacitor array boundary, affecting the reliability of the finally manufactured memory. To avoid this problem, in step S7, a boundary protection layer with insulation is formed to cover at least the uneven boundary of the capacitor array, so as to isolate the possible cracks generated in the subsequent process from the capacitor array boundary, thereby avoiding the short circuit problem between the conductive contact plug and the capacitor array boundary caused by the cracks and providing the reliability of the device.

[0109] In an embodiment of the present invention, in step S7, a boundary protection layer 150 is formed only on the uneven boundary of the capacitor array. The specific process includes:

[0110] First, please refer to Figure 9, an insulating material is deposited on the surface of the upper electrode covering layer 140 through processes such as chemical vapor deposition to form an insulating boundary protection layer 150 on the sidewalls and top surface of the upper electrode covering layer 140. The material of the boundary protection layer 150 includes at least one of silicon nitride, silicon carbonitride, and silicon oxynitride. The portion of the boundary protection layer 150 on the edge region of the device area 100A also has an uneven sidewall corresponding to the lateral support layer. At this time, the boundary protection layer 150, the upper electrode covering layer 140, the upper electrode filling layer 133, the upper electrode layer 132, and the capacitive dielectric layer 131 continuously extend from the device area 100A to the entire surface of the peripheral area 100B.

[0111] Then, please refer to Figure 10a , 10b , a sidewall etching process can be used to etch the boundary protection layer 150, thereby removing the boundary protection layer 150 on the upper surface of the upper electrode covering layer 140 in the outermost edge region of the peripheral area 100B, the device area 100A, and the device area 100A (i.e., the capacitor array area). The remaining boundary protection layer 150 only covers the uneven boundary of the capacitor array area (i.e., the uneven outer sidewall of the upper electrode covering layer 140 in the device area 100A) as a boundary sidewall. At this time, the boundary E1 of the capacitor array can be obtained, and the area between this boundary E1 and the boundary E2 of the device area 100A is the outermost edge area of the device area 100A.

[0112] Next, please refer to Figure 11a , 11b , the upper electrode covering layer 140, the upper electrode filling layer 133, the upper electrode layer 132, and the capacitive dielectric layer 131 on the peripheral area 100A can be removed by means of a contact hole mask plate on the capacitor array and further through photolithography and etching processes, thereby obtaining the boundary E2 of the device area 100A. The boundary E2 can be arranged parallel to the cylindrical structure of the lower electrode layer 130 in the vertical direction or can be arranged at a certain angle slope with respect to the substrate 100.

[0113] The boundary protection layer 150 formed by this method is only a sidewall structure, which can minimize the influence on the central area of the capacitor array while protecting the boundary of the capacitor array.

[0114] After that, step S8 can be executed to form an interlayer dielectric layer 160 and conductive contact plugs 170 located in the interlayer dielectric layer 160 on the sidewalls and top surface of the capacitor array with boundary sidewalls, the edge region of the device area 100A exposed by the boundary protection layer 150, and the peripheral area 100B. Specifically, please refer to Figure 12, First, a chemical vapor deposition process or a coating process can be adopted and combined with a further top planarization process to form an interlayer dielectric layer 160 on the bottom support layer 111 of the peripheral region 100B, the boundary protection layer 150 of the device region 100A, and the surface of the upper electrode covering layer 140 exposed by the boundary protection layer 150. The interlayer dielectric layer 160 is thick enough to bury the boundary protection layer 150 and the upper electrode covering layer 140 therein, and has a flat sidewall surface and a top surface. Next, the interlayer dielectric layer 160 of the device region 100A and the peripheral region 100B can be etched through contact holes to form contact holes (not shown) respectively located in the device region 100A and the peripheral region 100B. The contact hole in the device region 100A exposes the top surface of the upper electrode filling layer 133, and the contact hole in the peripheral region 100B exposes the upper surface of the conductive structure (such as a transistor, etc.) in the substrate 100 of the peripheral region 100B. Then, processes such as electroplating and sputtering can be used to fill each of the contact holes with a metal conductive material (the material thereof includes but is not limited to tungsten) until the contact holes are filled, and the excess metal conductive material can be further removed through a chemical mechanical planarization process, so as to form conductive contact plugs 170 in the interlayer dielectric layer 160 on the device region 100A and the peripheral region 100B. The conductive contact plug 170 in the device region 100A is in electrical contact with the upper surface of the upper electrode filling layer 133 in the device region 100A, and the conductive contact plug 170 in the peripheral region 100B is in electrical contact with the conductive structure in the substrate 100 of the peripheral region 100B.

[0115] In another embodiment of the present invention, please refer to Figure 9 , Figure 13a and Figure 13b , in step S7, a boundary protection layer 150 is formed on the uneven boundary and the top surface of the capacitor array. The specific process includes:

[0116] First, please refer to Figure 9 , an insulating material is deposited on the surface of the upper electrode covering layer 140 through a process such as chemical vapor deposition to form an insulating boundary protection layer 150 on the sidewall and the top surface of the upper electrode covering layer 140. The material of the boundary protection layer 150 includes at least one of silicon nitride, silicon carbonitride, and silicon oxynitride. The part of the boundary protection layer 150 on the edge region of the device region 100A also has an uneven sidewall corresponding to the lateral support layer. At this time, the boundary protection layer 150, the upper electrode covering layer 140, the upper electrode filling layer 133, the upper electrode layer 132, and the capacitor dielectric layer 131 all continuously extend from the device region 100A to the entire surface of the peripheral region 100B.

[0117] Then, please refer to Figure 13a and Figure 13b, the boundary protection layer 150, the upper electrode covering layer 140, the upper electrode filling layer 133, the upper electrode layer 132, and the capacitive dielectric layer 131 on the peripheral region 100A can be removed by means of the contact hole mask plate on the capacitor array and further through photolithography and etching processes, thereby obtaining the boundary E2 of the device region 100A. The boundary E2 can be arranged parallel to the cylindrical structure of the lower electrode layer 130 in the vertical direction, or can be arranged at a certain angle with respect to the substrate 100 in a sloped manner.

[0118] This method can form the boundary protection layer 150 and the boundary of the device region 100A through one etching process, simplifying the process. The remaining boundary protection layer 150 can not only protect the uneven boundary (i.e., the sidewall) of the capacitor array, but also protect the entire top surface of the capacitor array, that is, the protection of the capacitor array is enhanced, which is beneficial to further improving the device reliability.

[0119] After that, step S8 can be continued to form the interlayer dielectric layer 160 and the conductive contact plug 170 located in the interlayer dielectric layer 160 on the capacitor array with the boundary protection layer 150 and the peripheral region 100B. Specifically, please refer to Figure 14 , first, a coating or chemical vapor deposition process can be used in combination with a further top planarization process to form the interlayer dielectric layer 160 on the bottom support layer 111 of the peripheral region 100B and the surface (i.e., the uneven sidewall and top surface) of the boundary protection layer 150 of the device region 100A. And the interlayer dielectric layer 160 is thick enough to fill the gaps in the boundary protection layer 150 and completely bury the boundary protection layer 150 therein, and has a flat sidewall surface and a top surface. Then, the interlayer dielectric layer 160 of the device region 100A and the peripheral region 100B can be etched through contact holes to form contact holes (not shown) respectively located in the device region 100A and the peripheral region 100B. And the contact hole in the device region 100A exposes the top surface of the upper electrode filling layer 133, and the contact hole in the peripheral region 100B exposes the upper surface of the conductive structure (such as a transistor, etc.) in the substrate 100 of the peripheral region 100B. Then, a metal conductive material (the material thereof includes but is not limited to tungsten) can be filled into each of the contact holes by means of electroplating, sputtering, etc. until the contact holes are filled, and the excess metal conductive material can be removed further through a chemical mechanical planarization process, thereby forming the conductive contact plug 170 in the interlayer dielectric layer 160 on the device region 100A and the peripheral region 100B. The conductive contact plug 170 in the device region 100A is in electrical contact with the upper surface of the upper electrode filling layer 133 in the device region 100A, and the conductive contact plug 170 in the peripheral region 100B is in electrical contact with the conductive structure in the substrate 100 of the peripheral region 100B.

[0120] In yet another embodiment of the present invention, please refer to Figure 15 , Figure 16a and Figure 16b . In step S7, another method different from the above embodiment can also be adopted to form the boundary protection layer 150 on the uneven boundary and the top surface of the capacitor array. The specific process includes:

[0121] First, please refer to Figure 15 . The upper electrode covering layer 140, the upper electrode filling layer 133, the upper electrode layer 132, and the capacitive dielectric layer 131 on the peripheral region 100A can be removed by means of the contact hole mask plate on the capacitor array and further through photolithography and etching processes, thereby obtaining the boundary E2 of the device region 100A. The boundary E2 can be arranged parallel to the cylindrical structure of the lower electrode layer 130 in the vertical direction or can be arranged at a certain angle with respect to the substrate 100.

[0122] Next, please refer to Figure 16a , 16b . An insulating material is deposited on the surface of the upper electrode covering layer 140 and the bottom support layer 111 of the peripheral region 100B through processes such as chemical vapor deposition to form an insulating boundary protection layer 150 on the side wall and the top surface of the upper electrode covering layer 140 and on the bottom support layer 111 of the peripheral region 100B. The material of the boundary protection layer 150 includes at least one of silicon nitride, silicon carbonitride, and silicon oxynitride. The boundary protection layer 150 also has an uneven side wall corresponding to the lateral support layer in the edge region of the device region 100A. At this time, the boundary protection layer 150, the upper electrode covering layer 140, the upper electrode filling layer 133, the upper electrode layer 132, and the capacitive dielectric layer 131 continuously extend from the device region 100A to the entire surface of the peripheral region 100B.

[0123] This method first etches the boundary of the device region 100A and then forms the boundary protection layer 150, which simplifies the process. Moreover, the formed boundary protection layer 150 can not only protect the capacitor array in the device region 100A but also protect the structures in the peripheral region 100B, preventing adverse effects on them caused by subsequent conductive contact plug processes.

[0124] After that, step S8 can be continued to form the interlayer dielectric layer 160 and the conductive contact plug 170 located in the interlayer dielectric layer 160 on the capacitor array with the boundary protection layer 150 and the peripheral region 100B. Specifically, please refer to Figure 17, First, a process of coating or chemical vapor deposition can be adopted and combined with a further top planarization process to form an interlayer dielectric layer 160 on the surface (i.e., the uneven sidewalls and top surface) of the boundary protection layer 150. And the interlayer dielectric layer 160 is thick enough to fill the gaps in the uneven sidewalls of the boundary protection layer 150 in the device region 100A and completely bury the boundary protection layer 150. Eventually, the interlayer dielectric layer 160 has a flat sidewall surface and a top surface. Then, the interlayer dielectric layer 160 in the device region 100A and the peripheral region 100B can be etched through contact holes to form contact holes (not shown) located in the device region 100A and the peripheral region 100B respectively. And the contact hole in the device region 100A exposes the top surface of the upper electrode filling layer 133, and the contact hole in the peripheral region 100B exposes the upper surface of the conductive structure (such as a transistor, etc.) in the substrate 100 of the peripheral region 100B. Then, processes such as electroplating and sputtering can be used to fill the metal conductive material (the material thereof includes but is not limited to tungsten) into each of the contact holes until the contact holes are filled, and further, the excess metal conductive material is removed through a chemical mechanical planarization process, thereby forming conductive contact plugs 170 in the interlayer dielectric layer 160 on the device region 100A and the peripheral region 100B. The conductive contact plug 170 in the device region 100A is in electrical contact with the upper surface of the upper electrode filling layer 133 in the device region 100A, and the conductive contact plug 170 in the peripheral region 100B is in electrical contact with the conductive structure in the substrate 100 of the peripheral region 100B.

[0125] In the above embodiments, the deposition thickness of the boundary protection layer 150 is relatively thin and is not sufficient to fill the gaps in the uneven sidewalls of the upper electrode covering layer 140. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, the deposition thickness of the boundary protection layer 150 can be made thicker to fill the gaps in the uneven sidewalls of the upper electrode covering layer 140, so that the boundary of the capacitor array becomes a flat sidewall, thereby minimizing the possibility of cracks generated by the lateral support layer in the subsequent conductive contact plug process, and avoiding the short - circuit problem between the conductive contact plug and the capacitor array boundary caused by the cracks to the greatest extent.

[0126] In summary, for the preparation method of the capacitor array structure of the present invention, before the conductive contact plug process, a boundary protection layer that at least covers the uneven boundary of the capacitor array is first formed to reduce the possibility of cracks formed due to the uneven boundary of the capacitor array when filling the metal conductive material into the contact holes in the subsequent conductive contact plug process, and at the same time separate the possible cracks from the uneven boundary of the capacitor array to avoid the short - circuit problem between the formed conductive contact plug and the capacitor array boundary, and improve the device reliability.

[0127] Please refer to Figures 2 to 17 , the present invention also provides a method for manufacturing a semiconductor device, including: manufacturing a capacitor array structure by using the method for manufacturing the capacitor array structure of the present invention. The method for manufacturing the semiconductor device of the present invention is applicable to the manufacturing of semiconductor memories such as dynamic random access memories. Since the method for manufacturing the semiconductor device of the present invention manufactures the capacitor array structure by using the method for manufacturing the capacitor array structure of the present invention, a semiconductor device with higher reliability can be manufactured.

[0128] Please refer to Figure 12 , an embodiment of the present invention also provides a capacitor array structure, including a substrate 100, a lower electrode layer 130, a capacitive dielectric layer 131, an upper electrode layer 132, an upper electrode filling layer 133, an upper electrode covering layer 140, a boundary protection layer 150, a lateral support layer for supporting the lower electrode layer 130, an interlayer dielectric layer 160, and a conductive contact plug 170.

[0129] Specifically, the substrate 100 has a device region 100A and a peripheral region 100B located outside the device region 100A, and the device region 100A and the peripheral region 100B can be separated by a shallow trench isolation structure (not shown). The material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon on insulator (SOI), etc., or other materials known to those skilled in the art. A plurality of capacitive contact nodes 101 arranged in an array are further formed in the substrate 100 of the device region 100A, and the capacitive contact nodes 101 are electrically connected to the lower electrode layer 130; a conductive structure (which can be a transistor, etc., not shown) is further formed in the substrate 100 of the peripheral region 100B for electrical contact with the corresponding conductive contact plug 170.

[0130] The lower electrode layer 130 is disposed on the substrate 100 of the device region 100A, and the lower electrode layer 130 has a plurality of cylindrical structures, and the cylindrical structures can be inverted trapezoidal holes, rectangular holes, etc., and the side walls thereof can be irregular morphologies, such as having curved side walls, etc., which are not specifically limited herein. All the cylindrical structures are arranged in an array and correspond to the array in which the capacitive contact nodes 101 are arranged, so that the bottom of each cylindrical structure is electrically connected to the capacitive contact node 101 in the device region 100A. The lower electrode layer 130 can be a polysilicon electrode or a metal electrode. When the lower electrode layer 130 is a metal electrode, a stacked structure of titanium nitride (TiN) and Ti can also be adopted. When the lower electrode layer 130 is a polysilicon electrode, it can be formed by using undoped and / or doped polysilicon materials.

[0131] The lateral support layer is connected to the outer walls of the plurality of cylindrical structures of the lower electrode layer 130 and extends along a direction parallel to the surface of the substrate 100, and includes a bottom support layer 111, at least one intermediate support layer 112, and a top support layer 113. Among them, the top support layer 113 is located at the top periphery of the plurality of cylindrical structures of the lower electrode layer 130, the intermediate support layer 112 is located at the middle part of the plurality of cylindrical structures of the lower electrode layer 130, and the bottom support layer 111 is located at the bottom periphery of the plurality of cylindrical structures of the lower electrode layer 130. The materials of the respective support layers in the lateral support layer may be completely the same, for example, all are silicon oxide; or may not be completely the same, for example, the bottom support layer is silicon oxide, and the intermediate support layer 112 and the top support layer 113 are silicon oxide.

[0132] The capacitive dielectric layer 131 is disposed on the inner and outer surfaces of the lower electrode layer 130 and the surface of the lateral support layer to make full use of the two opposite surfaces of the lower electrode layer 130 to form a capacitor with a relatively large electrode surface area. Preferably, the capacitive dielectric layer 131 may be a high-K dielectric layer such as a metal oxide with a dielectric constant greater than 7. Further, the capacitive dielectric layer 131 is a multi-layer structure, for example, a two-layer structure of hafnium oxide-zirconium oxide. The capacitive dielectric layer 131 extends and covers the surface of the entire device area 100A, and the capacitive dielectric layer 131 has an uneven side wall corresponding to the lateral support layer at the boundary of the lower electrode layer, and the uneven side wall has an uneven topography.

[0133] The upper electrode layer 132 is disposed on the inner and outer surfaces of the capacitive dielectric layer 131. The upper electrode layer 132 can form capacitors with the capacitive dielectric layer 131 and the lower electrode layer 130 both inside and outside the cylindrical structure. Thus, the upper electrode layer 132, the capacitive dielectric layer 131, and the lower electrode layer 130 form a capacitor at each cylindrical structure of the lower electrode layer 130, thereby forming a capacitor array. The upper electrode layer 132 can be a single-layer structure or a multi-layer structure. When the upper electrode layer 132 is a single-layer structure, it can be, for example, a polysilicon electrode or a metal electrode. When the upper electrode layer 132 is a metal electrode, it can be formed by, for example, titanium nitride (TiN). In addition, in the edge region of the device region 100A (i.e., the boundary region of the capacitor via array), due to the presence of the lateral support layers (i.e., the intermediate support layer 112 and the top support layer 113), the upper electrode layer 132 also has an outer sidewall structure with an uneven morphology. The outer sidewall structure with the uneven morphology corresponds to the intermediate support layer 112 and the top support layer 113 outside the cylindrical structure of the lower electrode layer 130. Thus, the part of the upper electrode layer 132 in the edge region of the device region 100A (i.e., the boundary region of the capacitor via array) protrudes away from the lower electrode layer 130 corresponding to the intermediate support layer 112 and the top support layer 113, making the boundary of the capacitor array in the device region 100A uneven. In addition, in this embodiment, the capacitive dielectric layer 131 and the upper electrode layer 132 also sequentially extend and cover the surface of the bottom support layer 111 remaining on the peripheral region 100B.

[0134] The upper electrode filling layer 133 covers the surface of the upper electrode layer 132 and fills the gaps between the upper electrode layers 132. That is, the upper electrode filling layer 133 fills the gaps between adjacent cylindrical structures. Preferably, the material of the upper electrode filling layer 133 includes undoped or boron-doped polysilicon. The upper electrode covering layer 140 covers the outer surface of the upper electrode filling layer 133. The upper electrode covering layer 160 is preferably a stacked structure, including a conductive metal layer (the material of which includes but is not limited to tungsten) for connecting the surface of the upper electrode filling layer 132 and an oxide layer (the material of which includes but is not limited to silicon oxide) for preventing oxidation of the conductive metal layer. Similarly, the upper electrode filling layer 133 and the upper electrode covering layer 140 both have an outer sidewall structure with an uneven morphology (i.e., an uneven outer sidewall), and the uneven morphology of the outer sidewall corresponds to the intermediate support layer 112 and the top support layer 113.

[0135] In addition, the side walls of the upper electrode covering layer 140, the upper electrode filling layer 133, the upper electrode layer 132, and the capacitive dielectric layer 131 stacked at the boundary E2 of the device region 100A can be arranged parallel to the cylindrical structure of the lower electrode layer 130 in the vertical direction, or can be arranged with a slope at a certain angle to the upper surface of the substrate 100.

[0136] The boundary protection layer 150 covers the uneven outer side wall of the upper electrode covering layer 140 in the device region 100A as a boundary sidewall to isolate the cracks in the interlayer dielectric layer 160 and the boundary of the capacitor array, avoiding the short-circuit problem between the conductive contact plug 170 and the capacitor array boundary E1. The boundary protection layer 150 is an insulating material, including at least one of silicon nitride, silicon carbonitride, and silicon oxynitride.

[0137] The interlayer dielectric layer 160 not only covers the surface of the device region 100A having the boundary protection layer 150, but also extends to cover the entire surface of the peripheral region 100B, capable of completely burying the boundary protection layer 150 and the upper electrode covering layer 140 therein, and having a flat side wall surface and a top surface. Conductive contact plugs 170 are formed in the interlayer dielectric layer 60 in the device region 100A and the peripheral region 100B. The conductive contact plug 170 in the device region 100A is in electrical contact with the upper electrode filling layer 133 in the device region 100A, and the conductive contact plug 170 in the peripheral region 100B is in electrical contact with a conductive structure (not shown) in the peripheral region 100B. The material of the interlayer dielectric layer 160 can be a low-K dielectric with a dielectric constant K lower than 4, or silicon oxide, etc. The material of the conductive contact plug 170 includes, but is not limited to, tungsten.

[0138] The capacitor array structure of this embodiment is essentially to add a boundary protection sidewall (i.e., the boundary protection layer 150 that only covers the uneven boundary of the capacitor array) between the interlayer dielectric layer 160 and the uneven boundary of the capacitor array, for separating the possible cracks in the interlayer dielectric layer 160 from the uneven boundary of the capacitor array, so as to avoid the short-circuit problem between the conductive contact plug 170 and the capacitor array boundary caused by the conductive metal material filled in the cracks, and improve the device reliability.

[0139] In the above embodiment, the boundary protection layer 150 only covers the uneven boundary of the capacitor array, that is, only covers the uneven outer side wall formed by the upper electrode covering layer 140 corresponding to the lateral support layer in the device region 100A. However, the technical solution of the present invention is not limited thereto. In another embodiment of the present invention, please refer to Figure 14, the boundary protection layer 150 not only covers the uneven outer sidewalls formed by the upper electrode covering layer 140 corresponding to the lateral support layer in the device region 100A, but also covers the upper surface of the upper electrode covering layer. Thus, the boundary protection layer 150 can not only protect the uneven boundary of the capacitor array (i.e., the uneven outer sidewalls formed by the upper electrode covering layer 140 corresponding to the lateral support layer), but also protect the entire top surface of the capacitor array, that is, the protection strength for the capacitor array is increased, which is beneficial to further improving the device reliability; in another embodiment of the present invention, the boundary protection layer 150 not only covers the uneven outer sidewalls formed by the upper electrode covering layer 140 corresponding to the lateral support layer in the device region 100A, but also covers the upper surface of the upper electrode covering layer, and extends to cover the surface of the entire peripheral region 100B at the bottom of the interlayer dielectric layer 160. Thus, the boundary protection layer 150 can not only protect the capacitor array in the device region 100A, but also protect the structures in the peripheral region 100B, preventing the formation process of the conductive contact plug from causing adverse effects on the peripheral region 100B and the device region 100A.

[0140] In summary, for the capacitor array structure of the present invention, a boundary protection layer that at least covers the uneven boundary of the capacitor array is added between the upper electrode filling layer and the interlayer dielectric layer, so as to separate the possible cracks in the interlayer dielectric layer from the boundary of the capacitor array, effectively avoiding the short-circuit problem caused by the formation of cracks due to the uneven boundary of the capacitor array in the conductive contact plug process and improving the device reliability.

[0141] Correspondingly, the present invention also provides a semiconductor device including the capacitor array structure as described above. The semiconductor device is preferably a dynamic random access memory. Since the semiconductor device of the present invention adopts the capacitor array structure of the present invention, the reliability is improved.

[0142] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure are within the protection scope of the claims.

Claims

1. A capacitor array structure, characterized in that, Comprising: A substrate having a device region for forming a capacitor array; A lower electrode layer disposed on the device region of the substrate, and the lower electrode layer has a plurality of cylindrical structures arranged in an array; A capacitive dielectric layer covering the inner and outer surfaces of the lower electrode layer; An upper electrode layer covering the surface of the capacitive dielectric layer; An upper electrode filling layer; Covering the surface of the upper electrode layer and filling the gaps in the upper electrode layer, and the outer sidewall of the upper electrode filling layer has an uneven topography; and, A boundary protection layer that at least covers the outer sidewall of the upper electrode filling layer, and the boundary protection layer is an insulating material; An upper electrode covering layer that covers the surface of the upper electrode filling layer and has an uneven outer sidewall corresponding to the outer sidewall of the upper electrode filling layer; and the capacitive dielectric layer, the upper electrode layer, the upper electrode filling layer, and the upper electrode covering layer sequentially extend to cover the entire surface of the device region; the boundary protection layer at least covers the uneven outer sidewall of the upper electrode covering layer.

2. The capacitor array structure according to claim 1, wherein, The boundary protection layer covers the upper surface and the uneven outer sidewall of the upper electrode covering layer.

3. The capacitor array structure according to claim 1, wherein There is also a peripheral region on the substrate located outside the device region, and a conductive structure is formed in the peripheral region; the capacitor array structure further includes an interlayer dielectric layer that not only covers the surface of the device region having the boundary protection layer but also extends to cover the peripheral region; Conductive contact plugs are formed in the interlayer dielectric layer in the device region and in the peripheral region. The conductive contact plugs in the device region are in electrical contact with the upper electrode filling layer in the device region, and the conductive contact plugs in the peripheral region are in electrical contact with the conductive structure in the peripheral region.

4. The capacitor array structure according to claim 3, wherein The boundary protection layer extends to cover the surface of the peripheral region.

5. The capacitor array structure according to any one of claims 1 to 4, characterized in that It further includes a lateral support layer located on the substrate of the device region and laterally connecting the plurality of cylindrical structures of the lower electrode layer. Among them, the uneven topography of the outer sidewall of the upper electrode filling layer corresponds to the lateral support layer outside the cylindrical structure of the lower electrode.

6. The capacitor array structure according to claim 5, wherein, The lateral support layer includes a top support layer, at least one intermediate support layer, and a bottom support layer. The top support layer is located at the outer periphery of the top of the cylindrical structure of the lower electrode layer, the intermediate support layer is located at the middle part of the cylindrical structure of the lower electrode layer, and the bottom support layer is located at the outer periphery of the bottom of the cylindrical structure of the lower electrode layer.

7. The capacitor array structure according to any one of claims 1 to 4, characterized in that, A plurality of capacitive contact nodes are further formed in the substrate, and the lower electrode layer is connected to the corresponding contact nodes at the bottom of each cylindrical structure.

8. A semiconductor device, characterized in that, Comprising the capacitor array structure according to any one of claims 1 to 7.

9. A method for preparing a capacitor array structure, characterized in that, Comprising: Providing a substrate having a device region, and forming an alternating stack of a sacrificial layer and a support layer on the substrate; Etching the support layer and the sacrificial layer to form a plurality of capacitive holes in the device region, and the capacitive holes sequentially penetrate the support layer and the sacrificial layer to expose the surface of the substrate; Form a lower electrode layer on the sidewalls and bottom wall of the capacitor via holes to form a plurality of cylindrical structures; Remove the sacrificial layer and retain the support layer, and the support layer connects the plurality of cylindrical structures of the lower electrode layer; Form a capacitor dielectric layer and an upper electrode layer on the inner and outer surfaces of the lower electrode layer in sequence; Form an upper electrode filling layer on the surface of the upper electrode layer, the upper electrode filling layer fills the gaps in the upper electrode layer, and the outer sidewall of the upper electrode filling layer has an uneven topography; and, Form a boundary protection layer on the upper electrode filling layer, the boundary protection layer at least covers the outer sidewall of the upper electrode filling layer, and the boundary protection layer is an insulating material; Before forming the boundary protection layer, first form an upper electrode covering layer on the surface of the upper electrode filling layer, the outer sidewall of the upper electrode covering layer has an uneven outer sidewall corresponding to the outer sidewall of the upper electrode filling layer, and the boundary protection layer at least covers the uneven outer sidewall of the upper electrode covering layer.

10. The method for preparing the capacitor array structure according to claim 9, wherein The substrate further has a peripheral region located outside the device region. Before forming the boundary protection layer, the capacitor dielectric layer, the upper electrode layer, the upper electrode filling layer, and the upper electrode covering layer sequentially extend to cover the surfaces of the entire device region and the peripheral region.

11. The manufacturing method of the capacitor array structure according to claim 10, characterized in that, The steps of forming the boundary protection layer include: Deposit a boundary protection layer on the sidewalls and upper surface of the upper electrode covering layer; Etch and remove the boundary protection layer located on the peripheral region and the boundary protection layer located in the device region and covering the upper surface of the upper electrode covering layer, so that the remaining boundary protection layer serves as a boundary sidewall and covers the uneven outer sidewall of the upper electrode covering layer in the device region; and, Etch and remove the upper electrode covering layer, the upper electrode filling layer, the upper electrode layer, and the capacitor dielectric layer on the peripheral region; or, The steps of forming the boundary protection layer include: Deposit a boundary protection layer on the sidewalls and upper surface of the upper electrode covering layer; and, Etch and remove the boundary protection layer, the upper electrode covering layer, the upper electrode filling layer, the upper electrode layer, and the capacitor dielectric layer on the peripheral region, and the remaining boundary protection layer covers the upper surface and the uneven outer sidewall of the upper electrode covering layer in the device region; Or, the steps of forming the boundary protection layer include: Etch and remove the upper electrode covering layer, the upper electrode filling layer, the upper electrode layer, and the capacitor dielectric layer on the peripheral region; and, Deposit the boundary protection layer on the upper electrode covering layer and the peripheral region.

12. The method for preparing a capacitor array structure according to any one of claims 10 or 11, characterized in that, Further include: Form an interlayer dielectric layer on the device region having the boundary protection layer, and the interlayer dielectric layer also extends to cover the peripheral region; And, Form conductive contact plugs in the interlayer dielectric layer on the device region and the peripheral region, the conductive contact plugs in the device region are in electrical contact with the upper electrode filling layer in the device region, and the conductive contact plugs in the peripheral region are in electrical contact with the conductive structures in the peripheral region.

13. A method for manufacturing a semiconductor device, characterized in that, Include: The capacitor array structure is prepared by using the preparation method of the capacitor array structure described in any one of claims 9 to 12.

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