Semiconductor device layout, systems and semiconductor devices

Abstract

The present application provides a layout of a semiconductor device, which is stored in a non-temporary computer-readable medium. The layout includes a first transistor in an active device region and a second transistor in a guard ring region. The first transistor includes a first channel region, a first gate structure spanning the first channel region, and a first source region and a first drain region on opposite sides of the first channel region. The second transistor includes a second channel region, a second gate structure spanning the second channel region, and a second source region and a second drain region on opposite sides of the second channel region. The second channel region includes a semiconductor material having a higher thermal conductivity than the semiconductor material of the first channel region.

Description

Technical Field

[0001] The present disclosure relates to a layout, system and semiconductor device of a semiconductor device, and more particularly to a layout design, system and semiconductor device of a heat sink of an advanced FinFET integrated circuit. Background Art

[0002] Miniaturization of integrated circuits (ICs) has resulted in smaller devices that consume less power but provide more functionality at higher speeds than before. The miniaturization process has also led to various developments in IC design and / or manufacturing processes to help ensure device reliability and desired device performance. Summary of the invention

[0003] One aspect of the present disclosure is to provide a layout of a semiconductor element. The layout is stored in a non-temporary computer-readable medium and includes a first transistor and a second transistor. The first transistor is located in an active element region. The first transistor includes a first channel region in a first semiconductor fin, a first gate structure spanning the first channel region, and a first source region and a first drain region in the first semiconductor fin on opposite sides of the first channel region. The second transistor is located in a guard ring region. The second transistor includes a second channel region in a second semiconductor fin, a second gate structure spanning the second channel region, and a second source region and a second drain region in the second semiconductor fin on opposite sides of the second channel region. The second channel region includes a semiconductor material. The semiconductor material has a higher thermal conductivity than a semiconductor material in the first channel region.

[0004] One aspect of the present disclosure is to provide a system for processing the layout of semiconductor elements. The system includes at least one processor and a computer-readable storage medium connected to the at least one processor. The at least one processor is configured to execute instructions stored on the computer-readable storage medium so as to generate a first semiconductor fin in the active element region and a second semiconductor fin in the guard ring region, and generate a first transistor in the active element region. The first transistor includes a first channel region in the first semiconductor fin, a first gate structure spanning the first channel region, and a first source region and a first drain region in the first semiconductor fin on opposite sides of the first channel region. The second semiconductor fin includes a semiconductor material having a higher thermal conductivity than the semiconductor material used in at least the first source region and the first drain region.

[0005] One aspect of the present disclosure is to provide a semiconductor device. The semiconductor device includes a substrate, a transistor located in an active device region of the substrate, and a resistor located in a passive device region of the substrate. The transistor includes a channel region in a semiconductor fin, a gate structure spanning the channel region, and a source region and a drain region in the semiconductor fin on opposite sides of the channel region. The semiconductor device further includes a source contact structure overlying the source region of the transistor, and an interconnect metal layer electrically coupling the source contact structure and a first terminal of the resistor. The second terminal of the resistor is floating.

[0006] One aspect of the present disclosure is to provide a layout of a semiconductor device, the layout being stored in a non-temporary computer readable medium and comprising a first transistor located in an active device region, and a second transistor located in a guard ring region. The first transistor comprises a first channel region, a first source region, and a first drain region. The second transistor comprises a second channel region, a second source region, and a second drain region. The second channel region comprises a semiconductor material having a higher thermal conductivity than the semiconductor material of the first channel region.

[0007] One aspect of the present disclosure is to provide a system for processing the layout of semiconductor devices. The system includes at least one processor and a non-transitory computer-readable storage medium connected to the processor. The non-transitory computer-readable storage medium is used to store instructions, and the processor is configured to execute the instructions to generate a first transistor in an active device region and a second transistor in a guard ring region, wherein the first transistor includes a first channel region, and the second transistor includes a second channel region, and the thermal conductivity of the second channel region is higher than the thermal conductivity of the first channel region.

[0008] One aspect of the present disclosure is to provide a semiconductor device, including a substrate, a transistor located in an active device region of the substrate, a resistor located in a passive device region of the substrate, a contact structure and an interconnection layer. The transistor includes a channel region and a source / drain region. The contact structure overlies the source / drain region of the transistor. The interconnection layer electrically couples the contact structure and a first terminal of the resistor, and the second terminal of the resistor is floating. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, wherein components numbered with the same reference numerals represent similar components throughout. It should be emphasized that, in accordance with standard practice in the industry, various features may not be drawn to scale and are used for illustration purposes only. In fact, the dimensions of various features in the drawings may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1A is a plan view of a layout of a semiconductor element according to some embodiments;

[0011] Figure 1B According to some embodiments Figure 1A The layout is manufactured and along Figure 1A A cross-sectional view of the semiconductor element taken along line BB′ in FIG.

[0012] Figure 1C According to some embodiments Figure 1A The layout is manufactured and along Figure 1A A cross-sectional view of a semiconductor element cut along line CC′ in FIG.

[0013] Figure 2A is a plan view of a layout of a semiconductor element according to some embodiments;

[0014] Figure 2B According to some embodiments Figure 2A The layout is manufactured and along Figure 2A A cross-sectional view of the semiconductor element cut along line BB′ in FIG.

[0015] Figure 2C According to some embodiments Figure 2A The layout is manufactured and along Figure 2A A cross-sectional view of a semiconductor element cut along line CC′ in FIG.

[0016] Figure 3 is a plan view of a layout of a semiconductor element according to some embodiments;

[0017] Figure 4 is a plan view of a layout of a semiconductor element according to some embodiments;

[0018] Figure 5 is a plan view of a layout of a semiconductor element according to some embodiments;

[0019] Figure 6 is a plan view of a layout of a semiconductor element according to some embodiments;

[0020] Figure 7 is a schematic diagram of a simulation circuit according to some embodiments;

[0021] Fig. 8A is a plan view of a layout of an analog circuit according to some embodiments;

[0022] Figure 8B is based on Fig. 8A The layout is manufactured and along Fig. 8A A cross-sectional view of the semiconductor element cut along line BB′ in FIG.

[0023] Fig. 9 is a schematic diagram of a system for designing a layout of a semiconductor component according to some embodiments;

[0024] Fig.10 is a block diagram of a manufacturing system for fabricating a semiconductor device according to some embodiments.

[0025]

Explanation of symbols

[0026] 100, 200, 300, 400, 500, 600, 800: Layout

[0027] 100', 200', 800': semiconductor components

[0028] 100a, 800a: Active component area

[0029] 100b: Guard ring area

[0030] 100c: Dummy component area

[0031] 102, 802: Substrate

[0032] 104, 804: Isolation structure

[0033] 108: Shared SRB layer

[0034] 110, 120, 810: semiconductor fins

[0035] 112, 122, 812: Channel area

[0036] 114, 124, 814: Source region

[0037] 116, 126, 816: Drain region

[0038] 118, 128, 818: Strain relaxation buffer (SRB) layer

[0039] 130, 130a, 130b, 830: Gate structure

[0040] 132, 832: Gate dielectric layer

[0041] 134, 834: Gate electrode layer

[0042] 140a, 140b, 140c, 840: FinFET

[0043] 150: Gate cutting

[0044] 160: Channel blocking layer

[0045] 172, 172a, 172b, 872: Source contact structure

[0046] 174a, 174b, 874: Drain contact structure

[0047] 180: Interconnect metal layer

[0048] 182, 882: Source dielectric hole

[0049] 184: Guard ring interlayer hole

[0050] 193, 195, 197, 895, 897: Arrow

[0051] 260: Epitaxial barrier layer

[0052] 560: NT_N layer

[0053] 700: Analog Circuits

[0054] 800b: First passive component area

[0055] 800c: Second passive component area

[0056] 820a: First resistor

[0057] 820b: Second resistor

[0058] 822: Doping Well

[0059] 824: The first heavily doped region

[0060] 826: Second heavily doped region

[0061] 884: Drain dielectric hole

[0062] 886: Resistor vias

[0063] 892: First interconnect metal layer

[0064] 894: Second interconnect metal layer

[0065] 900: Electronic Design Automation (EDA) System

[0066] 902: Hardware Processor

[0067] 904: Computer readable storage medium

[0068] 906: Executable instructions

[0069] 907: Design Layout

[0070] 908: Bus

[0071] 909: Design Rule Check (DRC) Item

[0072] 910: I / O interface

[0073] 912: Network interface

[0074] 914: Network

[0075] 942: User Interface (UI)

[0076] 1000: Semiconductor component manufacturing system

[0077] 1020: Design Room

[0078] 1022: Design Layout

[0079] 1030: Mask Room

[0080] 1032: Mask data preparation

[0081] 1044: Mask Manufacturing

[0082] 1045: Mask / Main Mask

[0083] 1050: Semiconductor component manufacturers / fabricators (“fabs”)

[0084] 1052: Wafer Manufacturing

[0085] 1053: Semiconductor wafer

[0086] 1060: Semiconductor components

[0087] BB′, CC′: Line

[0088] A: Node

[0089] M1, M2, M3: transistors

[0090] R1, R2, R3, R4: Resistors

[0091] S: Source

[0092] D: Drain

[0093] S1, P, P1, P2: Spacing

[0094] Vdd: voltage

[0095] W1, W2: Width DETAILED DESCRIPTION

[0096] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. The following describes specific examples of elements, values, operations, materials, arrangements or the like to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. Other elements, values, operations, materials, arrangements or the like are expected. For example, in the following description, the first feature is formed on or on the second feature and may include an embodiment in which the first feature and the second feature are formed as direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be directly contacted. In addition, the present disclosure may repeat element symbols and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself represent the relationship between the various embodiments and / or configurations discussed.

[0097] Additionally, for simplicity of description, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another (other) component or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The system may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0098] Integrated circuits often increase in temperature during use, which often limits the performance and reliability of the integrated circuits. As device dimensions continue to shrink, self-heating effects in complementary metal oxide semiconductor (CMOS) logic transistors become increasingly difficult to address. Higher operating temperatures in the chip can lead to a number of problems, such as variations in device performance, increased off-state current, and reduced device reliability. For example, self-heating increases the temperature of metal interconnects, which accelerates electromigration (EM) failures of the metal interconnects. Self-heating also adversely affects intrinsic device reliability mechanisms, such as bias temperature instability (BTI) and hot carrier injection (HCI).

[0099] The recent trend to introduce new geometry-constrained device structures, such as FinFETs, and the continued incorporation of new materials with low thermal conductivity into device active areas and metal contacts to boost device performance further exacerbates self-heating and, therefore, device reliability issues.

[0100] For example, FinFETs are increasingly used in many logic and other applications and are integrated into various types of semiconductor components. FinFETs include semiconductor fins with a high aspect ratio in which a channel and source / drain regions for a transistor are formed. A gate is formed on and along the sides of a portion of the semiconductor fin. The use of fins increases the surface area of ​​the channel and source / drain regions, resulting in faster, more reliable, and better controlled transistors that consume less power than planar transistors. However, the FinFET architecture causes significant self-heating due to the higher component density and narrower conduction path (small fin width) compared to planar metal oxide semiconductor field effect transistor (MOSFET) components.

[0101] Strained silicon germanium (SiGe) has recently been used as a high mobility channel material in FinFETs. However, SiGe has a lower thermal conductivity than silicon (Si). For example, the thermal conductivity of SiGe with 50% Ge is only about 10% of that of pure Si. The low thermal conductivity of SiGe makes conduction cooling through the substrate inefficient and increases problems associated with self-heating. In addition, because the new technology uses cobalt (Co), which has a much higher conductivity than copper, as the source / drain contacts, heat dissipation through the upper interconnect metal layer in the back end of the line (BEOL) is also hindered due to the reduced thermal conductivity of cobalt compared to copper or tungsten.

[0102] Therefore, as technology scales to smaller dimensions, self-heating has become a design consideration for high-efficiency circuits. However, other FinFET layout designs cannot adequately dissipate heat because they lack an effective heat dissipation path to transfer heat into the substrate.

[0103] Embodiments of the present disclosure provide FinFET design layouts with superior heat dissipation capabilities over other approaches. In some embodiments, the FinFET design layout includes guard rings, dummy elements, or resistors to help dissipate heat generated by active FinFETs to the substrate, thereby overcoming or reducing problems associated with self-heating caused by low heat transfer of channel materials and contact metals in FinFET-based integrated circuits. In some embodiments, the disclosed layouts are useful for improving the reliability of analog mixed-signal or radio frequency (RF) circuits.

[0104] Figure 1A is a plan view of a layout 100 of a semiconductor device according to some embodiments.

[0105] refer to Figure 1A, the layout 100 includes a plurality of semiconductor fins 110, a plurality of semiconductor fins 110120 and a plurality of gate structures 130, which can be used to form a plurality of FinFETs 140a in an active device region 100a and a plurality of FinFETs 140b in a guard ring region 100b adjacent to the active device region 100a. The FinFETs 140a in the active device region 100a are capable of performing the functions of the integrated circuit, however, the FinFETs 140b in the guard ring region 100b are not used to perform the functions of the integrated circuit, but the FinFETs 140b are used to provide electromagnetic shielding between different parts of the integrated circuit, and the components in the integrated circuit maintain normal functions despite the parasitic effects from adjacent components. When in use, the FinFETs 140a generate heat. Because no power or negligible power is applied to the FinFETs 140b in the guard ring region 100b, the guard ring region 100b acts as a heat sink to remove the heat generated by the FinFETs 140a. Guard ring region 100b thus not only serves to provide electromagnetic shielding for FinFETs 140a in active device region 100a, but also helps dissipate heat generated by FinFETs 140a. Dissipating heat generated from active device region 100a mitigates electromigration degradation, for example, in BEOL interconnect metal layers.

[0106] The active device region 100a includes at least one semiconductor fin 110, and the guard ring region 100b includes at least one semiconductor fin 120. Although a single semiconductor fin 110 in the active device region 100a and a single semiconductor fin 120 in the guard ring region 100b are illustrated, the scope of the present disclosure is not limited thereto, and any number of semiconductor fins 110 and semiconductor fins 120 in the active device region 100a and the guard ring region 100b are contemplated. The semiconductor fins 110 and semiconductor fins 120 extend along a first direction (e.g., the x direction) and are isolated from each other by an isolation structure 104. Adjacent semiconductor fins 110 and 120 in the corresponding active device region 100a and the guard ring region 100b are separated from each other by a spacing S1. The minimum spacing permitted by the design rule for spacing S1 helps to maximize the heat dissipation rate. In some embodiments, at least one semiconductor fin 120 in the guard ring region 100b has a size and shape similar to at least one semiconductor fin 110 in the active device region 100a. In other embodiments, the semiconductor fin 120 in the guard ring region 100b is substantially larger or smaller than the semiconductor fin 110 in the active device region 100a.

[0107] The gate structure 130 extends across the semiconductor fins 110 and the semiconductor fins 120 along a second direction (e.g., y direction). In some embodiments, the second direction y is perpendicular to the first direction x. In some embodiments, the gate structures 130 have a uniform pitch. The gate pitch p is defined as the sum of the width of a single gate structure and the distance between the single gate structure and an adjacent gate structure. In some embodiments, the gate structures 130 have different pitches from each other. When the gate structures 130 have a fixed pitch, greater control over the critical dimensions of the gate structures 130 is achieved. Although in Figure 1A There are eight gate structures in the figure, but the scope of the present disclosure is not limited thereto. In some embodiments, a single gate structure or a different number of gate structures are used. The gate structure 130 includes a gate structure 130a that passes over the semiconductor fin 110 in the active device region 100a, and includes a gate structure 130b that passes over the semiconductor fin 120 in the guard ring region 100b.

[0108] Each FinFET 140a in the active device region 100a includes a channel region 112 in a portion of the semiconductor fin 110 underlying the corresponding gate structure 130a, and a source region 114 and a drain region 116 in portions of the semiconductor fin 110 on opposite sides corresponding to the gate structure 130a. The source region 114 and the drain region 116 surround the channel region 112. Each FinFET 140b in the guard ring region 100b includes a channel region 122 in a portion of the semiconductor fin 120 underlying the corresponding gate structure 130b, and a source region 124 and a drain region 126 in portions of the semiconductor fin 120 on opposite sides corresponding to the gate structure 130b. The source region 124 and the drain region 126 surround the channel region 122. The channel regions 112 and 122 are relatively lightly doped regions, while the source regions 114, 124, the drain regions 116, and the drain regions 126 are relatively heavily doped regions. In some embodiments, the channel regions 112 and 122 include a first conductivity type dopant, while the source regions 114, 124, and the drain regions 116, 126 include a second conductivity type dopant opposite to the first conductivity type. In some embodiments, when the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. In some embodiments, the channel regions 112 and 122 include an n-type dopant, while the source regions 114, 124, the drain regions 116, and the drain regions 126 include a p-type dopant, and the p-type dopant is used to form a p-type FinFET (pFinFET). In some embodiments, channel regions 112 and 122 include p-type dopants, while source regions 114 , 124 , drain regions 116 and 126 include n-type dopants for forming n-type FinFETs (nFinFETs).

[0109] The layout 100 further includes a gate cut layer 150 extending along the first direction. The gate cut layer 150 can be used to identify locations where the gate structure 130 is removed for electrical disconnection according to the integrated circuit design. Figure 1A The gate cut layer 150 in the layout 100 is located between the active device region 100a and the guard ring region 100b to indicate that the gate structure 130a and the gate structure 103b are disconnected from each other. In the design and manufacturing process of the layout 100 on a physical wafer, the presence of the gate cut layer 150 indicates that the gate structure 130 is initially formed as a long and continuous strip extending through the active device region 100a and the guard ring region 100b, and then etched (cut) into shorter pieces in subsequent processes to provide the gate structures 130a and 130b in the corresponding active device region 100a and the guard ring region 100b.

[0110] The layout 100 further includes a channel barrier layer 160 above the guard ring region 100b. The channel barrier layer 160 is placed in alignment with the channel region 122 and can be used to indicate that a semiconductor material is used as the channel material in the channel region 122, and this semiconductor material has a higher thermal conductivity than the semiconductor material of the provided channel region 112. The channel region 122 therefore has a high heat dissipation capability and can be used to remove heat from the active device region 100a to the guard ring region 100b. In some embodiments, when SiGe is used as the channel material to enhance the carrier mobility in the FinFET 140a, the channel barrier layer 160 is a SiGe barrier layer. The presence of the SiGe barrier layer indicates that SiGe is present only in the channel region 112, but not in the channel region 112, and a semiconductor material having a higher thermal conductivity than SiGe is used as the channel material in the FinFET 140b instead to facilitate heat dissipation to the guard ring region 100b. In some embodiments, when the channel region 112 of the FinFET 140a in the active device region 100a includes SiGe, the channel region 122 of the FinFET 140b in the guard ring region 100b includes intrinsic (undoped) Si or lightly doped Si. As used herein, lightly doped means less than about 1×10 13 atom / cm 3 Since the FinFET 140b in the guard ring region 100b is a non-active element, when SiGe does not exist in the channel region 122 of the FinFET 140b, the circuit performance will not be affected.

[0111] The via barrier layer 160 can be generated using available computer-aided design (CAD) libraries, so the introduction of the via barrier layer 160 in the layout 100 is accomplished without generating any new CAD layers.

[0112] The layout 100 further includes a plurality of source contact structures 172 and a plurality of drain contact structures 174a and 174b. The source contact structures 172 extend from the active device region 100a to the guard ring region 100b. Each source contact structure 172 is located above a corresponding source region 114 in the active device region 100a and a corresponding source region 124 in the guard ring region 100b so as to couple the corresponding source region 114 in the active device region 100a to the corresponding source region 124 in the guard ring region 100b. Each source contact structure 172 thus acts as a heat conducting layer and helps remove heat generated by the FinFET 140a from the source region 114 of the FinFET 140a to the guard ring region 100b. In some embodiments, each source contact structure 172 directly couples the corresponding source region 114 in the active device region 100a to the corresponding source region 124 in the guard ring region 100b. The drain contact structure includes a first set of drain contact structures 174a over the drain region 116 of the FinFET 140a in the active device region 100a, and a second set of drain contact structures 174b over the drain region 126 of the FinFET 140b in the guard ring region 100b. The drain contact structures 174a are configured to provide electrical connection to the underlying drain region 116 of the FinFET 140a in the active device region 100a, while the drain contact structures 174b are configured to provide electrical connection to the underlying drain region 126 of the FinFET 140b in the guard ring region 100b.

[0113] The layout 100 further includes a plurality of interconnect metal layers 180. Each interconnect metal layer 180 contacts at least one source via 182 over a first portion of a corresponding source contact structure 172 in the active device region 100a, and at least one guard ring via 184 over a second portion of a corresponding source contact structure 172 in the guard ring region 100b, thereby additionally coupling the corresponding source region 112 to the guard ring region 100b through at least the at least one source via 182, the interconnect metal layer 180, and the at least one guard ring via 184. Each interconnect metal layer 180 thus acts as a thermally conductive layer to provide an additional heat dissipation path through which heat removed from the corresponding source contact structure 172 is transferred to an upper interconnect metal layer (not shown) in the BEOL by means of the vias 182, the vias 184, and the interconnect metal layer 180. In some embodiments, each interconnect metal layer 180 is used in an integrated circuit as an electrical coupling element configured to connect a corresponding source region 114 in the active device region 100 a to one or more other devices of the integrated circuit.

[0114] In some embodiments, the layout 100 is represented by a plurality of masks, which are generated by one or more processors and / or stored in one or more non-transitory computer-readable media. Other formats for representing the layout 100 are within the scope of various embodiments. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more of optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), and the like. For example, the layout 100 is presented by: at least one first mask corresponding to the semiconductor fin 110 and the semiconductor fin 120; at least one second mask corresponding to the gate structure 130; at least one third mask corresponding to the gate cut layer 150; at least one fourth mask corresponding to the channel blocking layer 160; at least one fifth mask corresponding to the source contact structure 172, the drain contact structure 174a and the drain contact structure 174b; and at least one sixth mask corresponding to the interconnect metal layer 180, the via 182 and the via 184.

[0115] Figure 1B and Figure 1C Based on Figure 1A 1 is a cross-sectional view of a semiconductor component 100 ′ fabricated according to the layout 100 depicted in FIG. Figure 1B The cross-sectional view is along Figure 1A Line BB′ in. Figure 1C The cross-sectional view is along Figure 1A The semiconductor device 100' is a non-limiting example for the purpose of illustrating the present disclosure. Figure 1B and Figure 1C The configuration of the semiconductor device 100 ′ is described with reference to the accompanying drawings.

[0116] refer to Figure 1B and Figure 1C, the semiconductor device 100' includes a substrate 102 and an isolation structure 104, a semiconductor fin 110, a semiconductor fin 120, and a gate structure 103a and a gate structure 103b on the substrate 102. In some embodiments, the substrate 102 is a silicon substrate, or a substrate formed of other suitable semiconductor materials. In some embodiments, the substrate 102 is doped with n-type or p-type dopants. The isolation structure 104 electrically isolates various components of the semiconductor device 100' from each other. In some embodiments, the isolation structure 104 includes a dielectric material, such as silicon dioxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. The semiconductor fin 110 and the semiconductor fin 120 extend above the top surface of the isolation structure 104 and are electrically isolated from each other by the isolation structure 104. At least one semiconductor fin 110 is in the active device region 100a of the substrate 102. The gate structure 130a intersects with the semiconductor fin 110 to define a FinFET 140a in the active device region 100a of the substrate 102. At least one semiconductor fin 120 is in the guard ring region 100b of the substrate 102. The gate structure 130b intersects the semiconductor fin 120 to define a FinFET 140b in the guard ring region 100b of the substrate 102. FinFETs 140a and 140b have similar structures and will be described collectively below.

[0117] Each FinFET 140a in the active device region 100a includes a gate structure 130a spanning a channel region 112 of a semiconductor fin 110, and a source region 114 and a drain region 116 in a portion of the semiconductor fin 110 on opposite sides of the gate structure 130a. Each FinFET 140b in the guard ring region 100b includes a gate structure 130b spanning a channel region 122 of a semiconductor fin 120, and a source region 124 and a drain region 116 in a portion of the semiconductor fin 120 on opposite sides of the gate structure 130b. In some embodiments, the FinFETs 140a and the FinFETs 140a-140b are nFinFETs, and the channel regions 112 and 122 therefore include p-type dopants (such as boron), and the source regions 114, 124, 116, and 126 include n-type dopants (such as phosphorus or arsenic). To facilitate heat dissipation through the substrate 102, the corresponding channel region 122 in the guard ring region 110b is provided with a semiconductor material having a greater thermal conductivity than the semiconductor material providing the corresponding channel region 112 in the active device region 110a. The channel region 122 thus acts as a heat sink to dissipate heat generated by the FinFET 140a to the substrate 102. In some embodiments, when the channel region 112 of the FinFET 140a in the active device region 100a includes SiGe for increasing the electron mobility of the nFinFET, the channel region 122 of the FinFET 140b in the guard ring region 100b includes Si to facilitate heat dissipation through the substrate 102.

[0118] In some embodiments, each gate structure 130a and gate structure 130b contacts the semiconductor fin 110 and semiconductor fin 120 on its top surface and sidewalls. In some embodiments, each gate structure 130a and gate structure 130b only contacts the sidewalls (not shown) of the semiconductor fin 110 and semiconductor fin 120. Each gate structure 130a and gate structure 130b includes a gate dielectric layer 132 and a gate electrode layer 134. Exemplary materials of the gate dielectric layer 132 include, but are not limited to, high-k dielectric materials, interface layers, and / or combinations thereof. Exemplary materials for the high-k dielectric layer include, but are not limited to, silicon nitride, silicon oxynitride, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, metal oxynitrides, metal aluminates, zirconium silicate, zirconium aluminate, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloy, suitable high-k dielectric materials, and / or combinations thereof. In some embodiments, the gate dielectric layer 132 includes, for example, a multilayer structure of SiO2 with a high-k dielectric or SiON with a high-k dielectric. In some embodiments, the gate electrode layer 134 includes doped polysilicon (polysilicon). Alternatively, the gate electrode layer 134 includes a metal such as aluminum, copper, tungsten, titanium, thallium, TiN, TaN, NiSi, CoSi, other suitable conductive materials, or combinations thereof.

[0119] The semiconductor device 100' further includes a strain relaxation buffer (SRB) layer 118 and a strain relaxation buffer layer 128. Figure 1B and Figure 1CIn the exemplary configuration of FIG. 1 , the semiconductor device 100 ′ includes an SRB layer 118 located between the semiconductor fin 110 and the substrate 102 in the active device region 100 a, and an SRB layer 128 located between the semiconductor fin 120 and the substrate 102 in the guard ring region 100 b. The isolation structure 104 surrounds the SRB layer 118 and the SRB layer 128. In some embodiments, the SRB layer 118 and the SRB layer 128 merge at their bottoms to form a common SRB layer 108 for the semiconductor fin 110 and the semiconductor fin 120. In some embodiments, the SRB layer 118 and the SRB layer 128 are separated at the bottom (not shown). The SRB layer 118 includes a material capable of increasing the stress of the channel region 112 of the FinFET 140 a. In some embodiments, when the channel region 112 of the FinFET 140a includes SiGe having about 75% Si and 25% Ge for nFinFET, the SRB layer 118 includes SiGe having about 50% Si and 50% Ge. The SRB layer 118 provides tensile stress to the channel region 112, thereby increasing the electron mobility in the channel region 112. Therefore, the performance of the FinFET 140a is enhanced. The SRB layer 128 includes the same material as the SRB layer 118.

[0120] The semiconductor device 100' further includes a contact structure to provide electrical connection with the FinFET 140a and the FinFET 140b. The contact structure includes: a source contact structure 172, which is used to couple the source region 114 of the FinFET 140a in the active device region 100a to the source region 124 of the FinFET 140b in the guard ring region 100b; a drain contact structure 174a ( Figure 1A ), which covers the drain region 116 ( Figure 1A ); and drain contact structure 174b ( Figure 1A ), which covers the drain region 126 ( Figure 1A ). The source contact structure 172, the drain contact structure 174a, and the gate contact structure 174b include a metal such as, for example, cobalt, copper, or tungsten.

[0121] The semiconductor device 100' further includes an interconnect metal layer 180 to electrically couple the source contact structure 172 to one or more other devices of the semiconductor device 100'. Each interconnect metal layer 180 contacts at least one source via 182 on a first portion of a corresponding source contact structure 172 in the active device region 100a, and at least one guard ring via 184 on a second portion of a corresponding source contact structure 172 in the guard ring region 100b, so that heat generated by the FinFET 140a is transferred to an upper interconnect metal layer (not shown) of the BEOL, providing an additional heat dissipation path for the FinFET 140a. The interconnect metal layer 180, the via 182, and the via 184 include, for example, aluminum, copper, tungsten, or alloys thereof.

[0122] Figure 1B and Figure 1C The dashed arrows in the figure show the heat dissipation path in the semiconductor element 100'. By using a semiconductor material with high thermal conductivity as the channel material in the channel region 122 of the FinFET 140b in the guard ring region 100b, the channel region 122 in the guard ring region 100b (as shown by arrow 193 ( Figure 1B ), heat generated by FinFET 140a is removed out of the structure through substrate 102. In addition, with the help of source contact structure 172 as indicated by arrow 195, some of the heat generated by FinFET 140a is dissipated from the source region 114 of FinFET 140a to guard ring region 100b and then to substrate 102. In addition, some of the heat removed by source contact structure 172 can also be dissipated out of the structure through interconnect metal layer 180 above source contact structure 172 and further as indicated by arrow 197 through upper interconnect metal layer (not shown) of BEOL.

[0123] Figure 2A FIG. 2 is a plan view of a layout 200 of a semiconductor device according to some embodiments. Figure 1A Compared to the layout 100 of FIG. 2 , in the layout 200, the epitaxial barrier layer 260 replaces the channel barrier layer 160 in the guard ring region 100b to allow for the formation of a better heat dissipation structure. In some embodiments, in the layout 200, the gate structure 130b is removed from the guard ring region 100b to further promote heat dissipation. In some embodiments, the gate structure 130b remains in the guard ring region 100b (not shown).

[0124] The same or similar to the layout 200 Figures 1A to 1C The elements in the drawings will be given the same element numbers, and thus their detailed description will be omitted.

[0125] refer to Figure 2A, an epitaxial barrier layer 260 is placed in the guard ring region 100b. The epitaxial barrier layer 260 can be used to indicate that all low thermal conductivity materials used in the epitaxial region (including the channel region 112, the source region 114, and the drain region 116 of the FinFET 140a) and the SRB layer 118 in the active device region 110a are blocked in the guard ring region 100b. Therefore, only semiconductor materials with high thermal conductivity are utilized in the guard ring region 100b. In some embodiments, the guard ring region 100b includes a semiconductor material having a thermal conductivity greater than 100 W / mk. Depending on the design rules, in some embodiments, the epitaxial barrier layer 260 is provided as a continuous layer to cover the entirety of the guard ring region 100b (not shown), and in some embodiments, the epitaxial barrier layer 260 is provided as a plurality of non-continuous sections, so that the epitaxial barrier layer 260 only covers certain portions of the semiconductor material of the desired high thermal conductivity of the guard ring region 100b ( Figure 2A ). Similar to Figure 1A The channel barrier layer 160 in the layout 100 can be generated using an available computer-aided design (CAD) library to generate the epitaxial barrier layer 260 in the layout 200, thereby completing the introduction of the epitaxial barrier layer 260 in the layout 200 without generating any new CAD layers.

[0126] In some embodiments, the layout 200 is represented by a plurality of masks that are generated by one or more processors and / or stored in one or more non-transitory computer-readable media. Other formats for representing the layout 200 are within the scope of various embodiments. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more of optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), and the like. For example, the layout 200 is presented by: at least one first mask corresponding to the semiconductor fin 110, the semiconductor fin 120; at least one second mask corresponding to the gate structure 130a; at least one third mask corresponding to the epitaxial barrier layer 260; at least one fourth mask corresponding to the source contact structure 172, the drain contact structure 174a and the drain contact structure 174b; and at least one fifth mask corresponding to the interconnect metal layer 180, the via 182 and the via 184.

[0127] Figure 2B and Figure 2C Based on Figure 2A FIG. 2 is a cross-sectional view of a semiconductor component 200 ′ manufactured using the layout 200 . Figure 2B The cross-sectional view is along Figure 2A Line BB′ in. Figure 2C The cross-sectional view is along Figure 2A The line CC' in this article refers to Figure 2B and Figure 2C The configuration of the semiconductor device 200' is described with reference to the accompanying drawings. Figures 1A to 1C The elements in the drawings will be given the same element numbers, and thus their detailed description will be omitted.

[0128] refer to Figure 2B and Figure 2C ,and Figure 1B and Figure 1C Compared to the semiconductor device 100' of the embodiment of the present invention, in the semiconductor device 200', the SRB layer 128 is not formed in the guard ring region 100b, so that the semiconductor fin 120 in the guard ring region 100b is in direct contact with the substrate 102, thereby achieving direct heat dissipation from the semiconductor fin 120 to the underlying substrate 102. In addition, the entire semiconductor fin 120 in the guard ring region 100b is provided to include a semiconductor material having a higher thermal conductivity than the semiconductor material providing the corresponding channel region 112, source region 114 and drain region 116 of the FinFET 140a in the active device region 100a, so as to provide an increased heat dissipation surface area. For example, in the active device region 100a, when the channel region 112 includes strained Si and the source region 114 and the drain region 116 include n-doped SiGe for forming an nFinFET 140a, or when the channel region 112 includes strained SiGe and the source region 114 and the drain region 116 include p-doped SiGe for forming a pFinFET 140a, SiGe is not used in the guard ring region 100b, and the semiconductor fins 120 in the guard ring region 100b only include Si, which has a higher thermal conductivity than SiGe.

[0129] Additionally, the gate structure 130 b is removed from the guard ring region 100 b . The removal of the gate structure 130 b removes the dielectric material used in the gate structure 130 b , which has a lower conductivity than the guard ring region 100 b , so as to further promote heat dissipation through the substrate 102 .

[0130] Removing the epitaxial semiconductor material with low thermal conductivity in the gate structure 130 a and the guard ring region 100 b results in more efficient heat removal through the substrate 102 .

[0131] Similar to Figure 1B and Figure 1C In the semiconductor device 100', heat generated by the FinFET 140a in the active device region 100a can be dissipated via the substrate 102 (as indicated by arrow 193), the source contact structure 172 (as indicated by arrow 195), and the interconnect metal layer 180 (as indicated by arrow 197).

[0132] Figure 3 FIG. 3 is a plan view of a layout 300 of a semiconductor device according to some embodiments. Figure 1A Compared to the layout 100 of FIG. 1 , in the layout 300 , the FinFET 140 b in the guard ring region 100 b is configured to have a channel length longer than a channel length of the FinFET 140 a in the active device region 100 a . Figure 3 Same or similar to Figures 1A to 1C The elements in the drawings will be given the same element numbers, and thus their detailed description will be omitted.

[0133] refer to Figure 3 , the layout 300 includes a FinFET 140a in the active device area 100a and a FinFET 140b in the guard ring area 100b. Each FinFET 140a includes a gate structure 130a that spans the channel region 112 of the semiconductor fin 110. Each FinFET 140b includes a gate structure 130b that spans the channel region 122 of the semiconductor fin 120. The channel width of the FinFET is defined by the width of the gate structure. In the layout 300, each gate structure 130a in the active device area 110a has a width W1 that can be measured along the x-direction, and each gate structure 130b in the guard ring area 100b has a width W2 that can be measured along the x-direction. The width W2 is set to be greater than the width W1 so as to provide a larger channel length for the FinFET 140b in the guard ring area 100b. The larger channel length of the FinFET 140b in the guard ring region 100b increases the heat dissipation surface area, thereby allowing more heat to be dissipated through the underlying substrate. Thus, the self-heating effect of the resulting integrated circuit is reduced.

[0134] Unlike the layout 100 in which a single source contact structure 172 is used to couple both the source region 114 in the active device region 100a and the source region 124 in the guard ring region 100b, in the layout 300, a source contact structure 172a is formed to contact the corresponding source region 114 of the FinFET 140a in the active device region 100a, and a source contact structure 172b is formed to contact the corresponding source region 124 in the guard ring region 100b. The source contact structure 172a provides an electrical connection to the source region 114, while the source contact structure 172b provides an electrical connection to the source region 124. Because there is no single source contact structure coupling both the source region 114 and the source region 124 in the layout 300, heat dissipation in the layout 300 is mainly performed through the substrate on which the FinFETs 140a, 140b are formed.

[0135] In some embodiments, the layout 300 is represented by a plurality of masks (generated by one or more processors) and / or stored in one or more non-transitory computer-readable media. Other formats for representing the layout 300 are within the scope of various embodiments. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more of optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), and the like. For example, the layout 300 is presented by: at least one first mask corresponding to the semiconductor fins 110 and the semiconductor fins 120; at least one second mask corresponding to the gate structure 130a and the gate structure 130b; at least one third mask corresponding to the channel blocking layer 160; at least one fourth mask corresponding to the source contact structure 172a, 172b and the drain contact structure 174a, 174b; and at least one fifth mask corresponding to the interconnect metal layer 180, the via 182 and the via 184.

[0136] The layout 300 uses a channel blocking layer 160 in the guard ring region 100b. It should be understood by those skilled in the art that the channel blocking layer 160 used in the guard ring region 100b is not limited to the channel blocking layer 160 of FIG. Figure 2A The epitaxial barrier layer 260 is contemplated and falls within the scope of the present disclosure.

[0137] Figure 4 FIG. 4 is a plan view of a layout 400 of a semiconductor device according to some embodiments. Figure 1A Compared to the layout 100 of the present invention, in the layout 400, the gate structure 130b in the guard ring region 100b is configured to have a gate pitch P2 that is larger than the gate pitch P1 of the gate structure 130a in the active device region 100a. Figures 1A to 1C The elements in the drawings will be given the same element numbers, and thus their detailed description will be omitted.

[0138] refer to Figure 4, layout 400 includes FinFETs 140a in the active device region 100a and FinFETs 140b in the guard ring region 100b. Each FinFET 140a includes a gate structure 130a that spans the channel region 112 of the semiconductor fin 110. Each FinFET 140b includes a gate structure 130b that spans the channel region 122 of the semiconductor fin 120. In layout 400, the gate structure 130a in the active device region 100a has a spacing P1 that can be measured along the x-direction, and the gate structure 130b in the guard ring region 100b has a spacing P2 that can be measured along the x-direction. The gate spacing P2 is set to be greater than the gate spacing P1. The larger gate spacing of the gate structure 130b in the guard ring region 100b helps to reduce the self-heating effect of the resulting integrated circuit due to the larger area for heat dissipation. In some embodiments and as Figure 4 As shown in FIG. 1 , the gate structure 130 b has the same width as the gate structure 130 a , while the source region 124 has a greater width than the source region 114 , and the drain region 126 has a greater width than the drain region 116 .

[0139] The layout 400 further includes a source contact structure 172a that contacts the corresponding source region 114 of the FinFET 140a in the active device region 100a, and a source contact structure 172b that contacts the corresponding source region 124 in the guard ring region 100b. The source contact structure 172a provides an electrical connection to the source region 114, while the source contact structure 172b provides an electrical connection to the source region 124. Because there is no single source contact structure coupling both the source region 114 and the source region 124 in the layout 400, heat dissipation in the layout 400 is primarily through the underlying substrate.

[0140] In some embodiments, the layout 400 is represented by a plurality of masks (generated by one or more processors) and / or stored in one or more non-transitory computer-readable media. Other formats for representing the layout 400 are within the scope of various embodiments. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more of optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), and the like. For example, the layout 400 is presented by: at least one first mask corresponding to the semiconductor fins 110 and the semiconductor fins 120; at least one second mask corresponding to the gate structure 130a and the gate structure 130b; at least one third mask corresponding to the channel blocking layer 160; at least one fourth mask corresponding to the source contact structure 172a, the source contact structure 172b, the drain contact structure 174a and the drain contact structure 174b; and at least one fifth mask corresponding to the interconnect metal layer 180, the via 182 and the via 184.

[0141] Layout 400 uses a channel blocking layer 160 in the guard ring region 100b. It should be understood by those skilled in the art that the channel blocking layer 160 used in the guard ring region 100b is not limited to the channel blocking layer 160 used in the guard ring region 100b. Figure 2A The epitaxial barrier layer 260 is contemplated and falls within the scope of the present disclosure.

[0142] Figure 5 FIG. 5 is a plan view of a layout 500 of a semiconductor device according to some embodiments. Figure 1A Compared to the layout 100 of FIG. 5 , in the layout 500 , the native or NT_N layer 560 replaces the channel barrier layer 160 in the guard ring region 100 b. Figures 1A to 1C The elements in the drawings will be given the same element numbers, and thus their detailed description will be omitted.

[0143] refer to Figure 5, the NT_N layer 560 is aligned with the channel region 122 of the FinFET 140b. The NT_N layer 560 can be used to define an undoped area. In some embodiments, the NT_N layer 560 is added to the layout 500 to indicate that the channel region 122 of the FinFET 140b in the guard ring region 100b is not doped with a p-type dopant or an n-type dopant. In some embodiments, the NT_N layer 560 is added to the layout 500 to indicate that the channel region 122 of the FinFET 140b in the guard ring region 100b has a lower doping concentration than the doping concentration of the channel region 112 of the FinFET 140a in the active device region 100a. Due to increased phonon boundary scattering, it is known that higher doping concentrations reduce the thermal conductivity of Si. Therefore, reducing the doping concentration in the channel region 122 in the guard ring region 100b reduces the thermal resistance of the channel material, which helps to promote heat dissipation through the underlying substrate.

[0144] Similar to Figure 1A The channel barrier layer 160 in the layout 100 of FIG. 5 can generate the NT_N layer 560 in the layout 500 using an available computer-aided design (CAD) library, so the introduction of the NT_N layer 560 in the layout 500 is accomplished without generating any new CAD layers.

[0145] Layout 500 is capable of dissipating the generated heat out of the structure with the help of the underlying substrate, source contact structure 172 and interconnect metal layer 180 .

[0146] Although in the layout 500, the gate structure 130b in the guard ring region 100b is illustrated as having the same gate width and the same gate pitch as the gate structure 130a in the active device region 100a, in some embodiments, the gate structure 130b may have the same gate width and the same gate pitch as the gate structure 130a in the active device region 100a. Figure 3 and Figure 4 It is foreseeable that the gate structure 130 b with a larger gate width and / or a larger gate pitch as shown in the figure can be combined with the addition of the NT_N layer 560 to further improve the heat dissipation capability of the integrated circuit.

[0147] In some embodiments, the layout 500 is represented by a plurality of masks (generated by one or more processors) and / or stored in one or more non-transitory computer-readable media. Other formats for representing the layout 500 are within the scope of various embodiments. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more of optical disks (such as DVDs), magnetic disks (such as hard disks), semiconductor memories (such as ROM, RAM, memory cards), and the like. For example, the layout 500 is presented by: at least one first mask corresponding to the semiconductor fin 110, the semiconductor fin 120; at least one second mask corresponding to the gate structure 130; at least one third mask corresponding to the gate cut layer 150; at least one fourth mask corresponding to the NT_N layer 560; at least one fifth mask corresponding to the source contact structure 172, the drain contact structure 174a and the drain contact structure 174b; and at least one sixth mask corresponding to the interconnect metal layer 180, the via 182 and the via 184.

[0148] Figure 6 FIG. 6 is a plan view of a layout 600 of a semiconductor device according to some embodiments. Figure 1A Compared to the layout 100 in FIG. 6 , in the layout 600 , the dummy FinFET 140 c in the dummy element region 100 c replaces the FinFET 140 b in the guard ring region 100 b. Figures 1A to 1C The elements in the drawings will be given the same element numbers, and thus their detailed description will be omitted.

[0149] refer to Figure 6, the layout 600 includes a FinFET 140a in the active device region 100a and a dummy FinFET 140c in the dummy device region 100c adjacent to the active device region 100a. As used herein, a dummy structure refers to a structure in the final manufactured component that is used to mimic the physical properties of another structure and is inoperable for the circuit (that is, it is not part of the circuit current flow path). The dummy FinFET 140c is therefore substantially equivalent to the FinFET 140a in the active device region 100a in terms of configuration, but is not used to control the current flow between the source region and the drain region based on the gate voltage. Therefore, a detailed description of the components of the dummy FinFET 140c is omitted. Because no current flows through the dummy FinFET 140c, the dummy FinFET 140c helps to remove heat from the FinFET 140a in the active device region 110a through the underlying substrate. In some embodiments, including the dummy FinFET 140c in the layout 600 not only dissipates heat, but also mitigates the effects of non-ideal conditions that occur during manufacturing on the active FinFET (i.e., FinFET 140a), thereby making the manufacturability of the resulting integrated circuit more efficient. The minimum spacing S1 allowed by the design rules between the active device region 100a and the dummy device region 100c is desired to maximize the heat dissipation rate.

[0150] In the layout 600, the channel barrier layer 160 is above the dummy device region 100c and aligned with the channel region of the dummy FinFET 140c. The presence of the channel barrier layer 160 in the dummy device region 100c indicates that a semiconductor material having a higher thermal conductivity than the semiconductor material providing the channel region 112 of the FinFET 140a in the active device region 100a is used as the channel material of the dummy FinFET 140c in the dummy device region 100c. The dummy FinFET 140c can be used as a heat sink to facilitate heat dissipation to the underlying substrate.

[0151] Layout 600 is capable of dissipating the generated heat outside the structure by means of the underlying substrate, source contact structure 172 and interconnect metal layer 180 .

[0152] Those skilled in the art will understand that any of the above Figures 2A to 5 The features discussed (including epitaxial barrier layer ( Figure 2A ), maximum channel length ( Figure 3 ), larger gate spacing ( Figure 4 ) and NT_N layer ( Figure 5 )) can be used for the dummy FinFET 140c in the dummy device area 100c to maximize heat dissipation.

[0153] Figure 7FIG. 7 is a schematic diagram of an analog circuit 700 according to some embodiments. Figure 7 The analog circuit 700 includes a transistor M1, a transistor M2, and a transistor M3, and a resistor R1, a resistor R2, a resistor R3, and a resistor R4.

[0154] Transistor M1 and transistor M2 each have a source terminal electrically coupled to each other at node A. The drain terminal of transistor M1 is electrically coupled to the first terminal of resistor R1, and the drain terminal of transistor M2 is electrically coupled to the first terminal of resistor R2. The second terminal of resistor R1 and the second terminal of resistor R2 are electrically coupled to supply voltage Vdd. The drain terminal of transistor M3 is electrically coupled to node A, and the source terminal of transistor M3 is coupled to ground. Resistors R3 and R4 each have a first terminal coupled to node N, and the second terminal is floating. Resistors R3 and R4 are configured so as to be located adjacent to transistor M1 and transistor M2, respectively. Because the second terminals of the respective resistors R3 and R4 are floating, and no current flows through resistors R3 and R4, resistors R3 and R4 can be used to dissipate the heat generated by the respective transistors M1 and M2.

[0155] Fig. 8A is a plan view of a layout 800 of an analog circuit according to some embodiments.

[0156] refer to Fig. 8A , the layout 800 includes at least one semiconductor fin 810 and a plurality of gate structures 830 in an active device region 800a. The gate structure 830 intersects the semiconductor fin 810, thereby defining a plurality of FinFETs 840 in the active device region 800a. Each FinFET 840 includes a gate structure 830 that spans a channel region 812 of the semiconductor fin 810, and includes a source region 814 and a drain region 816 on opposite sides of the gate structure 830 that surrounds the channel region 812.

[0157] The layout 800 further includes a first resistor 820a, which is located in a first passive device region 800b adjacent to a first side of the active device region 800a, and a second resistor 820b, which is located in a second passive device region 800c adjacent to a second side of the active device region 800a. The active device region 800a, the first passive device region 800b, and the second passive device region 800c are separated from each other by an isolation structure 804. The first passive device region 800b is separated from the active device region 800a by a first spacing S1, and the second passive device region 800c is separated from the active device region 800a by a second spacing S2. The minimum spacing allowed by the design rules for spacing S1 and spacing S2 is expected to maximize the heat dissipation rate. Each resistor 820a and resistor 820b include a doping well 822, and a first heavily doped region 824 and a second heavily doped region 826 in the doping well 822.

[0158] The layout 800 further includes a plurality of source contact structures 872 and a plurality of drain contact structures 874. Each source contact structure 872 overlies a corresponding source region 814 to provide an electrical connection to the corresponding source region 814. Each drain contact structure 874 overlies a corresponding drain region 816 to provide an electrical connection to the corresponding drain region 816.

[0159] The layout 800 further includes a plurality of source vias 882 contacting the respective source contact structures 872 , a plurality of drain vias 884 contacting the respective drain contact structures 874 , and a plurality of resistor vias 886 contacting the first heavily doped regions 824 of the respective resistors 820 a and 820 b .

[0160] The layout 800 further includes a first interconnect metal layer 892 over the source vias 882 and the resistor vias 886. The first interconnect metal layer 892 couples the source region 814 to the first heavily doped regions 824 of the respective resistors 820a and 820b via the source contact structure 872, the source vias 882, and the resistor vias 886. The heat generated by the FinFET 840 can thus be dissipated from the source region 814 of the FinFET 840 to the resistor 820a via the first interconnect metal layer 892. The second heavily doped regions 826 of the respective resistors 820a and 820b are floated so that no current flows through the respective resistors 820a and 820b. The resistors 820a and 820b thus act as heat sinks to allow the heat generated by the FinFET 840 in the active device region 800a to reach the resistors 820a and 820b.

[0161] The layout 800 further includes a second interconnect metal layer 894 over the drain vias 884. The second interconnect metal layer 894 couples the drain regions 816 of the FinFETs 840 together.

[0162] Figure 8B Based on Fig. 8A The layout 800 depicted in FIG. Fig. 8A 8 is a cross-sectional view of a semiconductor device 800' taken along line BB' in FIG. The semiconductor device 800' is a non-limiting example for facilitating the description of the present disclosure.

[0163] The semiconductor device 800 ′ includes a substrate 802 , such as a silicon substrate. In some embodiments, the substrate 802 is doped with a p-type dopant, such as boron. In other embodiments, the substrate 802 is doped with an n-type dopant, such as phosphorus or arsenic.

[0164] The semiconductor device 800' includes a plurality of FinFETs 840 formed in an active device region 800a of a substrate 802. In some embodiments, the FinFETs 840 are configured as pFinFETs. In some embodiments, the FinFETs 840 are configured as nFinFETs. Each FinFET 840 includes a channel region 812, a source region 814 on a first side of the channel region 812, a drain region 816 on a second side of the channel region 812, and a gate structure 830 on the channel region 812. Each gate structure 830 includes a gate dielectric layer 832 and a gate electrode layer 834. The FinFETs 840 are substantially identical in configuration to the above-described Figure 1B to Figure 1C and Figure 2B to Figure 2C FinFET 140a in. Figure 1B and Figure 1C The above materials for the various components of FinFET 140 a are suitable for corresponding components of FinFET 840 .

[0165] Each FinFET 840 is formed on the SRB layer 818. In some embodiments, the SRB layer 818 includes SiGe configured to provide stress to the overlying channel region 812.

[0166] The semiconductor device 800′ further includes a first resistor 820a formed in the first passive device region 800b of the substrate 802; and a second resistor 820b formed in the second passive device region 800c ( Fig. 8A). In some embodiments, each resistor 820a and resistor 820b is configured as an n-type well resistor. In some embodiments, each resistor 820a and resistor 820b is configured as a p-type well resistor. Each resistor 820a and resistor 820b includes a doped well 822, and a heavily doped region 824 and a heavily doped region 826 formed in the substrate 802. The corresponding passive component region 800b and passive component region 800c are separated from the active component region 800a by an isolation structure 804. In some embodiments, the isolation structure 804 includes the dielectric material described above with respect to the isolation structure 104.

[0167] Doped wells 822 are formed in the substrate 802. In some embodiments, each doped well 822 is doped with a dopant having a doping polarity opposite to that of the substrate 802. In some embodiments, each doped well 822 is an n-type well for forming an n-type well resistor. In some embodiments, each doped well 822 is a p-type well for forming a p-type well resistor. A heavily doped region 824 and a heavily doped region 826 are formed at an upper surface of each doped well 822 and are adjacent to the isolation structure 804. The heavily doped region 824 and the heavily doped region 826 have the same doping polarity as the doped well 822, but have a higher doping concentration.

[0168] The semiconductor device 800' further includes a source contact structure 872 on the corresponding source region 814, and a drain contact structure 874 on the corresponding drain region 816. In some embodiments, the source contact structure 872 and the drain contact structure 874 include cobalt, copper, or tungsten.

[0169] The semiconductor device 800′ further includes a source via hole 882 on the corresponding source contact structure 872, a drain via hole 884 on the corresponding drain contact structure 874, and a drain via hole 886 on the corresponding drain contact structure 874. Fig. 8A ), and a resistor via 886 over the corresponding heavily doped region 824. A first interconnect metal layer is over the source via 882 and the resistor via 886 to couple the source region 814 of the corresponding FinFET 840 to the heavily doped region 824 of each resistor 820a and resistor 820b. A second interconnect metal layer 894 is over the drain via to couple the drain region 816 of the corresponding FinFET 840. The heavily doped region 826 of each resistor 820a and resistor 820b is floating. The via 882, the via 884, the via 886, the interconnect metal layer 892, and the interconnect metal layer 894 include a metal such as aluminum, copper, tungsten, or alloys thereof.

[0170] Figure 8BThe dashed arrows in FIG. 8 show the heat dissipation path in the semiconductor device 800 ′. Since no current flows through the corresponding resistor 820 a or resistor 820 b, the resistor 820 a and the resistor 820 b adjacent to the FinFET 840 act as a heat sink to remove the heat generated by the FinFET 840 to the passive device regions 880 b, 880 c of the substrate 802, as indicated by arrows 895. In addition, some of the heat generated by the FinFET 840 can be dissipated from the source region 814 of the FinFET 840 to the resistor 820 a and the resistor 820 b via the source contact structure 872, the source via 882, the first interconnect metal layer 892, and the resistor via 886, as indicated by arrows 897.

[0171] Although specific examples of n-type well resistors or p-type well resistors are described, other types of resistors such as, for example, polysilicon resistors, TiN resistors, metal resistors, or OD (active region) resistors are contemplated and within the scope of the present disclosure.

[0172] Fig. 9 900 . According to some embodiments, the method described herein for generating design layouts (e.g., layout 100, layout 200, layout 300, layout 400, layout 500, layout 600, and layout 800) may be implemented using, for example, EDA system 900 according to one or more embodiments. In some embodiments, EDA system 900 is a general purpose computing device that includes a hardware processor 902 and a non-transitory, computer-readable storage medium 904. Computer-readable storage medium 904 is encoded with (i.e., stores) a set of executable instructions 906, design layouts 907, design rule checking (DRC) items 909, or any intermediate data for executing such a set of instructions, among other things. Each design layout 907 includes a graphical representation of an integrated chip, such as, for example, a GSII file. Each DRC item 909 includes a list of design rules specific to a semiconductor process selected for manufacturing design layout 907. Execution of instructions 906, design layout 907, and DRC items 909 by hardware processor 902 represents (at least in part) an EDA tool that implements, for example, part or all of the methodologies described herein according to one or more of the processes and / or methods mentioned herein.

[0173] The processor 902 is electrically coupled to the computer-readable storage medium 904 via a bus 908. The processor 902 is also electrically coupled to an I / O interface 910 via the bus 908. A network interface 912 is also electrically connected to the processor 902 via the bus 908. The network interface 912 is connected to a network 914, so that the processor 902 and the computer-readable storage medium 904 can be connected to external components via the network 914. The processor 902 is configured to execute instructions 906 encoded in the computer-readable storage medium 904 so that the EDA system 900 can be used to perform some or all of the processes and / or methods mentioned. In one or more embodiments, the processor 902 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0174] In one or more embodiments, the computer-readable storage medium 904 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 904 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 904 includes a compact disk-read only memory (CD-ROM), a compact disk-read / write (CD-R / W), and / or a digital video disk (DVD).

[0175] In one or more embodiments, the computer-readable storage medium 904 stores instructions 906, design layouts 907, and DRC items 909 that are configured to enable the EDA system 900 (where such execution (at least in part) represents an EDA tool) to be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 904 also stores information that facilitates the execution of part or all of the processes and / or methods mentioned.

[0176] The EDA system 900 includes an I / O interface 910. The I / O interface 910 is coupled to external circuits. In one or more embodiments, the I / O interface 910 includes a keyboard, a keypad, a mouse, a trackball, a touchpad, a touch screen, and / or cursor arrow keys for communicating information and commands to the processor 902.

[0177] The EDA system 900 also includes a network interface 912 coupled to the processor 902. The network interface 912 allows the EDA system 900 to communicate with a network 914 connected to one or more other computer systems. The network interface 912 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented with two or more EDA systems 900.

[0178] The EDA system 900 is configured to receive information via the I / O interface 910. The information received via the I / O interface 910 includes one or more of instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by the processor 902. The information is transmitted to the processor 902 via the bus 908. The EDA system 900 is configured to receive information related to a user interface (UI) 942 via the I / O interface 910. The information is stored in the computer-readable medium 904 as the UI 942.

[0179] In some embodiments, a CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0180] In some embodiments, the process is implemented as a function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / embedded storage or memory units, such as one or more of an optical disk (such as a DVD), a magnetic disk (such as a hard disk), a semiconductor memory (such as a ROM, RAM, a memory card), and the like.

[0181] Fig.10 FIG. 1 is a block diagram of a semiconductor device manufacturing system 1000 and a device manufacturing process associated therewith according to some embodiments. In some embodiments, based on a design layout (e.g., layout 100, layout 200, layout 300, layout 400, layout 500, layout 600, layout 800), the semiconductor device manufacturing system 1000 is used to manufacture at least one of one or more semiconductor masks or at least one device in a layer of a semiconductor integrated circuit.

[0182] exist Fig.10In the present invention, the semiconductor device manufacturing system 1000 includes entities (such as a design room 1020, a mask room 1030, and a semiconductor device manufacturer / fabricator ("wafer fab") 1050) that interact with each other in the design, development, and manufacturing cycles and / or services related to manufacturing semiconductor devices 1060. The entities in the semiconductor device manufacturing system 1000 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design room 1020, the mask room 1030, and the wafer fab 1050 are owned by a single larger company. In some embodiments, two or more of the design room 1020, the mask room 1030, and the wafer fab 1050 coexist in a shared facility and use shared resources.

[0183] The design office (or design team) 1020 generates a design layout 1022. The design layout 1022 includes various geometric patterns designed for the semiconductor element 1060. The geometric patterns correspond to the patterns of the metal, oxide or semiconductor layers of the various elements constituting the semiconductor element 1060 to be manufactured. Various layers are combined to form various element features. For example, a portion of the design layout 1022 includes various circuit features (such as active regions, gate structures, source contact structures, drain contact structures, and interconnected metal wiring or vias) to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 1020 implements an appropriate design program to form the design layout 1022. The design program includes one or more of a logical design, a physical design or a layout and wiring. The design layout 1022 is presented in one or more data files having information of the geometric patterns. For example, the design layout 1022 can be expressed in a GDSII file format or a DFII file format.

[0184] The mask chamber 1030 includes mask data preparation 1032 and mask manufacturing 1044. The mask chamber 1030 uses the design layout 1022 to manufacture one or more masks 1045, which are used to manufacture various layers of the semiconductor device 1060 according to the design layout 1022. The mask chamber 1030 performs mask data preparation 1032, wherein the design layout 1022 is translated into a representative data file ("RDF"). The mask data preparation 1032 provides the RDF to the mask manufacturing 1044. The mask manufacturing 1044 includes a mask direct writer. The mask direct writer converts the RDF into an image on a substrate, such as a mask (master mask) 1045 or a semiconductor wafer 1053. The mask data preparation 1032 manipulates the design layout 1022 to conform to the specific characteristics of the mask direct writer and / or the requirements of the wafer fab 1050. In Fig.10 , mask data preparation 1032 and mask manufacturing 1044 are depicted as separate components. In some embodiments, mask data preparation 1032 and mask manufacturing 1044 may be collectively referred to as mask data preparation.

[0185] In some embodiments, mask data preparation 1032 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, and the like. OPC adjusts the design layout 1022. In some embodiments, mask data preparation 1032 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography techniques (ILT) are also used, which treat OPC as an inverse imaging problem.

[0186] In some embodiments, mask data preparation 1032 includes a mask rule checker (MRC) that checks a design layout 1022 that has undergone a process in an OPC having a set of mask generation rules that contain certain geometric and / or connection constraints to ensure adequate tolerances, taking into account variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the design layout 1022 to compensate for the constraints during mask generation 1044, which may undo some of the modifications performed by the OPC to comply with the mask generation rules.

[0187] In some embodiments, mask data preparation 1032 includes a lithography process check (LPC) that simulates a process to be performed by fab 1050 to manufacture semiconductor device 1060. LPC simulates this process based on design layout 1022 to generate a simulated manufactured device, such as semiconductor device 1060. Process parameters in the LPC simulation may include parameters associated with various processes of an IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and the like or combinations thereof. In some embodiments, after LPC has generated a simulated manufactured device, if the shape of the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further improve design layout 1022.

[0188] It should be understood by those skilled in the art that the above-described mask data preparation 1032 has been simplified for the purpose of clarity. In some embodiments, the mask data preparation 1032 includes additional features such as logic operations (LOPs) to modify the design layout 1022 according to manufacturing rules. In addition, the processes applied to the design layout 1022 during the mask data preparation 1032 may be performed in a variety of different orders.

[0189] After mask data preparation 1032 and during mask fabrication 1044, a mask 1045 or a group of masks 1045 are fabricated based on design layout 1022. In some embodiments, mask fabrication 1044 includes performing one or more lithographic exposures based on design layout 1022. In some embodiments, an electron beam (e-beam) or a mechanism of multiple electron beams is used to form a pattern on a mask (e.g., a mask or a master mask) based on design layout 1022. Mask 1045 can be formed by various techniques. In some embodiments, mask 1045 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (such as an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque areas and passes through the transparent areas. In one example, a binary mask version of mask 1045 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In another example, a phase transfer technique is used to form the mask 1045. In a phase transfer mask (PSM) version of the mask 1045, various features in the pattern formed on the phase transfer mask are configured to have appropriate phase differences in order to enhance resolution and imaging quality. In various examples, the phase transfer mask can be an attenuated PSM or an alternating PSM. The mask(s) produced by the mask manufacturing 1044 are used in a variety of processes. For example, the mask(s) are used in an ion implantation process to form various doped regions in the semiconductor wafer 1053, in an etching process to form various etched regions in the semiconductor wafer 1053, and / or in other suitable processes.

[0190] Wafer fab 1050 includes wafer fabrication 1052. Wafer fab 1050 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, wafer fab 1050 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of multiple IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility may provide back-end manufacturing (BEOL manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility may provide other services for the foundry company.

[0191] The wafer fab 1050 uses the mask(s) 1045 manufactured by the mask chamber 1030 to manufacture the semiconductor device 1060. Therefore, the wafer fab 1050 at least indirectly uses the design layout 1022 to manufacture the semiconductor device 1060. In some embodiments, the semiconductor wafer 1053 is manufactured by the wafer fab 1050 using the mask(s) 1045 to form the semiconductor device 1060. In some embodiments, the device manufacturing includes performing one or more lithography exposures based at least indirectly on the design layout 1022. The semiconductor wafer 1053 includes a silicon substrate or other suitable substrate having a material layer formed thereon. The semiconductor wafer 1053 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent manufacturing steps).

[0192] With respect to integrated circuit (IC) manufacturing systems (e.g., Fig.10 Details of the semiconductor device manufacturing system 1000 and the IC manufacturing process associated therewith can be found in (for example) U.S. Patent No. 9,256,709 issued on February 9, 2016, U.S. Patent Publication No. 20150278429 published on October 1, 2015, U.S. Patent Publication No. 20140040838 published on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, each of which is hereby incorporated by reference in its entirety.

[0193] One aspect of the present description relates to a layout of a semiconductor device. The layout is stored in a non-transitory computer-readable medium and includes a first transistor in an active device region and a second transistor in a guard ring region. The first transistor includes a first channel region in a first semiconductor fin, a first gate structure spanning the first channel region, and a first source region and a first drain region in the first semiconductor fin on opposite sides of the first channel region. The second transistor includes a second channel region in a second semiconductor fin, a second gate structure spanning the second channel region, and a second source region and a second drain region in the second semiconductor fin on opposite sides of the second channel region. The second channel region includes a semiconductor material having a higher thermal conductivity than the semiconductor material of the first channel region. In some embodiments, the guard ring region is separated from the active device region by a spacing based on a minimum spacing design rule. In some embodiments, the layout further includes a channel barrier layer, the channel barrier layer being above the guard ring region and aligned with the second channel region. The channel barrier layer can be used to indicate that the semiconductor material of the second channel region has a higher thermal conductivity than the semiconductor material of the first channel region. In some embodiments, the layout further includes a source contact structure, the source contact structure coupling the first source region and the second source region. In some embodiments, the source contact structure is in direct contact with the first source region and the second source region. In some embodiments, the second gate structure has a greater width than the first gate structure. In some embodiments, the second source region has a greater width than the first source region, and the second drain region has a greater width than the first drain region. In some embodiments, the layout further includes an NT_N layer above the guard ring region to indicate that the second channel region has a doping concentration less than the doping concentration of the first channel region. In some embodiments, the layout further includes an interconnect metal layer electrically coupled to the source contact structure.

[0194] Another aspect of this description relates to a system for processing the layout of semiconductor devices. The system includes at least one processor and a computer-readable storage medium connected to the at least one processor. The at least one processor is configured to execute instructions stored on the computer-readable storage medium to generate a first semiconductor fin in the active device area and a second semiconductor fin in the guard ring area, and to generate a first transistor in the active device area. The first transistor includes a first channel region in the first semiconductor fin, a first gate structure spanning the first channel region, and a first source region and a first drain region in the first semiconductor fin on opposite sides of the first channel region. The second semiconductor fin includes a semiconductor material having a higher thermal conductivity than the semiconductor material used in at least the first source region and the first drain region. In some embodiments, the at least one processor is further configured to execute instructions on the computer-readable medium to generate a source contact structure, the source contact structure coupling the first source region and the second semiconductor fin. In some embodiments, the at least one processor is further configured to execute instructions on the computer-readable medium to generate an interconnect metal layer, the interconnect metal layer electrically coupled to the source contact structure. In some embodiments, at least one processor is further configured to execute instructions on a computer-readable medium to generate a strain relaxation buffer (SRB) layer below the first channel region. In some embodiments, at least one processor is further configured to execute instructions on a computer-readable medium to generate an epitaxial barrier layer above the guard ring region. The epitaxial barrier layer can be used to indicate that the semiconductor material of the second semiconductor fin has a higher thermal conductivity than the semiconductor material used in at least the first source region and the first drain region. In some embodiments, at least one processor is further configured to execute instructions on a computer-readable medium to generate the epitaxial barrier layer as a continuous layer covering the entirety of the guard ring region.

[0195] Another aspect of this description relates to a semiconductor element. The semiconductor element includes a substrate, a transistor in an active element region of the substrate, and a resistor in a passive element region of the substrate. The transistor includes a channel region in a semiconductor fin, a gate structure spanning the channel region, and a source region and a drain region in the semiconductor fin on opposite sides of the channel region. The semiconductor element further includes a source contact structure overlying the source region of the transistor, and an interconnect metal layer electrically coupling the source contact structure and the first terminal of the resistor. The second terminal of the resistor is floating. In some embodiments, the resistor includes a well region in the substrate, and a first heavily doped region and a second heavily doped region in a surface portion of the well region. The first heavily doped region is a first terminal, and the second heavily doped region is a second terminal. In some embodiments, the semiconductor structure further includes a source via hole overlying the source contact structure and a resistor via hole overlying the first heavily doped region of the resistor. The interconnect metal layer electrically couples the source contact structure and the first heavily doped region of the resistor via the source via hole and the resistor via hole. In some embodiments, the passive device region is adjacent to the active device region and is separated from the active device region by a spacing based on a minimum spacing design rule. In some embodiments, the substrate includes a first type dopant having a first conductivity type and a well region, and the first heavily doped region and the second heavily doped region of the resistor include a second type dopant having a second conductivity type opposite to the first conductivity type.

[0196] It will be readily apparent to one of ordinary skill in the art that the disclosed embodiments achieve one or more of the advantages described above. After reading the foregoing description, one of ordinary skill in the art will be able to effect various changes, substitutions of equivalents, and various other embodiments as broadly disclosed herein. Although the features of the various embodiments are expressed in particular combinations in the claims, it is contemplated that such features may be arranged in any combination and order. It is therefore contemplated that the protection granted herein is limited to the definitions contained in the appended claims and their equivalents.

Claims

1. A layout of a semiconductor element, characterized in that: The layout is stored in a non-transitory computer readable medium and includes: a first transistor located in an active device region, the first transistor comprising a first channel region in a first semiconductor fin, a first gate structure spanning the first channel region, and a first source region and a first drain region in the first semiconductor fin on opposite sides of the first channel region; and a second transistor located in a guard ring region, the second transistor comprising a second channel region in a second semiconductor fin, a second gate structure spanning the second channel region, and a second source region and a second drain region in the second semiconductor fin on opposite sides of the second channel region, The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

2. The arrangement according to claim 1, characterized in that The guard ring region is separated from the active device region by a spacing based on a minimum spacing design rule.

3. The arrangement according to claim 1, characterized in that The layout further includes a channel barrier layer, the channel barrier layer being over the guard ring region and aligned with the second channel region, the channel barrier layer being used to indicate that the semiconductor material of the second channel region has a higher thermal conductivity than the semiconductor material of the first channel region.

4. The arrangement according to claim 1, characterized in that The layout further includes a source contact structure coupling the first source region and the second source region.

5. The arrangement according to claim 4, characterized in that The source contact structure is in direct contact with the first source region and the second source region.

6. The arrangement according to claim 1, characterized in that The second gate structure has a greater width than the first gate structure.

7. The arrangement according to claim 1, characterized in that The second source region has a greater width than the first source region, and the second drain region has a greater width than the first drain region.

8. The arrangement according to claim 1, characterized in that The layout further includes a native layer above the guard ring region for indicating that the second channel region has a doping concentration less than a doping concentration of the first channel region.

9. The arrangement according to claim 4, characterized in that The layout further includes an interconnect metal layer electrically coupled to the source contact structure.

10. A system for processing a layout of a semiconductor component, characterized in that The system includes: at least one processor; as well as A computer-readable storage medium connected to the processor, the processor being configured to execute instructions stored on the computer-readable storage medium to generate a first semiconductor fin in an active device region and a second semiconductor fin in a guard ring region, and generate a first transistor in the active device region, the first transistor comprising a first channel region in the first semiconductor fin, a first gate structure spanning the first channel region, and a first source region and a first drain region in the first semiconductor fin on opposite sides of the first channel region, the second semiconductor fin comprising a semiconductor material having a higher thermal conductivity than a semiconductor material used in the first source region and the first drain region.

11. The system according to claim 10, characterized in that The processor is further configured to execute instructions on the computer-readable storage medium to generate a source contact structure coupling the first source region and the second semiconductor fin.

12. The system according to claim 11, characterized in that The processor is further configured to execute instructions on the computer-readable storage medium to generate an interconnect metal layer electrically coupled to the source contact structure.

13. The system according to claim 10, characterized in that The processor is further configured to execute instructions on the computer-readable storage medium to create a strain relaxation buffer layer beneath the first channel region.

14. The system according to claim 10, characterized in that The processor is further configured to execute instructions on the computer-readable storage medium to generate an epitaxial barrier layer over the guard ring region, the epitaxial barrier layer being operable to indicate that the semiconductor material of the second semiconductor fin has a higher thermal conductivity than the semiconductor material used in the first source region and the first drain region.

15. The system according to claim 14, characterized in that The processor is further configured to execute instructions on the computer-readable storage medium to generate the epitaxial barrier layer as a continuous layer covering the entirety of the guard ring area.

16. A semiconductor device, characterized in that: include: a substrate; a first transistor located in an active device region of the substrate, the first transistor comprising a first channel region in a first semiconductor fin, a gate structure spanning the first channel region, and a first source region and a first drain region in the first semiconductor fin on opposite sides of the first channel region; a second transistor located in a guard ring region of the substrate, the second transistor comprising a second channel region in a second semiconductor fin, a second gate structure spanning the second channel region, and a second source region and a second drain region in the second semiconductor fin on opposite sides of the second channel region, wherein the second channel region comprises a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region; a resistor located in a passive component region of the substrate; a source contact structure overlying the first source region of the first transistor; as well as An interconnect metal layer electrically couples the source contact structure and a first terminal of the resistor, and a second terminal of the resistor is floating.

17. The semiconductor device according to claim 16, characterized in that The resistor includes a well region in the substrate, and a first heavily doped region and a second heavily doped region in a surface portion of the well region, the first heavily doped region being the first terminal, and the second heavily doped region being the second terminal.

18. The semiconductor device according to claim 17, characterized in that The semiconductor structure further comprises: a source via hole covering the source contact structure; and A resistor via hole covers the first heavily doped region of the resistor. The interconnect metal layer electrically couples the source contact structure and the first heavily doped region of the resistor through the source via hole and the resistor via hole.

19. The semiconductor device according to claim 17, characterized in that The passive component region is adjacent to the active component region and is separated from the active component region by a distance based on a minimum spacing design rule.

20. The semiconductor device according to claim 17, wherein: The substrate includes a first type dopant having a first conductivity type and the well region. The first heavily doped region and the second heavily doped region of the resistor include a second type dopant having a second conductivity type opposite to the first conductivity type.

21. A layout of a semiconductor element, characterized in that: The layout is stored in a non-transitory computer readable medium and includes: a first transistor located in an active device region, the first transistor comprising a first channel region, a first source region and a first drain region; and a second transistor located in a guard ring region, the second transistor comprising a second channel region, a second source region and a second drain region, The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.

22. The arrangement according to claim 21, characterized in that The first channel region is aligned with the second channel region.

23. The arrangement according to claim 21, characterized in that The layout further includes: a first gate structure spanning the first channel region; and A second gate structure spans across the second channel region, wherein the first gate structure is electrically isolated from the second gate structure.

24. The arrangement according to claim 21, characterized in that The layout further includes a source contact structure, which crosses the first source region and the second source region.

25. The arrangement according to claim 21, characterized in that The layout further includes an isolation structure, a first portion of the isolation structure is located between the first channel region and the second channel region.

26. The arrangement according to claim 25, characterized in that The first channel region is located between a second portion of the isolation structure and the second channel region.

27. The arrangement according to claim 21, characterized in that The second channel region includes silicon.

28. The arrangement according to claim 27, characterized in that The doping concentration of silicon is less than about 1x10 13 atoms / cm 3 .

29. A system for processing a layout of a semiconductor device, characterized in that The system includes: at least one processor; as well as A non-transitory computer-readable storage medium connected to the processor, wherein the non-transitory computer-readable storage medium is used to store instructions, and the processor is configured to execute the instructions to generate a first transistor in an active device area and a second transistor in a guard ring area, the first transistor includes a first channel area, the second transistor includes a second channel area, and a thermal conductivity of the second channel area is higher than a thermal conductivity of the first channel area.

30. The system according to claim 29, characterized in that The processor is configured to transmit data for fabricating at least one mask based on the fabricated first transistor and the second transistor.

31. The system according to claim 29, characterized in that The processor is configured to transmit data for fabricating at least one semiconductor device based on the fabricated first transistor and the second transistor.

32. The system according to claim 29, characterized in that The processor manufactures the first transistor and the second transistor according to the design rules stored in the non-transitory computer readable storage medium.

33. The system according to claim 29, characterized in that The processor is used to receive information based on a computer-aided design library.

34. The system according to claim 33, characterized in that The processor uses the received information to generate a native layer aligned with the second transistor.

35. A semiconductor component comprising: a substrate; A first transistor located in an active device region of the substrate, the first transistor comprising a first channel region and a first source / drain region; A second transistor located in a guard ring region of the substrate, the second transistor comprising a second channel region and a second source / drain region, wherein the second channel region has a higher thermal conductivity than the first channel region; a resistor located in a passive component region of the substrate; a contact structure overlying the first source / drain region of the first transistor; as well as An interconnection layer electrically couples the contact structure and a first terminal of the resistor, and a second terminal of the resistor is floating.

36. The semiconductor device according to claim 35, characterized in that The resistor includes a doped well.

37. The semiconductor device according to claim 36, characterized in that The semiconductor device further includes an isolation structure located between the first channel region and the doping well.

38. The semiconductor device according to claim 37, characterized in that The depth of the doping well is greater than the depth of the isolation structure.

39. The semiconductor device according to claim 35, characterized in that The semiconductor device further includes a strain relaxation buffer layer below the first channel region.

40. The semiconductor device according to claim 39, characterized in that The strain relaxation buffer layer includes SiGe.

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