Chopper amplifier with decoupled chopping frequency and threshold frequency

Abstract

The present disclosure relates to a chopper amplifier having a decoupled chopping frequency and a threshold frequency. The chopper amplifier circuit (400, FIG. 4) includes a first amplifier path (202A) having a chopper circuit system (404, 406), a switched capacitor filter (408) and a plurality of gain stages (403, 214A). The chopper amplifier circuit (400) also includes a second amplifier path (220A) having a feedforward gain stage (422). The chopping frequency of the chopper circuit system (404, 406) is greater than the threshold frequency, in which case the second amplifier path (220A) is used instead of the first amplifier path (202A).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 737,948, filed on September 28, 2018, entitled “High-Bandwidth Low-Input Bias Current Chopper Amplifier Architecture,” which is incorporated herein by reference. Technical Field Background Art

[0003] Modern electronic systems involve different circuits and networks, where the voltage or current level of a signal transmitted along a link between components or circuits is often adjusted. A signal amplifier circuit is a circuit used to adjust the voltage or current level of a signal along a link, where the purpose of signal amplification is to increase the signal strength without introducing errors such as offset voltage, noise, distortion, etc. There are several different signal amplifier topologies, each suitable for different scenarios.

[0004] One signal amplifier topology is known as a chopper amplifier. In the example chopper amplifier topology, the chopping frequency is a function of the bandwidth (increasing the bandwidth requires increasing the chopping frequency). Unfortunately, increasing the chopping frequency of a chopper amplifier to increase the bandwidth results in an undesirable increase in the input bias current. The input bias current is proportional to the chopping frequency because the chopping frequency determines the number of charge transfers that occur per second at the input. This is because charge transfer from the clock feedthrough and charge injection from the input chopper switches contribute to the input bias current in the chopper amplifier. To the extent that the input bias current level interacts with the impedance of the input source, an error voltage is introduced in the signal path. Summary of the invention

[0005] According to at least one example of the present disclosure, a chopper amplifier circuit includes a first amplifier path having a chopper circuit system, a switched capacitor filter, and a plurality of gain stages. The chopper amplifier circuit also includes a second amplifier path having a feedforward gain stage. The chopping frequency of the chopper circuit system is greater than a threshold frequency, in which case the second amplifier path is used instead of the first amplifier path.

[0006] According to at least one example of the present disclosure, a system includes a chopper amplifier circuit having a first amplifier path, the first amplifier path having a chopper circuit system, a switched capacitor filter, a first gain stage before the switched capacitor filter, and a second gain stage after the switched filter. The chopper amplifier circuit also includes a second amplifier path having a feedforward gain stage, wherein the chopping frequency of the chopper circuit system is greater than a threshold frequency, in which case the second amplifier path is used instead of the first amplifier path. The chopper amplifier circuit is configured to receive a differential input signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a detailed description of various examples, reference will now be made to the accompanying drawings, in which:

[0008] Figure 1 is a schematic diagram showing a chopper amplifier topology;

[0009] Figure 2 is a schematic diagram illustrating another chopper amplifier topology according to various examples;

[0010] Figure 3 is a graph showing chopper amplifier gain as a function of frequency according to various examples.

[0011] Figure 4 is a schematic diagram illustrating another chopper amplifier according to various examples;

[0012] Figure 5 is a schematic diagram illustrating post-filter gain stages according to various examples;

[0013] Figure 6 is shown as Figure 5 a graph of the gain of a post filter gain stage as a function of frequency;

[0014] Figure 7 and Figure 8 is a schematic diagram illustrating post-filter gain stage options according to various examples; and

[0015] Fig. 9 is a graph of differential output current as a function of differential input voltage of a gain stage according to various examples. DETAILED DESCRIPTION

[0016] Disclosed herein are chopper amplifier topologies, systems, and methods that decouple a chopping frequency from a threshold frequency for selecting between different amplifier paths in a chopper amplifier. Decoupling the chopping frequency from the threshold frequency enables the chopper amplifier to meet predetermined design goals for input bias current (e.g., input bias current below a target) and bandwidth (e.g., bandwidth above a target). In different examples, the bandwidth and input bias current goals vary. Without limitation, the disclosed chopper amplifier topologies are useful in systems such as instrumentation or sensing systems where small signals need to be amplified without distortion (or distortion less than a threshold).

[0017] In some examples, the disclosed chopper amplifier adopts a first amplifier path and a second amplifier path. The first amplifier path includes a gain stage, a chopper circuit system, a switch capacitor filter, and at least one gain stage (referred to as a post-filter gain stage) after the switch capacitor filter. Meanwhile, the second amplifier path includes a feed-forward gain stage. According to at least some examples, the first amplifier path includes a post-filter gain stage, which sets a threshold frequency so that the threshold frequency is decoupled from the chopper frequency of the chopper circuit system. In one example, the post-filter gain stage sets the threshold frequency based on the relationship GM2 / CM2, wherein GM2 is the transconductance of the post-filter gain stage, and CM2 is a capacitor associated with the post-filter gain stage. In another example, the post-filter gain stage has a first parallel gain path and a second parallel gain path, wherein the first parallel gain path includes a cascade gain stage, and wherein the second parallel gain path includes a feed-forward gain stage. In at least some examples, the gain of the first parallel gain path is higher than the gain of the second parallel gain path. In addition, the first parallel gain path is applied to frequencies below the threshold frequency, and the second parallel gain path is applied to frequencies above the threshold frequency. With any of these post-filter gain stage options, the threshold frequency is decoupled from the chopping frequency and the threshold frequency is less than the chopping frequency. For better understanding, various chopper amplifier options, post-filter gain stage options and related issues are described using the following figures.

[0018] Figure 1 is a schematic diagram illustrating an example chopper amplifier 100. Figure 1In the example of , the chopper amplifier 100 includes a first amplifier path 102 and a second amplifier path 120, each of which receives a differential input signal (V_IN) at its input. In some examples, V_IN is provided by an input side circuit (e.g., the input side circuit is part of the same integrated circuit as the chopper amplifier 100, or is part of another integrated circuit, chip, or device). The first amplifier path 102 includes a set of switches 104 and a first gain stage (gm1) 103, wherein the set of switches 104 samples V_IN based on a chopping frequency. The sampled and amplified V_IN is passed to a filter 108 (to remove chopping noise) via another set of switches 106. Figure 1 , the control signals for a set of switches 104 and a set of switches 106 are labeled “phase 1 ” and “phase 2 ,” where the phase 1 and phase 2 signals do not overlap.

[0019] As shown, the filter 108 includes two capacitors (labeled C5 and C6) between two sets of switches 110 and 112. Another capacitor (labeled C4) is coupled to the switch set 112 and provides the output of the filter 108. The switch set 110 and the switch set 112 are guided by control signals (labeled "phase3" and "phase4"). In some examples, phase3 is shifted 90 degrees from phase1, and phase4 is shifted 90 degrees from phase2. The output of the filter 108 is provided to the second gain stage (gm2) 114 of the chopper amplifier 100. The output of the second gain stage 114 is provided to the third gain stage (gm3) 116 of the chopper amplifier 100. In some examples, the first amplifier path 102 uses the first gain stage 103, the second gain stage 114, and the third gain stage 116 to amplify the frequencies of V_IN below the threshold.

[0020] At the same time, the second amplifier path 120 of the chopper amplifier 100 amplifies the frequencies of V_IN above the threshold. As shown, the second amplifier path 120 includes a feed-forward gain stage (gm4) 122, wherein the output of the feed-forward gain stage 122 is provided to the third gain stage 116. Therefore, the second amplifier path 120 amplifies the frequencies of V_IN above the threshold using the feed-forward gain stage 122 and the third gain stage 116. Figure 1 In the example chopper amplifier 100, the chopper amplifier 100 also includes various capacitors (e.g., C1, C2a, C2b, C3a, C3b) for frequency compensation. In the example chopper amplifier 100, increasing the bandwidth of the chopper amplifier 100 requires a proportional increase in the chopping frequency at the expense of increased input bias current (resulting in increased amplifier error).

[0021] Figure 22 is a schematic diagram showing another chopper amplifier 200 according to various examples. As shown in the figure, the chopper amplifier 200 includes a first amplifier path 202 and a second amplifier path 220, each receiving a differential input signal (VIN_P and VIN_N, which corresponds to Figure 1 In some examples, VIN_P and VIN_N are provided by input side circuits (e.g., the input side circuits are part of the same integrated circuit as the chopper amplifier 200, or are part of another integrated circuit, chip, or device). The first amplifier path 202 includes a set of switches 204 and a first gain stage (GM1) 203, wherein the set of switches 204 samples VIN_P and VIN_N based on the chopping frequency. The sampled and amplified VIN_P and VIN_N are passed to a filter 208 (to remove chopping noise) via another set of switches 206. Figure 2 , the control signals for switch group 204 and switch group 206 are labeled “ Φ1 ” and “ Φ1z ”, where the Φ1 and Φ1z signals do not overlap.

[0022] exist Figure 2 In the example, filter 208 includes two capacitors (labeled as C SC1 and C SC2 ) and two sets of switches 210 and 212. More specifically, C SC1 The first electrode of is coupled to S1 in switch group 210 and is coupled to S4 in switch group 212. SC1 The second electrode of is coupled to the ground node. SC2 The first electrode of is coupled to S3 in switch group 210 and is coupled to S2 in switch group 212. SC2 The second electrode of is coupled to the ground node. Switch group 210 and switch group 212 are guided by control signals (labeled "Φ1+90°" and "Φ1z+90°"). More specifically, S1 and S2 are guided by the Φ1+90° signal, and S3 and S4 are guided by the Φ1z+90° signal. The output of filter 208 is provided to a second gain stage or first post-filter gain stage (GM2) 214 with threshold frequency selection.

[0023] In some examples, the post-filter gain stage 214 selects the threshold frequency based on the relationship GM2 / CM2, where GM2 is the transconductance of the post-filter gain stage and CM2 is the first frequency compensation capacitor. In other examples, the post-filter gain stage 214 uses a parallel gain path to select the threshold frequency (e.g., see Figure 4 More specifically, in some examples, the first parallel gain path includes cascaded gain stages (see, e.g., Figure 4 GM2_1 and GM2_2 in FIG. 1 ), and the second parallel gain path includes a feed-forward gain stage (see, e.g. Figure 4 214). In at least some examples, the gain of the first parallel gain path is higher than the gain of the second parallel gain path. In addition, the first parallel gain path is applied to frequencies below a threshold, while the second parallel gain path is applied to frequencies above a threshold. The output of the post-filter gain stage 214 is provided to a third gain stage or second post-filter gain stage (GM3) 216 of the chopper amplifier 200. In some examples, the first amplifier path 202 amplifies the frequencies of VIN_N and VIN_P below the threshold frequency using the first gain stage 203, the second gain stage 214, and the third gain stage 216.

[0024] At the same time, the second amplifier path 220 of the chopper amplifier 200 amplifies the frequencies of VIN_N and VIN_P above the threshold frequency. As shown, the second amplifier path 220 includes a feed-forward gain stage (GMFF) 222, wherein the output of the feed-forward gain stage 222 is provided to the third gain stage or the second post-filter gain stage (GM3) 216. Therefore, in some examples, the second amplifier path 220 uses the feed-forward gain stage (GMFF) 222 and the third gain stage (GM3) 216 to amplify the frequencies of VIN_N and VIN_P above the threshold frequency. The chopper amplifier 200 also includes various capacitors (e.g., CM1, CM2) to provide frequency compensation for the chopper amplifier 200. It should be noted that when the different threshold frequency selection options for the post-filter gain stage 214 are effective, the parallel gain path using the post-filter gain stage 214 has the benefit of suppressing the offset voltage from the second amplifier path 220.

[0025] Figure 3 3 is a graph 300 showing a chopper amplifier gain 301 as a function of frequency according to various examples. In the graph 300, the chopper amplifier gain 301 is referred to as A OL (s) and varies with frequency. In the graph 300, various poles, zeros, and associated frequencies are identified, including the dominant pole frequency (f_p1), the non-dominant pole frequency (f_p3), the pole-zero doublet frequency (f_p2, z2), the threshold frequency 302, the chopping frequency (f_c) 304, and the unity gain frequency (UGF). As shown in the graph 300, the A at low frequencies below f_p1 is OL (s) is relatively constant until the dominant pole 308 associated with f_p1. After f_p1, A OL (s) decreases as a function of frequency. In some examples, A for frequencies below the threshold frequency 302 OL(s) is provided by the first amplifier path (e.g., the first amplifier path 202). In some examples, the threshold frequency 302 (referred to as the stitching frequency) is set by the pole-zero double peak associated with f_p2, z2. In most cases, p2=z2, where z2 is given by Given, where GM is the transconductance of the first gain stage (eg, gain stage 203), GM2_FF is the transconductance of the feedforward gain stage along the second parallel gain path of the post-filter gain stage 214 (see, e.g., Figure 5 ), GMFF is used for the second amplifier path (e.g., Figure 2 A feed-forward gain stage (eg, Figure 2 The transconductance of the feed-forward gain stage 222 in FIG. 1 and CM1 is for a chopper amplifier (eg, Figure 2 In other examples, the threshold frequency 302 is set by the relationship GM2 / CM2, where GM2 is the post-filter gain stage (e.g., Figure 2 The post-filter gain stage 214) of the transconductance, and CM2 is for the chopper amplifier (e.g., Figure 2 The second compensation frequency capacitor of the chopper amplifier 200). Above the threshold frequency 302, A OL (s) continues to decrease, where UGF corresponds to A OL (s) = 0. At f_p3, A OL The rate at which (s) decreases increases. A for frequencies above the threshold frequency 302 OL (s) is provided by the second amplifier path (eg, second amplifier path 220). Additionally, it should be noted that f_c 304 is above the threshold frequency 302.

[0026] In some examples, f_c 304 is set to a sufficiently low value so that the input bias current is below the input bias current target. To ensure that the phase delay of the switched capacitor filter does not affect the overall stability of the system, the threshold frequency 302 is set below f_c 304, as shown in graph 300. In some examples, f_c 304 is at least twice the threshold frequency 302.

[0027] Figure 4 is a schematic diagram showing another chopper amplifier 400 according to various examples. As shown in the figure, the chopper amplifier 400 includes a first amplifier path 202A ( Figure 2 2) and the second amplifier path 220A ( Figure 24 and 5. In some examples, VIN_P and VIN_N are provided by input-side circuitry (e.g., the input-side circuitry is part of the same integrated circuit as the chopper amplifier 400 or is part of another integrated circuit, chip, or device). The first amplifier path 202A includes a set of switches 404 and a first gain stage 403, wherein the set of switches 404 samples VIN_P and VIN_N based on a chopping frequency. The sampled and amplified VIN_P and VIN_N are passed to a filter 408 (to remove chopping noise) via another set of switches 406. Figure 4 , the control signals of switch groups 404 and 406 are labeled “ Φ1 ” and “ Φ1z ”, where the Φ1 and Φ1z signals do not overlap.

[0028] exist Figure 4 In the example, filter 408 includes two capacitors (labeled as C SC1 and C SC2 ) and two sets of switches 410 and 412. More specifically, C SC1 The first electrode of is coupled to S1 in switch group 410 and is coupled to S4 in switch group 412. SC1 The second electrode of is coupled to the ground node. SC2 The first electrode of is coupled to S3 in switch group 410 and is coupled to S2 in switch group 412. SC2 The second electrode of is coupled to the ground node. Switch group 410 and switch group 412 are guided by control signals (labeled "Φ1+90°" and "Φ1z+90°"). More specifically, S1 and S2 are guided by the Φ1+90° signal, and S3 and S4 are guided by the Φ1z+90° signal. The output of filter 408 is provided to the second gain stage or first post-filter gain stage 214A ( Figure 2 1 ). An example of a first post-filter gain stage 214 of FIG.

[0029] In some examples, post-filter gain stage 214A includes a first parallel gain path 440 and a second parallel gain path 450. More specifically, in some examples, first parallel gain path 440 includes cascaded gain stage 442 and cascaded gain stage 444, and second parallel gain path 444 includes feedforward gain stage 452. As shown, first parallel gain path 440 also includes a capacitor (C2_FF) between cascaded gain stage 442 and cascaded gain stage 444. In at least some examples, the gain of first parallel gain path 440 is higher than the gain of second parallel gain path 450. In addition, first parallel gain path 440 is applied to frequencies below a threshold frequency, while second parallel gain path 450 is applied to frequencies above a threshold frequency.

[0030] The output of the post-filter gain stage 214A is provided to a third gain stage or a second post-filter gain stage 416 of the chopper amplifier 400. In some examples, the first amplifier path 202A amplifies frequencies below a threshold frequency (eg, Figure 3 At the same time, the second amplifier path 220A of the chopper amplifier 400 amplifies the frequencies of VIN_N and VIN_P above the threshold frequency (e.g., Figure 3 302 in the threshold frequency 302). As shown, the second amplifier path 220A includes a feed-forward gain stage 422, wherein the output of the feed-forward gain stage 422 is provided to a third gain stage or a second post-filter gain stage 416. Thus, in some examples, the third gain stage 416 is shared by the first amplifier path 202A and the second amplifier path 220A. The chopper amplifier 400 also includes various capacitors (e.g., CM1, CM2) for frequency compensation of the chopper amplifier 400. It should be noted that the parallel gain path of the post-filter gain stage 214A is used to set the threshold frequency (e.g., using Setting the threshold frequency) has the benefit of suppressing the offset voltage from the second amplifier path 220A (compared to using GM2 / CM2 to set the threshold frequency).

[0031] Figure 5 is a schematic diagram illustrating a post-filter gain stage 214B according to various examples. Figure 5 , the post-filter gain stage 214B is Figure 2 The post-filter gain stage is 214 or Figure 4 As shown in the figure, the post-filter gain stage 214B includes: a first parallel gain path 440A ( Figure 4 ) and the second parallel gain path 450A ( Figure 4 4. The first parallel gain path 440A includes a cascaded gain stage 502 and a cascaded gain stage 504, wherein the gain stage 502 and the gain stage 504 are Figure 4 4. As shown, the first parallel gain path 440A includes a resistor (R2_1) and a capacitor (C2_1) between the gain stage 502 and the gain stage 504. The second parallel gain path 450A includes a feed-forward gain stage 506 ( Figure 4In at least some examples, the gain of the first parallel gain path 440A is higher than the gain of the second parallel gain path 450A. In addition, the first parallel gain path 440A is applied to frequencies below a threshold, while the second parallel gain path 450A is applied to frequencies above the threshold frequency. In addition, in some examples, the cascaded gain stage 502 and the cascaded gain stage 504 are configured to suppress the gain from the feedforward gain stage (e.g., Figure 4 The offset of the feed-forward gain stage 422).

[0032] In some examples, Figure 4 The post-filter gain stage 214A involves the selection of poles and zeros to achieve Figure 3 A OL (s) transfer function. More specifically, for the post-filter gain stage 214A, in is the variation of output current as a function of frequency, and where is the variation of input voltage as a function of frequency. In addition, where R2_1 is the resistance associated with the cascaded gain stage along the first parallel gain path of the post-filter gain stage (see e.g. Figure 5 ), and C2_1 is the capacitance associated with the cascaded gain stage along the first parallel gain path of the post-filter gain stage (see e.g. Figure 5 ).also, where GM2_1 is the transconductance of the first cascaded gain stage along the first parallel gain path of the post-filter gain stages (see e.g. Figure 5 ), GM2_2 is the transconductance of the second cascaded gain stage along the first parallel gain path of the post-filter gain stage (see e.g. Figure 5 ), GM2_FF is the transconductance of the feed-forward gain stage along the second parallel gain path of the post-filter gain stage (see e.g. Figure 5 ), and C2_1 is the capacitance associated with the cascaded gain stage along the first parallel gain path (see e.g. Figure 5 In some examples, GM2_1*R2_1*GM2_2 is set large enough to reduce the feed-forward gain level from the second amplifier path (eg, Figure 2 In addition, in some examples, p1, z1 are set to be lower than the threshold frequency (e.g., Figure 3 In addition, in some examples, GM2_FF is used to set the threshold frequency (e.g., Figure 3 In one example, GM2_FF is based on the relationship to set the threshold frequency.

[0033] Figure 6 is shown as Figure 5 A graph 600 of the gain GM2(s) of the post-filter gain stage 214B as a function of frequency is shown. As shown, GM2(s) is at a relatively constant level at frequencies below the dominant pole frequency f_p1, where GM2(s) is given by Figure 5 After f_p1, GM2(s) decreases until it reaches zero frequency f_z1. After f_z1, GM2(s) remains constant at GM2_FF, where GM2_FF is determined by Figure 5 Using a gain curve such as GM2(s), the post-filter gain stage (e.g., Figure 5 The first post-filter gain stage 214B) enables the chopper amplifier (eg, Figure 2 Chopper amplifier 200, Figure 2 The chopper amplifier 200 or Figure 4 The bandwidth of the chopper amplifier 400) is higher than the target bandwidth and the input bias current is lower than the target input bias current.

[0034] Figure 7 and Figure 8 is a schematic diagram of post-filter gain stage 214C and post-filter gain stage 214D according to various examples. Figure 7 , the post-filter gain stage 214C is Figure 2 The post-filter gain stage 214, Figure 4 The post-filter gain stage 214A or Figure 5 For the post-filter gain stage 214C, transistors (MN1-MN6, MP1, MP2), current sources (IT2-IT4), and common mode feedback (CMFB) circuit 702 are used to implement various gain stages, such as those previously discussed (e.g., Figure 4 Cascaded gain stage 442 and cascaded gain stage 444 and feedforward gain stage 452 in; or Figure 5 Cascaded gain stage 502 and cascaded gain stage 504 and feed-forward gain stage 506 in FIG. 7 ). In some examples, CMFB circuit 702 includes transistors (MP3, MP4) and a current source (IT1).

[0035] More specifically, the first cascaded gain stage (eg, Figure 4 The gain stage is 442, or Figure 5 The gain stage 502 in FIG. 5 is formed by MN1, MN2, IT3 and CMFB circuit 702. Furthermore, the second cascaded gain stage (e.g., Figure 4 The gain stage is 444, or Figure 5The gain stage 504 in FIG. 5 is formed by MN3, MN4 and IT2. Furthermore, the feed-forward gain stage (eg, Figure 4 The feed forward gain stage 452 in, or Figure 5 The feed-forward gain stage 506 in FIG. 5 is formed by MN5, MN6, and IT4. In some examples, IT4 is greater than IT2 to set the feed-forward gain stage (e.g., Figure 4 The feed forward gain stage 452 in, or Figure 5 The feed-forward gain stage 506 in the embodiment is higher than the second cascade gain stage (eg, Figure 4 The gain stage is 444, or Figure 5 The input differential range of the gain stage 504 in the feedforward circuit 702 is such that the post-filter gain stage 214C helps with overload recovery. For the post-filter gain stage 214C, the CMFB circuit 702 supports a fully differential output. In addition, in some examples, the feedforward gain stage (e.g., Figure 4 The feed forward gain stage 452 in, or Figure 5 The feed-forward gain stage 506 in is designed to have a nonlinear response to extend the input differential range.

[0036] exist Figure 8 , the post-filter gain stage 214D is Figure 2 The post-filter gain stage 214, Figure 4 The post-filter gain stage 214A, Figure 5 The post-filter gain stage 214B or Figure 7 8, and the like. For the post-filter gain stage 214D, various gain stages, such as those previously discussed (e.g., cascaded gain stage 442 and cascaded gain stage 444, and feedforward gain stage 452) are implemented using transistors (MN1-MN8, MP1-MP8), current sources (IT2-IT5), and CMFB circuit 802. In some examples, CMFB circuit 702 includes transistors (MP3, MP4) and current source (IT1).

[0037] More specifically, the first cascaded gain stage (eg, Figure 4 The gain stage is 442, or Figure 5 The gain stage 502 in FIG. 5 is formed by MN1, MN2, IT3 and CMFB circuit 702. Furthermore, the second cascaded gain stage (e.g., Figure 4 The gain stage is 444, or Figure 5 The gain stage 504 in FIG. 5 is formed by MN3, MN4 and IT2. Furthermore, the feed-forward gain stage (eg, Figure 4 The feed forward gain stage 452 in, or Figure 5In some examples, the resistor (R1) is positioned between the first current terminals of MP5 and MP6, such as Figure 8 As shown. Using the post-filter gain stage 114E, Figure 8 The feedforward stage is nonlinear to aid large signal response.

[0038] Fig. 9 is a graph 900 showing differential output current as a function of differential input voltage of a gain stage according to various examples. In some examples, graph 900 represents a nonlinear response of the gain stage, e.g. Figure 8 The feedforward gain stage represented in . With the nonlinear response, the feedforward gain stage (e.g. Figure 4 The feedforward gain stage 452 in Figure 5 The feed forward gain stage 506 or Figure 8 The related components in the Figure 8 The nonlinear GM2_FF stage of the post-filter gain stage 214D is related to Figure 7 Compared to the post-filter gain stage 214C of FIG. 2, a much larger input differential range is supported. The larger input differential range is useful during large signal events when the inputs of the GM2 stage are moved apart (e.g., startup, brownout, amplifier swing, output overload, etc.). Specifically, using a nonlinear GM2_FF stage (such as Figure 8 ) supports the target input differential range, which maintains regulation and thus shortens the recovery time after large signal events.

[0039] In some examples, the first post-filter gain stage (e.g., Figure 4 The first post-filter gain stage 214A in Figure 5 The first post-filter gain stage 214B in Figure 7 The first post-filter gain stage 214C or Figure 8 The cascaded gain stage of the first post-filter gain stage 214D in the embodiment suppresses the gain from the second amplifier path (eg, Figure 2 The second amplifier path 220, or Figure 4 The feed-forward gain stage of the second amplifier path 220A in FIG. Figure 2 GMFF 222, or Figure 4 In some examples, the first post-filter gain stage (e.g., Figure 4 The first post-filter gain stage 214A in Figure 5 The first post-filter gain stage 214B in Figure 7 The first post-filter gain stage 214C or Figure 8Each of the cascaded gain stages of the first post-filter gain stage 214D in the parallel gain path includes a differential transistor pair. In addition, the feed-forward gain stage of the second parallel gain path (e.g., Figure 4 GM2_FF 452 in, or Figure 5 GM2_FF 506) in includes a differential transistor pair.

[0040] Additionally, in some examples, the gain stage (e.g., Figure 2 The first post-filter gain stage 214 in Figure 4 The first post-filter gain stage 214A in Figure 5 The first post-filter gain stage 214B in Figure 7 The first post-filter gain stage 214C or Figure 8 The first post-filter gain stage 214D in FIG. 2 includes a first differential transistor pair ( GM2_1 ) associated with a cascaded gain stage (eg, GM2_1 ). Figure 7 and Figure 8 MP1 and MP2, or MN1 and MN2) of the current source (for example, Figure 7 and Figure 8 The gain stage also includes a second differential transistor pair (eg, GM2_2) associated with the cascaded gain stage (eg, GM2_3). Figure 7 and Figure 8 MN3 and MN4) of the second current source (eg, Figure 7 and Figure 8 The gain stage also includes a third differential transistor pair (eg, GM2_FF) for use in association with a feed-forward gain stage of a second parallel gain path (eg, GM2_FF). Figure 7 and Figure 8 MN3 and MN4) of the third current source (eg, Figure 7 and Figure 8 , wherein the third current source (eg, IT4) is set to a higher value than the second current source (eg, IT2).

[0041] Certain terms are used throughout the specification and claims to refer to specific system components. This document does not intend to distinguish between components that differ only in name but in their respective functions or structures. In this disclosure and claims, the terms "including" and "comprising" are used in an open-ended manner and should therefore be interpreted to mean "including but not limited to...". In addition, the terms "coupled" or "coupled" are intended to mean an indirect or direct wired or wireless connection. Thus, if a first device is coupled to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The statement "based on" is intended to mean "based at least in part on". Thus, if X is based on Y, then X may be a function of Y and any number of other factors.

[0042] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many changes and modifications will become apparent to those skilled in the art. It is intended that the appended claims be interpreted as including all such changes and modifications.

Claims

1. A chopper amplifier circuit, comprising: a first amplifier path having chopping circuitry, a switched capacitor filter, and a plurality of gain stages; as well as a second amplifier path having a feed-forward gain stage, wherein a chopping frequency of the chopping circuitry is greater than a threshold frequency, in which case the second amplifier path is used instead of the first amplifier path; wherein the plurality of gain stages of the first amplifier path includes a first gain stage before the switched capacitor filter and a second gain stage after the switched capacitor filter, wherein the second gain stage sets the threshold frequency; The second gain stage includes a first parallel gain path having a cascade gain stage, and a second parallel gain path having a feedforward gain stage. 2 . The chopper amplifier circuit of claim 1 , wherein a gain of the first parallel gain path is higher than a gain of the second parallel gain path, and wherein the first parallel gain path is applied to a frequency below a threshold.

3. The chopper amplifier circuit of claim 1, wherein the cascaded gain stage suppresses an offset from the feedforward gain stage of the second amplifier path. 4 . The chopper amplifier circuit of claim 1 , wherein the feed-forward gain stage of the second parallel gain path sets the threshold frequency.

5. The chopper amplifier circuit of claim 1, wherein each of the cascaded gain stages comprises a differential transistor pair, and wherein the feedforward gain stage of the second parallel gain path comprises a differential transistor pair.

6. The chopper amplifier circuit according to claim 4, further comprising: a first current source for a first differential transistor pair associated with the cascaded gain stage; a second current source for a second differential transistor pair associated with the cascaded gain stage; as well as A third current source for a third differential transistor pair associated with the feed-forward gain stage of the second parallel gain path, wherein the third current source is set to a higher value than the second current source.

7. The chopper amplifier circuit of claim 1, wherein the feedforward gain stage of the second parallel gain path has a nonlinear response.

8. A system comprising: A chopper amplifier circuit having: a first amplifier path having chopping circuitry, a switched capacitor filter, a first gain stage before the switched capacitor filter, and a second gain stage after the switched capacitor filter; as well as a second amplifier path having a feed-forward gain stage, wherein a chopping frequency of the chopping circuitry is greater than a threshold frequency, in which case the second amplifier path is used instead of the first amplifier path; as well as an input side circuit configured to provide a differential input signal to the chopper amplifier circuit; The second gain stage includes a first parallel gain path and a second parallel gain path having different gains. 9 . The system of claim 8 , wherein the first parallel gain path of the second gain stage comprises a cascade gain stage, and wherein the second parallel gain path of the second gain stage comprises a feed-forward gain stage.

10. The system of claim 9, wherein a gain of the first parallel gain path is higher than a gain of the second parallel gain path, and wherein the first parallel gain path is applied to frequencies below the threshold frequency.

11. The system of claim 8, wherein the chopping frequency is at least twice the threshold frequency.

12. The system of claim 9, wherein each of the cascaded gain stages comprises a differential transistor pair, and wherein the feed-forward gain stage of the second parallel gain path comprises a differential transistor pair.

13. The system of claim 12, further comprising: a first current source for a first differential transistor pair associated with a first one of the cascaded gain stages; a second current source for a second differential transistor pair associated with a second one of the cascaded gain stages; as well as A third current source for a third differential transistor pair associated with the feed-forward gain stage of the second parallel gain path, wherein the third current source is set to a higher value than the second current source.

14. The system of claim 9, wherein the feedforward gain stage of the second parallel gain path has a nonlinear response.

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