Monolithic chip stacking using dies with double-sided interconnect layers

Abstract

A device is provided, comprising: a first tube core having a first surface and a second surface, the first tube core comprising: a first layer formed on the first surface of the first tube core, and a second layer formed on the second surface of the first tube core; a second tube core coupled to the first layer; and a plurality of structures for coupling the device to an external component, wherein the plurality of structures are coupled to the second layer.

Description

Background Art

[0001] Generally, when two or more semiconductor dies are to be stacked, die-to-die interconnection may be achieved using additional interconnect dies (such as interposers, bridge dies), using through-silicon via (TSV) structures, etc. However, adding such additional die-to-die interconnect elements may result in increased cost and complexity, and may also increase the die-to-die interconnect length. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure, which however should not be considered to limit the present disclosure to the specific embodiments but are only for explanation and understanding.

[0003] Figure 1 A semiconductor package is schematically illustrated according to some embodiments, the semiconductor package including a first die having interconnect layers formed on two opposing sides and a second die coupled to the first die.

[0004] Figures 2A-2K A process of forming a semiconductor package is shown in accordance with some embodiments, wherein the semiconductor package includes a first die having interconnect layers formed on two opposing sides and a second die coupled to the first die.

[0005] Figure 3A A semiconductor package is schematically illustrated according to some embodiments, the semiconductor package including a first die having interconnect layers formed on two opposite sides and a second die coupled to the first die without any intermediate redistribution layer (RDL) between the first die and the second die.

[0006] Figure 3B A semiconductor package including a plurality of stacked dies is schematically illustrated, wherein each of at least two dies has interconnect layers formed on two opposite sides, according to some embodiments.

[0007] Figure 4 A computer system, computing device, or SoC (system on chip) is shown according to some embodiments, wherein one or more components of the computing system are formed using a semiconductor package including two or more stacked dies, wherein at least one of the stacked dies has interconnect layers formed on two opposing surfaces. DETAILED DESCRIPTION

[0008] In some embodiments, a semiconductor package may include a plurality of stacked dies. The stacked dies may include a first die having interconnect layers formed on two opposing surfaces of the first die. For example, a first interconnect layer on a first surface of the first die may be coupled to a second die; and a second interconnect layer on a second surface of the first die may be coupled to a package interconnect structure (e.g., for coupling the device to an external component).

[0009] In some embodiments, a first die having interconnect layers formed on two opposing surfaces may not have any TSVs for connecting the interconnect layers. For example, two interconnect layers may be connected to active components of the first die. Accordingly, the thickness of the first die may be relatively small, and this may result in a relatively thin die-to-die interconnect. Other technical effects will be apparent from the various embodiments and accompanying drawings.

[0010] In the following description, many details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other examples, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring the embodiments of the present disclosure.

[0011] Note that in the corresponding figures of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths, and / or have arrows at one or more ends to indicate the main information flow direction. Such indications are not intended to be restrictive. Instead, these lines are used in conjunction with one or more exemplary embodiments to facilitate easier understanding of circuits or logic units. As indicated by design needs or preferences, any represented signal may actually include one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0012] Throughout the specification and in the claims, the term "connection" means a direct connection (such as electrical, mechanical or magnetic connection) between connected things without any intermediate device. The term "coupling" means a direct or indirect connection, such as a direct electrical, mechanical or magnetic connection between connected things or an indirect connection through one or more passive or active intermediate devices. The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal or data / clock signal. The meaning of "a, an" and "the" includes plural references. The meaning of "in..." includes "in..." and "on...". The terms "substantially", "close", "approximately", "close to" and "approximately" generally refer to within + / -10% of the target value.

[0013] Unless otherwise specified, the use of ordinal adjectives "first," "second," and "third," etc. to describe common objects indicates merely that different instances of similar objects are being referenced, and is not intended to imply that the objects so described must be in a given sequence in time, space, order, or in any other manner.

[0014] For purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). The terms "left", "right", "front", "back", "top", "bottom", "above", "below", and the like in the specification and claims, if any, are used for descriptive purposes and are not necessarily intended to describe fixed relative positions.

[0015] Figure 1 A semiconductor package 100 (hereinafter also referred to as "package 100") according to some embodiments is schematically shown, the semiconductor package 100 including a first die 102 having interconnect layers formed on two opposing sides and a second die 105 coupled to the first die. In some embodiments, the dies 102, 105 may be any suitable type of die to implement any suitable type of functionality, such as a memory die, a processor die, a graphics die, etc.

[0016] In some embodiments, die 102 may include interconnect layers 106 and 107 formed on two opposing sides or surfaces of die 102, where interconnect layers 106 and 107 are symbolically illustrated using bold lines. For example, each of interconnect layers 106 and 107 may be coupled to various corresponding internal components (e.g., active components, transistors, etc.) of die 102.

[0017] In some embodiments, interconnect layers 106 and 107 may include traces, redistribution layers (RDLs), wiring structures, wiring layers, interconnect structures (e.g., bumps, bump pads, metal pillars, balls formed using metals, alloys, solderable materials, solder formed using metals, alloys, solderable materials, etc.), and / or other interconnect components on respective surfaces of die 102. In some embodiments, die 102 may be encapsulated using an encapsulant or molding compound 114.

[0018] In some embodiments, the RDL layer 108 may be attached or coupled to the interconnect layer 107, wherein the RDL layer 108 may be embedded within the encapsulant or molding compound 126. In some embodiments, the RDL layer 108 may redistribute the connections of the interconnect layer 107.

[0019] The die 105 may be attached or coupled to the RDL layer 108 via an interconnect structure 110. The interconnect structure 110 may include, for example, bumps, bump pads, metal pillars (e.g., copper pillars), balls formed using metals, alloys, solderable materials, solder formed using metals, alloys, solderable materials, etc. In some embodiments, the die 105 may be encapsulated using an encapsulant or molding compound 124.

[0020] In some embodiments, RDL layer 112 can be attached to interconnect layer 106, wherein RDL layer 112 can be embedded within encapsulant or molding compound 116. In some embodiments, RDL layer 112 can redistribute connections of interconnect layer 106. In some embodiments, RDL layer 112 can be attached to or coupled to package interconnect structure 120. Interconnect structure 120 can include, for example, bumps, bump pads, metal pillars (e.g., copper pillars), balls formed using metals, alloys, solderable materials, solder formed using metals, alloys, solderable materials, etc. In some embodiments, package 100 can be attached to external components (e.g., Figure 1 substrate, main board, etc. not shown).

[0021] Thus, in package 100, die 102 may be coupled to die 105 using interconnect layer 107 formed on a first side of die 102. In addition, die 102 may be coupled to package interconnect structure 120 (e.g., for attachment to external components) using interconnect layer 106 formed on a second side of die 102. Thus, die 102 may be stacked on die 105 without any intermediate die structures, such as interposers, bridge dies, etc. In some embodiments, interconnect layers 106 and 107 may not be connected to each other by vias or TSVs. This may result in a reduction in the die-to-die interconnect length between die 102 and 105.

[0022] Figures 2A-2K Schematic diagram of forming a semiconductor package (eg, Figure 1 A process for packaging a semiconductor package 100), wherein the semiconductor package includes a first die having interconnect layers formed on two opposite sides and a second die coupled to the first die. Figure 2A , shows an assembly 200a including a temporary substrate or wafer (eg, carrier 202) and an adhesive layer 204 attached to the carrier 202. Figure 2B , shows an assembly 200b formed from assembly 200a, wherein assembly 200b may include RDL layers 112a, 112b, 112c formed on a temporary carrier 202. In some embodiments, the RDL layers 112a, 112b, 112c may be embedded in an encapsulant or molding compound 116. The RDL layers 112a, 112b, 112c may correspond to Figure 1 The RDL layer 112 .

[0023] Please note, Figures 2A-2K The formation of three example packages is shown, each of which can be similar to Figure 1 In some examples, more than three packages may be formed. For ease of discussion, this article discusses Figure 2A -2L three packages of one or some of the formation of the package. For example, refer to Figure 2B , three packages may be formed over the RDL layers 112a, 112b, and 112c, respectively, however, for ease of discussion, the package formed on one of the RDL layers 112 (e.g., the RDL layer 112b) may be discussed in detail (and the same discussion may apply to the other two packages formed on both sides).

[0024] Elements referred to herein with a common reference numeral followed by a particular number or letter may be referred to collectively by the reference numeral alone. For example, the RDLs 112a, 112b, and 112c may be collectively and generically referred to as the plural RDLs 112 and the singular RDL 112. Similarly, the dies 104a, 104b, and 104c (e.g., discussed later herein) may be collectively and generically referred to as the plural dies 104 and the singular die 104.

[0025] Reference now Figure 2C , dies 104a, 104b, and 104c are placed over carrier 202, for example, over RDL layers 112a, 112b, and 112c, respectively, to form component 200c. As an example, die 104b may include section 102b, which may include active components such as transistors. Interconnect layers 106b and 107b may be formed on two opposite sides of section 102b. For example, interconnect layer 106b may be attached or coupled to RDL layer 112b. Die 104b may further include section 103b, which may be formed on interconnect layer 107b. In some embodiments, section 103b may not include active circuit components. For example, section 103b may not include any transistors. In an example, section 103b may be referred to as a "body layer", "body section", "non-active layer", "support layer", "sacrificial layer", etc. In some embodiments, segment 103b may include bulk silicon, while in some other embodiments, segment 103b may include silicon and / or heterogeneous integration such as III-V, III-N, sapphire, glass, and the like.

[0026] In some embodiments, segment 103b can provide mechanical strength and stability to segment 102b and interconnect layer 107b. In an example, the segment of die 104b between interconnect layers 106b and 107b can be referred to as a transistor layer (eg, because this segment includes active components). Interconnect layer 107b can be between the transistor layer and bulk layer 103b.

[0027] Reference now Figure 2D , the dies 104a, 104b, and 104c are encapsulated by an encapsulant or molding compound 114 to form assembly 200d. Referring now to Figure 2E , the molding compound 114 may be selectively or partially removed (e.g., using grinding, chemical mechanical planarization or CMP, surface planarization (e.g., by blade cutting), etching, etc.) to form the assembly 200e. For example, the top portion of the molding compound 114 may be removed in the assembly 200e along with the segments 103a, 103b, 103c of the dies 104a, 104b, 104c, respectively. In some embodiments, due to the Figure 2E The removal process is performed, and the interconnect layers 107a, 107b, 107c can be exposed through the molding compound 114. In some embodiments, the removal in the component 200e can be performed using, for example, mechanical grinding, a polishing process (such as chemical mechanical planarization (CMP)), etching (e.g., dry etching, wet etching, etc.), surface planarization (e.g., blade dicing), etc.

[0028] Reference now Figure 2F In the assembly 200f, the RDL layers 108a, 108b, and 108c may be formed on the interconnect layers 107a, 107b, and 107c, respectively. In some embodiments, the RDL layers 108a, 108b, and 108c may be embedded in the encapsulant or molding compound 126. In an example, the RDL layers 108a, 108b, and 108c may correspond to Figure 1 The RDL layer 108 .

[0029] Reference now Figure 2G In assembly 200g, dies 105a, 105b, and 105c may be placed on RDL layers 108a, 108b, and 108c, respectively, of assembly 200f. In an example, dies 105a, 105b, and 105c may correspond to Figure 1 The tube core 105.

[0030] Reference now Figure 2HIn the assembly 200h, in some embodiments, the die 105a, 105b, 105c may be encapsulated using an encapsulant or molding compound 124. For example, the molding compound 124 may encapsulate the die 105a, 105b, 105c so that the die are completely encapsulated by the molding compound 124 and are not exposed through the molding compound 124.

[0031] Reference now Fig.2I In assembly 200i, in some embodiments, assembly 200h may be flipped and wafer carrier 202 may be removed. Removal of wafer carrier 202 may depend on the adhesive used in the temporary carrier and may use one or more processes, such as ultraviolet (UV) release mechanism, thermal release mechanism, mechanical release mechanism, infrared release mechanism, etc.

[0032] Reference now Figure 2J In assembly 200j, in some embodiments, interconnect structures 120a, 120b, and 120c may be attached to RDL layers 112a, 112b, and 112c, respectively. In an example, interconnect structures 120a, 120b, 120c, and 120b may correspond to Figure 1 The interconnect structure 120 of the component 100.

[0033] Reference now Figure 2K , the component 200j can be singulated to form three semiconductor packages 200k1, 200k2 and 200k3. In an example, each of the packages 200k1, 200k2 and 200k3 can be similar to Figure 1 Package 100.

[0034] therefore, Figure 1 A die 102 is shown including interconnect layers 106 and 107 on both sides of the transistor layer of the die 102, and Figures 2A-2K An example process for forming such a die is shown.In some embodiments, die 102 can be attached from both sides to an RDL, another die, a package interconnect structure (eg, interconnect structure 120 ), etc. through interconnects 106 and 107 .

[0035] In an example, there may be no vias, such as thick vias like TSVs, in the die 102. For example, there may be no vias (eg, TSVs) interconnecting the interconnect layers 106 and 107.

[0036] In some embodiments and as with respect to Figures 2A-2K As discussed, there may not be any thin die handling, for example, when forming package 100. For example, die 102 may be relatively thin. However, as discussed with respect to Figure 2CAs discussed, die 102 may be assembled as a relatively thick die 104 (e.g., including a thinner die 102 and a supporting body layer 103). Assembling a thick die 104 (e.g., rather than assembling a thin die 103) and later removing body layer 103 may, for example, enable the elimination of supporting thickness in the final die 102. For example, interconnect layer 107 may initially be buried within die 104 and may be removed later. Figure 2E The interconnect layer 107 is exposed after the bulk layer 103 is thinned and removed. Such a process can enable the formation of interconnect layers 106 and 107 on both sides of the die 102 without any need for any TSVs or a higher thickness of the die 102 to support or connect the two layers.

[0037] Reference again Figure 1 , this figure shows an example package 100. Variations of this package 100 may be possible. For example, the RDL layer 108 between the dies 102 and 105 may be removed, for example, as Figure 3A For example, Figure 3A Schematically illustrates a semiconductor package 300a (hereinafter also referred to as “package 300a”) according to some embodiments, the semiconductor package 300a includes a first die 102 having interconnect layers formed on two opposite sides and a second die 105 coupled to the first die 102 without any intermediate RDL layer between the first die 102 and the second die 105. The package 300a is at least partially similar to Figure 1 However, unlike package 100, in package 300, there is no intermediate RDL layer between dies 102 and 105 (e.g., RDL layer 108 of package 100 is not formed in package 300a). The formation and other details of package 300a may be at least partially apparent from those of package 100, and therefore, package 300a is not discussed in further detail herein.

[0038] exist Figure 1 In FIG. 1 , a single die 102 is shown with interconnect layers on both sides. However, in some embodiments, multiple such dies may be stacked, for example, as in FIG. Figure 3B For example, Figure 3B Schematically illustrates a semiconductor package 300b (hereinafter also referred to as “package 300b”) including a plurality of stacked dies, wherein each of at least two dies has interconnect layers formed on two opposite sides, according to some embodiments. Package 300b is at least partially similar to Figure 1 However, unlike package 100, in package 300b, an additional die 302 may be present. Die 302 may be at least partially similar to Figure 1For example, die 302 may have interconnect layers 306 and 307 formed on two opposing surfaces of die 302. In some embodiments, as Figure 3B As shown in FIG. 1 , dies 102 , 302 , and 105 may be stacked. Figure 3B Only two dies (e.g., dies 102 and 302) with interconnect layers on both sides are shown, but more than two such dies may be stacked. The formation and other details of package 300b may be at least partially apparent from those of package 100, and thus package 300b is not discussed in further detail herein.

[0039] Packages 100, 300a, 300b can be used in many fields. As discussed, in these packages, a die (e.g., die 102, 302) can have interconnect layers formed on two opposing sides without any through-holes or TSVs interconnecting the two opposing sides. In some embodiments, this can result in a relatively small thickness of die 102, 302, for example, compared to the thickness of a conventional die with TSVs, which can result in better performance (e.g., due to a reduction in die-to-die interconnect length and coupling capacitance). In addition, with respect to Figures 2A-2K The discussed die assemblies may allow integration of different technologies, die and / or raw wafer sizes.

[0040] In some embodiments, dies 102 , 105 , and / or 302 may be used for various purposes, for example, as a microprocessor, a memory die, a graphics die, a micro-electromechanical system (MEMS) die, an analog and RF integrated die, etc.

[0041] Figure 4 A computer system, computing device, or SoC (system on chip) 2100 is shown in accordance with some embodiments, wherein one or more components of the computing system 2100 are formed using a semiconductor package including two or more stacked dies, wherein at least one of the stacked dies has interconnect layers formed on two opposing surfaces. It is noted that elements having the same reference numerals (or names) as elements of any other figure Figure 4 Those elements of can operate or function in any manner similar to that described, but are not limited thereto.

[0042] In some embodiments, computing device 2100 represents a suitable computing device, such as a computing tablet, a mobile phone or smartphone, a laptop, a desktop computer, an IOT device, a server, a set-top box, a wireless-enabled e-reader, etc. It will be understood that certain components are generally shown and not all components of such a device are shown in computing device 2100.

[0043] In some embodiments, computing device 2100 includes a first processor 2110. Various embodiments of the present disclosure may also include a network interface within 2170, such as a wireless interface, so that system embodiments may be incorporated into a wireless device, such as a cellular phone or a personal digital assistant.

[0044] In one embodiment, the processor 2110 may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing component. The processing operations performed by the processor 2110 include the execution of an operating platform or operating system on which applications and / or device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or with other devices, operations related to power management, and / or operations related to connecting the computing device 2100 to another device. The processing operations may also include operations related to audio I / O and / or display I / O.

[0045] In one embodiment, the computing device 2100 includes an audio subsystem 2120, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone outputs and microphone input. Devices for such functionality may be integrated into the computing device 2100 or connected to the computing device 2100. In one embodiment, a user interacts with the computing device 2100 by providing audio commands that are received and processed by the processor 2110.

[0046] The display subsystem 2130 represents hardware (e.g., display device) and software (e.g., driver) components that provide a visual and / or tactile display for a user to interact with the computing device 2100. The display subsystem 2130 includes a display interface 2132, which includes a specific screen or hardware device for providing a display to the user. In one embodiment, the display interface 2132 includes logic separate from the processor 2110 to perform at least some processing related to the display. In one embodiment, the display subsystem 2130 includes a touch screen (or touchpad) device that provides both output and input to the user.

[0047] I / O controller 2140 represents hardware devices and software components related to user interaction. I / O controller 2140 is operable to manage hardware that is part of audio subsystem 2120 and / or display subsystem 2130. In addition, I / O controller 2140 shows connection points for additional devices connected to computing device 2100 through which a user may interact with the system. For example, devices that may be attached to computing device 2100 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices (such as a card reader or other device) for use with specific applications.

[0048] As mentioned above, the I / O controller 2140 can interact with the audio subsystem 2120 and / or the display subsystem 2130. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 2100. In addition, audio output can be provided instead of display output, or in addition to display output. In another example, if the display subsystem 2130 includes a touch screen, the display device also acts as an input device, which can be managed at least in part by the I / O controller 2140. There may also be additional buttons or switches on the computing device 2100 to provide I / O functions managed by the I / O controller 2140.

[0049] In one embodiment, I / O controller 2140 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or manages other hardware that may be included in computing device 2100. The input can be part of direct user interaction, as well as providing environmental input to the system to affect its operation (such as filtering for noise, adjusting the display for brightness detection, applying a flash to a camera, or other features).

[0050] In one embodiment, the computing device 2100 includes power management 2150 that manages battery power usage, charging of the battery, and features related to power saving operation. The memory subsystem 2160 includes memory devices for storing information in the computing device 2100. The memory may include non-volatile (the state does not change if power to the memory device is interrupted) and / or volatile (the state is indeterminate if power to the memory device is interrupted) memory devices. The memory subsystem 2160 may store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of the computing device 2100. In one embodiment, the computing device 2100 includes a clock generation subsystem 2152 for generating a clock signal.

[0051] Elements of the embodiments are also provided as machine-readable media (e.g., memory 2160) for storing computer-executable instructions (e.g., instructions for implementing any other process discussed herein). The machine-readable medium (e.g., memory 2160) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memories (PCMs), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by means of a data signal via a communication link (e.g., a modem or a network connection).

[0052] Connectivity 2170 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) used to enable computing device 2100 to communicate with external devices. Computing device 2100 can be a standalone device, such as other computing devices, wireless access points or base stations, and peripherals, such as headsets, printers, or other devices.

[0053] Connectivity 2170 may include multiple different types of connectivity. In summary, computing device 2100 is shown with cellular connectivity 2172 and wireless connectivity 2174. Cellular connectivity 2172 generally refers to cellular network connectivity provided by a wireless carrier, such as cellular network connectivity provided via GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 2174 refers to wireless connectivity that is not cellular and may include personal area networks (such as Bluetooth, near field, etc.), local area networks (such as Wi-Fi) and / or wide area networks (such as WiMax) or other wireless communications.

[0054] Peripheral connections 2180 include hardware interfaces and connectors and software components (e.g., drivers, protocol stacks) used to make peripheral connections. It will be understood that computing device 2100 can be both a peripheral device to other computing devices ("to" 2182) and have peripheral devices connected to it ("from" 2184). Computing device 2100 typically has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on computing device 2100. In addition, the docking connector may allow computing device 2100 to connect to certain peripherals that allow computing device 2100 to control content output, such as to an audio-visual system or other system.

[0055] In addition to a dedicated docking connector or other dedicated connection hardware, the computing device 2100 may also make peripheral connections 2180 via common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may include any of a variety of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High-Definition Multimedia Interface (HDMI), Firewire, or other types.

[0056] In some embodiments, one or more components of computing system 2100 may be formed using a semiconductor package including two or more stacked dies, wherein at least one of the stacked dies has interconnect layers formed on two opposing surfaces, e.g., as described with respect to Figure 1-3B As an example only, a first component of the computing device 2100 (eg, a memory of the memory subsystem 2160) may be included in Figure 1-3B One of the dies 102 or 105, and a second component of the computing device 2100 (eg, the processor 2110) may be included in Figure 1-3B Another die among die 102 or 105 .

[0057] References in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least some embodiments, but not necessarily in all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" do not necessarily all refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claims refer to "a" or "an" element, this does not mean that there is only one of the elements. If the specification or claims refer to "additional" elements, this does not exclude the presence of more than one of the additional elements.

[0058] In addition, the specific features, structures, functions or characteristics can be combined in one or more embodiments in any suitable manner. For example, the first embodiment can be combined with the second embodiment wherever the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0059] Although the present disclosure has been described in conjunction with the specific embodiments of the present disclosure, many alternatives, modifications and variations of such embodiments will be apparent to those skilled in the art based on the foregoing description. The embodiments of the present disclosure are intended to cover all such alternatives, modifications and variations that fall within the broad scope of the appended claims.

[0060] In addition, for simplicity of illustration and discussion, and in order not to obscure the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures. In addition, the arrangement may be shown in block diagram form so as not to obscure the present disclosure, and the arrangement is also shown in view of the fact that the details of the implementation of such block diagram arrangements are highly dependent on the platform in which the present disclosure is to be implemented (i.e., such details should be well within the knowledge of those skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the present disclosure, it should be apparent to those skilled in the art that the present disclosure can be practiced without or with variations of these specific details. Therefore, this description is to be regarded as illustrative rather than restrictive.

[0061] The following example clauses relate to further embodiments. The details in the example clauses may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0062] Example 1. A device comprising: a first die having a first surface and a second surface, the first die comprising: a first layer formed on the first surface of the first die, wherein the first layer comprises one or more first interconnects, and a second layer formed on the second surface of the first die, wherein the second layer comprises one or more second interconnects; a second die coupled to the first layer; and a plurality of structures for coupling the device to an external component, wherein the plurality of structures are coupled to the second layer.

[0063] Example 2. The apparatus of Example 1 or any other example, wherein the first die lacks a through silicon via (TSV) connecting the first layer on the first surface and the second layer on the second surface.

[0064] Example 3. The apparatus of Example 1 or any other example, wherein the first die comprises: a first plurality of active components coupled to the first layer; and a second plurality of active components coupled to the second layer.

[0065] Example 4. The apparatus of any of Examples 1-3 or any other example, wherein the plurality of structures is a first plurality of structures, and wherein the apparatus further comprises: a second plurality of structures coupled to the second die, wherein the second die is coupled to the first layer through the second plurality of structures.

[0066] Example 5. The apparatus of Example 4 or any other example, further comprising: a third layer coupled to the first layer, wherein the third layer comprises one or more redistribution structures, wherein the second die is coupled to the first layer through the third layer.

[0067] Example 6. The apparatus of Example 4 or any other example, wherein the second die is coupled to the first layer without any intermediate layers including a redistribution structure between the second die and the first layer.

[0068] Example 7. The device of any of Examples 1-3 or any other example, further comprising: a third layer coupled to the second layer, wherein the third layer comprises one or more redistribution structures, wherein the plurality of structures are coupled to the second layer via the third layer.

[0069] Example 8. The apparatus of any of Examples 1-3 or any other example, further comprising: a third die disposed between the first die and the second die, wherein the second die is coupled to the first layer via the third die.

[0070] Example 9. The apparatus of Example 8 or any other example, wherein the third die comprises: a third layer formed on a first surface of the third die; and a fourth layer formed on a second surface of the third die, wherein the third die lacks a through-silicon via (TSV) connecting the third layer and the fourth layer.

[0071] Example 10. A semiconductor package comprising: a first die, a second die, and a third die arranged in a stacked arrangement, wherein the second die comprises: a first interconnect layer, the first interconnect layer being formed on a first surface of the second die and coupled to the first die, and a second interconnect layer, the second interconnect layer being formed on a second surface of the second die and coupled to the third die, and wherein the second die lacks any through-silicon vias (TSVs) for connecting the first interconnect layer and the second interconnect layer.

[0072] Example 11. The semiconductor package of Example 10 or any other example, wherein the first surface of the second die and the second surface of the second die are two opposite surfaces of the second die.

[0073] Example 12. A semiconductor package as described in Example 10 or any other example, wherein the first die includes: a third interconnect layer, which is formed on a first surface of the first die and coupled to a package interconnect structure to couple the semiconductor package to an external component; and a fourth interconnect layer, which is formed on a second surface of the first die and coupled to the first interconnect layer of the second die, wherein the first die lacks any through-silicon vias (TSVs) used to connect the third interconnect layer and the fourth interconnect layer.

[0074] Example 13. The semiconductor package of any of Examples 10-12 or any other example, wherein the second die comprises: a first plurality of active components coupled to the first interconnect layer; and a second plurality of active components coupled to the second interconnect layer.

[0075] Example 14. The semiconductor package of any one of Examples 10-12 or any other example, further comprising: a molding compound for encapsulating the first die, the second die, and the third die.

[0076] Example 15. A method comprising: placing a first die on a substrate, the first die comprising: a first layer comprising one or more active devices, a second layer on a first side of the first layer, wherein the second layer comprises one or more first interconnects, a third layer on a second side of the first layer, wherein the third layer comprises one or more second interconnects, and a fourth layer comprising a bulk material, wherein the second layer is between the first layer and the fourth layer; and selectively removing the fourth layer to expose the second layer so that two opposite surfaces of the first die respectively comprise the second layer and the third layer.

[0077] Example 16. The method of Example 15 or any other example, further comprising: forming a fifth layer on the substrate, wherein the fifth layer comprises a redistribution structure, and wherein the first die is placed on the substrate such that the third layer is disposed on the fifth layer.

[0078] Example 17. The method of Example 15 or any other example, wherein selectively removing the fourth layer comprises: depositing a molding compound to encapsulate the first die; and selectively removing at least a portion of the molding compound along with the fourth layer to expose the second layer through the molding compound.

[0079] Example 18. The method of Example 15 or any other example, wherein selectively removing the fourth layer comprises selectively removing the fourth layer via one or more of etching, grinding, or polishing operations.

[0080] Example 19. The method of Example 15 or any other example, further comprising: forming a fifth layer on the second layer, the fifth layer comprising a redistribution structure; and placing a second die on the fifth layer.

[0081] Example 20. The method of any of Examples 15-18 or any other example, further comprising placing a second die on the second layer without any intermediate layers including a redistribution structure between the second die and the first die.

[0082] Example 21. The method of any one of Examples 15-18 or any other example, further comprising: removing the substrate to expose the third layer; and depositing a plurality of interconnect structures on the third layer.

[0083] Example 22. The method of Example 21 or any other example, wherein: the plurality of interconnect structures are to couple the first die to external components.

[0084] Example 23. The method of any of Examples 15-18 or any other example, wherein placing the first die on the substrate comprises placing the third layer of the first die on the substrate.

[0085] Example 24. The method of any of Examples 15-18 or any other example, wherein selectively removing the fourth layer comprises selectively removing the fourth layer while placing the first die on the substrate.

[0086] Example 25. The method of any one of Examples 15-18 or any other example, further comprising: avoiding forming any vias for connecting the second layer and the third layer.

[0087] Example 26. An apparatus comprising: means for performing the method as described in any of Examples 15-25 or any other example.

[0088] Example 27. A device comprising: a component for placing a first tube core on a substrate, the first tube core comprising: a first layer including one or more active devices, a second layer on a first side of the first layer, wherein the second layer includes one or more first interconnects, a third layer on a second side of the first layer, wherein the third layer includes one or more second interconnects, and a fourth layer including a bulk material, wherein the second layer is between the first layer and the fourth layer; and a component for selectively removing the fourth layer to expose the second layer so that two opposite surfaces of the first tube core include the second layer and the third layer, respectively.

[0089] Example 28. The apparatus of Example 27 or any other example, further comprising: means for forming a fifth layer on the substrate, wherein the fifth layer comprises a redistribution structure, and wherein the first die is placed on the substrate such that the third layer is disposed on the fifth layer.

[0090] Example 29. An apparatus as described in Example 27 or any other example, wherein the means for selectively removing the fourth layer includes: means for depositing molding compound to seal the first tube core; and means for selectively removing at least a portion of the molding compound together with the fourth layer to expose the second layer through the molding compound.

[0091] Example 30. The apparatus of Example 27 or any other example, wherein the means for selectively removing the fourth layer comprises means for selectively removing the fourth layer via one or more of etching, grinding, or polishing operations.

[0092] Example 31. The apparatus of Example 27 or any other example, further comprising: means for forming a fifth layer on the second layer, the fifth layer comprising a redistribution structure; and means for placing a second die on the fifth layer.

[0093] Example 31. The apparatus of any of Examples 27-30 or any other example, further comprising means for placing a second die on the second layer without any intermediate layers including a redistribution structure between the second die and the first die.

[0094] Example 32. The apparatus of any one of Examples 27-30 or any other example, further comprising: means for removing the substrate to expose the third layer; and means for depositing a plurality of interconnect structures on the third layer.

[0095] Example 33. The apparatus of Example 32 or any other example, wherein: the plurality of interconnect structures are to couple the first die to an external component.

[0096] Example 34. The apparatus of any of Examples 27-30 or any other example, wherein the means for placing the first die on the substrate comprises means for placing the third layer of the first die on the substrate.

[0097] Example 35. The apparatus of any of Examples 27-30 or any other example, wherein the means for selectively removing the fourth layer comprises means for selectively removing the fourth layer while placing the first die on the substrate.

[0098] Example 36. The apparatus of any one of Examples 27-30 or any other example, further comprising: means for avoiding formation of any vias for connecting the second layer and the third layer.

[0099] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment.

Claims

1. A device comprising: A first tube die having a first surface and a second surface, the first tube die comprising: a first layer formed on the first surface of the first die, wherein the first layer includes one or more first interconnects, and a second layer formed on the second surface of the first die, wherein the second layer includes one or more second interconnects; a second die coupled to the first layer; and a plurality of structures for coupling the device to external components, wherein the plurality of structures are coupled to the second layer, a third tube die disposed between the first tube die and the second tube die, wherein the second die is coupled to the first layer via the third die, and The third tube core comprises: a third layer formed on the first surface of the third die; and a fourth layer formed on the second surface of the third die, The third die lacks a through silicon via (TSV) connecting the third layer and the fourth layer. 2 . The apparatus of claim 1 , wherein the first die lacks a through silicon via (TSV) connecting the first layer on the first surface and the second layer on the second surface.

3. The apparatus of claim 1 , wherein the first die comprises: a first plurality of active components coupled to the first layer; as well as A second plurality of active components is coupled to the second layer.

4. The apparatus of any one of claims 1 to 3, wherein the plurality of structures is a first plurality of structures, and wherein the apparatus further comprises: a second plurality of structures coupled to the second die, Wherein the second die is coupled to the first layer through the second plurality of structures.

5. The apparatus of claim 4, further comprising: a third layer coupled to the first layer, wherein the third layer includes one or more redistribution structures, Wherein the second die is coupled to the first layer through the third layer.

6. The apparatus of claim 4, wherein the second die is coupled to the first layer without any intermediate layers including a redistribution structure between the second die and the first layer.

7. The apparatus of any one of claims 1 to 3, further comprising: a third layer coupled to the second layer, wherein the third layer includes one or more redistribution structures, Wherein the plurality of structures are coupled to the second layer via the third layer.

8. A semiconductor package, comprising: a first die, a second die, and a third die arranged in a stacked arrangement, The second tube core comprises: a first interconnect layer formed on a first surface of the second die and coupled to the first die, and a second interconnect layer formed on a second surface of the second die and coupled to the third die, and wherein the second die lacks any through silicon vias (TSVs) for connecting the first interconnect layer and the second interconnect layer, The first tube core comprises: a third interconnect layer formed on the first surface of the first die and coupled to a package interconnect structure to couple the semiconductor package to an external component; and a fourth interconnect layer formed on a second surface of the first die and coupled to the first interconnect layer of the second die, Wherein the first die lacks any through silicon vias (TSVs) for connecting the third interconnect layer and the fourth interconnect layer. 9 . The semiconductor package of claim 8 , wherein the first surface of the second die and the second surface of the second die are two opposite surfaces of the second die.

10. The semiconductor package of any one of claims 8-9, wherein the second die comprises: a first plurality of active components coupled to the first interconnect layer; as well as A second plurality of active components is coupled to the second interconnect layer.

11. The semiconductor package according to any one of claims 8 to 9, further comprising: A molding compound is used to encapsulate the first die, the second die, and the third die.

12. A method comprising: A first die is placed on a substrate, the first die comprising: a first layer comprising one or more active devices, a second layer on a first side of the first layer, wherein the second layer includes one or more first interconnects, a third layer on a second side of the first layer, wherein the third layer includes one or more second interconnects, and a fourth layer comprising a bulk material, wherein the second layer is between the first layer and the fourth layer; and The fourth layer is selectively removed to expose the second layer, so that two opposite surfaces of the first die include the second layer and the third layer, respectively.

13. The method of claim 12, further comprising: A fifth layer is formed on the substrate, wherein the fifth layer includes a redistribution structure, and wherein the first die is placed on the substrate such that the third layer is disposed on the fifth layer.

14. The method of claim 12, wherein selectively removing the fourth layer comprises: depositing a molding compound to encapsulate the first die; as well as At least a portion of the molding compound together with the fourth layer is selectively removed to expose the second layer through the molding compound.

15. The method of claim 12, wherein selectively removing the fourth layer comprises: The fourth layer is selectively removed via one or more of etching, grinding, or polishing operations.

16. The method of claim 12, further comprising: forming a fifth layer on the second layer, the fifth layer comprising a redistribution structure; as well as A second die is placed on the fifth layer.

17. The method of any one of claims 12 to 15, further comprising: A second die is placed on the second layer without any intervening layers including a redistribution structure between the second die and the first die.

18. The method of any one of claims 12-15, further comprising: removing the substrate to expose the third layer; as well as A plurality of interconnect structures are deposited on the third layer.

19. The method of claim 18, wherein: The plurality of interconnect structures are to couple the first die to external components.

20. The method of any one of claims 12-15, wherein placing the first die on the substrate comprises: The third layer of the first die is placed on the substrate.

21. The method of any one of claims 12-15, wherein selectively removing the fourth layer comprises: The fourth layer is selectively removed while the first die is placed on the substrate.

22. The method of any one of claims 12-15, further comprising: Avoid forming any vias for connecting the second layer and the third layer.

23. A device comprising: Means for performing the method as claimed in any one of claims 12-22.

24. A computer-readable medium having instructions stored thereon, which, when a computing device executes the instructions, causes the computing device to execute the method according to any one of claims 12 to 22.

25. A computer program product comprising program instructions, which, when executed by a processor, implement the steps of the method according to any one of claims 12 to 22.

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