Improved Contact to an N-Type Transistor with an L-Groove Channel

Abstract

A device is provided that includes: a first region over a substrate, where the first region includes a first semiconductor material having an L-valley transport band structure; a second region in contact with the first region at a junction, where the second region includes a second semiconductor material having an X-valley transport band structure, where a <111> crystal direction of one or more crystals of the first and second semiconductor materials is substantially orthogonal to the junction; and a metal adjacent to the second region, the metal being conductively coupled to the first region through the junction. Other embodiments are also disclosed and claimed.

Description

BACKGROUND OF THE INVENTION

[0001] In semiconductor devices, as transistor sizes scale down, the regions forming contacts between metals and source / drain epitaxial regions become smaller and contact resistance increases. Additionally, Schottky barriers make direct connections between certain metals and semiconductor materials difficult to achieve. In contrast to the intrinsic resistance of materials, contact resistance refers to the resistance attributable to current flowing across the interface between materials, e.g., across the interface between a metal and a silicide or between different semiconductor materials. Contact resistance increases the overall resistance of the transistor conduction path, thereby reducing the drive current flowing in the channel.

[0002] The reduction in transistor drive current attributable to contact resistance is one of the main factors limiting enhanced computer processor performance. Some efforts to minimize contact resistance include using specific metals and doped silicides in the source / drain regions. Heavier n-type doping in the source / drain regions results in lower contact resistance for electronic devices. Si can be n-type doped more heavily than most other semiconductors, resulting in lower n-type contact resistance than materials such as, but not limited to, Ge. Si is a so-called X-valley material, while Ge is an L-valley material. The high n-type contact resistance of L-valley materials limits their applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. However, the various embodiments should not be taken to limit the disclosure to specific embodiments, but are for explanation and understanding only.

[0004] Figure 1 Illustrates an example heterostructure according to some embodiments,

[0005] Figure 2 Illustrates an example crystal orientation at a heterojunction according to some embodiments,

[0006] Figure 3 Illustrates an example momentum space at a heterojunction according to some embodiments,

[0007] Figure 4 Illustrates an example transverse momentum space at a heterojunction according to some embodiments,

[0008] Figure 5 Illustrates an example transverse momentum space at a heterojunction according to some embodiments,

[0009] Figure 6 Illustrates an example transverse momentum space at a heterojunction according to some embodiments,

[0010] Figure 7A perspective view of an example semiconductor device in accordance with some embodiments is illustrated, the example semiconductor device having an improved contact to an n-type transistor having an L-valley channel.

[0011] Figure 8 A cross-sectional view of an example semiconductor device in accordance with some embodiments is illustrated, the example semiconductor device having an improved contact to an n-type transistor having an L-valley channel.

[0012] Figure 9 A perspective view of an example semiconductor device in accordance with some embodiments is illustrated, the example semiconductor device having an improved contact to an n-type transistor having an L-valley channel.

[0013] Figure 10 A cross-sectional view of an example semiconductor device in accordance with some embodiments is illustrated, the example semiconductor device having an improved contact to an n-type transistor having an L-valley channel.

[0014] Figure 11 A cross-sectional view of an example semiconductor device in accordance with some embodiments is illustrated, the example semiconductor device having an improved contact to an n-type transistor having an L-valley channel.

[0015] Figure 12 A flowchart of a method of forming a semiconductor device in accordance with some embodiments is illustrated, the semiconductor device having an improved contact to an n-type transistor having an L-valley channel, and

[0016] Figure 13 An intelligent device or a computer system or a SoC (system-on-chip) in accordance with some embodiments is illustrated, which includes a semiconductor device having an improved contact to an n-type transistor having an L-valley channel. Detailed Description

[0017] An improved contact to an n-type transistor having an L-valley channel is generally presented. In this regard, embodiments of the present disclosure achieve a lower contact resistance to the L-valley channel through a heterostructure with an X-valley transport material, the X-valley transport material being adjacent to the L-valley channel in a specific crystal orientation. Current flows from a metal contact into the heavily doped X-valley material and then into the L-valley channel material. Since the X-valley material can be n-type heavily doped, the resistance across the metal / X-valley material interface is optimized. As described in the present disclosure, the resistance across the X-valley / L-valley material interface is minimized by designing the crystal orientation. In this regard, for an n-type transistor with an L-valley channel material, the problem of the metal-to-semiconductor Schottky barrier can be alleviated and the heterointerfacial resistance can be minimized. Those skilled in the art will appreciate that alternative n-type channel materials, such as but not limited to Ge and In y Ga 1-y As.

[0018] In the following description, numerous specific details are discussed to provide a more thorough explanation of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present disclosure.

[0019] Note that in the corresponding drawings of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more constituent signal paths, and / or some lines have arrows at one or more ends to indicate the primary information flow direction. Such indications are not intended to be restrictive. Rather, the lines are used in conjunction with one or more exemplary embodiments to facilitate easier understanding of a circuit or logic unit. Depending on design requirements or preferences, any represented signal may in fact comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0020] Throughout this specification and in the claims, the term "connected" means a direct connection between the objects being connected, such as an electrical, mechanical, or magnetic connection, without any intermediate device. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the connected objects or an indirect connection through one or more passive or active intermediate devices. The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide an intended function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include plural references. The meaning of "in" includes "in" and "on".

[0021] Unless otherwise specified, the use of ordinal adjectives "first", "second", and "third", etc. to describe a common object only indicates different instances of similar objects being referred to and is not intended to imply that the objects so described must be in a given order in time, in space, in rank, or otherwise.

[0022] For the purposes of the present disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). Terms such as "left", "right", "front", "back", "top", "bottom", "above", "below", etc. (if any) in the specification and in the claims are used for descriptive purposes and need not be used to describe permanent relative positioning.

[0023] Figure 1 Illustrated is an example heterostructure according to some embodiments. As shown, the heterostructure 100 includes a first material 102, a second material 104, a heterojunction 106, a power source 108, and a conduction path 110. In some embodiments, the first material 102 and the second material 104 are different semiconductor materials. When the power source 108, which can represent a battery, a voltage regulator, or other power source, is active, electrons can flow around the conduction path 110, travel through the first material 102, cross the heterojunction 106, and travel through the second material 104. As shown in more detail below, among other factors, the resistance of electrons crossing the heterojunction 106 can be affected by the composition and crystal orientation of the first material 102 and the second material 104.

[0024] Figure 2 Illustrated is an example crystal orientation at a heterojunction according to some embodiments. As shown, the heterojunction 200 includes an X-valley crystal 202, an L-valley crystal 204, an X valley 206, and an L valley 208. The X-valley crystal 202 and the L-valley crystal 204 can represent crystals of an X-valley semiconductor material and an L-valley semiconductor material, respectively. As used herein, an X-valley semiconductor material is a semiconductor material having a band structure that will indicate that transport is dominated by X-valley electrons. Those skilled in the art will recognize that, for example, examples of X-valley semiconductor materials include, but are not limited to, Si and Si x Ge 1-x . Moreover, an L-valley semiconductor material is a semiconductor material having a band structure that will indicate that transport is dominated by L-valley electrons. Those skilled in the art will recognize that, for example, examples of L-valley semiconductor materials include, but are not limited to, Ge and In y Ga 1-y As.

[0025] Valley X 206 and Valley L 208 represent theoretical positions where conduction electrons will most likely be present in Valley X crystal 202 and Valley L crystal 204, respectively. As shown, Valley X crystal 202 and Valley L crystal 204 butt against each other in the <100> crystal direction, and electrons guided across the interface from Valley X crystal 202 to Valley L crystal 204 will move from Valley X 206 of Valley X crystal 202 to Valley L 208 of Valley L crystal 204.

[0026] Figure 3 An example momentum space at a heterojunction according to some embodiments is illustrated. As shown, FIG. 300 includes Valley X 302, Valley L 304, and transverse plane 306. Valley X 302 is placed along the main crystal axis, while Valley L 304 is placed along the equivalent <111> crystal direction. Transverse plane 306 is a plane transverse to the direction of electron flow between the Valley X and Valley L crystals, which in this case is the <100> crystal direction.

[0027] Figure 4 An example transverse momentum space at a heterojunction according to some embodiments is illustrated. As shown, FIG. 400 includes Valley X 402, double Valley X 404, and double Valley L 406. FIG. 400 represents the transverse momentum space (such as transverse plane 306) when electrons are guided across the Valley X crystal / Valley L crystal interface along the <100> crystal direction. As can be seen, Valley X 402 and double Valley X 404 are not aligned with double Valley L 406. Therefore, the transverse momentum will not be conserved, and significant electron reflection and poor conductance across the interface are expected.

[0028] Figure 5 An example transverse momentum space at a heterojunction according to some embodiments is illustrated. As shown, FIG. 500 includes Valley X 502, double Valley X 504, Valley L 506, and double Valley L 508. FIG. 500 represents the transverse momentum space when electrons are guided across the Valley X crystal / Valley L crystal interface along the <110> crystal direction. As can be seen, Valley X 502 and double Valley X 504 do not overlap with Valley L 506 and double Valley L 508. Therefore, the transverse momentum will not be conserved, and significant electron reflection and poor conductance across the interface are expected.

[0029] Figure 6 An example transverse momentum space at a heterojunction according to some embodiments is illustrated. As shown, FIG. 600 includes Valley X 602, Valley L 604, and double Valley L 606. FIG. 600 represents the transverse momentum space when electrons are guided across the Valley X crystal / Valley L crystal interface along the <111> crystal direction. As can be seen, Valley X 602 is aligned with Valley L 604, and enhanced transport across the interface is expected due to the conservation of transverse momentum. This crystal orientation will tend to increase conductance and reduce contact resistance.

[0030] Figure 7 FIG. 1 shows a perspective view of an exemplary semiconductor device with enhanced metal contact regions in accordance with some embodiments. As shown, device 700 includes a substrate 702, a fin 704, an insulator 706, a drain region 708, a channel region 710, a source region 712, a gate dielectric 714, a gate region 716, a nucleation layer 718, a contact metal 720, a heterojunction 722, an electron flow direction 724, and a crystal orientation 726. Although shown as a FinFET transistor, in other embodiments, device 700 can be a different topology, such as a planar transistor, or a different device, such as a diode. Although shown as including a single fin 704 and gate region 716, in some embodiments, device 700 can include multiple fins 704 and / or gate regions 716.

[0031] In some embodiments, substrate 702 includes at least one layer of undoped semiconductor, such as Ge, Si, SiGe, InGaAs, AlSb, etc., which can form fin 704. In some embodiments, fin 704, which can include drain region 708, semiconductor region 710, and source region 712, can be formed separately from substrate 702 and can contain different semiconductor materials. Substrate 702 can be composed of one or more semiconductor material layers on top of another semiconductor material such as silicon. In some embodiments, insulator 706 is composed of a buried oxide layer adjacent to fin 704. When device 700 is in an active mode, channel region 710 can serve as a conduction path between source region 712 and drain region 708 located on opposite sides of channel region 710. In some embodiments, device 700 can be an NMOS transistor, and source region 712 and drain region 708 are n-doped variants of the same semiconductor (e.g., germanium) as semiconductor region 710. Although only source region 712 is shown as having a rhombus shape with peaks and slanted surfaces, in some embodiments, drain region 708 has the same shape as source region 712. In some embodiments, fin 704 includes Ge or In y Ga 1-y As, where y < 0.3. In some embodiments, source region 712 (and drain region 708) can be formed by epitaxial growth that selectively forms <111> crystal orientation facets. In some embodiments, source region 712 (and drain region 708) can be overgrown, and a stop etch that selectively forms <111> crystal orientation facets can be utilized.

[0032] Nucleation layer 718 can represent a substantially conformal thin film epitaxially formed on the surface of source region 712, thereby forming heterojunction 722. In some embodiments, nucleation layer 718 can include Si x Ge 1-x . In some embodiments, nucleation layer 718 can include graded Six Ge 1-x , where x varies from nearly 1 at the contact metal 720 to nearly 0 at the heterojunction 722. In some embodiments, the nucleation layer 718 may include dopants such as phosphorus or arsenic or similar molecules for improved contact properties. Although shown as present in the source region 712, the nucleation layer 718 may also cover the surface of the drain region 708. The contact metal 720 may contact the nucleation layer 718. In some embodiments, the contact metal 720 may include titanium, cobalt, or other metals.

[0033] The gate region 716 together with the gate dielectric 714 may form a gate stack over the channel region 710. The gate region 716 may be a metal coupled to an interconnect (not shown) to provide a voltage proximate the channel region 710 to place the device 700 into an active mode. In some embodiments, the gate dielectric 714 may include an oxide and / or a nitride.

[0034] In some embodiments, the substrate 702 has cubic crystallinity and the crystal direction 726 is the <100> crystal direction. In some embodiments, the substrate 702 is part of a (100) wafer. In some embodiments, the heterojunction 722 is approximately 45 degrees (within about ten degrees) relative to the (100) plane of the substrate 702. Those skilled in the art will appreciate that the electron flow direction 724, which is approximately orthogonal (within about ten degrees) to the heterojunction 722, will correspond to the <111> crystal direction in the nucleation layer 718 and the source region 712.

[0035] Figure 8 A cross-sectional view of an example semiconductor device in accordance with some embodiments is illustrated, the example semiconductor device having an improved contact to an n-type transistor having an L-valley channel. As shown, the device 800 includes a substrate 802, a channel region 804, a source region 806, a metal contact 808, a gate region 810, a gate dielectric 812, spacers 814, a heterojunction 818, an electron flow direction 820, and a crystal direction 822. In some embodiments, the device 800 represents a cross-section of a planar transistor, however in other embodiments, different semiconductor devices may be used. For example, in some embodiments, the device 800 may be a triple-gate FinFET. Moreover, the device 800 may include additional layers not shown.

[0036] In some embodiments, the channel region 804 includes Ge or In y Ga 1-y As, where y < 0.3. In some embodiments, the source region 806 may be formed by epitaxial growth after a stop etch that selectively forms <111> crystal direction facets in the channel region 804, thereby forming the heterojunction 818. In some embodiments, the source region 806 may include Six Ge 1-X 。In some embodiments, the source region 806 may include graded Si x Ge 1-x , where x varies from nearly 1 at the contact metal 808 to nearly 0 at the heterojunction 818.

[0037] The gate region 810, together with the gate dielectric 812, may form a gate stack over the channel region 804. The gate region 810 may be a metal coupled to an interconnect (not shown) to provide a voltage proximate the channel region 804 to place the device 800 in an active mode. In some embodiments, the gate dielectric 812 may include an oxide and / or a nitride. The spacers 814 may provide further insulation between the gate region 810 and the source / drain regions.

[0038] In some embodiments, the substrate 802 has cubic crystallinity and the crystal orientation 822 is the <100> crystal orientation. In some embodiments, the substrate 802 is part of a (100) wafer. In some embodiments, the heterojunction 818 is generally at about 45 degrees (within about ten degrees) with respect to the (100) plane of the substrate 802. Those skilled in the art will appreciate that the electron flow direction 820, which is generally orthogonal (within about ten degrees) to the heterojunction 818, will correspond to the <111> crystal orientation in the source region 806 and the channel region 804.

[0039] Figure 9 A perspective view of an example semiconductor device with an enhanced metal contact region in accordance with some embodiments is illustrated. As shown, the device 900 includes a substrate 902, a fin 904, an insulator 906, a drain region 908, a channel region 910, a source region 912, a gate dielectric 914, a gate region 916, a nucleation layer 918, a contact metal 920, a heterojunction 922, an electron flow direction 924, and a crystal orientation 926. Although shown as a FinFET transistor, in other embodiments, the device 900 may be a different topology, such as a planar transistor, or a different device, such as a diode. Although shown as including a single fin 904 and a gate region 916, in some embodiments, the device 900 may include multiple fins 904 and / or gate regions 916.

[0040] In some embodiments, substrate 902 includes at least one layer of undoped semiconductor, such as Ge, Si, SiGe, InGaAs, AlSb, etc., which may form fin 904. In some embodiments, fin 904, which may include drain region 908, channel region 910, and source region 912, may be formed separately from substrate 902 and may comprise different semiconductor materials. Substrate 902 may consist of one or more semiconductor material layers on top of another semiconductor material such as silicon. In some embodiments, insulator 906 consists of a buried oxide layer adjacent to fin 904. When device 900 is in the active mode, channel region 910 may serve as a channel between source region 912 and drain region 908 located on opposite sides of channel region 910. In some embodiments, device 900 may be an NMOS transistor, and source region 912 and drain region 908 are n-doped variants of the same semiconductor (e.g., germanium) as channel region 910. In some embodiments, fin 904 includes Ge or In y Ga 1-y As, where y < 0.3.

[0041] Nucleation layer 918 may represent a substantially conformal thin film epitaxially formed on the surface of source region 912 to form heterojunction 922. In some embodiments, nucleation layer 918 may include Si x Ge 1-x . In some embodiments, nucleation layer 918 may include graded Si x Ge 1-x , where x varies from nearly 1 at contact metal 920 to nearly 0 at heterojunction 922. In some embodiments, nucleation layer 918 may include dopants such as phosphorus or arsenic or similar molecules for improved contact properties. Although shown as present in source region 912, nucleation layer 918 may also cover the surface of drain region 908. Contact metal 920 may contact nucleation layer 918. In some embodiments, contact metal 920 may include titanium, cobalt, or other metals.

[0042] Gate region 916 together with gate dielectric 914 may form a gate stack over channel region 910. Gate region 916 may be a metal coupled to an interconnect (not shown) to provide a voltage proximate to channel region 910 to put device 900 into the active mode. In some embodiments, gate dielectric 914 may include oxide and / or nitride.

[0043] In some embodiments, the substrate 902 has cubic crystallinity and the crystal direction 926 is a <110> crystal direction. In some embodiments, the substrate 902 is part of a (110) wafer. In some embodiments, the heterojunction 922 is substantially orthogonal (within about ten degrees) to the (110) plane of the substrate 902. Those skilled in the art will appreciate that the electron flow direction 924, which is substantially orthogonal (within about ten degrees) to the heterojunction 922, will correspond to the <111> crystal direction in the nucleation layer 918 and the source region 912.

[0044] Figure 10 A cross-sectional view of an example semiconductor device according to some embodiments is illustrated, the example semiconductor device having an improved contact to an n-type transistor having an L valley channel. As shown, the device 1000 includes a substrate 1002, a channel region 1004, a source region 1006, a metal contact 1008, a gate region 1010, a gate dielectric 1012, spacers 1014, a heterojunction 1016, an electron flow direction 1018, and a crystal direction 1020. In some embodiments, the device 1000 represents a cross-section of a planar transistor, however in other embodiments, different semiconductor devices may be used. For example, in some embodiments, the device 1000 may be a triple-gate FinFET. Moreover, the device 1000 may include additional layers not shown.

[0045] In some embodiments, the channel region 1004 includes Ge or In y Ga 1-y As, where y < 0.3. In some embodiments, the source region 1006 may be formed by epitaxial growth after a stop etch that selectively forms <111> crystal direction facets in the channel region 1004, thereby forming the heterojunction 1016. In some embodiments, the source region 1006 may include Si x Ge 1 -X . In some embodiments, the source region 1006 may include graded Si x Ge 1-x , where x varies from nearly 1 at the contact metal 1008 to nearly 0 at the heterojunction 1016.

[0046] The gate region 1010 together with the gate dielectric 1012 may form a gate stack over the channel region 1004. The gate region 1010 may be a metal coupled to an interconnect (not shown) to provide a voltage proximate the channel region 1004 to place the device 1000 in an active mode. In some embodiments, the gate dielectric 1012 may include an oxide and / or a nitride. The spacers 1014 may provide further insulation between the gate region 1010 and the source / drain regions.

[0047] In some embodiments, the substrate 1002 has cubic crystallinity and the crystal orientation 1020 is a <110> crystal orientation. In some embodiments, the substrate 1002 is part of a (110) wafer. In some embodiments, the heterojunction 1016 is substantially orthogonal (within about ten degrees) to the (110) plane of the substrate 1002. Those skilled in the art will appreciate that the electron flow direction 1018, which is substantially orthogonal (within about ten degrees) to the heterojunction 1016, will correspond to the <111> crystal orientation in the source region 1006 and the channel region 1004.

[0048] Figure 11 FIG. shows a cross-sectional view of an exemplary semiconductor device according to some embodiments, the exemplary semiconductor device having an improved contact to an n-type transistor having an L-valley channel. As shown, the device 1100 includes a substrate 1102, a channel region 1104, a source region 1106, a contact metal 1108, a gate region 1110, a gate dielectric 1112, spacers 1114, a heterojunction 1118, an electron flow direction 1120, and a crystal orientation 1122. In some embodiments, the device 1100 represents a cross-section of a planar transistor, however in other embodiments, different semiconductor devices may be used. For example, in some embodiments, the device 1100 may be a tri-gate FinFET. Also, the device 1100 may include additional layers not shown.

[0049] In some embodiments, the channel region 1104 includes Ge or In y Ga 1-y As, where y < 0.3. In some embodiments, the source region 1106 may be formed by epitaxial growth after replacement of the source / drain in the channel region 1104, thereby forming the heterojunction 1118. In some embodiments, the source region 1106 may include Si x Ge 1-x . In some embodiments, the source region 1106 may include graded Si x Ge 1-x , where x varies from nearly 1 at the contact metal 1108 to nearly 0 at the heterojunction 1118.

[0050] The gate region 1110 together with the gate dielectric 1112 may form a gate stack over the channel region 1104. The gate region 1110 may be a metal coupled to an interconnect (not shown) to provide a voltage proximate the channel region 1104 to put the device 1100 into an active mode. In some embodiments, the gate dielectric 1112 may include an oxide and / or a nitride. The spacers 1114 may provide further insulation between the gate region 1110 and the source / drain regions.

[0051] In some embodiments, the substrate 1102 has cubic crystallinity and the crystal direction 1122 is the <111> crystal direction. In some embodiments, the substrate 102 is part of a (111) wafer. In some embodiments, the heterojunction 1118 is substantially parallel (within about ten degrees) to the (111) plane of the substrate 1102. Those skilled in the art will appreciate that the electron flow direction 1120, which is substantially orthogonal (within about ten degrees) to the heterojunction 1118, will correspond to the <111> crystal direction in the source region 1106 and the channel region 1104.

[0052] Figure 12 A flowchart illustrating a method of forming a semiconductor device in accordance with some embodiments, the semiconductor device having an improved contact to an n-type transistor having an L-valley channel. Although the blocks in the flowchart are shown in a particular order with reference Figure 12 to, the order of the actions can be modified. Accordingly, the illustrated embodiments can be performed in a different order and some actions / blocks can be performed in parallel. According to certain embodiments, Figure 12 some of the blocks and / or operations listed in are optional. The numbers assigned to the presented blocks are for clarity and are not intended to prescribe the order in which the various blocks must occur in the operation. Additionally, operations from various flows can be utilized in various combinations.

[0053] Method 1200 begins with receiving (1202) a substrate. In some embodiments, the substrate can be: part of a (100) wafer, such as substrates 702 and 802; part of a (110) wafer, such as substrates 902 and 1002; or part of a (111) wafer, such as substrate 1102. Next, an L-valley channel material is formed (1204) over the substrate. In some embodiments, the channel material can include Ge or In y Ga 1-y As, where y < 0.3.

[0054] Then, a gate stack is formed (1206) over the channel material. In some embodiments, a dummy gate is initially formed and then replaced with a metal gate in a subsequent step. In some embodiments, a metal gate can be formed and then temporarily covered with a masking material. Next, the channel material can be etched or diced (1208) as needed to form facets. In some embodiments, a wet stop etch selective to the <111> crystal direction interface can be utilized to form facets in the channel material.

[0055] The method continues by forming (1210) X-valley source and drain regions. In some embodiments, the X-valley material can include Si x Ge 1-x . In some embodiments, the X-valley material can include graded Six Ge 1-x , where x varies from nearly 1 at the contact with the metal to nearly 0 at the L-valley heterojunction. Next, the source and drain regions (1212) can be etched as needed. In some embodiments, the source and drain regions can be etched back or undercut to expose the facets.

[0056] Then, metal contacts (1214) can be formed on the source and drain regions. In some embodiments, a contact metal is formed over the source and drain regions, which can be titanium, cobalt, or another metal. Finally, additional processing steps (1216) can be performed to form the device. In some embodiments, gate replacement can be performed, followed by the formation of multiple interconnect layers.

[0057] Figure 13 An intelligent device or computer system or SoC (system-on-chip) 1300 according to some embodiments is illustrated, which includes a semiconductor device having an improved contact with an n-type transistor having an L-valley channel. In some embodiments, the computing device 1300 represents a mobile computing device, such as a computing tablet, a mobile phone or a smart phone, a wireless-enabled e-reader, or other wireless mobile devices. It will be understood that certain components are generally shown, and not all components of such a device are shown in the computing device 1300. In some embodiments, one or more components of the computing device 1300, such as the processor 1310 and / or the memory subsystem 1360, include a semiconductor device having an X-valley / L-valley semiconductor heterojunction as described above.

[0058] For the purposes of the embodiments, the transistors in the various circuits and logic blocks described herein are metal-oxide semiconductor (MOS) transistors or derivatives thereof, where the MOS transistor includes a drain, a source, a gate, and a body terminal. The transistor and / or MOS transistor derivatives also include triple-gate and FinFET transistors, tunneling FETs (TFETs), square or circular wire transistors or rectangular strip transistors, ferroelectric FETs (FeFETs), or other devices that implement transistor functionality, such as carbon nanotubes or spintronic devices. The source and drain terminals of the MOSFET are symmetric, i.e., the same terminals and are used interchangeably herein. On the other hand, the TFET device has asymmetric source and drain terminals. Those skilled in the art will appreciate that other transistors can be used, such as bipolar junction transistors - BJT PNP / NPN, BiCMOS, CMOS, etc., without departing from the scope of the present disclosure.

[0059] In some embodiments, the computing device 1300 includes a first processor 1310. Various embodiments of the present disclosure can also include a network interface within 1370, such as a wireless interface, so that the system embodiments can be incorporated into a wireless device, such as a mobile phone or a personal digital assistant.

[0060] In one embodiment, the processor 1310 may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing means. The processing operations performed by the processor 1310 include the execution of an operating platform or operating system on which applications and / or device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or with other devices, operations related to power management, and / or operations related to connecting the computing device 1300 to another device. The processing operations may also include operations related to audio I / O and / or display I / O.

[0061] In one embodiment, the computing device 1300 includes an audio subsystem 1320, which represents the hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. The audio functionality may include speaker and / or headphone output, and microphone input. Devices for such functionality may be integrated into the computing device 1300 or connected to the computing device 1300. In one embodiment, the user interacts with the computing device 1300 by providing audio commands that are received and processed by the processor 1310.

[0062] The display subsystem 1330 represents the hardware (e.g., a display device) and software (e.g., drivers) components that provide a visual and / or tactile display for a user to interact with the computing device 1300. The display subsystem 1330 includes a display interface 1332, which includes a particular screen or hardware device for providing a display to the user. In one embodiment, the display interface 1332 includes logic separate from the processor 1310 to perform at least some of the processing related to the display. In one embodiment, the display subsystem 1330 includes a touch screen (or touchpad) device that provides both output and input to the user.

[0063] The I / O controller 1340 represents the hardware devices and software components related to interaction with the user. The I / O controller 1340 is operable to manage the hardware that is part of the audio subsystem 1320 and / or the display subsystem 1330. Additionally, the I / O controller 1340 illustrates connection points for additional devices connected to the computing device 1300 through which the user may interact with the system. For example, devices that may be attached to the computing device 1300 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use with a particular application, such as a card reader or other device.

[0064] As mentioned above, the I / O controller 1340 can interact with the audio subsystem 1320 and / or the display subsystem 1330. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the audio applications of the computing device 1300. Additionally, instead of or in addition to a display output, an audio output can be provided. In another example, if the display subsystem 1330 includes a touchscreen, the display device also acts as an input device, which can be at least partially managed by the I / O controller 1340. Additional buttons or switches can also be present on the computing device 1300 to provide I / O functions managed by the I / O controller 1340.

[0065] In one embodiment, the I / O controller 1340 manages devices such as accelerometers, cameras, light sensors, or other environmental sensors, or other hardware that may be included in the computing device 1300. The input can be part of a direct user interaction, as well as providing environmental input to the system to affect its operation (such as filtering for noise, adjusting the display for brightness detection, firing the camera flash, or other features).

[0066] In one embodiment, the computing device 1300 includes power management 1350, which manages battery power usage, charging of the battery, and features related to power-saving operations. The memory subsystem 1360 includes memory devices for storing information in the computing device 1300. The memory can include non-volatile (the state does not change if power to the memory device is interrupted) and / or volatile (the state is indeterminate if power to the storage device is interrupted) memory devices. The memory subsystem 1360 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the application programs and functions of the computing device 1300.

[0067] The elements of the embodiments are also provided as a machine-readable medium (e.g., memory 1360) for storing computer-executable instructions. The machine-readable medium (e.g., memory 1360) can include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the present disclosure can be downloaded as a computer program (e.g., BIOS), which can be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem or network connection) in the form of a data signal.

[0068] Connectivity 1370 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable computing device 1300 to communicate with external devices. Computing device 1300 can be a standalone device such as other computing devices, wireless access points or base stations, and peripheral devices such as headsets, printers or other devices.

[0069] Connectivity 1370 can include various different types of connectivity. Generally speaking, computing device 1300 is illustrated as having cellular connectivity 1372 and wireless connectivity 1374. Cellular connectivity 1372 generally refers to cellular network connectivity provided by a wireless carrier, such as via GSM (Global System for Mobile Communications) or variants or derivatives, CDMA (Code Division Multiple Access) or variants or derivatives, TDM (Time Division Multiplexing) or variants or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1374 refers to non-cellular wireless connectivity and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and / or wide area networks (such as WiMax) or other wireless communications.

[0070] Peripheral connection 1380 includes hardware interfaces and connectors, and software components (e.g., drivers, protocol stacks) for making peripheral connections. It will be understood that computing device 1300 can be both a peripheral device to other computing devices (“to” 1382), and also have peripheral devices connected to it (“from” 1384). Computing device 1300 typically has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on computing device 1300. Additionally, the docking connector can allow computing device 1300 to connect to certain peripheral devices that allow computing device 1300 to control content output to, for example, an audiovisual or other system.

[0071] In addition to proprietary docking connectors or other proprietary connection hardware, computing device 1300 can implement peripheral connection 1380 via common or standard-based connectors. Common types can include Universal Serial Bus (USB) connectors (which can include any of several different hardware interfaces), display ports including Mini DisplayPort (MDP), High-Definition Multimedia Interface (HDMI), FireWire, or other types.

[0072] References to "an embodiment", "one embodiment", "some embodiments" or "other embodiments" in the specification mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least some embodiments, but not necessarily in all embodiments. The various occurrences of "an embodiment", "one embodiment" or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may", "might", or "could" be included, then that particular component, feature, structure, or characteristic need not be included. If the specification or claim refers to "a" or "an" element, it does not mean that there is only one of the elements. If the specification or claim refers to "an additional" element, it does not preclude the presence of more than one additional element.

[0073] In addition, in one or more embodiments, specific features, structures, functions, or characteristics may be combined in any suitable manner. For example, wherever a particular feature, structure, function, or characteristic associated with two embodiments is not mutually exclusive, the first embodiment may be combined with the second embodiment.

[0074] Although the present disclosure has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the present disclosure are intended to cover all such alternatives, modifications, and variations as fall within the broad scope of the appended claims.

[0075] In addition, for the sake of simplicity of illustration and discussion, and so as not to obscure the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the figures presented. Also, the arrangements may be shown in block diagram form in order to avoid obscuring the present disclosure, and also in view of the fact that details regarding the implementation of such block diagram arrangements are highly dependent on the platform within which the present disclosure is to be implemented (i.e., these details should be well within the purview of those of ordinary skill in the art). In cases where specific details (e.g., circuits) are set forth in order to describe example embodiments of the present disclosure, it should be apparent to those of skill in the art that the present disclosure may be practiced with or without variation of these specific details. Accordingly, the description should be regarded as illustrative rather than restrictive.

[0076] The following examples relate to additional embodiments. The details in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[0077] In one example, a device is provided that includes: a first region over a substrate, where the first region includes a first semiconductor material having an L-valley transport band structure; a second region in contact with the first region at a junction, where the second region includes a second semiconductor material having an X-valley transport band structure, where the <111> crystal direction of one or more crystals of the first and second semiconductors is substantially orthogonal to the junction; and a metal adjacent to the second region, the metal being conductively coupled to the first region through the junction.

[0078] In some embodiments, the substrate has cubic crystallinity, and where the junction is substantially at a 45-degree angle with respect to the surface of the first region closest to the (100) plane of the substrate. In some embodiments, the substrate has cubic crystallinity, and where the junction is substantially orthogonal to the surface of the first region closest to the (110) plane of the substrate. In some embodiments, the substrate has cubic crystallinity, and where the junction is substantially parallel to the surface of the first region closest to the (111) plane of the substrate. In some embodiments, the junction includes a facet of the first semiconductor material. In some embodiments, the first semiconductor material includes germanium or indium gallium arsenide. In some embodiments, the second semiconductor material includes silicon or silicon germanium. In some embodiments, the second semiconductor material includes silicon germanium having a graded germanium concentration, the graded concentration including a germanium concentration greater than 50% near the junction.

[0079] In another example, an NMOS device is provided that includes: a channel region over a substrate, where the channel region includes a first semiconductor material having an L-valley transport band structure; a gate stack over the channel region; a source region in contact with the channel region at a junction, where the source region includes a second semiconductor material having an X-valley transport band structure, where the <111> crystal direction of one or more crystals of the first and second semiconductor materials is substantially orthogonal to the junction; and a metal adjacent to the source region, the metal being conductively coupled to the channel region through the junction.

[0080] In some embodiments, the substrate has cubic crystallinity, and where the junction is substantially at a 45-degree angle with respect to the surface of the first region closest to the (100) plane of the substrate. In some embodiments, the substrate has cubic crystallinity, and where the junction is substantially orthogonal to the surface of the first region closest to the (110) plane of the substrate. In some embodiments, the substrate has cubic crystallinity, and where the junction is substantially parallel to the surface of the first region closest to the (111) plane of the substrate. In some embodiments, the junction includes a facet of the first semiconductor material. In some embodiments, the first semiconductor material includes germanium or indium gallium arsenide. In some embodiments, the second semiconductor material includes silicon or silicon germanium. In some embodiments, the second semiconductor material includes silicon germanium having a graded germanium concentration, the graded concentration including a germanium concentration greater than 50% near the junction.

[0081] In another example, a system is provided that includes: a display subsystem; a wireless communication interface; and an integrated circuit device, the integrated circuit device including: a channel region over a substrate, wherein the channel region includes a first semiconductor material having an L-valley conduction band structure; a gate stack over the channel region; a source region contacting the channel region at a junction, wherein the source region includes a second semiconductor material having an X-valley conduction band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials is substantially orthogonal to the junction; and a metal adjacent to the source region, the metal being conductively coupled to the channel region through the junction.

[0082] In some embodiments, the substrate has cubic crystallinity, and wherein the junction is substantially at a 45-degree angle with respect to a surface of a first region of the (100) plane closest to the substrate. In some embodiments, the substrate has cubic crystallinity, and wherein the junction is substantially orthogonal to a surface of a first region of the (110) plane closest to the substrate. In some embodiments, the substrate has cubic crystallinity, and wherein the junction is substantially parallel to a surface of a first region of the (111) plane closest to the substrate. In some embodiments, the junction includes a facet of the first semiconductor material. In some embodiments, the first semiconductor material includes germanium or indium gallium arsenide. In some embodiments, the second semiconductor material includes silicon or silicon germanium. In some embodiments, the second semiconductor material includes silicon germanium having a graded germanium concentration, the graded concentration including a germanium concentration greater than 50% near the junction.

[0083] In another example, a method of forming an NMOS device is provided, the method including: receiving a substrate; epitaxially forming a first region over the substrate, wherein the first region includes a first semiconductor material having an L-valley conduction band structure; epitaxially forming a second region contacting the first region at a junction, wherein the second region includes a second semiconductor material having an X-valley conduction band structure, wherein a <111> crystal direction of one or more crystals of the first and second semiconductor materials is substantially orthogonal to the junction; and forming a metal adjacent to the second region, the metal being conductively coupled to the first region through the junction.

[0084] In some embodiments, the receiving substrate includes a receiving (100) substrate, and wherein epitaxially forming a second region in contact with the first region at the junction includes epitaxially forming the second region in contact with a (111) grown facet of the first region. In some embodiments, the receiving substrate includes a receiving (100) substrate, and wherein epitaxially forming a second region in contact with the first region at the junction includes epitaxially forming the second region in contact with a (111) etched facet of the first region. In some embodiments, the receiving substrate includes a receiving (110) substrate, and wherein epitaxially forming a second region in contact with the first region at the junction includes epitaxially forming the second region in contact with an undercut vertical sidewall of the first region. In some embodiments, the receiving substrate includes a receiving (110) substrate, and wherein epitaxially forming a second region in contact with the first region at the junction includes epitaxially forming the second region in contact with an outer vertical sidewall of a fin of the first region. In some embodiments, the receiving substrate includes a receiving (111) substrate, and wherein epitaxially forming a second region in contact with the first region at the junction includes epitaxially forming the second region in contact with an irregular etched surface of the first region. In some embodiments, epitaxially forming a first region over the substrate includes epitaxially forming germanium or indium gallium arsenide. In some embodiments, epitaxially forming a second region in contact with the first region at the junction includes epitaxially forming silicon or silicon germanium. In some embodiments, epitaxially forming a second region in contact with the first region at the junction includes epitaxially forming silicon germanium having a graded germanium concentration, the graded concentration including a germanium concentration greater than 50% near the junction.

[0085] A summary is provided that will allow the reader to determine the nature and gist of the technical disclosure. The summary is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, where each claim stands on its own as a separate embodiment.

Claims

1. An NMOS device, comprising: A channel region over a substrate, wherein the channel region comprises a first semiconductor material having an L-valley transport band structure; A gate stack over the channel region; A source region in contact with the channel region at a junction, wherein the source region comprises a second semiconductor material having an X-valley transport band structure, wherein the <111> crystal direction of one or more crystals of the first and second semiconductor materials is substantially orthogonal to the junction; and A metal adjacent to the source region, the metal being conductively coupled to the channel region through the junction, Wherein the second semiconductor material comprises silicon and germanium having a graded germanium concentration.

2. The NMOS device according to claim 1, wherein, The substrate has cubic crystallinity, and wherein the junction is substantially at a 45-degree angle with respect to the surface of the channel region of the (100) plane closest to the substrate.

3. The NMOS device according to claim 1, wherein The substrate has cubic crystallinity, and wherein the junction is substantially orthogonal to the surface of the channel region of the (110) plane closest to the substrate.

4. The NMOS device according to claim 1, wherein, The substrate has cubic crystallinity, and wherein the junction is substantially parallel to the surface of the channel region of the (111) plane closest to the substrate.

5. The NMOS device according to any one of claims 1 to 4, wherein The junction comprises a facet of the first semiconductor material.

6. The NMOS device according to any one of claims 1 to 4, wherein The first semiconductor material comprises germanium or indium gallium arsenide.

7. The NMOS device according to any one of claims 1 to 4, wherein The graded concentration comprises a germanium concentration greater than 50% near the junction.

8. A system, comprising: A display subsystem; A wireless communication interface; And An integrated circuit device, the integrated circuit device comprising: A channel region over a substrate, wherein the channel region comprises a first semiconductor material having an L-valley transport band structure; A gate stack over the channel region; A source region in contact with the channel region at a junction, wherein the source region comprises a second semiconductor material having an X-valley transport band structure, wherein the <111> crystal direction of one or more crystals of the first and second semiconductor materials is substantially orthogonal to the junction, wherein the second semiconductor material comprises silicon and germanium having a graded germanium concentration; and A metal adjacent to the source region, the metal being conductively coupled to the channel region through the junction.

9. The system according to claim 8, wherein, The substrate has cubic crystallinity, and wherein the junction is substantially at a 45-degree angle with respect to the surface of the channel region of the (100) plane closest to the substrate.

10. The system according to claim 8, wherein, The substrate has cubic crystallinity, and wherein the junction is substantially orthogonal to the surface of the channel region of the (110) plane closest to the substrate.

11. The system according to claim 8, wherein, The substrate has cubic crystallinity, and wherein the junction is substantially parallel to the surface of the channel region of the (111) plane closest to the substrate.

12. The system according to any one of claims 8 to 11, wherein, The junction comprises a facet of the first semiconductor material.

13. The system according to any one of claims 8 to 11, wherein, The first semiconductor material comprises germanium or indium gallium arsenide.

14. The system according to any one of claims 8 to 11, wherein, The graded concentration comprises a germanium concentration greater than 50% near the junction.

15. A method of forming an NMOS device, comprising: Receiving a substrate; Epitaxially forming a first region over the substrate, wherein the first region comprises a first semiconductor material having an L-valley transport band structure; Epitaxially form a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having an X-valley transport band structure, wherein the <111> crystal direction of one or more crystals of the first and second semiconductor materials is substantially orthogonal to the junction, and wherein the second semiconductor material comprises silicon and germanium having a graded germanium concentration; and Form a metal adjacent to the second region, the metal being conductively coupled to the first region through the junction.

16. The method according to claim 15, wherein, The receiving substrate comprises a receiving (100) substrate, and wherein epitaxially forming a second region in contact with the first region at a junction comprises epitaxially forming a second region in contact with a (111)-grown facet of the first region.

17. The method according to claim 15, wherein, The receiving substrate comprises a receiving (100) substrate, and wherein epitaxially forming a second region in contact with the first region at a junction comprises epitaxially forming a second region in contact with a (111)-etched facet of the first region.

18. The method according to claim 15, wherein, The receiving substrate comprises a receiving (110) substrate, and wherein epitaxially forming a second region in contact with the first region at a junction comprises epitaxially forming a second region in contact with an undercut vertical sidewall of the first region.

19. The method according to claim 15, wherein, The receiving substrate comprises a receiving (110) substrate, and wherein epitaxially forming a second region in contact with the first region at a junction comprises epitaxially forming a second region in contact with an outer vertical sidewall of a fin of the first region.

20. The method according to claim 15, wherein The receiving substrate comprises a receiving (111) substrate, and wherein epitaxially forming a second region in contact with the first region at a junction comprises epitaxially forming a second region in contact with an irregularly etched surface of the first region.

21. The method according to any one of claims 15 to 20, wherein, Epitaxially forming a first region over a substrate comprises epitaxially forming germanium or indium gallium arsenide.

22. The method according to any one of claims 15 to 20, wherein The graded concentration comprises a germanium concentration greater than 50% near the junction.

23. A computer-readable medium having instructions stored thereon that, when executed, cause a computing device to perform the method according to any one of claims 15 to 22.

24. An apparatus for forming an NMOS device, comprising: A component for receiving a substrate; A component for epitaxially forming a first region over the substrate, wherein the first region comprises a first semiconductor material having an L-valley transport band structure; A component for epitaxially forming a second region in contact with the first region at a junction, wherein the second region comprises a second semiconductor material having an X-valley transport band structure, wherein the <111> crystal direction of one or more crystals of the first and second semiconductor materials is substantially orthogonal to the junction, and wherein the second semiconductor material comprises silicon and germanium having a graded germanium concentration; and A component for forming a metal adjacent to the second region, the metal being conductively coupled to the first region through the junction.

25. The apparatus according to claim 24, wherein, The component for receiving a substrate comprises a component for receiving a (100) substrate, and wherein the component for epitaxially forming a second region in contact with the first region at a junction comprises a component for epitaxially forming a second region in contact with a (111)-grown facet of the first region.

26. The device according to claim 24, wherein The component for receiving a substrate includes a component for receiving a (100) substrate, and wherein the component for epitaxially forming a second region in contact with the first region at the junction includes a component for epitaxially forming a second region in contact with the (111) etched facet of the first region.

27. The apparatus according to claim 24, wherein, The component for receiving a substrate includes a component for receiving a (110) substrate, and wherein the component for epitaxially forming a second region in contact with the first region at the junction includes a component for epitaxially forming a second region in contact with the undercut vertical sidewall of the first region.

28. The apparatus according to claim 24, wherein The component for receiving a substrate includes a component for receiving a (110) substrate, and wherein the component for epitaxially forming a second region in contact with the first region at the junction includes a component for epitaxially forming a second region in contact with the outer vertical sidewall of the fin of the first region.

29. The apparatus according to claim 24, wherein, The component for receiving a substrate includes a component for receiving a (111) substrate, and wherein the component for epitaxially forming a second region in contact with the first region at the junction includes a component for epitaxially forming a second region in contact with the irregular etched surface of the first region.

30. The device according to any one of claims 24 to 29, wherein, The component for epitaxially forming a first region over a substrate includes a component for epitaxially forming germanium or indium gallium arsenide.

31. The apparatus according to any one of claims 24 to 29, wherein The graded concentration includes a germanium concentration greater than 50% near the junction.

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