Apparatus, methods, and systems are provided for stressed channels of transistors

Abstract

Techniques and mechanisms to apply stress on a transistor including a channel region and a source or drain region each in a fin structure. In one embodiment, a gate structure of the transistor extends over the fin structure with a first spacer portion at a sidewall of the gate structure and a second spacer portion adjoining the first spacer portion. Either or both of the two features are present at or below a respective bottom edge of the spacer portions. One of the features includes a discontinuous line on the fin structure. The other feature includes a concentration of dopants in the second spacer portion greater than a concentration of dopants in the source or drain region. In another embodiment, the fin structure is disposed on a buffer layer with stress on the channel region at least partially applied through the buffer layer.

Description

Technical Field

[0001] Embodiments of the present invention relate generally to semiconductor technology and, more particularly, but not exclusively, to stressed transistors. Background Art

[0002] In semiconductor processing, transistors are typically formed on semiconductor wafers. In CMOS (complementary metal oxide semiconductor) technology, transistors are typically one of two types: NMOS (negative channel metal oxide semiconductor) or PMOS (positive channel metal oxide semiconductor) transistors. Transistors and other devices can be interconnected to form integrated circuits (ICs) that perform a variety of useful functions.

[0003] The operation of such an IC depends, at least in part, on the performance of the transistors, which in turn can be improved by applying stress to the channel region. Specifically, the performance of an NMOS transistor is improved by providing tensile stress in its channel region, and the performance of a PMOS transistor is improved by providing compressive stress in its channel region.

[0004] A FinFET is a transistor built around a thin strip of semiconductor material, commonly called a fin. The transistor includes standard field-effect transistor (FET) nodes, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of such a device is provided outside the fin, beneath the gate dielectric. Specifically, current runs along / within both sidewalls of the fin (the sides perpendicular to the substrate surface) and along the top of the fin (the sides parallel to the substrate surface). Because the conductive channel of this configuration resides essentially along three different external planar regions of the fin, this FinFET design is sometimes referred to as a tri-gate FinFET. Other types of FinFET configurations are also available, such as the so-called dual-gate FinFET, in which the conductive channel resides primarily only along the two sidewalls of the fin (rather than along the top of the fin). There are several significant issues associated with manufacturing such fin-based transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various embodiments of the invention are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which:

[0006] Figure 1 Various views are shown illustrating elements of an integrated circuit that facilitate transistor stress according to an embodiment.

[0007] Figure 2 is a flow chart illustrating components of a method for promoting stress in a transistor channel according to an embodiment.

[0008] Figure 3A 、 3BCross-sectional views are shown, each illustrating a structure at a respective stage of a semiconductor fabrication process according to an embodiment.

[0009] Figure 4A 、 4B Cross-sectional views are shown, each illustrating a structure at a respective stage of a semiconductor fabrication process according to an embodiment.

[0010] Figure 5A 、 5B Cross-sectional views are shown, each illustrating a structure at a respective stage of a semiconductor fabrication process according to an embodiment.

[0011] Figure 6 is a functional block diagram illustrating a computing device according to one embodiment.

[0012] Figure 7 is a functional block diagram illustrating an exemplary computer system according to one embodiment. DETAILED DESCRIPTION

[0013] In various embodiments, devices and methods related to stressed transistors are described. In short, some embodiments promote channel stress in various ways to enhance the performance of one or more NMOS transistors and / or one or more PMOS transistors. However, the various embodiments may be implemented without one or more of the specific details, or with other methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention. Similarly, for purposes of explanation, specific quantities, materials, and configurations are set forth to provide a thorough understanding of some embodiments. However, some embodiments may be implemented without the specific details. Further, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0014] The technology described herein can be implemented in one or more electronic devices. Non-limiting examples of electronic devices that can utilize the technology described herein include any type of mobile and / or fixed device, such as a camera, a cellular phone, a computer terminal, a desktop computer, an e-reader, a fax machine, an information kiosk, a laptop computer, a netbook computer, a notebook computer, an Internet device, a payment terminal, a personal digital assistant, a media player and / or recorder, a server (e.g., a blade server, a rack server, a combination thereof, etc.), a set-top box, a smart phone, a tablet personal computer, an ultra-mobile personal computer, a landline telephone, and a combination thereof, etc. More generally, embodiments can be embodied in any of a variety of electronic devices that include one or more transistors containing a structure formed according to the technology described herein.

[0015] Figure 1 An integrated circuit (IC) device 100 including a structure for applying stress on a transistor is shown in perspective view according to one embodiment. Figure 1 Also shown are a cutaway perspective view 102 and a top view 104 of the IC device 100 .

[0016] IC device 100 is an example of an embodiment in which the structure of a transistor includes a signature of a manufacturing process in which a spacer structure is formed continuously on a given side of a gate electrode. Such a transistor may include a doped source or drain region of a fin structure, and a gate structure extending over the fin structure—e.g., including a gate dielectric and a gate electrode. The fin structure may be formed from a first semiconductor body that is disposed on a second semiconductor body (referred to herein as a “buffer layer”) that helps to exert stress on the transistor. The use of a doped spacer structure and / or a multi-stage doping process may alleviate the need for alternative manufacturing processes that may otherwise alleviate such stress.

[0017] In the example embodiment shown, the IC device 100 includes a buffer layer 110 having a side 112. The buffer layer 110 may include one or more epitaxial single crystalline semiconductor layers (e.g., silicon, germanium, silicon germanium, gallium arsenide, indium phosphide, gallium indium arsenide, gallium aluminum arsenide, etc.), which may, for example, be grown atop a different bulk semiconductor substrate (such as the illustrative silicon substrate 140 shown).

[0018] Although some embodiments are not limited in this regard, the buffer layer 110 may include various epitaxially grown semiconductor sublayers having different lattice constants. Such semiconductor sublayers may be used to grade the lattice constant along the z-axis of the xyz coordinate system shown. For example, the germanium concentration of the SiGe buffer layer 110 may increase from 30% germanium in the bottommost buffer layer to 70% germanium in the topmost buffer layer, thereby gradually increasing the lattice constant.

[0019] The IC device 100 may further include a first semiconductor body on the buffer layer 110, the first semiconductor body forming a fin structure (such as the illustrative fin structure 120 shown). For example, the first semiconductor body may be partially formed of an epitaxially grown single crystalline semiconductor, such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In some embodiments, the fin structure 120 may extend to the side 112. In other embodiments, the first semiconductor body may further include a lower sublayer portion from which the fin structure 120 extends (e.g., wherein the lower sublayer portion is disposed between the side 112 and the fin structure 120 and abuts each of them).

[0020] As used herein, a "source or drain region" (or alternatively, a "source / drain region") refers to a structure configured to function as either a source of a transistor or a drain of a transistor. Doped portions of the fin structure 120 may provide a source of the transistor and a drain of the transistor (such as the illustrative source / drain regions 124, 126 shown). A channel region of the transistor may be disposed between the source / drain regions 124, 126, with a gate dielectric 132 and a gate electrode 130 extending in various manners over a portion of the fin structure 120 including the channel region. For example, the source / drain regions 124, 126 may extend below laterally opposite sides of the gate electrode 130.

[0021] The source / drain regions 124, 126 and the channel region can be configured to conduct current during operation of the IC device 100, for example, current controlled by the gate electrode 130. For example, the source / drain regions 124, 126 can be disposed in source / drain wells formed with the fin structure 120. The source / drain regions 124, 126 can include any of a variety of suitable n-type dopants, such as phosphorus or arsenic. Alternatively, the source / drain regions 124, 126 can include any of a variety of suitable p-type dopants, such as boron.

[0022] The structure of the buffer layer 110 and / or the structure of the fin structure 120 can be at least partially electrically isolated from other circuit structures of the IC device 100 by an insulating structure 114 (for example). The insulating structure 114 can include silicon dioxide or any of a variety of other dielectric materials adapted according to conventional isolation techniques. The size, shape, number, and relative configuration of the insulating structure 114 are merely illustrative, and in other embodiments, the IC device 100 can include any of a variety of additional or alternative insulating structures.

[0023] The gate dielectric 132 may include a high-k gate dielectric such as hafnium oxide. In various other embodiments, the gate dielectric 132 may include hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. In another embodiment, the gate dielectric 132 includes silicon dioxide.

[0024] The gate electrode 130 can be formed of any suitable gate electrode material. In one embodiment, the gate electrode 130 comprises doped polysilicon. Alternatively or additionally, the gate electrode 130 can comprise a metal material, such as, but not limited to, tungsten, tantalum, titanium, and their nitrides. It should be appreciated that the gate electrode 130 need not necessarily be a single material, but can be a composite stack of thin films, such as, but not limited to, a polysilicon / metal electrode or a metal / polysilicon electrode.

[0025] Although some embodiments are not limited in this respect, the transistor may include multiple distinct channel regions, each channel region between source / drain regions 124, 126—for example, the multiple channel regions include one or more nanowire structures. Such one or more nanowires may be formed from any of a variety of suitable materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, InP, and carbon nanotubes.

[0026] In one embodiment, the first semiconductor body forming the fin structure 120 can have a crystal structure that is different from the crystal structure of the adjacent buffer layer 110. The mismatch (e.g., lattice constant mismatch) between the fin structure 120 and the side 112 can result in compressive stress or tensile stress being applied in the channel region between the source / drain regions 124, 126. For example, the lattice constant of the side 112 can be different from the lattice constant of the fin structure 120. In one such embodiment, one of the side 112 and the fin structure 120 includes silicon germanium having a first silicon to germanium composition ratio, wherein the other of the side 112 and the fin structure 120 includes pure silicon or includes silicon germanium having a second silicon to germanium composition ratio that is different from the first silicon to germanium composition ratio. However, in different embodiments, any of a variety of other lattice mismatches can be provided to 110 and the fin structure 120.

[0027] Conventional fabrication of non-planar transistor devices often includes an epitaxial undercut process to form recesses into which doped source / drain regions are subsequently grown. However, a significant amount of stress between the fin structure 120 and the side 112 may otherwise be relieved by this epitaxial undercut process. Various embodiments may mitigate or avoid this stress penalty through improved techniques for forming doped source / drain regions—for example, where such techniques obviate the need to cut away and replace portions of the fin structure 120.

[0028] The IC device 100 may include one or more artifacts of this improved technique—one or more artifacts including features formed by or disposed beneath a spacer structure on at least one side of the gate electrode 130. By way of illustration and not limitation, a spacer portion 152 may abut a sidewall of the gate electrode 130, with another spacer portion 150 abutting the spacer portion 152. In such an embodiment, either or both of the two features may be present in a region 154 that includes or is disposed beneath respective bottom edges of the spacer portions 150, 152. One such feature includes a discontinuous line formed on the fin structure 120 at the interface of the spacer portions 150, 152. Such a discontinuous line may be formed at least in part by the top side 122 of the fin structure 120 and / or by other structures (e.g., including the spacer portions 150, 152) disposed on the side 122. Another feature includes the spacer portion 150 and the source / drain regions 124 each having respective amounts of dopants, wherein the dopant concentration in the spacer portion 150 is greater than the dopant concentration in the source / drain regions 124 .

[0029] Alternatively or additionally, the spacer portion 162 can abut an opposing sidewall of the gate electrode 130, with another spacer portion 160 abutting the spacer portion 162. In such an embodiment, either or both of two features can be present in the illustrated region 164. One such feature includes a discontinuous line formed on the fin structure 120 at the interface of the spacer portions 160, 162. Another feature includes the spacer portion 160 and the source / drain region 124, each having a respective amount of dopant, wherein the dopant concentration in the spacer portion 160 is greater than the dopant concentration in the source / drain region 124.

[0030] Figure 2 Features of a method 200 for providing a stressed channel region of a transistor according to one embodiment are shown. The method 200 may, for example, include processes for fabricating some or all of the structures of the IC device 100. To illustrate certain features of various embodiments, reference is made herein to Figure 3A 、 3B However, in various embodiments, any of a variety of additional or alternative structures may be fabricated according to method 200.

[0031] like Figure 2 As shown in , method 200 may include forming a gate structure of a transistor at 210, wherein the gate structure extends over a fin structure disposed on a buffer layer. Figure 3AAs shown in FIG, at stage 300, a fin structure 320 may be disposed directly or indirectly on a buffer layer 315—for example, where the fin structure 320 and the buffer layer 315 functionally correspond to the fin structure 120 and the buffer layer 110, respectively. A gate dielectric 332 and a gate electrode 330 may be selectively formed in sequence, each extending at least partially around the fin structure 320. Such selective formation may include operations adapted according to conventional semiconductor fabrication techniques—for example, including masking, photolithography, deposition (e.g., chemical vapor deposition), etching, and / or other processes—which are not described in detail herein to avoid obscuring certain features of various embodiments.

[0032] Method 200 may further include, at 220, depositing a first spacer portion on the sidewalls of the gate structure. For example, as shown in stage 301, one or both of spacer portions 352, 362 may be formed—e.g., each at a respective one of two opposing sidewalls of gate electrode 330. Spacers 352, 362 may be formed by blanket deposition of a conformal dielectric film, such as, but not limited to, silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. The dielectric material of spacers 352, 362 may be deposited in a conformal manner such that the dielectric film forms substantially equal heights on vertical surfaces, such as the sidewalls of gate electrode 330. In one exemplary embodiment, the dielectric film is a silicon nitride film formed by a hot-wall low-pressure chemical vapor deposition (LPCVD) process. The deposited thickness of the dielectric film may determine the width or thickness of the formed spacers 352, 362. In one embodiment, the thickness of one of spacer portions 352, 362 may facilitate isolation of gate electrode 330 during a subsequent doping process. In one example embodiment, such a dielectric film is formed to a thickness (x-axis dimension) in the range of 0.5 nanometers (nm) to 15 nm—for example, with a thickness in the range of 0.5 nm to 5 nm, and in some embodiments, in the range of 1 nm to 3 nm.

[0033] In one embodiment, method 200 further includes: after depositing the first spacer portion, forming (at 230) a second spacer portion adjacent to the first spacer portion. Method 200 may further include, at 240, forming a source / drain region of the transistor in the fin structure. A discontinuous line may be formed on the fin structure at an interface between the first spacer portion and the second spacer portion. Alternatively or additionally, the second spacer portion and the source / drain region may each include a dopant, wherein the dopant concentration in the second spacer portion is greater than the dopant concentration in the source / drain region.

[0034] For example, forming the source / drain regions at 240 may include forming a doped layer (e.g., comprising doped epitaxially doped glass) on the fin structure, wherein the formation is performed after depositing the first spacer portion at 220. In such an embodiment, forming the source / drain regions at 240 may further include performing indiffusion from the doped layer into the fin structure (before forming the second spacer portion at 230). For example, as shown at stage 302, a layer 322 of doped epitaxial material (or alternatively, doped glass) may be conformally grown around the fin structure 320. The dopant of layer 322 may then be indiffused into the fin structure 320 during an annealing process, for example, performed at a relatively low temperature (650° C. to 800° C.) or at a higher temperature (e.g., up to 1200° C.), such as in a rapid thermal annealing (RTA) or flash annealing process. However, the range of possible annealing temperatures is not limited to some embodiments and may vary depending on implementation-specific details.

[0035] As shown in stage 304, annealing to provide in-diffusion from layer 322 can result in the formation of one or both of illustrative doped regions 324—e.g., each at a respective one of two opposing ends of gate dielectric 332 (and in some embodiments, partially underneath). For example, one or both of doped regions 324 can include any suitable n-type dopant, such as phosphorus and arsenic. Alternatively, one or both of doped regions 324 can include a p-type dopant, such as boron.

[0036] In such an embodiment, forming the second spacer portion at 230 may include, after forming one or both doped regions 324, depositing one or both of two additional spacer portions 350, 360—e.g., one on each of two opposing sides of gate electrode 330. For example, spacer portion 350 may abut spacer portion 352, and / or spacer portion 360 may abut spacer portion 362. In such an embodiment, forming the source or drain region at 240 may further include, after forming the second spacer portion at 230, and—in some embodiments—after etching to remove at least a portion of doped layer 322, performing additional doping (e.g., including ion implantation, plasma implantation, or in-diffusion) of fin structure 320. As shown in stage 305, one or both of doped regions 326 may be formed by such additional doping—e.g., where one of doped regions 326 includes one of doped regions 324 or is combined with one of doped regions 324 to form a source / drain region. In such an embodiment, one of doped regions 324 may be a tip portion of the source / drain region. In some embodiments, one or more insulating structures (not shown)—for example, including insulating structure 114 —may be formed during or after stages 300 - 305 .

[0037] The thickness of one of the spacer portions 350, 360 (along the x-axis shown)—e.g., combined with the thickness of one of the adjacent spacer portions 352, 362—can be sufficient to protect the adjacent sidewall of the gate electrode 330 from such additional doping processes. By way of illustration and not limitation, the spacer including the spacer portions 350, 352 (or including the spacer portions 360, 362) can have a thickness in the range of 0.5 nm to 10 nm.

[0038] The processing illustrated by stages 300-305 may result in a structure, referred to herein as a “discontinuity line,” extending along the width (y-axis dimension) of the fin structure 320. This discontinuity line may form a recessed edge having a height (z-axis) of at least 0.5 nm.

[0039] In an example embodiment, such a discontinuous line (e.g., at region 370) can be formed by respective bottom edges of spacer portions 350, 352—e.g., where the discontinuous line at least partially defines a recess in which the bottom side of spacer portion 352 is disposed. Alternatively or additionally, another discontinuous line can be formed by respective bottom edges of spacer portions 360, 362—e.g., where the discontinuous line at least partially defines a recess in which the bottom side of spacer portion 362 is disposed.

[0040] In alternative embodiments, some or all of the doped layer 322 can be etched away before forming the spacer portions 350, 360. In such embodiments, a different discontinuity line can instead be formed in the region 370. For example, etching away the doped layer 322 can result in an etch artifact that removes a top portion of the fin structure 320. As a result, the subsequently deposited spacer portion 350 will have a bottom edge—across the (y-axis) width of the fin structure 320—that is lower than the corresponding bottom edge of the spacer portion 352 across the width of the fin structure 320. Alternatively or additionally, the subsequently deposited spacer portion 360 will have a bottom edge—across the (y-axis) width of the fin structure 320—that is lower than the corresponding bottom edge of the spacer portion 362 across the width of the fin structure 320. Accordingly, a discontinuity line can be formed by the corresponding bottom edges of the spacer portions 350, 352—e.g., where the discontinuity line at least partially defines a recess in which the bottom side of the spacer portion 350 is disposed. Alternatively or additionally, another line of discontinuity can be formed by respective bottom edges of the spacer portions 360 , 362 —eg, where the line of discontinuity at least partially defines a recess in which the bottom side of the spacer portion 360 is disposed.

[0041] In some embodiments, forming the source / drain regions at 240 includes performing ion implantation or plasma implantation of the fin structure, wherein the implantation is performed after depositing the first spacer portion at 220 and before forming the second spacer portion at 230. For example, referring now to Figure 4A 、 4B , showing cross-sectional side views of respective stages 400 - 405 of a process for fabricating a transistor structure according to an embodiment. Figure 4A 、 4B Also shown are cross-sectional end views 400a-405a corresponding to stages 400-405, respectively.

[0042] At stage 400, a fin structure 420 may be disposed directly or indirectly on a buffer layer 415—e.g., where the fin structure 420 and the buffer layer 415 functionally correspond to the fin structure 120 and the buffer layer 110, respectively. A gate dielectric 432 and a gate electrode 430 may each extend at least partially around the fin structure 420. In some embodiments, one or both of illustrative spacer portions 452, 462 may be formed—e.g., each at a respective one of two opposing sidewalls of the gate electrode 430. The structure shown at stage 400 may, for example, include features of the corresponding structure shown at stage 301 in various ways.

[0043] At stage 401, an implant 454 can be performed on the fin structure 420—for example, as part of forming the source / drain regions at 240. Implant 454 can include an ion implantation process and / or a plasma implantation process—for example, wherein implant 454 is performed at an offset angle from the z-axis shown and dopes the fin structure 420 at least partially through its sidewalls. As shown at stage 402, a doped region 424 can be formed in the fin structure 420 via implant 454. In some embodiments, implant 454 can be corrosive to a portion of the fin structure 320. For example, one or more recesses (such as the illustrative recesses 451 and 461 shown) can be formed by removing a top portion of the fin structure 420 via implant 454. Each of the one or more recesses can extend to a respective one of the spacer portions 452 and 462—for example, wherein one end of one such recess forms a discontinuous line with the remaining portion of the fin structure 120 beneath the spacer portion. One or each of recesses 451 and 461 can, for example, have a (z-axis) height of at least 0.5 nm.

[0044] As shown in stage 403, one or more other spacer portions (such as illustrative spacer portions 450, 460) can each be formed alongside a corresponding one of spacer portions 452, 462. Spacer portion 450 and / or spacer portion 460 can be deposited, for example, by the formation at 230 of method 200. At stage 404, additional doping 456 of fin structure 420 can be performed—for example, as part of forming the source / drain regions at 240. For example, implantation 456 can include any of a variety of implantation processes or in-diffusion processes. As shown in stage 405, one or both of doped regions 426 can be formed by additional doping 456—for example, where one of doped regions 426 includes one of doped regions 424, or alternatively, forms a source / drain region in combination with one of doped regions 424. In some embodiments, one or more insulating structures (not shown) can be formed during or after stages 400-405—for example, including insulating structure 114.

[0045] At 220 of method 200, forming the second spacer portion may include, for example, depositing a doped glass material including the first dopant on the fin structure. In such an embodiment, forming the source or drain region (at 240 of method 200) may include performing an indiffusion from the doped glass material into the fin structure.

[0046] For example, now refer to Figure 5A 、 5B , showing cross-sectional side views of respective stages 500 - 503 of a process for fabricating a transistor structure according to an embodiment. Figure 5A 、 5B Also shown are cross-sectional end views 500a-503a corresponding to stages 500-503, respectively. Figure 3A 、 3B , 4A, 4B, 5A and 5B are variously shown as straight lines, but it will be appreciated that some or all such features—including, for example, horizontal top or bottom surfaces, sidewalls, corners, etc.—may be variously angled, curved, tapered, roughened, etc. in different embodiments.

[0047] At stage 500, a fin structure 520 can be disposed directly or indirectly on a buffer layer 515—e.g., where the fin structure 520 and the buffer layer 515 functionally correspond to the fin structure 120 and the buffer layer 110, respectively. A gate dielectric 532 and a gate electrode 530 can each extend at least partially around the fin structure 520. In some embodiments, one or both of illustrative spacer portions 552, 562 can be formed—e.g., each at a respective one of two opposing sidewalls of the gate electrode 530. The structure shown at stage 500 can, for example, include features of the corresponding structure shown in stage 301 in various ways.

[0048] As shown in stage 501, one or more other doped spacer portions (such as illustrative spacer portions 550, 560) can each be formed alongside a corresponding one of the spacer portions 552, 562. The doped glass material of the spacer portion 550 and / or the spacer portion 560 can be deposited, for example, by the formation at 230 of method 200. In one embodiment, the thickness of one of the spacer portions 552, 562 can facilitate isolation of the gate electrode 530 during a subsequent doping process. In one exemplary embodiment, such thickness (x-axis dimension) is in the range of 0.5 nm to 8 nm, and in some embodiments, in the range of 1 nm to 3 nm.

[0049] As shown in stage 502, doping 554 of the fin structure 520 can be performed after one or each of the spacer portions 550, 560 has been formed—for example, as part of the formation of the source / drain regions in 240. Doping 554 can include an annealing process to diffuse the dopant from one or each of the spacer portions 550, 560 into the fin structure 520. As shown in stage 503, doping 554 can form a doped region 524 (and / or a doped region 526) beneath the spacer portion 550 in the fin structure 520. In such an embodiment, the concentration of the dopant in the spacer portion 550 can be greater than the concentration of the same dopant in the doped region 524. Alternatively or additionally, the concentration of the dopant in the spacer portion 560 can be greater than the concentration of the same dopant in the doped region 526. The doped regions 524, 526 can each serve as a respective source or drain region of a transistor including the gate electrode 530.

[0050] Figure 6 A computing device 600 is illustrated, according to one embodiment. Computing device 600 houses a board 602. The integrated circuits of computing device 600 may include one or more transistors that are stressed according to the techniques described herein. Board 602 may include several components, including, but not limited to, a processor 604 and at least one communication chip 606. Processor 604 is physically and electrically coupled to board 602. In some implementations, at least one communication chip 606 is also physically and electrically coupled to board 602. In other implementations, communication chip 606 is part of processor 604.

[0051] Depending on its application, the computing device 600 may include other components that may or may not be physically and electrically coupled to the board 602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). The display device of the computing device 600 may be coupled to display an image based on one or more signals communicated with the circuit structure having the features described herein.

[0052] The communication chip 606 enables wireless communication to transfer data to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transfer data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any wires, although in some embodiments they may not. The communication chip 606 can implement any of several wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G and higher. The computing device 600 may include multiple communication chips 606. For example, the first communication chip 606 may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, while the second communication chip 606 may be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0053] The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The communication chip 606 also includes an integrated circuit die packaged within the communication chip 606.

[0054] In various implementations, computing device 600 may be a laptop computer, a netbook, a notebook, an ultrabook, a smartphone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In other implementations, computing device 600 may be any other electronic device that processes data.

[0055] Some embodiments may be provided as a computer program product or software that may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to an embodiment. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium (e.g., read-only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine-readable (e.g., computer-readable) transmission medium (electrical, optical, acoustic, or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

[0056] Figure 7 A diagrammatic representation of a machine in the exemplary form of a computer system 700 is illustrated within which a set of instructions for causing the machine to perform any one or more of the methodologies described herein may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The machine may operate as a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a World Wide Web appliance, a server, a network router, a switch, or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specifies actions to be taken by the machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to encompass any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

[0057] The exemplary computing system 700 includes a processor 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 718 (e.g., a data storage device), which communicate with each other via a bus 730.

[0058] The processor 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processor 702 may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computer (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements another instruction set or a combination of instruction sets. The processor 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processor 702 is configured to execute processing logic 726 for performing the operations described herein.

[0059] The computing system 700 may further include a network interface device 708. The computing system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), and a signal generating device 716 (e.g., a speaker). The video display unit 710 may be coupled to display an image based on one or more signals communicated with the circuit structures having the features described herein.

[0060] The secondary memory 718 may include a machine-accessible storage medium (or more specifically, a computer-readable storage medium) 732 on which is stored one or more sets of instructions (e.g., software 722) that implement any one or more of the methodologies or functionality described herein. The software 722 may also reside, completely or at least partially, within the main memory 704 and / or processor 702 during its execution by the computer system 700, with the main memory 704 and processor 702 also constituting machine-readable storage media. The software 722 may also be transmitted or received over the network 720 via the network interface device 708.

[0061] Although the machine-accessible storage medium 732 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" will also be taken to include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more embodiments. The term "machine-readable storage medium" should therefore be taken to include, but is not limited to, solid-state memories and optical and magnetic media.

[0062] In one implementation, an integrated circuit (IC) device includes: a buffer layer comprising a semiconductor lattice; a fin structure disposed on the buffer layer, the fin structure comprising a channel region of a transistor and a source or drain region of the transistor, wherein stress is applied to the channel region through the buffer layer; a gate structure of the transistor, wherein the gate structure extends over the fin structure; a first spacer portion disposed on a sidewall of the gate structure; and a second spacer portion adjacent to the first spacer portion. A discontinuity line is formed on the fin structure at an interface between the first spacer portion and the second spacer portion; or the second spacer portion and the source or drain region each include a dopant, wherein a dopant concentration in the second spacer portion is greater than a dopant concentration in the source or drain region.

[0063] In one embodiment, the discontinuous line is formed on the surface of the fin structure, wherein the discontinuous line at least partially defines a recessed portion below the first spacer portion. In another embodiment, the discontinuous line is formed on the surface of the fin structure, wherein the discontinuous line at least partially defines a recessed portion below the second spacer portion. In another embodiment, the dopant concentration in the second spacer portion is greater than the dopant concentration in the source or drain region, and the discontinuous line is formed on the fin structure at the interface.

[0064] In another embodiment, the discontinuity line is formed on the fin structure at the interface of the first spacer portion and the second spacer portion, or the dopant concentration in the second spacer portion is greater than the dopant concentration in the source or drain region. In another embodiment, one of the buffer layer and the fin structure includes silicon germanium having a first silicon to germanium composition ratio, the first silicon to germanium composition ratio being different from a second silicon to germanium composition ratio of the other of the buffer layer and the fin structure. In another embodiment, the discontinuity line forms an edge of a recess, wherein the height of the recess is at least 0.5 nanometers. In another embodiment, the total thickness of the first spacer portion and the second spacer portion is in a range of 0.5 nanometers (nm) to 15 nm.

[0065] In another embodiment, a method includes forming a gate structure of a transistor, wherein the gate structure extends over a fin structure disposed on a buffer layer comprising a semiconductor lattice; depositing a first spacer portion on sidewalls of the gate structure; forming a second spacer portion adjacent to the first spacer portion after depositing the first spacer portion; and forming a source or drain region of the transistor in the fin structure. Stress is applied to a channel region of the transistor through the buffer layer, wherein a discontinuity is formed in the fin structure at an interface between the first spacer portion and the second spacer portion; or the second spacer portion and the source or drain region each include a dopant, wherein a concentration of the dopant in the second spacer portion is greater than a concentration of the dopant in the source or drain region.

[0066] In one embodiment, forming the source or drain region includes: forming a doped epitaxial layer on the fin structure after depositing the first spacer portion; and performing an indiffusion from the doped epitaxial layer into the fin structure. In another embodiment, forming the source or drain region includes: depositing a doped glass material on the fin structure after forming the first spacer portion; and performing an indiffusion from the doped glass material into the fin structure. In another embodiment, the dopant concentration in the second spacer portion is greater than the dopant concentration in the source or drain region, and wherein forming the source or drain region includes performing an indiffusion from the doped material into the fin structure. In another embodiment, forming the source or drain region also includes: forming a doped layer on the fin structure after depositing the first spacer portion; and performing an indiffusion from the doped layer into the fin structure before forming the second spacer portion.

[0067] In another embodiment, forming the source or drain region comprises performing an ion implantation of the fin structure after forming the first spacer portion and before forming the second spacer portion. In another embodiment, forming the source or drain region comprises performing a plasma implantation of the fin structure after forming the first spacer portion and before forming the second spacer portion. In another embodiment, one of the buffer layer and the fin structure comprises silicon germanium having a first silicon to germanium composition ratio that is different from a second silicon to germanium composition ratio of the other of the buffer layer and the fin structure. In another embodiment, the discontinuity forms an edge of a recess, wherein the height of the recess is at least 0.5 nanometers. In another embodiment, the total thickness of the first spacer portion and the second spacer portion is in a range of 0.5 nanometers (nm) to 15 nm.

[0068] In another embodiment, a system includes an integrated circuit (IC) device comprising: a buffer layer comprising a semiconductor lattice; a fin structure disposed on the buffer layer, the fin structure comprising a channel region of a transistor and a source or drain region of the transistor, wherein stress is applied to the channel region through the buffer layer; a gate structure of the transistor, wherein the gate structure extends over the fin structure; a first spacer portion disposed on a sidewall of the gate structure; and a second spacer portion adjacent to the first spacer portion. A discontinuous line is formed on the fin structure at an interface between the first spacer portion and the second spacer portion; or the second spacer portion and the source or drain region each comprise a dopant, wherein a dopant concentration in the second spacer portion is greater than a dopant concentration in the source or drain region. The system further includes a display device coupled to the IC device, the display device displaying an image based on a signal communicated with the IC device.

[0069] In one embodiment, the discontinuous line is formed on the surface of the fin structure, wherein the discontinuous line at least partially defines a recessed portion below the first spacer portion. In another embodiment, the discontinuous line is formed on the surface of the fin structure, wherein the discontinuous line at least partially defines a recessed portion below the second spacer portion. In another embodiment, the dopant concentration in the second spacer portion is greater than the dopant concentration in the source or drain region, and the discontinuous line is formed on the fin structure at the interface.

[0070] In another embodiment, the discontinuity line is formed on the fin structure at the interface of the first spacer portion and the second spacer portion, or the dopant concentration in the second spacer portion is greater than the dopant concentration in the source or drain region. In another embodiment, one of the buffer layer and the fin structure includes silicon germanium having a first silicon to germanium composition ratio, the first silicon to germanium composition ratio being different from a second silicon to germanium composition ratio of the other of the buffer layer and the fin structure. In another embodiment, the discontinuity line forms an edge of a recess, wherein the height of the recess is at least 0.5 nanometers. In another embodiment, the total thickness of the first spacer portion and the second spacer portion is in a range of 0.5 nanometers (nm) to 15 nm.

[0071] This document describes techniques and architectures for promoting stress in transistors. In the above description, for illustrative purposes, numerous specific details are set forth to provide a thorough understanding of certain embodiments. However, it will be apparent to those skilled in the art that certain embodiments can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form to avoid obscuring the description.

[0072] References in the specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment.

[0073] Some parts of the detailed description herein are presented in terms of symbolic representations and algorithms for the operations of the data bits in a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of computing most effectively convey the essence of their work to those skilled in the art. An algorithm is herein and generally considered to be a self-consistent sequence of steps for obtaining a desired result. These steps are steps requiring the physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated. Mainly for reasons of common use, it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0074] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise stated, it will be apparent from the discussion herein that discussions throughout the specification utilizing terms such as "process" or "calculate" or "calculate" or "determine" or "display" refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage, transmission, or display devices.

[0075] Certain embodiments also relate to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the required purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a computer-readable storage medium, such as, but not limited to, any type of disk including: a floppy disk, an optical disk, a CD-ROM, and magneto-optical disk, a read-only memory (ROM), a random access memory (RAM) such as dynamic RAM (DRAM), an EPROM, an EEPROM, a magnetic or optical card, or any type of medium suitable for storing electrical instructions and coupled to a computer system bus.

[0076] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may prove convenient to construct more specialized equipment to perform the required method steps. The desired structure of various such systems will become apparent from the description herein. In addition, certain embodiments are described without reference to any particular programming language. It will be appreciated that various programming languages ​​may be used to implement the teachings of such embodiments described herein.

[0077] In addition to what is described herein, various modifications may be made to the disclosed embodiments and their implementations without departing from the scope thereof. Therefore, the illustrations and examples herein should be considered illustrative rather than restrictive. The scope of the present invention should be measured solely by reference to the following claims.

Claims

1. An integrated circuit (IC) device for providing an electrical signal, the IC device comprising: a buffer layer comprising a semiconductor lattice; A fin structure extending from the buffer layer along a first dimension, the fin structure comprising: a channel region of a transistor, wherein stress is exerted on the channel region through the buffer layer; and a doped source or drain region of the transistor, wherein the doped source or drain region extends to a surface of the fin structure; a gate structure of the transistor, wherein the gate structure extends over the fin structure; a first spacer portion disposed on a sidewall of the gate structure; a second spacer portion adjacent to the first spacer portion; and a residual doped layer portion on a surface of the fin structure, wherein, along a first line in the first dimension, the residual doped layer portion is located between the second spacer portion and the doped source or drain region and is adjacent to each of the second spacer portion and the doped source or drain region; wherein the first spacer portion extends along a second line in the first dimension, passing through a bottom of the second spacer portion and along the residual doped layer portion to be adjacent to the doped source or drain region at the surface of the fin structure; and Wherein, at the surface of the fin structure, the doped source or drain region is away from the first spacer portion and extends along a third line direction in a second dimension orthogonal to the first dimension, under the residual doped layer portion, and then passes through the edge of the residual doped layer portion.

2. The IC device of claim 1 , wherein one of the buffer layer and the fin structure comprises silicon germanium having a first silicon to germanium composition ratio that is different from a second silicon to germanium composition ratio of the other of the buffer layer and the fin structure.

3. The IC device of claim 1, wherein respective bottom edges of the first spacer portion and the second spacer portion form edges of a recess, wherein a height of the recess is at least 0.5 nanometers.

4. The IC device of claim 1, wherein a total thickness of the first spacer portion and the second spacer portion is in a range of 0.5 nanometers (nm) to 15 nm.

5. A method for manufacturing an integrated circuit, the method comprising: forming a gate structure of a transistor, wherein the gate structure extends from a fin structure extending along a first dimension from a buffer layer comprising a semiconductor lattice; depositing a first spacer portion on a sidewall of the gate structure; forming a doped layer on the fin structure after depositing the first spacer portion, wherein the first spacer portion extends to a surface of the fin structure; After forming the doping layer on the fin structure, forming a second spacer portion adjacent to the first spacer portion; performing an in-diffusion from the doped layer into the fin structure to form a source or drain region of the transistor, wherein the doped source or drain region extends to a surface of the fin structure; as well as After performing the inner diffusion, performing etching to remove a portion of the doped layer to expose the source or drain region; wherein, after the etching: a residual second portion of the doped layer remaining on the fin structure, wherein, along a first line in the first dimension, the residual doped layer portion is between the second spacer portion and the doped source or drain region and adjacent to each of the second spacer portion and the doped source or drain region; The first spacer portion extends along a second line in the first dimension, past a bottom of the second spacer portion and along the residual doped layer portion to abut the doped source or drain region at a surface of the fin structure; and Stress is applied to the channel region of the transistor through the buffer layer. The method of claim 5 , wherein forming the doped layer on the fin structure comprises forming a doped epitaxial layer. 7 . The method of claim 5 , wherein forming the doped layer on the fin structure comprises depositing a doped glass material on the fin structure.

8. The method of claim 5, wherein one of the buffer layer and the fin structure comprises silicon germanium having a first silicon to germanium composition ratio that is different from a second silicon to germanium composition ratio of the other of the buffer layer and the fin structure.

9. The method of claim 5, wherein respective bottom edges of the first spacer portion and the second spacer portion form edges of a recess, wherein a height of the recess is at least 0.5 nanometers.

10. The method of claim 5, wherein a total thickness of the first spacer portion and the second spacer portion is in a range of 0.5 nanometers (nm) to 15 nm.

11. A system for providing an electrical signal, the system comprising: An integrated circuit IC device, the integrated circuit IC device comprising: a buffer layer comprising a semiconductor lattice; A fin structure extending from the buffer layer along a first dimension, the fin structure comprising: a channel region of a transistor, wherein stress is exerted on the channel region through the buffer layer; and a doped source or drain region of the transistor, wherein the doped source or drain region extends to a surface of the fin structure; a gate structure of the transistor, wherein the gate structure extends over the fin structure; a first spacer portion disposed on a sidewall of the gate structure; a second spacer portion adjacent to the first spacer portion; and a residual doped layer portion on a surface of the fin structure, wherein, along a first line in the first dimension, the residual doped layer portion is located between the second spacer portion and the doped source or drain region and is adjacent to each of the second spacer portion and the doped source or drain region; wherein the first spacer portion extends along a second line in the first dimension, passing through a bottom of the second spacer portion and along the residual doped layer portion to be adjacent to the doped source or drain region at the surface of the fin structure; and wherein, at the surface of the fin structure, the doped source or drain region is away from the first spacer portion and extends along a third line direction in a second dimension orthogonal to the first dimension, under the residual doped layer portion, and then passes through the edge of the residual doped layer portion; and a display device coupled to the IC device, the display device displaying an image based on a signal communicated with the IC device.

12. The system of claim 11, wherein one of the buffer layer and the fin structure comprises silicon germanium having a first silicon to germanium composition ratio that is different from a second silicon to germanium composition ratio of the other of the buffer layer and the fin structure.

13. The system of claim 11, wherein respective bottom edges of the first and second spacer portions form edges of a recess, wherein a height of the recess is at least 0.5 nanometers.

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