Embedded industrial control motherboard and video testing method

Abstract

The invention relates to an embedded industrial control mainboard and a video testing method, comprising at least one group of industrial control chips distributed in a 2-by-2 matrix; the industrial control chips comprise an upper left chip P1, an upper right chip P2, a lower left chip P3 and a lower right chip P4; in the upper left chip P1, a terminal V23PI10 is connected to a terminal W22PI5 through a resistor R14; a terminal W24PI7 is connected to a terminal Y23PI4 through a resistor R15; a terminal W23PI6 is connected to a terminal V22PI9 through a resistor R16; a terminal W20PI8 is connected to a terminal E23PH1 through a resistor R17; a terminal AB23PG10 is connected to a terminal AC24PG9 through a resistor R19; and a terminal AB24PG11 is connected to a terminal AD23PG7 through a resistor R21; the invention improves a mainboard with a good testing method, and the invention has reasonable design, compact structure and convenient use.

Description

Technical Field

[0001] The invention relates to an embedded industrial control mainboard and a video testing method. Background Art

[0002] The core board is an electronic motherboard that packages the core functions of the MINI PC. Most core boards integrate CPU, storage devices and pins, and are connected to the matching baseboard through pins to realize a system chip in a certain field. People often call such a system a single-chip microcomputer, or an embedded development platform. Because the core board integrates the core's general functions, it has the versatility of a core board that can customize various baseboards, which greatly improves the development efficiency of the single-chip microcomputer. Because the core board is separated as an independent module, it also reduces the difficulty of development and increases the stability and maintainability of the system.

[0003] Industrial computer motherboards are designed for industrial applications. They must adapt to harsh environments and high-load work. Their main features are long life, moisture resistance, high temperature resistance and durability. In addition to the different use environments and working temperatures, ordinary PC motherboards and industrial computer motherboards differ in specifications, dimensions, components, interface design, materials, and manufacturing. Industrial motherboards require special customization to ensure reliability and stability. 1. Specifications and dimensions. Unlike the single architecture of ordinary PC motherboards, industrial motherboards have multiple specifications to adapt to a variety of application environments. 2. Support for expansion slots and the use of components. From the appearance point of view, the biggest difference between industrial motherboards and PC motherboards is that industrial motherboards have more interfaces. Industrial motherboards require more external devices due to the particularity of their use locations. In order to ensure the long-term use of products in harsh environments, industrial boards have higher requirements for components. 3. Life cycle. The common PC computers on our market are updated very quickly, while in the industrial market, industrial motherboards have a longer life cycle. 4. Product reliability. Industrial-grade motherboards are targeted at the industrial market. Due to the need for reliability, each motherboard will undergo more industrial and required certifications than ordinary PC motherboards before it is launched. 5. Market size and customization. Commercial PC motherboards are mass-produced according to market demand and scale-unified design. The market size is larger, while industrial control motherboards are generally suitable for industrial control equipment, such as GPS navigation, smart retail machines, face recognition and other high-precision scenarios. Therefore, the market size is relatively small, but they can be flexibly customized according to the special needs of customers to better cooperate with customers. Therefore, in terms of price, the cost of industrial control motherboards is relatively high. Summary of the invention

[0004] The technical problem to be solved by the present invention is generally to provide an embedded industrial control mainboard and a video testing method.

[0005] To solve the above problems, the technical solution adopted by the present invention is:

[0006] An embedded industrial control mainboard comprises at least one group of industrial control chips distributed in a 2-by-2 matrix; the industrial control chips comprise an upper left chip P1, an upper right chip P2, a lower left chip P3 and a lower right chip P4; in the upper left chip P1, terminal V23PI10 is connected to terminal W22PI5 via a resistor R14; terminal W24PI7 is connected to terminal Y23PI4 via a resistor R15; terminal W23PI6 is connected to terminal V22PI9 via a resistor R16; terminal W20PI8 is connected to terminal E23PH1 via a resistor R17; terminal AB23PG10 is connected to terminal AC24PG9 via a resistor R19; terminal AB24PG11 is connected to terminal AD23PG7 via a resistor R21; the present invention provides a mainboard with a good testing method, which is reasonably designed, low in cost, strong and durable, safe and reliable, simple to operate, time-saving, labor-saving, money-saving, compact in structure and easy to use. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a flow chart of the present invention.

[0008] Figure 2 It is a structural schematic diagram of the substrate arrangement of the present invention.

[0009] Figure 3 It is a schematic diagram of the structure of the test display of the present invention.

[0010] Figure 4-30 It is a partial block diagram of the present invention. DETAILED DESCRIPTION

[0011] As shown in all the figures, an embedded industrial control motherboard includes at least one group of industrial control chips distributed in a 2 by 2 matrix; the industrial control chips include an upper left chip P1, an upper right chip P2, a lower left chip P3, and a lower right chip P4; in the upper left chip P1, terminal V23PI10 is connected to terminal W22PI5 through resistor R14; terminal W24PI7 is connected to terminal Y23PI4 through resistor R15; terminal W23PI6 is connected to terminal V22PI9 through resistor R16; terminal W20PI8 is connected to terminal E23PH1 through resistor R17; terminal AB23PG10 is connected to terminal AC24PG9 through resistor R19; terminal AB24PG11 is connected to terminal AD23PG7 through resistor R21; terminal AC23PG8 ...5 through resistor R14; terminal W24PI7 is connected to terminal Y23PI4 through resistor R15; terminal W23PI6 is connected to terminal V22PI9 through resistor R16; terminal W20PI8 is connected to terminal E23PH1 through resistor R17 Resistor R23 is connected to terminal AD22PG6; terminal AB21PG2 is connected to terminal AC22PG5 through resistor R25; terminal Y20PG1 is connected to terminal AB22PG4 through resistor R29; terminal AA20PG0 is connected to terminal AC21PG3 through resistor R31; terminal USBVBUS is connected to power supply VCC through resistor R98; terminal PWRON is grounded through parallel contact switch K2 and capacitor C47; terminal TS is grounded through resistor R11; power supply VCC is connected to resistor R38, LED lamp D2 is connected to terminal U22PI15; power supply VCC is connected to resistor R13, LED lamp D1 is connected to terminal CHGLED; terminal D22PH12 is connected to terminal W19PE3 through resistor R20; terminal K21PB6 Connect terminal J20PB7 through resistor R22; connect terminal W17PE2 through resistor R18 to terminal AB20PE10; connect terminal AC20PE11 through resistor R24 ​​to terminal Y17PE1; connect terminal AD20PE9 to base of transistor Q4 through resistor R136, connect resistor R137 between base and emitter of transistor Q4; connect collector of transistor Q4 to G pole of MOS field effect transistor Q3, connect resistor R135 between G pole and S pole of MOS field effect transistor Q3, connect D pole of MOS field effect transistor Q3 to ground through series diodes D8, D9 and LED diode D10; connect S pole of MOS field effect transistor Q3 to output power supply; connect terminal AA17PE0 to terminal Y19PE4 through resistor R32; Sub AD19PE8 is connected to terminal AA19PE5 through resistor R30; terminal AC19PE7 is connected to terminal Y22PI3 through resistor R26; terminal AB19PE6 is connected to terminal AA23PI1 through resistor R34; terminal AA22PI0 is connected to terminal AA24PI2 through resistor R37; terminal PWRON is grounded through parallel contact switch K2 and capacitor C47; terminal ACIN is connected to four paths, the first path is connected to chip U5 pin 4 through resistor R118, and the second path is connected to chip U5 pins 1-3; the third path is grounded through parallel capacitors C36-38 and voltage regulator D5, and the fourth path fuse F1 is connected to integrated circuit P17; integrated circuit P17 is externally connected to socket P12; terminal VBAT is grounded through LED diode D10;In the upper right chip P2, terminal D18PH17 is connected to terminal C23PH4 through resistor R1; terminal U23PI14 is connected to terminal G20PB13 through resistor R2; terminal USB0P is connected to terminal USB1P through resistor R6; terminal USB0N is connected to terminal USB1N through resistor R7; terminal J21PB8 is connected to terminal D19PH21 through resistor R5; terminal D23PH0 is connected to terminal DNPK20PB5 through resistor R39; power supply VCC is connected to resistor R10, LED lamp D7 is connected to terminal J23PB10; in the lower left chip P3, terminal T21PI20 is connected to terminal N19PA12 through resistor R48; terminal R23PI21 is connected to terminal E22PH3 through resistor R50; Terminal B24PH6 is connected to terminal G17PH22 through resistor R52; terminal B22PH7 is connected to terminal F18PH20 through resistor R54; terminal N20PA11 is connected to terminal L23PA0 through resistor R56; terminal N22PA9 is connected to terminal M19PA1 through resistor R57; terminal R22PA15 is connected to terminal M22PA3 through resistor R58; terminal N21PA10 is connected to terminal M23PA2 through resistor R59; terminal N23PA8 is connected to terminal R21PA16 through resistor R62; terminal P22PA14 is connected to terminal M24PA6 through resistor R64; terminal N24PA7 is connected to terminal M21PA4 through resistor R66; terminal P23PA13 is connected to terminal M23PA3 through resistor R67 7 is connected to terminal M20PA5; terminal R20PA17 is connected to terminal D24PH2 through resistor R68; power supply VCC is connected to resistor R27, LED lamp D3 is connected to terminal C24PH5; terminal G23PB18 is connected to terminal F24PB20 through resistor R40; terminal J24PB4 is connected to terminal T24PI18 through resistor R41; terminal U18PI12 is connected to terminal T23PI17 through resistor R42; terminal T19PI16 is connected to terminal T22PI19 through resistor R43; terminal E18PH25 is connected to terminal A18PH26 through resistor R44; terminal F21PB21 is connected to terminal G24PB19 through resistor R45; terminal E19PH19 is connected to terminal C1 through resistor R46 8PH18; terminal D21PH16 is connected to terminal C22PH13 through resistor R47; terminal A21PH15 is connected to terminal B18PH24 through resistor R49; terminal B19PH27 is connected to terminal B21PH14 through resistor R51; terminal B23PH8 is connected to terminal C19PH23 through resistor R53; terminal J22PB9 is connected to terminal K23PB2 through resistor R69; switch S2 is electrically connected between terminals BOOT1 and BOOT2; terminal RESET is grounded through parallel contact switch K3 and capacitor C48; in the lower right chip P4, terminal U1PD21 is connected to terminal R4PD19 through resistor R60; terminal U6PD27 is connected to terminal T4PD24 through resistor R61;Terminal T3PD23 is connected to terminal T5PD25 through resistor R63; terminal U5PD26 is connected to terminal U2PD22 through resistor R65; terminal M4PD13 is connected to terminal A23PH9 through resistor R71; terminal R5PD18 is connected to terminal T2PD20 through resistor R72; terminal N4PD15 is connected to terminal P5PD16 through resistor R73; terminal N3PD14 is connected to terminal P4PD17 through resistor R74; terminal R2PD8 is connected to terminal L5PD10 through resistor R75; terminal R1PD6 is connected to terminal M1PD1 through resistor R76; terminal R3PD9 is connected to terminal L4PD11 through resistor R77; terminal P2PD5 is connected to terminal M3PD3 through resistor R78; terminal M2PD0 is connected to terminal P3PD7 through resistor R79; terminal Sub-P1PD4 is connected to terminal N2PD2 through resistor R80; terminal L3PD12 is connected to terminal A22PH10 through resistor R94; a TV0 circuit is connected between terminal TVIN0 and terminal TVOUT0; in the TV0 circuit, terminal TVIN0 is grounded through capacitor C20 and outputs two paths through inductor L1, one path is grounded through capacitor C54, and the other path is electrically connected to capacitor C10 through a series resistor R104, and the TV0 circuit is grounded through resistor R120 and connected to capacitor C10; a TV1 circuit is connected between terminal TVIN1 and terminal TVOUT1; a TV2 circuit is connected between terminal TVIN2 and terminal TVOUT2; a TV3 circuit is connected between terminal TVIN3 and terminal TVOUT3; TV0-3 circuits are the same. It also includes a display driver chip P5 connected through a MIPI-DSI protocol interface, wherein ports K24MIPIDSIPWM, C21MIPIDSIEN, MIPIDSICKP, MIPIDSICKN, MIPIDSID3P, MIPIDSID3N, MIPIDSID2P, MIPIDSID2N, MIPIDSID1P, MIPIDSID1N, MIPIDSID0P, and MIPIDSID0N are respectively connected to corresponding ports of the lower right chip P4; it also includes an HDMI chip U1, wherein the power supply VCC is supplied to the HDMI chip through parallel resistors R84-R87 and capacitor C5. The chip power input terminals HDMISDA, HDMIHPD, HDMISCL, HDMICEC, HDMICLKN, HDMICLKP, HDMITX0-2N, and HDMITX0-2P are connected to the corresponding ports of the upper right chip P2; the output terminal HPDETOUT is connected to the HDMI chip P8 terminal HOT-PLUG-DET; the output terminal HDMIDDCDATOUT is connected to the HDMI chip P8 terminal 12C-DATA; the output terminal HDMICECOUT is connected to the HDMI chip P8 terminal 12C-CLK; the output terminal HDMICECOUT is connected to the power supply VCC through the resistor R97 and the voltage regulator D4;The output terminal HDMICLK is connected to the terminal CK of the HDMI chip P8; the output terminal HDMITX is connected to the terminal D of the HDMI chip P8; the hard disk chip P6 is also connected; the terminals SATATX and SATARX are connected to the corresponding ports of the upper right chip P2; the touch module chip U4 is also connected; among them, the terminal C is connected to the terminal G19PB12 of the upper right chip P2, the terminal TPX is connected to the resistor R90 and then divided into two paths, one is connected to the terminal TPX1 of the upper right chip P2 through the resistor R89, and the other is connected to the terminal TPX2 of the upper right chip P2 through the resistor R91; the terminal TPY is connected to two paths, one is connected to the terminal TPY1 of the upper right chip P2 through the resistor R92, and the other is connected to the terminal TPY2 of the upper right chip P2 through the resistor R93; the language module U2 is connected; among them, the terminal SHDN is connected to the terminal K20SPKSHDN of the lower right chip P4; the terminal INN is connected to the terminal PHONEOUT N of the lower right chip P4 through the resistor R36 and the capacitor C70; the terminal INP is connected to the terminal PHONEOUT of the lower right chip P4 through the resistor R96 and the capacitor C71 P; terminals VOP and VON are connected to plug P18SPK through the filter module, which is connected to the audio module; among them, terminals HPCOMFB and HPCOM of the upper right chip P2 are grounded through their respective capacitors; terminal HPOUTR / L of the upper right chip P2 is connected to LINEINR / L of the upper right chip P2 through a polarity capacitor; audio green phone module is connected to terminal HPDETR105; one path of the audio green phone module is grounded through a resistor, and the other path is grounded through a series resistor and capacitor; a call module is connected; among them, terminal PHONEOUTN of the upper right chip P2 is grounded through capacitor C33; terminal PHONEOUTP of the upper right chip P2 is divided into two paths after passing through capacitor C31 and resistor R107 in series, one path is grounded after passing through resistor R112 and capacitor C35 in series and resistor R110, and the other path is connected to Audio Blue PHONE module; Audio Blue The PHONE module is electrically connected to the K20PB5 corresponding to the terminal K20SPKSHDN through the resistor R103; a microphone module is connected to the substrate; wherein, the terminal MICIN1 of the upper right chip P2 is connected to the terminal MICL through the capacitor C27, and the terminal MICL is grounded through the capacitor C28; the terminal MICIN2 of the upper right chip P2 is connected to the terminal MICR through the capacitor C29, and the terminal MICR is grounded through the capacitor C30; the terminal VMIC of the upper right chip P2 is respectively connected to the terminal MICL and the terminal MICR through the filter circuit, and the resistors MICRFB1, R109, and MICRFB2 are electrically connected between the terminals HPOUTR and HPOUTRL of the Audio Pink MIC module; a communication chip U6 is connected to the substrate; a capacitor is electrically connected between the terminal pins C+ and C-; the terminal pin TIOUT is connected to the terminal RS232TX; the terminal pin R1IN is connected to the terminal RS232RX;The terminal pin TIIN is connected to the lower left chip P3 terminal F22UART0TX; the terminal pin R1OUT is connected to the lower left chip P3 terminal F22UART0RX; the terminal RS232TX / RX is connected to the plug-in board P15; the industrial control chip is a Feiling chip; the hard disk chip P6 is grounded through a diode bridge; a voltage regulator and an SDCARD module are set on the substrate; the terminal pin P14 of the SDCARD module chip is connected to the corresponding terminal of the upper right chip P2; the terminal pin DAT2 is connected to W13SDC0D2; the terminal pin CD / DAT3 is connected to Y13SDC0D3; the terminal pin CMD is connected to AA 13SDC0CMD; terminal CLK is connected to W11SDC0CLK through resistor R133; terminal DAT0 is connected to Y11SDC0D0; terminal DAT1 is connected to AA11SDC0D1; terminal DAT0 is connected to V24SDC0DET; a USB chip U7 is arranged on the substrate, wherein, in the USB chip U7, terminal D- is connected to terminal USB2N of the upper right chip P2, terminal D+ is connected to terminal USB2P of the upper right chip P2, terminal RXD1 is connected to socket P16, terminal TXD1 is connected to socket P16, and socket P16 is connected to the lower left chip P3 Terminal F22UABT0TX, socket P16 is connected to the lower left chip P3 terminal F23UABT0RX, a memory chip U9 is arranged on the substrate, the terminal pin CS# is connected to the upper left chip P1 terminal AB17PC23; the terminal pin DO (IO1) is connected to the upper left chip P1 terminal AC10PC1; the terminal pin CLK is connected to the upper left chip P1 terminal AD10PC2; the terminal pin DI (IO0) is connected to the upper left chip P1 terminal AB11PC0; a flash memory chip U10 is arranged on the substrate, the terminal pin CS# is connected to the upper left chip P1 terminal AA16PC19; the terminal pin DO (IO1) is connected to the upper left chip P1 terminal Y16PC22; the terminal CLK is connected to the upper left chip P1 terminal AB19PC20; the terminal DI (IO0) is connected to the upper left chip P1 terminal AA14PC21; the upper right chip P2 terminal KEYADC0 is grounded through the capacitor C64 and the resistor R33, and the resistor R33 is grounded to the electric shock switch K1 through the parallel resistor R95; the upper right chip P2 terminal KEYADC1 is grounded through the capacitor C65 and the resistor R70, and the resistor R70 is grounded to the electric shock switch K4 through the parallel resistor R141. Input a 3-color image into the tvouti (i=0, 1, 2, 3) controller, and turn off other tvoutj (j≠i) controllers. When the camera display is started, the code is implemented as follows. cd / sys / class / sunxi_dump / / / Write register path;

[0012] echo 01c90028 0x82714201>write / / Turn on the sending mode of tvouti.

[0013] echo 01c90048 0x82714200>write / / Turn off the sending mode of tvoutj≠i.

[0014] echo 01c90068 0x82714200>write / / Turn off the sending mode of tvoutk≠i.

[0015] echo 01c90088 0x82714200>write / / Turn off the sending mode of tvoutm≠i.

[0016] echo 01c94004 0x07070103>write / / Input three-color image.

[0017] A video testing method for an embedded industrial control motherboard, firstly, building an embedded industrial control motherboard;

[0018] Then, short-circuit tvout and tvin; secondly, input a 3-color image to tvout0 and turn off other tvout controllers;

[0019] Again, from tvout output to the corresponding input of tvin, the code is implemented as follows;

[0020] cd / sys / class / sunxi_dump / / / Write register path

[0021] echo 01c90028 0x82714201>write / / Turn on the sending mode of tvout0.

[0022] echo 01c90048 0x82714200>write / / Turn off the sending mode of tvout1.

[0023] echo 01c90068 0x82714200>write / / Turn off the sending mode of tvout2.

[0024] echo 01c90088 0x82714200>write / / Turn off the sending mode of tvout3.

[0025] echo 01c94004 0x07070103>write / / Input three-color image

[0026] Next, start the camera and display it on the LCD screen;

[0027] Afterwards, three-color images are input into tvouti=i+1 (i=0, i≤2) one by one, and other tvout controllers are turned off for testing.

[0028] When testing the core board, it is necessary to check whether several tvin pins and tvout pins are short-circuited / open-circuited or have cold solder joints.

[0029] Example 1: Tvin is a 4-channel CVBS video input pin, tvout is a video output pin, tvin: the signal of tvin is collected through an external analog camera, and the image result is displayed on the LCD screen.

[0030] tvout: Display the output signal of tvout on the TV screen and judge whether it is normal by checking the TV image.

[0031] This embodiment is tested by connecting tvin to an external camera for video acquisition and tvout to an external analog TV for video output.

[0032] This embodiment has too many test interfaces, which makes the disassembly of the tooling more complicated and requires more manual intervention. It requires additional analog camera tooling and TVout output display, and the test requires a lot of extra space. The test method is also complicated, requiring checking both the screen and the TV, and frequently plugging and unplugging the analog camera.

[0033] Embodiment 2: By short-circuiting the tvin signal line and the tvout signal line and writing into the control register of tvout, the color stripe test analog signal is controlled to be output to tvin, and the collected signal is then directly displayed on the screen.

[0034] In this way, by controlling the switch of the TVOUT register and outputting the color stripe test analog signal, you can know whether the TVIN line and TVOUT line are normal by checking the display on the screen.

[0035] Specifically, the present invention firstly short-circuits the corresponding tvin and tvout in hardware: tvin1-tvout1, tvin2-tvout2, tvin3-tvout3, tvin4-tvout4.

[0036] Then, the signal is input by controlling the TVOUT controller; secondly, the image display of TVIN is used for testing.

[0037] Display the image of tvin on the four sides of the screen respectively, and then open the control registers of tvout0, tvout1, tvout2, and tvout3 in sequence when the image is displayed. If the board functions normally, the test image output by tvout will be displayed in the upper left, upper right, lower left, and lower right in sequence.

[0038] When tvout or tvin is short-circuited, multiple screens will be displayed. For example, when images are displayed on the upper left and upper right, we can conclude that tvin0 and tvin1 are short-circuited or tvout0 and tvout1 are short-circuited. When a certain image is not displayed, such as tvin0, it is certain that the tvin0 line or tvout0 line is suspected of being faulty. By testing in this way, the corresponding test operation steps can be reduced, the test process can be simplified, and the efficiency of the mass production test link can be improved.

[0039] The present invention short-circuits TVOUT and TVIN, outputs from TVOUT to the corresponding input of TVIN, and then displays it on the LCD screen. In this way, if TVOUT0 and TVOUT1 are short-circuited or TVIN0 and TVIN1 are short-circuited, when a signal is input, TVIN0 and TVIN1 will both receive the signal, and two images will appear on the screen. When the TVOUT0 or TVIN0 pin is disconnected, when TVOUT0 outputs a test signal, TVIN0 will not receive the signal, and no image will appear on the screen. The present invention is simple to operate, convenient for viewing the results, and does not require more human participation in the plugging and unplugging of the equipment. Through the display in four directions of the screen, it is more convenient to locate the problem after it occurs. The office space is reduced, and the number of additional tooling is also reduced, saving costs.

[0040] Implementation process

[0041] 3.1tvout0 / tvin0 detection

[0042] We first input a three-color image into tvout0, turn off other tvout controllers, and then start the camera display. The code is as follows.

[0043] cd / sys / class / sunxi_dump / / / Write register path

[0044] echo 01c90028 0x82714201>write / / Turn on the sending mode of tvout0.

[0045] echo 01c90048 0x82714200>write / / Turn off the sending mode of tvout1.

[0046] echo 01c90068 0x82714200>write / / Turn off the sending mode of tvout2.

[0047] echo 01c90088 0x82714200>write / / Turn off the sending mode of tvout3.

[0048] echo 01c94004 0x07070103>write / / Input three-color image.

[0049] The correct phenomenon at this time is that only the upper left corner (tvin0) displays the image.

[0050] 3.2tvout1 / tvin1 detection

[0051] We turn off the image display of tvin0, turn on the image display of tvin1, and then start the camera display.

[0052] cd / sys / class / sunxi_dump /

[0053] echo 01c90028 0x82714200>write / / Close the control register of tvout0.

[0054] echo 01c90048 0x82714201>write / / Open the control register of tvout1.

[0055] The correct phenomenon at this time is that only the upper right corner (tvin1) displays the image.

[0056] 3.3tvout2 / tvin2 detection

[0057] Then we turn off the image display of tvin1, turn on the image display of tvin2, and then start the display of the camera

[0058] cd / sys / class / sunxi_dump /

[0059] echo 01c90048 0x82714200>write / / Close the control register of tvout1

[0060] echo 01c90068 0x82714201>write / / Open the control register of tvout2

[0061] At this point, there should be only the lower left corner (tvin2) showing an image.

[0062] 3.4 Testing of tvout3 / tvin3

[0063] Then we turn off the image display of tvin2, turn on the image display of tvin3, and then start the camera display.

[0064] cd / sys / class / sunxi_dump /

[0065] echo 01c90068 0x82714200>write / / Close the control register of tvout1.

[0066] echo 01c90088 0x82714201>write / / Open the control register of tvout2.

[0067] At this point, there should be only the lower right corner (tvin3) showing an image.

Claims

1. An embedded industrial control motherboard, characterized in that: It includes at least one group of industrial control chips distributed in a 2-by-2 matrix; the industrial control chips include an upper left chip P1, an upper right chip P2, a lower left chip P3, and a lower right chip P4; In the upper left chip P1, Terminal V23PI10 is connected to terminal W22PI5 through resistor R14; Terminal W24PI7 is connected to terminal Y23PI4 through resistor R15; Terminal W23PI6 is connected to terminal V22PI9 via resistor R16; Terminal W20PI8 is connected to terminal E23PH1 through resistor R17; Terminal AB23PG10 is connected to terminal AC24PG9 through resistor R19; Terminal AB24PG11 is connected to terminal AD23PG7 through resistor R21; Terminal AC23PG8 is connected to terminal AD22PG6 through resistor R23; Terminal AB21PG2 is connected to terminal AC22PG5 through resistor R25; Terminal Y20PG1 is connected to terminal AB22PG4 through resistor R29; Terminal AA20PG0 is connected to terminal AC21PG3 through resistor R31; Terminal USBVBUS is connected to power supply VCC through resistor R98; Terminal PWRON is grounded through a parallel contact switch K2 and capacitor C47; Terminal TS is grounded via resistor R11; The power supply VCC is connected to the resistor R38, and the LED light D2 is connected to the terminal U22PI15; The power supply VCC is connected to the resistor R13, and the LED light D1 is connected to the terminal CHGLED; Terminal D22PH12 is connected to terminal W19PE3 through resistor R20; Terminal K21PB6 is connected to terminal J20PB7 through resistor R22; Terminal W17PE2 is connected to terminal AB20PE10 through resistor R18; Terminal AC20PE11 is connected to terminal Y17PE1 through resistor R24; Terminal AD20PE9 is connected to the base of transistor Q4 through resistor R136, and resistor R137 is electrically connected between the base and emitter of transistor Q4; the collector of transistor Q4 is connected to the G pole of MOS field effect transistor Q3, and resistor R135 is connected between the G pole and S pole of MOS field effect transistor Q3, and the D pole of MOS field effect transistor Q3 is grounded through diodes D8, D9 and LED diode D10 connected in series; The S pole of MOS field effect tube Q3 is connected to the output power supply; Terminal AA17PE0 is connected to terminal Y19PE4 through resistor R32; Terminal AD19PE8 is connected to terminal AA19PE5 through resistor R30; Terminal AC19PE7 is connected to terminal Y22PI3 through resistor R26; Terminal AB19PE6 is connected to terminal AA23PI1 through resistor R34; Terminal AA22PI0 is connected to terminal AA24PI2 through resistor R37; Terminal ACIN is connected to four paths, the first path is connected to chip U5 pin 4 through resistor R118, the second path is connected to chip U5 pin 1-3; the third path is connected to ground through parallel capacitors C36-38 and voltage regulator D5, and the fourth path fuse F1 is connected to integrated circuit P17; integrated circuit P17 is externally connected to socket P12; Terminal VBAT is connected to ground through LED diode D10; In the upper right chip P2, Terminal D18PH17 is connected to terminal C23PH4 through resistor R1; Terminal U23PI14 is connected to terminal G20PB13 through resistor R2; Terminal USB0P is connected to terminal USB1P through resistor R6; Terminal USB0N is connected to terminal USB1N via resistor R7; Terminal J21PB8 is connected to terminal D19PH21 through resistor R5; Terminal D23PH0 is connected to terminal DNPK20PB5 through resistor R39; The power supply VCC is connected to the resistor R10, and the LED light D7 is connected to the terminal J23PB10; In the lower left chip P3 Terminal T21PI20 is connected to terminal N19PA12 through resistor R48; Terminal R23PI21 is connected to terminal E22PH3 through resistor R50; Terminal B24PH6 is connected to terminal G17PH22 through resistor R52; Terminal B22PH7 is connected to terminal F18PH20 through resistor R54; Terminal N20PA11 is connected to terminal L23PA0 through resistor R56; Terminal N22PA9 is connected to terminal M19PA1 through resistor R57; Terminal R22PA15 is connected to terminal M22PA3 through resistor R58; Terminal N21PA10 is connected to terminal M23PA2 through resistor R59; Terminal N23PA8 is connected to terminal R21PA16 through resistor R62; Terminal P22PA14 is connected to terminal M24PA6 through resistor R64; Terminal N24PA7 is connected to terminal M21PA4 through resistor R66; Terminal P23PA13 is connected to terminal M20PA5 through resistor R67; Terminal R20PA17 is connected to terminal D24PH2 through resistor R68; The power supply VCC is connected to the resistor R27, and the LED light D3 is connected to the terminal C24PH5; Terminal G23PB18 is connected to terminal F24PB20 through resistor R40; Terminal J24PB4 is connected to terminal T24PI18 through resistor R41; Terminal U18PI12 is connected to terminal T23PI17 through resistor R42; Terminal T19PI16 is connected to terminal T22PI19 via resistor R43; Terminal E18PH25 is connected to terminal A18PH26 through resistor R44; Terminal F21PB21 is connected to terminal G24PB19 through resistor R45; Terminal E19PH19 is connected to terminal C18PH18 through resistor R46; Terminal D21PH16 is connected to terminal C22PH13 through resistor R47; Terminal A21PH15 is connected to terminal B18PH24 through resistor R49; Terminal B19PH27 is connected to terminal B21PH14 through resistor R51; Terminal B23PH8 is connected to terminal C19PH23 through resistor R53; Terminal J22PB9 is connected to terminal K23PB2 through resistor R69; A switch S2 is electrically connected between the terminals BOOT1 and BOOT2; Terminal RESET is grounded through a contact switch K3 and capacitor C48 connected in parallel; In the lower right chip P4, Terminal U1PD21 is connected to terminal R4PD19 via resistor R60; Terminal U6PD27 is connected to terminal T4PD24 via resistor R61; Terminal T3PD23 is connected to terminal T5PD25 via resistor R63; Terminal U5PD26 is connected to terminal U2PD22 via resistor R65; Terminal M4PD13 is connected to terminal A23PH9 through resistor R71; Terminal R5PD18 is connected to terminal T2PD20 via resistor R72; Terminal N4PD15 is connected to terminal P5PD16 via resistor R73; Terminal N3PD14 is connected to terminal P4PD17 via resistor R74; Terminal R2PD8 is connected to terminal L5PD10 via resistor R75; Terminal R1PD6 is connected to terminal M1PD1 via resistor R76; Terminal R3PD9 is connected to terminal L4PD11 via resistor R77; Terminal P2PD5 is connected to terminal M3PD3 via resistor R78; Terminal M2PD0 is connected to terminal P3PD7 via resistor R79; Terminal P1PD4 is connected to terminal N2PD2 via resistor R80; Terminal L3PD12 is connected to terminal A22PH10 through resistor R94; A TV0 circuit is connected between the terminal TVIN0 and the terminal TVOUT0; In the TV0 circuit, the terminal TVIN0 is grounded through the capacitor C20 and outputs two paths through the inductor L1, one path is grounded through the capacitor C54, and the other path is electrically connected to the capacitor C10 through the series resistor R104. The TV0 circuit is grounded through the resistor R120 and connected to the capacitor C10. A TV1 circuit is connected between the terminal TVIN1 and the terminal TVOUT1; A TV2 circuit is connected between the terminal TVIN2 and the terminal TVOUT2; A TV3 circuit is connected between the terminal TVIN3 and the terminal TVOUT3; TV0-3 circuits are the same; The embedded industrial control motherboard also includes the display driver chip P5 connected via the MIPI-DSI protocol interface. in, Port K24MIPIDSIPWM, C21MIPIDSIEN, MIPIDSICKP, MIPIDSICKN, MIPIDSID3P, MIPIDSID3N, MIPIDSID2P, MIPIDSID2N, MIPIDSID1P, MIPIDSID1N, MIPIDSID0P, and MIPIDSID0N are respectively connected to the corresponding ports of the lower right chip P4; It also includes an HDMI chip U1, wherein the power supply VCC supplies power to the HDMI chip through parallel resistors R84-R87 and capacitor C5 The input terminals HDMISDA, HDMIHPD, HDMISCL, HDMICEC, HDMICLKN, HDMICLKP, HDMITX0-2N, and HDMITX0-2P are connected to the corresponding ports of the upper right chip P2; The output terminal HPDETOUT is connected to the HDMI chip P8 terminal HOT-PLUG-DET; The output terminal HDMIDDCDATOUT is connected to the HDMI chip P8 terminal 12C-DATA; The output terminal HDMICECOUT is connected to the 12C-CLK terminal of the HDMI chip P8; the output terminal HDMICECOUT is connected to the power supply VCC through the resistor R97 and the voltage regulator tube D4; The output terminal HDMICLK is connected to the CK terminal of the HDMI chip P8; The output terminal HDMITX is connected to the terminal D of the HDMI chip P8; It is also connected to the hard disk chip P6; the terminals SATATX and SATARX are connected to the corresponding ports of the upper right chip P2; It is also connected to the touch module chip U4; wherein, Terminal C is connected to the upper right chip P2 terminal G19PB12, After the terminal TPX is connected to the resistor R90, it is divided into two paths. One path is connected to the upper right chip P2 terminal TPX1 through the resistor R89, and the other path is connected to the upper right chip P2 terminal TPX2 through the resistor R91. Terminal TPY is connected to two paths, one path is connected to terminal TPY1 of upper right chip P2 through resistor R92, and the other path is connected to terminal TPY2 of upper right chip P2 through resistor R93; A language module U2 is connected; wherein, Terminal SHDN is connected to the lower right chip P4 terminal K20SPKSHDN; The terminal INN is connected to the terminal PHONEOUT N of the lower right chip P4 through the resistor R36 and the capacitor C70; The terminal INP is connected to the terminal PHONEOUT P of the lower right chip P4 through the resistor R96 and the capacitor C71; Terminals VOP and VON are connected to plug P18SPK through the filter module An audio module is connected; wherein, The terminals HPCOMFB and HPCOM of the upper right chip P2 are grounded through their respective capacitors; The terminal HPOUTR / L of the upper right chip P2 is connected to the LINEINR / L of the upper right chip P2 through a polarized capacitor; The audio green phone module is connected to the terminal HPDETR105; one path of the audio green phone module is connected to the ground through a resistor, and the other path is connected to the ground through a series resistor and capacitor; A call module is connected; wherein, The terminal PHONEOUTN of the upper right chip P2 is grounded through capacitor C33; The terminal PHONEOUTP of the upper right chip P2 is divided into two paths through the series capacitor C31 and the resistor R107. One path is connected to the ground through the series resistor R112 and the capacitor C35 and the resistor R110, and the other path is connected to the Audio Blue PHONE module; the Audio Blue PHONE module is electrically connected to the K20PB5 corresponding to the terminal K20SPKSHDN through the resistor R103; A microphone module is connected to the substrate; wherein, The terminal MICIN1 of the upper right chip P2 is connected to the terminal MICL through the capacitor C27, and the terminal MICL is grounded through the capacitor C28; The terminal MICIN2 of the upper right chip P2 is connected to the terminal MICR through the capacitor C29, and the terminal MICR is grounded through the capacitor C30; The terminal VMIC of the upper right chip P2 is connected to the terminal MICL and the terminal MICR through the filter circuit. Audio Pink MIC module Resistors MICRFB1, R109, and MICRFB2 are electrically connected between terminals HPOUTR and HPOUTRL; The base plate is connected with a communication chip U6; A capacitor is electrically connected between the terminals C+ and C-; Terminal pin TIOUT is connected to terminal RS232TX; Terminal R1IN is connected to terminal RS232RX; The terminal TIIN is connected to the P3 terminal F22UART0TX of the lower left chip; The terminal R1OUT is connected to the lower left chip P3 terminal F22UART0RX; Terminal RS232TX / RX plug-in board P15; The industrial control chip is a chip from Feiling Company; the hard disk chip P6 is grounded through a diode bridge; A voltage regulator and an SDCARD module are provided on the substrate; the SDCARD module chip P14 pin is connected to the corresponding terminal of the upper right chip P2; Terminal DAT2 is connected to W13SDC0D2; Terminal CD / DAT3 is connected to Y13SDC0D3; The CMD pin is connected to AA13SDC0CMD; The terminal CLK is connected to W11SDC0CLK through resistor R133; Terminal DAT0 is connected to Y11SDC0D0; Terminal DAT1 is connected to AA11SDC0D1; Terminal DAT0 is connected to V24SDC0DET; A USB chip U7 is provided on the substrate, wherein in the USB chip U7, Terminal D- is connected to the upper right chip P2 terminal USB2N, Connect terminal D+ to the upper right chip P2 terminal USB2P, Terminal RXD1 connects to socket P16, Terminal TXD1 connects to socket P16, Socket P16 connects to the lower left chip P3 terminal F22UABT0TX, Socket P16 connects to the lower left chip P3 terminal F23UABT0RX, A memory chip U9 is provided on the substrate. The CS# pin is connected to the upper left chip P1 terminal AB17PC23; Pin DOIO1 is connected to the upper left chip P1 terminal AC10PC1; The CLK pin is connected to the upper left chip P1 terminal AD10PC2; Pin DIIO0 is connected to the upper left chip P1 terminal AB11PC0; A flash memory chip U10 is provided on the substrate. The CS# pin is connected to the upper left chip P1 terminal AA16PC19; Terminal DOIO1 is connected to the upper left chip P1 terminal Y16PC22; The CLK pin is connected to the upper left chip P1 terminal AB19PC20; Pin DIIO0 is connected to the upper left chip P1 terminal AA14PC21; The terminal KEYADC0 of the upper right chip P2 is connected to the ground through the capacitor C64 and the resistor R33, and the resistor R33 is connected to the ground through the parallel resistor R95 and the electric shock switch K1; At the upper right chip P2 terminal KEYADC1 is connected to ground through capacitor C65 and resistor R70 respectively, and resistor R70 is connected to ground through parallel resistor R141 and electric shock switch K4; Input a 3-color image into the controller tvouti, i=0, 1, 2, 3, and turn off other controllers tvoutj, j≠i. When starting the camera display, the code is implemented as follows; cd / sys / class / sunxi_dump / , write the register path; echo 01c900280x82714201>write, turn on the sending mode of tvouti; echo 01c900480x82714200>write, turn off the sending mode of tvoutj≠i; echo 01c900680x82714200>write, turn off the sending mode of tvoutk≠i; echo 01c900880x82714200>write, turn off the sending mode of tvoutm≠i; echo 01c940040x07070103>write, input three-color image.

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