Robust method and circuit for controlling the timing window that enables sense amplifier operation

Abstract

Various embodiments of the present disclosure relate to robust methods and circuits for controlling a timing window in which sense amplifier operation is enabled. In response to an indication that a sufficient voltage difference has been formed across a bit line of a memory, a sense amplifier enable signal and a tracking signal are generated. The sense amplifier enable signal has a pulse width between a leading edge and a trailing edge. The sense amplifier enable signal propagates along a first U-turn signal line to generate a sense amplifier enable return signal, which first U-turn signal line extends parallel to the rows of a memory array and is coupled to sense amplifiers arranged in a row. The tracking signal propagates along a second U-turn signal line to generate a tracking return signal, which second U-turn signal line extends parallel to the columns of the memory array. The sense amplifier enable return signal and the tracking return signal are logically combined to generate a reset signal. The timing of the trailing edge of the pulse width is controlled by the reset signal.

Description

Technical Field

[0001] The present invention relates generally to sense amplifier control circuits, and more particularly, to a circuit that controls a timing window (pulse width) to enable sense amplifier operation within a memory and / or memory compiler. Background Art

[0002] A memory circuit is formed by an array of memory cells arranged in rows and columns and a plurality of sense amplifiers selectively coupled to the columns of the array. Proper operation of the memory depends on a timing window in which the sense amplifiers can operate. When a sufficient voltage difference is formed on the bit line of each selected column, the sense amplifier must be enabled to operate in order to read the data stored in the memory cell. Additionally, after the read data is latched, the sense amplifier must be disabled with a safety margin across process, voltage, and temperature (PVT) variations. In practice, it is the pulse width of the sense amplifier enable (SAEN) signal that must be controlled. Generally speaking, the timing for triggering the SAEN signal on (i.e., the leading edge of the SAEN pulse) can be managed by schemes such as bitline tracking, which are adjusted to enable the sense amplifier when a sufficient voltage difference exists on the differential input nodes of the sense amplifier to ensure correct interpretation and successful latching of the read data. However, the timing for triggering the SAEN signal off (i.e., the trailing edge of the SAEN pulse) is more difficult to control in a way that balances the successful latching of the read data with the penalty of the cycle time for completing the data read. In many prior art memories, the circuitry controlling the timing for triggering the SAEN signal to turn off is designed to address the worst-case scenario, at the expense of a delay in cycle time. Consequently, the sense amplifier's operation is suboptimal. Furthermore, this becomes more complex in memory compilers, which support a range of rows and columns, where the SAEN signal's turn-off triggering needs to be adjusted based on the worst-case cut size, which incurs a cycle time penalty for smaller cuts.

[0003] Figure 1AA circuit diagram of a prior art circuit 10 for generating an SAEN signal is shown. Circuit 10 includes an n-channel metal oxide semiconductor field effect transistor (MOSFET) 18 having a gate terminal coupled to input 12 and a source terminal coupled to a reference power supply node (e.g., ground). The source-drain path of a p-channel MOSFET 22 is connected in series with the source-drain path of transistor 18. More specifically, the drain terminal of transistor 22 is connected to the drain terminal of transistor 18 at node 26. The source terminal of transistor 22 is coupled to a power supply node (Vdd). The gate terminal of transistor 22 is coupled to receive a reset signal RESET. A latch circuit 30 is connected to node 26. Latch circuit 30 can be formed, for example, by a pair of cross-coupled complementary metal oxide semiconductor (CMOS) logic inverter circuits. The input of a first CMOS inverter circuit 34 is connected to node 26. The input of a second CMOS inverter circuit 36 is connected to the output of the first inverter circuit 34. The SAEN signal is generated at the output of inverter circuit 36. The output of inverter circuit 36 is further connected to the input of adjustable delay circuit 40, which applies an adjustable delay period td to the received SAEN signal. The output of adjustable delay circuit 40 generates reset signal RESET. Adjustable delay 40 is adjusted based on the worst-case requirement for the SAEN pulse width. The pulse width should be substantially greater than the sum of the sense amplifier's resolution time and the time it takes for the sense amplifier's output to settle on the global output line and latch into the output latch.

[0004] The operation of the circuit 10 for generating the SAEN signal is as follows (see also Figure 1B): Circuit 10 receives a control signal CTRL at input 12, the logic state of which transitions from a logic low (logic "0") to a logic high (logic "1") in response to tracking circuit 14 determining that data on a bit line of the memory array is ready to be read. Tracking circuit 14 may, for example, include a pseudo bit line tracking circuit that ensures that there is a sufficient voltage difference on the actual bit line so that the sense amplifier can ensure successful resolution of the voltage and that the read data can be latched. In response to the logic high state of control signal CTRL, transistor 18 turns on and drives node 26 to a logic low state. This logic low state is latched by latch circuit 30. The SAEN signal output from inverter circuit 36 is also driven to a logic low state after a small delay introduced by the operation of inverters 34 and 36. The transition to logic low is the leading edge 44 of the pulse of the SAEN signal. Sense amplifier circuit 48 includes a sense amplifier 48a, which is enabled for operation by the logic low state of the SAEN signal. When enabled, sense amplifier 48a resolves the voltage difference between the bit lines (BL / BLB) and generates an output that is stable on global output line 130 and latched by output latch 48b as a global output signal. Adjustable delay circuit 40 receives the SAEN signal and delays the transition to the logic low state of reset signal RESET by an adjustable delay time period td. In response to the transition of reset signal RESET to the logic low state, transistor 22 turns on and pulls node 26 to a logic high state (Vdd). This logic high state is latched by latch circuit 30. The SAEN signal output from inverter circuit 36 is also driven to a logic high state after a small delay is introduced by the operation of inverters 34 and 36. The transition to logic high is the trailing edge 46 of the pulse of the SAEN signal. Therefore, the pulse width PW of the pulse for the SAEN signal (i.e., from leading edge 44 to trailing edge 46) is controlled by the length of adjustable delay time period td.

[0005] Figure 2A simplified block diagram of an integrated circuit of a memory 100 based on a bank architecture is shown. The memory includes a first (upper) memory bank 112t and a second (lower) memory bank 112b. Each memory bank 112 includes an array of memory cells (C) 114 arranged in rows and columns, where rows are associated with word lines 116 and columns are associated with bit lines 118. The memory cells 114 may be, for example, static random access memory (SRAM) cells. The word lines 116 of the first (upper) memory core 112t are selectively driven by a first (upper) row decoder 120t. The word lines 116 of the second (lower) memory core 112b are selectively driven by a second (lower) row decoder 120b. The row decoder 120 receives a memory address on an address bus 122 and decodes the address bits (or a subset thereof) of the received memory address to select a memory bank 112 and one of the word lines 116 within the selected memory bank to be activated (e.g., driven to logic high). The memory 100 also includes a column decoder and sense amplifier circuit (COL DEC and SA) 124, which is also coupled to the address bus 122 and the bit lines 118 from both the first (upper) memory core 112t and the second (lower) memory core 112b. The column decoder and sense amplifier circuit 124 also receives a memory address from the address bus 122 and decodes the address bits (or a subset thereof) of the received memory address to select a plurality of bit lines 118 to couple to corresponding sense amplifier circuits of a plurality of sense amplifier circuits (not explicitly shown, see Figure 3 , reference numeral 48, where each sense amplifier circuit 48 includes a sense amplifier 48 a coupled to a latch circuit 48 b that is configured to hold an output on line 130 when sense amplifier 48 a is reset. Input / output (I / O) circuitry 128 is coupled to receive the output of the sense amplifier circuits within column decoder and sense amplifier circuitry 124 on global output line 130.

[0006] refer to Figure 3 , details of the sense amplifier portion of the column decoder and the sense amplifier circuit 124 are shown. The column decoder function of the column decoder and the sense amplifier circuit 124 are omitted so that attention can be focused on the sense amplifier portion. The column decoder will be provided between the plurality of sense amplifiers and each of the memory banks 112. The sense amplifier circuit portion includes a SAEN generator circuit 10 (e.g., a SAEN generator circuit 10 configured to generate a SAEN signal) Figure 1A), the SAEN signal is applied to each of the sense amplifier circuits 48 (and specifically, to sense amplifier 48 a therein) via SAEN signal line 140. SAEN signal line 140 extends through (or passes through) each of the sense amplifiers 48 a of the plurality of sense amplifier circuits 48 within the column decoder and sense amplifier circuit 124.

[0007] In read mode, a memory address is applied to address bus 122, where the bits of the memory address specify the location within memory bank 112 from which data is to be retrieved. Row decoder 120 and column decoder 124 decode the address bits of the received memory address and select the memory bank 112, word line 116 within the selected memory bank, and bit line 118 for the memory address. Tracking circuit 14 then determines whether a sufficient voltage difference exists on bit line 118 for sense amplifier 48a to resolve the voltage difference, write the output on output line 130, and ensure that the read data is successfully latched in output latch 48b. Control signal CTRL is asserted to a logic high state by tracking circuit 14, and the SAEN signal is driven to a logic low state to enable all sense amplifiers 48a via SAEN signal line 140. The read data generated by sense amplifier 48a and latched by output latch 48b is output to input / output (I / O) circuit 128 via global output line 130. After the adjustable delay period td expires, the RESET signal is driven to a logic low state, which causes the SAEN signal to be driven to a logic high state. In response, the operation of the sense amplifier 48a is disabled, and the read operation ends. Summary of the Invention

[0008] In one embodiment, a circuit includes: a plurality of sense amplifiers arranged in a row, wherein an input of each sense amplifier is coupled to a sense amplifier enable signal line extending along the row from a first end at one end of the row of sense amplifiers to a second end at an opposite end of the row of sense amplifiers; a sense amplifier enable signal return line extending from a third end at the opposite end of the row of sense amplifiers to a fourth end at one end of the row of sense amplifiers; wherein the third end of the sense amplifier enable signal return line is coupled to the second end of the sense amplifier enable signal line; a sense amplifier enable signal generator circuit configured to apply a sense amplifier enable signal to the first end of the sense amplifier enable signal line, the sense amplifier enable signal having a pulse width between a leading edge and a trailing edge, receive the sense amplifier enable return signal at the fourth end of the sense amplifier enable signal return line, and generate the sense amplifier enable return signal in response to the sense amplifier enable signal; and wherein timing of the trailing edge of the pulse width is set by the sense amplifier enable signal generator circuit in response to a change in a logic state of the sense amplifier enable return signal.

[0009] In one embodiment, a circuit includes: a first U-turn signal line extending parallel to rows of a memory array, the first U-turn signal line having an input configured to receive a sense amplifier enable signal and an output configured to output a sense amplifier enable return signal generated in response to the sense amplifier enable signal; a plurality of sense amplifiers arranged in rows and having inputs connected to receive the sense amplifier enable signal from the first U-turn signal line; a second U-turn signal line extending parallel to columns of the memory array, the second U-turn signal line having an input configured to receive a tracking signal and an output configured to output a tracking return signal generated in response to the tracking signal; a sense amplifier enable signal generator circuit configured to generate both the sense amplifier enable signal and the tracking signal, the sense amplifier enable signal having a pulse width between a leading edge and a trailing edge; and wherein timing of the trailing edge of the pulse width is set by a reset signal output by a logic circuit in response to a logical combination of the sense amplifier enable return signal and the tracking return signal.

[0010] In one embodiment, a method includes: generating a sense amplifier enable signal and a tracking signal in response to an indication that a sufficient voltage difference has been formed across a bit line of a memory, wherein the sense amplifier enable signal has a pulse width between a leading edge and a trailing edge; propagating the sense amplifier enable signal through a first U-turn signal line to generate a sense amplifier enable return signal, the first U-turn signal line extending parallel to a row of a memory array and coupled to a plurality of sense amplifiers arranged in the row; propagating the tracking signal through a second U-turn signal line to generate a tracking return signal, the second U-turn signal line extending parallel to a column of the memory array; logically combining the sense amplifier enable return signal and the tracking return signal to generate a reset signal; and controlling timing of a trailing edge of the pulse width in response to the reset signal.

[0011] In one embodiment, a circuit includes: a sense amplifier having an input coupled to a sense amplifier enable signal line, wherein the sense amplifier is connected to a pair of bit lines extending along a column; a tracking circuit configured to generate a tracking signal indicating a sufficient voltage difference between the pair of bit lines to be sensed by the sense amplifier; a tracking signal line extending along the column from a first end to a second end, the tracking signal being applied to the first end of the tracking signal line; a tracking signal return line extending from a third end to a fourth end, wherein the third end of the tracking signal return line is coupled to the second end of the tracking signal line; a sense amplifier enable signal generator circuit configured to apply the sense amplifier enable signal to the sense amplifier enable signal line, the sense amplifier enable signal having a pulse width between a leading edge and a trailing edge, wherein the timing of the leading edge of the pulse width is set in response to the tracking signal, and a tracking return signal is received at the fourth end of the tracking signal return line, the tracking return signal being generated in response to the tracking signal; and wherein the timing of the trailing edge of the pulse width is set by the sense amplifier enable signal generator circuit in response to a change in the logic state of the tracking return signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0013] Figure 1A A circuit diagram illustrating a prior art circuit for generating a sense amplifier enable (SAEN) signal;

[0014] Figure 1B Shown Figure 1A a timing diagram of the operation of the circuit;

[0015] Figure 2 is a block diagram of the memory;

[0016] Figure 3 yes Figure 2A simplified circuit example of a sense amplifier circuit portion within a memory;

[0017] Figure 4 yes Figure 2 A simplified circuit example of a sense amplifier circuit portion within a memory and tracking signals in parallel with rows and columns;

[0018] Figure 5 is a circuit diagram of a circuit for generating a SAEN signal;

[0019] Figure 6 Shown Figure 5 a timing diagram of the operation of the circuit;

[0020] Figure 7 is a circuit diagram of an alternative embodiment of a driver circuit for vertically tracking a U-turn signal line; and

[0021] Figure 8 Figure 2 is a circuit diagram of a sense amplifier circuit and the accompanying output latch. DETAILED DESCRIPTION

[0022] Now refer to Figure 4 , which shows that with Figure 2 A simplified circuit example of a portion of a sense amplifier circuit for use with a memory device of the type shown in FIG. 1 is shown in FIG. 1 . Like reference numerals refer to circuits of the same type as those of FIG. Figure 3 The same or similar components shown in FIG. Figure 4 The sense amplifier circuit portion is connected to Figure 3 The sense amplifier circuit portion of the CMOS circuit differs in that a different SAEN generator circuit 10' is used (details of which are given in Figure 5 ), and using the U-turn signal lines for the sense amplifier enable (SAEN) signal and the vertical tracking (VTRACK) signal.

[0023] The U-turn signal line for the SAEN signal includes a SAEN signal line 200 and a SAEN signal return line 202. The SAEN signal line 200 extends from a first end 200a coupled to a first output of the SAEN generator circuit, where the SAEN signal is generated, to a second end 200b. The first end 200a passes through or is electrically connected to each of the included sense amplifiers 48a. For sense amplifiers 48a arranged in a row, the SAEN signal line 200 extends from one end of the row to the opposite end of the row. The SAEN signal return line 202 extends parallel to the SAEN signal line 200 from a first end 202a to a second end 202b coupled to a first input of the SAEN generator circuit. The second end 200b of the SAEN signal line 200 is coupled to the first end 202a of the SAEN signal return line 202 via a first driver circuit 204. First driver circuit 204 is formed by a pair of CMOS inverter circuits connected in series, where the input of the first inverter circuit is coupled to second terminal 200b and the output of the second inverter circuit is coupled to first terminal 202a. With this configuration of first driver circuit 204, the logic state of the SAEN RETURN signal on SAEN signal return line 202 is the same as the logic state of the SAEN signal on SAEN signal line 200. In alternative embodiments, first driver circuit 204 can instead be implemented using a non-inverting buffer circuit.

[0024] The U-turn signal line for the vertical tracking (VTRACK) signal includes a tracking signal line 210 and a tracking signal return line 212. Tracking signal line 210 extends from a first end 210a coupled to a second end 210b, with first end 210a coupled to a second output of the SAEN generator circuit, such that the length of tracking signal line 210 is substantially equal to the length of each global output line 130 (i.e., within ±1%-3%). Tracking signal return line 212 extends parallel to tracking signal line 210 from a first end 212a to a second end 212b, with second end 212b coupled to a second input of the SAEN generator circuit. Second end 210b of tracking signal line 210 is coupled to first end 212a of tracking signal return line 212 via a second driver circuit 214. Second driver circuit 214 is formed from three serially connected CMOS inverter circuits, with the input of the first inverter circuit coupled to second end 210b and the output of the third inverter circuit coupled to first end 212a. With this configuration of second driver circuit 214, the logic state of the VTRACK RETURN signal on tracking signal return line 212 is the inverted logic state of the VTRACK signal on tracking signal line 210. In an alternative embodiment, second driver circuit 214 may be implemented with a single logic inverter circuit.

[0025] It will be noted that the SAEN signal line 200 and the SAEN signal return line 202 run in the same direction as the word lines and rows of memory cells within the memory bank (in Figure 3 4. In the illustration of FIG. 4, the SAEN signal line 200 extends horizontally). The change in logic state of the SAEN RETURN signal accordingly provides information about the time it takes for the SAEN signal to propagate horizontally from the SAEN generator circuit 10′ through all sense amplifiers 48a and back to the SAEN generator circuit 10′. This propagation time is affected by the RC delay of the SAEN signal line 200 (schematically represented by RC circuit 220).

[0026] It will be further noted that the tracking signal line 210 and the tracking signal return line 212 are in the same direction as the global output line 130 (in Figure 3 2, which extends vertically in the illustration of the VTRACK RETURN signal. Changes in the logic state of the VTRACK RETURN signal accordingly provide information about the time it takes for the VTRACK signal to propagate vertically from the SAEN generator circuit 10' to the input / output (I / O) circuit 128 and back to the SAEN generator circuit 10'. This propagation time is affected by the RC delay of the tracking signal line 210, which effectively emulates the RC delay of the global output line 130 (schematically represented by the RC circuit 222).

[0027] It will be further noted that in some memory configurations, the SAEN generator circuit 10 ′ may be separate from the column decoder and sense amplifier circuit (COL DEC and SA) 124 ′.

[0028] Now refer to Figure 5, which shows a circuit diagram of SAEN generator circuit 10'. Circuit 10' includes an n-channel metal oxide semiconductor field effect transistor (MOSFET) 318, whose gate terminal is coupled to receive a control signal CTRL and whose source terminal is coupled to a reference power supply node (e.g., ground). Control signal CTRL is generated by inverter circuit 338, which receives a VTRACK signal generated by tracking circuit 14, which is used to determine when data on a bit line of the memory array is ready to be read. The VTRACK signal is further coupled to first terminal 210a of tracking signal line 210. The source-drain path of p-channel MOSFET 322 is connected in series with the source-drain path of transistor 318. More specifically, the drain terminal of transistor 322 is connected to the drain terminal of transistor 318 at node 326. The source terminal of transistor 322 is coupled to a power supply node (Vdd). The gate terminal of transistor 322 is coupled to receive a reset signal RESET. Latch circuit 330 is connected to node 326. Latch circuit 330 can be formed, for example, by a pair of cross-coupled complementary metal oxide semiconductor (CMOS) logic inverter circuits. A first CMOS inverter circuit 334 has an input connected to node 326 and an output connected to node 328. A second CMOS inverter circuit 336 has an input connected to node 328 and an output connected to the first end 200a of the SAEN signal line 200. The SAEN signal is generated at the output of inverter circuit 336.

[0029] A reset signal, RESET, is generated by logic circuit 340, which logically combines the SAEN RETURN signal (received at second end 202b of SAEN signal return line 202), the logical inversion of the SAEN signal (received from node 328), and the VTRACK RETURN signal (received at second end 212b of tracking signal return line 212). Logic circuit 340 includes a logic inverter 342 having an input coupled to receive the SAEN RETURN signal and generating a signal 344 having a logic state that is the inverse of the logic state of the SAEN RETURN signal. A logic NAND gate 348 has a first input that receives signal 344 and a second input that receives the logical inversion of the SAEN signal (from node 328), and generates a signal 350. The logical inversion of the SAEN signal (from node 328) serves as an enable control signal that enables operation of logic circuit 340. A logic inverter 354 receives signal 350 and generates a signal 356. Logic NAND gate 360 has a first input that receives signal 356 and a second input that receives the VTRACK RETURN signal and generates a reset signal RESET.

[0030] Circuit 10' for generating SAEN signal (see Figure 5 ) is as follows (see also Figure 6 ): Circuit 10 receives the VTRACK signal, and in response to the tracking circuit 14 determining that the data on the bit line of the memory array is ready to be read, the logic state of the VTRACK signal transitions from a logic high (logic "1") to a logic low (logic "0"). The VTRACK signal is further coupled to the first end 210a of the tracking signal line 210. In response to the operation of the inverter 338, the logic state of the control signal CTRL transitions from a logic low (logic "0") to a logic high (logic "1"). In response to the logic high state of the control signal CTRL, the transistor 318 turns on and drives the node 326 to a logic low state. This logic low state is latched by the latch circuit 330. The SAEN signal output from the inverter circuit 336 at the first end 200a of the SAEN signal line 200 is also driven to a logic low state after a small delay introduced by the operation of the inverters 334 and 336. The logical inversion of the SAEN signal is output at the node 328 to enable the logic circuit 340 to operate.

[0031] The transition of the SAEN signal to logic low is the leading edge 44 of the SAEN pulse. A plurality of sense amplifiers 48a are enabled to operate by the logic low state of the SAEN signal. When enabled, the sense amplifiers 48a interpret the data available on the bit lines (BL / BLB), write the output data on the global output line 130, and latch the output data in the associated latch 48b.

[0032] The SAEN signal propagates on the U-turn signal line formed by the SAEN signal line 200 and the SAEN signal return line 202 to generate the SAEN RETURN signal. The VTRACK signal propagates on the U-turn signal line formed by the tracking signal line 210 and the tracking signal return line 212 to generate the VTRACK RETURN signal. The logic circuit 340 is enabled to operate by the logic high state of the logical inversion of the SAEN signal from the node 328. The logic circuit 340 logically combines the SAEN RETURN signal and the VTRACK RETURN signal to generate the reset signal RESET. More specifically, in response to the logic low state of the SAEN RETURN signal and the logic high state of the VTRACK RETURN signal, the logic circuit 340 drives the reset signal RESET to a logic low state. In response to the transition of the reset signal RESET to a logic low state, the transistor 322 turns on and pulls the node 326 to a logic high state (Vdd). This logic high state is latched by the latch circuit 330. The SAEN signal output from inverter circuit 336 is also driven to a logic high state after a small delay introduced by the operation of inverters 334 and 336. The transition to logic high is the trailing edge 46 of the SAEN pulse. Therefore, the pulse width PW of the pulse of the SAEN signal (i.e., from the leading edge 44 to the trailing edge 46) is controlled by the propagation delay of the SAEN signal and the VTRACK signal, which is determined by the RC delay of the horizontal SAEN signal and the vertical VTRACK signal on their respective U-turn signal lines. This ensures that the SAEN pulse width is automatically adjusted based on the horizontal RC delay that is proportional to the length of the SAEN signal line 200 and the vertical RC delay of the VTRACK signal that is proportional to the length of the global output line 130.

[0033] Now refer to Figure 7 , which shows a circuit diagram of an alternative embodiment of a second driver circuit 214 for a U-turn signal line associated with the propagation of the VTRACK signal. Second driver circuit 214 includes a logic NOR gate 370 having a first input coupled to the second end 210b of tracking signal line 210 and a second input coupled to receive a clock signal CLK. Clock signal CLK is a clock used to time memory read operations. Logic NOR gate 342 generates signal 372. This signal passes through a pair of serially connected inverters 374 and 376 to generate a VTRACKRETURN signal, which is coupled to the first end 212a of tracking signal return line 212.

[0034] Now refer to Figure 8, which shows a circuit diagram of sense amplifier 48a and output latch 48b. Sense amplifier 48a includes latch circuit 400, which has complementary internal nodes IN and INB and is formed by a cross-coupled CMOS inverter circuit. Latch circuit 400 includes tail current source MOSFET 402, whose gate terminal is driven by the logical inverse of the SAEN signal (SAEN bar). Internal node IN is coupled to bit line BL via transmission gate MOSFET 404. Internal node INB is coupled to bit line BLB via transmission gate MOSFET 406. The gate terminals of transistors 404 and 406 are driven by the logical inverse of the SAEN signal (SAEN bar). Internal node IN is coupled to the gate terminal of n-channel MOSFET 414 via inverter 410. Internal node INB is coupled to the gate terminal of p-channel MOSFET 416. Transistors 414 and 416 have their source-drain paths coupled in series at node 420. Output latch circuit 48 b is coupled to node 420 , and global output line 130 is also coupled to node 420 .

[0035] When SAEN is logic high, latch circuit 400 is disabled and pass-gate MOSFETs 404 and 406 are turned on to couple the voltage available on bit lines BL / BLB to internal nodes IN / INB. Then, when SAEN transitions to logic low, latch circuit 400 is enabled for operation and transistors 404 and 406 are turned off. Latch circuit 400 of sense amplifier 48a resolves the voltage difference available between nodes IN and INB and drives output node 420 to a high or low logic state corresponding to the voltage from bit lines BL / BLB. The voltage at output node 420 is then stabilized on global output line 130 and latched in output latch 48b.

[0036] In one embodiment, the transistors included in the final driver of second driver circuit 214 are sized to correspond to the n-channel MOSFET 414 and p-channel MOSFET 416 of the driver circuit for sense amplifier 48, which drives global output line 130. To simulate the actual behavior of the signal on the global output line, this is preferred so that a load that is exactly similar in terms of RC delay is seen by the final driver of circuit 214. This ensures that any change in the output global line 130 will produce a proportional shift in the SAEN pulse width.

[0037] Reference again Figure 4It will be noted that the first driver circuit 204 includes a logic inverter that generates the SAEN RETURN signal from the SAEN signal, allowing for rapid transitions in the logic state of the SAEN RETURN signal. This is done so that the horizontal RC delay of interest (i.e., the delay associated with the SAEN signal line 200 from terminal 200a to terminal 200b) is tracked at the input of circuit 204. Using the driver of circuit 204, the reverse path of the SAEN RETURN signal on the SAEN return signal line 202 is made as fast as possible. This eliminates any need to tap the SAEN RETURN signal to address speed issues or concerns.

[0038] The timing window of the SAEN pulse (i.e., pulse width PW) depends largely on the RC delay of the SAEN / SAEN RETURN signals (reference numeral 220), as well as the RC delay of the VTRACK and VTRACK RETURN signals, which is proportional to the RC delay of the global output line (reference numeral 222). The signal propagation length depends on the size of the memory. Therefore, using Figure 5 An advantage of the SAEN generator circuit 10' is that the solution automatically scales to the size of the memory in which it is used. The SAEN evaluation timing window is optimized for the memory size and process, voltage, and temperature (PVT) distribution.

[0039] Although the present invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary rather than restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

1. A circuit comprising: a plurality of sense amplifiers arranged in a row, wherein each sense amplifier is connected to a pair of bit lines, and wherein each sense amplifier has an input coupled to a sense amplifier enable signal line extending along the row from a first end of the sense amplifier at one end of the row to a second end of the sense amplifier at an opposite end of the row; a sense amplifier enable signal return line extending from a third end at the opposite end of the row of sense amplifiers to a fourth end at the one end of the row of sense amplifiers; wherein the third end of the sense amplifier enable signal return line is coupled to the second end of the sense amplifier enable signal line; a tracking circuit configured to determine that a sufficient voltage difference exists on the pair of bit lines for sensing by the sense amplifier and to generate a tracking signal; a tracking signal line extending along the column from a first end to a second end, the tracking signal being applied to the first end of the tracking signal line; Trace the signal return line from the third terminal to the fourth terminal; wherein the third end of the tracking signal return line is coupled to the second end of the tracking signal line; a sense amplifier enable signal generator circuit configured to apply a sense amplifier enable signal to the first end of the sense amplifier enable signal line, the sense amplifier enable signal having a pulse width between a leading edge and a trailing edge, and configured to receive a sense amplifier enable return signal at the fourth end of the sense amplifier enable signal return line, and further receive a tracking return signal at the fourth end of the tracking signal return line, the sense amplifier enable return signal being generated in response to the sense amplifier enable signal; wherein the timing of the leading edge of the pulse width is set by the sense amplifier enable signal generator circuit in response to the tracking signal generated by the tracking circuit; and wherein the timing of the trailing edge of the pulse width is set by the sense amplifier enable signal generator circuit in response to changes in logic states of both the sense amplifier enable return signal and the tracking return signal.

2. The circuit of claim 1 , wherein the third end of the sense amplifier enable signal return line is coupled to the second end of the sense amplifier enable signal line through a first driver circuit, the first driver circuit having an input connected to the second end of the sense amplifier enable signal line and an output connected to the third end of the sense amplifier enable signal return line. 3 . The circuit of claim 1 , wherein the sense amplifier enable signal return line extends parallel to the sense amplifier enable signal line.

4. The circuit according to claim 1, Wherein the sense amplifier enable signal generator circuit includes a logic circuit configured to logically combine the sense amplifier enable return signal and a tracking return signal to generate a reset signal, wherein the reset signal controls the timing of the trailing edge of the pulse width.

5. The circuit according to claim 1 , further comprising: output circuitry coupled to the plurality of sense amplifiers via a corresponding plurality of global output lines extending parallel to the columns; The tracking signal line and the tracking signal return line extend parallel to the plurality of global output lines.

6. The circuit of claim 1 , wherein the third end of the tracking signal return line is coupled to the second end of the tracking signal line through a second driver circuit, the second driver circuit having an input connected to the second end of the tracking signal line and an output connected to the third end of the tracking signal return line.

7. The circuit of claim 6 , wherein the second driver circuit comprises an additional logic circuit configured to logically combine the tracking signal at the second end of the tracking signal line with a clock signal to generate the tracking return signal at the third end of the tracking signal return line.

8. The circuit of claim 4 , wherein the logic circuit comprises: a first logic gate configured to logically combine the sense amplifier enable return signal with a signal derived from the sense amplifier enable signal to generate a first logic signal; a second logic gate configured to logically invert the first logic signal to generate a second logic signal; as well as A third logic gate is configured to logically combine the second logic signal and the trace return signal to generate the reset signal.

9. A circuit comprising: a first U-turn signal line extending parallel to a row of the memory array, the first U-turn signal line having an input and an output, the input being configured to receive a sense amplifier enable signal, the output being configured to output a sense amplifier enable return signal generated in response to the sense amplifier enable signal; a plurality of sense amplifiers arranged in a row and having inputs connected to receive the sense amplifier enable signal from the first U-turn signal line; a second U-turn signal line extending parallel to a column of the memory array, the second U-turn signal line having an input and an output, the input being configured to receive a tracking signal and the output being configured to output a tracking return signal generated in response to the tracking signal; a sense amplifier enable signal generator circuit configured to generate both the sense amplifier enable signal and the tracking signal, the sense amplifier enable signal having a pulse width between a leading edge and a trailing edge; and wherein the timing of the trailing edge of the pulse width is set by a reset signal output by a logic circuit in response to a logical combination of the sense amplifier enable return signal and the tracking return signal; The logic circuit includes: a first logic gate configured to logically combine the sense amplifier enable return signal with a signal derived from the sense amplifier enable signal to generate a first logic signal; A second logic gate is configured to logically invert the first logic signal to generate a second logic signal; and A third logic gate is configured to logically combine the second logic signal and the trace return signal to generate the reset signal.

10. The circuit of claim 9, wherein: The first U-turn signal line includes a sense amplifier enable signal line and a sense amplifier enable signal return line, the sense amplifier enable signal line extending in a first direction along the plurality of sense amplifiers arranged in the row, the sense amplifier enable signal return line extending in a second direction opposite to the first direction along the plurality of sense amplifiers arranged in the row; and The second U-turn signal line includes a tracking signal line extending in parallel to the column in a third direction, and a tracking signal return line extending in a fourth direction opposite to the third direction.

11. The circuit of claim 10, wherein: the sense amplifier enable signal return line being coupled to the sense amplifier enable signal line through a first driver circuit that generates a sense amplifier enable return signal from the sense amplifier enable signal to propagate along the sense amplifier enable signal return line; and The tracking signal return line is coupled to the tracking signal line by a second driver circuit that generates the tracking return signal from the tracking signal to propagate along the tracking signal return line.

12. The circuit of claim 10, further comprising: output circuitry coupled to the plurality of sense amplifiers via a corresponding plurality of global output lines extending parallel to the columns; The tracking signal line and the tracking signal return line extend parallel to the plurality of global output lines.

13. A method for controlling operation of a sense amplifier, comprising: generating both a sense amplifier enable signal and a tracking signal in response to an indication that a sufficient voltage difference has been formed across a bit line of the memory array, wherein the sense amplifier enable signal has a pulse width between a leading edge and a trailing edge; propagating the sense amplifier enable signal through a first U-turn signal line to generate a sense amplifier enable return signal, the first U-turn signal line extending parallel to a row of the memory array and coupled to a plurality of sense amplifiers arranged in the row; propagating the tracking signal through a second U-turn signal line to generate a tracking return signal, the second U-turn signal line extending parallel to a column of the memory array; logically combining the sense amplifier enable return signal and the tracking return signal to generate a reset signal; as well as In response to the reset signal, the timing of the trailing edge of the pulse width is controlled.

14. A circuit comprising: a sense amplifier having an input coupled to a sense amplifier enable signal line, wherein the sense amplifier is connected to a pair of bit lines extending along the column; a tracking circuit configured to generate a tracking signal indicating that a sufficient voltage difference exists on the pair of bit lines for sensing by the sense amplifier; a tracking signal line extending along the column from a first end to a second end, the tracking signal being applied to the first end of the tracking signal line; Trace the signal return line from the third terminal to the fourth terminal; wherein the third end of the tracking signal return line is coupled to the second end of the tracking signal line; a sense amplifier enable signal generator circuit configured to apply a sense amplifier enable signal to the sense amplifier enable signal line, the sense amplifier enable signal having a pulse width between a leading edge and a trailing edge, and wherein a timing of the leading edge of the pulse width is set in response to the tracking signal, and configured to receive a tracking return signal at the fourth end of the tracking signal return line, the tracking return signal being generated in response to the tracking signal; and wherein the timing of the trailing edge of the pulse width is set by the sense amplifier enable signal generator circuit in response to a change in the logic state of the tracking return signal. 15 . The circuit of claim 14 , wherein the sense amplifier enable signal generator circuit comprises a logic circuit configured to logically combine the tracking return signal with an enable signal generated in response to the sense amplifier enable signal.

16. The circuit of claim 15, wherein the logic circuit comprises: a first logic gate configured to logically combine the sense amplifier enable return signal with the enable signal to generate a first logic signal; a second logic gate configured to logically invert the first logic signal to generate a second logic signal; as well as A third logic gate is configured to logically combine the second logic signal and the tracking return signal to generate a reset signal, wherein the reset signal triggers setting of the trailing edge of the pulse width.

17. The circuit of claim 16, wherein the sense amplifier enable signal line extends along a row from a first end to a second end, the first end being configured to receive the sense amplifier enable signal, and further comprising: a sense amplifier enable signal return line extending from the third terminal to the fourth terminal; wherein the third end of the sense amplifier enable signal return line is coupled to the second end of the sense amplifier enable signal line; and wherein the sense amplifier enables a return signal to be generated at the fourth terminal.

18. The circuit of claim 14, further comprising: an output circuit coupled to the sense amplifier via a global output line extending parallel to the column; The tracking signal line and the tracking signal return line extend parallel to the global output line.

19. The circuit of claim 14 , wherein the third end of the tracking signal return line is coupled to the second end of the tracking signal line through a second driver circuit, the second driver circuit having an input connected to the second end of the tracking signal line and an output connected to the third end of the tracking signal return line.

20. The circuit of claim 19 , wherein the second driver circuit comprises additional logic circuitry configured to logically combine the tracking signal at the second end of the tracking signal line with a clock signal to generate the tracking return signal at the third end of the tracking signal return line.

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