image sensor

Abstract

An imaging device can include an active pixel region, the active pixels included in the generation of photoelectric signals, and a dummy pixel region, the dummy pixels not included in the generation of photoelectric signals. Electrical characteristics of the dummy pixels can affect photoelectric signals produced by the active pixels unless insulation reducing electrical conductivity is provided between the two. An image sensor includes a substrate including an active pixel region and a dummy pixel region, a pixel isolation structure at least partially penetrating the substrate and configured to reduce electrical conductivity between an active pixel in the active pixel region and a dummy pixel in the dummy pixel region, and a dummy isolation structure at least partially penetrating the substrate in the dummy pixel region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2018-0121588, filed on October 12, 2018, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The exemplary embodiments disclosed herein relate to image sensors and methods of manufacturing image sensors. Background Technology

[0004] An image sensor is a semiconductor device used to convert optical images into electrical signals. With the development of the computer and communications industries, there is a strong demand for high-performance image sensors in various devices, such as digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, and medical miniature cameras. Summary of the Invention

[0005] According to an exemplary embodiment of the present invention, an image sensor may include: a substrate including an active pixel region and a dummy pixel region; and a pixel isolation structure configured to at least partially penetrate the substrate, wherein the pixel isolation structure is configured to reduce the conductivity between active pixels in the active pixel region and dummy pixels in the dummy pixel region.

[0006] According to an exemplary embodiment of the present invention, an image sensor may include: an active pixel region including an active pixel; a dummy pixel region including a dummy pixel; a second dummy pixel region; and a pixel isolation structure configured to reduce conductivity between the dummy pixel and the second dummy pixel region.

[0007] According to an exemplary embodiment of the present invention, an image sensor may include: a substrate comprising at least two pixel regions, the at least two pixel regions including an active pixel region and a dummy pixel region; and a pixel isolation structure located in the substrate, configured to reduce conductivity between the at least two pixel regions and having a lattice shape. Attached Figure Description

[0008] Figure 1 This is a block diagram of an image sensor according to an example embodiment.

[0009] Figure 2 This is a schematic circuit diagram of the pixel array of an image sensor according to an example embodiment.

[0010] Figure 3 This is a circuit diagram of the pixel array of an image sensor according to an example embodiment.

[0011] Figure 4This is a plan view of an image sensor according to an example embodiment.

[0012] Figure 5A yes Figure 4 A magnified view of part A.

[0013] Figure 5B It is along Figure 5A The cross-sectional view taken from line I-I'.

[0014] Figure 5C It is along Figure 5A The cross-sectional view taken from line II-II'.

[0015] Figure 6 This is a diagram of an image sensor according to an example embodiment.

[0016] Figure 7A This is a diagram of an image sensor according to an example embodiment.

[0017] Figure 7B It is along Figure 7A The cross-sectional view taken from line III-III'.

[0018] Figure 8 This is a diagram of an image sensor according to an example embodiment. Detailed Implementation

[0019] Various exemplary embodiments will now be described more fully below with reference to the accompanying drawings. Similar reference numerals may refer to similar elements throughout the text.

[0020] Some imaging devices are designed to generate images based on input from a pixel array. This generation may include processes such as comparing digital signals with background noise, such as electrical current. This comparison may include comparing active pixels with dummy pixels, where the dummy pixels are structurally similar to the active pixels but are not included in the generation of the photoelectric signal. It is desirable to provide electrical insulation between the regions of the active and dummy pixels to reduce currents that might otherwise occur between them and alter the performance of the imaging device.

[0021] Figure 1 This is a block diagram of an image sensor according to an example embodiment of the technology presented herein.

[0022] Reference Figure 1 The image sensor according to the example embodiment may include a pixel array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and / or an input / output (I / O) buffer 8.

[0023] The pixel array 1 may include multiple unit pixels arranged in rows and / or columns, and can convert light incident on the unit pixels into electrical signals.

[0024] The pixel array 1 can be driven by multiple drive signals (such as select signals, reset signals, and / or charge transfer signals) provided by the row decoder 2.

[0025] The line decoder 2 can provide a drive signal to the unit pixels in each row. In addition, the electrical signal converted by the pixel array 1 in response to the drive signal can be provided to the associated double sampler 6.

[0026] The row driver 3 can provide multiple driving signals for driving the plurality of unit pixels to the pixel array 1 based on the result decoded by the row decoder 2. When the unit pixels are arranged in rows and / or columns, the driving signals can be provided to the unit pixels in each row.

[0027] The timing generator 5 can control the row decoder 2 and / or column decoder 4, the correlated double sampler 6, the analog-to-digital converter 7 and / or the input / output buffer 8, and can provide control signals for their operation, such as clock signals, timing control signals, etc. The timing generator 5 may include logic control circuits, phase-locked loop circuits, timing control circuits, communication interface circuits, etc.

[0028] The correlated double sampler 6 can hold and sample the output signal generated from the pixel array 1. For example, the correlated double sampler 6 can double sample the signal level at a certain noise level and / or electrical signal level, thereby outputting a difference level corresponding to the difference between the noise level and the signal level.

[0029] The analog-to-digital converter 7 can convert the analog signal corresponding to the difference level output from the correlated dual sampler 6 into a digital signal and can output the digital signal.

[0030] The input / output buffer 8 latches the digital signal output from the analog-to-digital converter 7. The latched signal can be sequentially output to the image signal processing unit according to the result of decoding by the column decoder 4.

[0031] Figure 2 This is a schematic circuit diagram of the pixel array of an image sensor according to an example embodiment.

[0032] Reference Figure 2 The pixel array 1 may include multiple pixel regions P arranged two-dimensionally along rows and / or columns. An electrical signal can be generated in each pixel region P by incident light. The pixel regions P can be driven by a drive signal transmitted via a pixel select line SEL, a charge transfer line Tx, and / or a reset line Rx connected to the pixel regions P. The converted electrical signals in the pixel regions P can be provided to the control circuit via the output line Vout.

[0033] Figure 3 This is a circuit diagram of the pixel array of an image sensor according to an example embodiment.

[0034] Reference Figure 3 The pixel array 1 may include multiple pixel regions P, which may be arranged in a matrix along the row and / or column directions. Pixel region P may include a first photoelectric conversion element PD1 and a second photoelectric conversion element PD2, transmission transistors TX1 and TX2, and / or logic transistors RX, SX, and DX. Logic transistors RX, SX, and DX may include a reset transistor RX, a select transistor SX, and / or a drive transistor (or source follower transistor) DX. The gate electrodes of the first transmission transistor TX1 and the second transmission transistor TX2, the reset transistor RX, and the select transistor SX may be connected to drive signal lines TG1, TG2, RG, and SG, respectively.

[0035] The first transmission transistor TX1 may include a first transmission gate and a first photoelectric conversion element PD1. The second transmission transistor TX2 may include a second transmission gate and a second photoelectric conversion element PD2. The first transmission transistor TX1 and the second transmission transistor TX2 may share a charge detection node (i.e., a floating diffusion region) FD.

[0036] The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 can generate and accumulate photocharge in proportion to the amount of incident light from the outside. The first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 may each include a photodiode, a phototransistor, an optical gate, a pinned photodiode, or a combination thereof.

[0037] The first and second transmission gates can transfer the accumulated charge in the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2 to the charge detection node FD. Complementary signals can be applied to the first and second transmission gates. In other words, charge can be transferred from either the first photoelectric conversion element PD1 or the second photoelectric conversion element PD2 to the charge detection node FD.

[0038] The charge detection node FD can receive and store the charge generated from the first photoelectric conversion element PD1 and the second photoelectric conversion element PD2. The driving transistor DX can be controlled according to the amount of charge accumulated in the charge detection node FD.

[0039] The reset transistor RX periodically resets the accumulated charge in the charge detection node FD. The drain of the reset transistor RX can be connected to the charge detection node FD, and the source of the reset transistor RX can be connected to the power supply voltage V. DD When the reset transistor RX is turned on, the power supply voltage V connected to the source electrode of the reset transistor RX is...DD It can be transferred to the charge detection node FD. Therefore, when the reset transistor RX is turned on, the charge accumulated in the charge detection node FD can be discharged, so that the charge detection node FD can be reset.

[0040] The driving transistor DX can be combined with a constant current source located outside the pixel region P to serve as a source follower buffer amplifier, so that the driving transistor DX can amplify the potential change value at the charge detection node FD and output the amplified value to the output line Vout.

[0041] The selector transistor SX allows for the selection of pixel regions P to be read, line by line. When the selector transistor SX is turned on, the power supply voltage V connected to the drain electrode of the drive transistor DX is... DD It can be transferred to the drain electrode of the select transistor SX.

[0042] Figure 4 This is a plan view of an image sensor according to an example embodiment. Figure 5A Discuss in more detail in the context of Figure 4 Examples of part A.

[0043] Reference Figure 4 Image sensor 10 may include an active pixel region APR and a dummy pixel region DPR. In a plan view, the active pixel region APR may be located in the central region of image sensor 10, and the dummy pixel region DPR may be located in the peripheral region of image sensor 10. The dummy pixel region DPR may surround the active pixel region APR. The active pixel region APR may be the region in which active pixels may be located. The dummy pixel region DPR may be the region in which dummy pixels may be located. The active pixel may correspond to a reference. Figure 2 and Figure 3 The pixel region P is described. Each dummy pixel may have a similar structure to each active pixel, but may not perform operations similar to those of each active pixel (i.e., receiving light and generating photoelectric signals). In an example embodiment, the image sensor 10 may include a peripheral region in which peripheral circuitry may be located.

[0044] Figures 5A to 5C This is a diagram of an image sensor according to an example embodiment. Figure 5A yes Figure 4 A magnified view of part A. Figure 5B It is along Figure 5A The cross-sectional view taken from line I-I'. Figure 5C It is along Figure 5A The cross-sectional view taken from line II-II'.

[0045] Reference Figures 5A to 5CThe image sensor 10 may include a substrate 100. The substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. In an example embodiment, the first surface 100a may be the front surface of the substrate 100, and the second surface 100b may be the rear surface of the substrate 100. Circuitry may be located on the first surface 100a of the substrate 100. Light may be incident on the second surface 100b of the substrate 100. In an example embodiment, the substrate 100 may be a silicon substrate doped with a first conductivity type impurity (e.g., an n-type impurity). In an example embodiment, the substrate 100 may be one of the following: a germanium substrate, a silicon-germanium substrate, a group II-V compound semiconductor substrate, a group III-V compound semiconductor substrate, and / or a silicon-on-insulator (SOI) substrate. In an example embodiment, the concentration of the first conductivity type impurity in the substrate 100 may decrease in the direction from the first surface 100a to the second surface 100b.

[0046] The substrate 100 may include an active pixel region (APR) and a dummy pixel region (DPR). The active pixel region (APR) may be one region of the substrate 100, and the dummy pixel region (DPR) may be another region of the substrate 100.

[0047] Active pixel access points (APs) can be set within active pixel regions (APRs). Active pixel APs can correspond to references. Figure 2 and Figure 3 The pixel region P is described. Dummy pixels DP can be set in the dummy pixel region DPR. Each dummy pixel DP may have the same or similar structure as each active pixel AP, but may not perform operations similar to those of each active pixel AP (i.e., receiving light and generating photoelectric signals).

[0048] A pixel isolation structure (PIS) may be located in a substrate 100 and configured to reduce conductivity between multiple unit pixel regions arranged in a matrix along a first direction D1 and a second direction D2. A unit pixel region may refer to a region including both the region where an active pixel (AP) is located and the region where a dummy pixel (DP) is located. In a planar view, the pixel isolation structure (PIS) may surround each unit pixel region. In an example embodiment, the pixel isolation structure (PIS) may include a first portion extending parallel to the first direction D1 and a second portion intersecting the first portion and extending parallel to the second direction D2. In a planar view, the pixel isolation structure (PIS) may have a lattice shape.

[0049] The pixel isolation structure (PIS) may be configured to at least partially penetrate the substrate 100. The PIS may extend vertically from a first surface 100a to a second surface 100b of the substrate 100. The vertical thickness of the PIS may be substantially the same as the vertical thickness of the substrate 100. The PIS may include deep trench isolation (DTI) located in the substrate 100. The PIS may also include front-side deep trench isolation (FDTI) formed by etching the substrate 100 from the first surface 100a to the second surface 100b and depositing material.

[0050] A pixel isolation structure (PIS) may include a first insulating layer 103 and a first conductor 102 located on the first insulating layer 103. In an example embodiment, the first insulating layer 103 may include an electrically insulating material, such as silicon oxide, silicon nitride, air, or a combination thereof. In an example embodiment, the first conductor 102 may include a conductive material, such as undoped polysilicon, metal silicide, a metal-containing layer, or a combination thereof. After forming a trench defining the shape of the pixel isolation structure (PIS), the first insulating layer 103 may be formed along the inner surface of the trench, and the first conductor 102 may be formed to fill the trench having the first insulating layer 103.

[0051] The dummy pixel region DPR may include a first dummy pixel region DPR1 and a second dummy pixel region DPR2. The first dummy pixel region DPR1 may be the region between the conductive contact 140 and the active pixel region APR. The second dummy pixel region DPR2 may be the remaining region of the dummy pixel region DPR excluding the first dummy pixel region DPR1.

[0052] The conductive contact 140 can be electrically connected to external wiring and can apply a negative voltage to the pixel isolation structure (PIS). The conductive contact 140 can be connected to the first conductor 102 of the pixel isolation structure (PIS). When a negative voltage is applied through the conductive contact 140, holes in the substrate 100 can move toward the interface of the pixel isolation structure (PIS) and accumulate therein. Therefore, dark current generation in the image sensor can be reduced. As shown, the conductive contact 140 can be disposed on the second surface 100b of the substrate 100. In an example embodiment, the conductive contact 140 can be disposed on the first surface 100a of the substrate 100.

[0053] Multiple dummy pixels (DPs) can be set in a first dummy pixel region (DPR1). The first dummy pixel region (DPR1) may include multiple adjacent dummy pixel DPs. In an example embodiment, as shown in the figure, the first dummy pixel region (DPR1) may include three dummy pixel DPs. However, the number of dummy pixels is not limited to this.

[0054] In an example embodiment, the first dummy pixel region DPR1 includes a dummy isolation structure DIS. The dummy isolation structure DIS may be located in the substrate 100 of the first dummy pixel region DPR1. The dummy isolation structure DIS may be located in a dummy pixel DP in a planar view and may divide the dummy pixel DP into at least two parts. (Refer to...) Figure 5A The dummy isolation structure DIS may have a line shape extending in the second direction D2. However, the direction and shape of the dummy isolation structure DIS are not limited to this.

[0055] In an example embodiment, the dummy isolation structure DIS may be configured to at least partially penetrate the substrate 100. The dummy isolation structure DIS may extend vertically from a first surface 100a to a second surface 100b of the substrate 100. The vertical thickness of the dummy isolation structure DIS may be substantially the same as the vertical thickness of the substrate 100. The dummy isolation structure DIS may include a deep trench isolation (DTI) located in the substrate 100. The dummy isolation structure DIS may include a front-side deep trench isolation (FDTI) formed by etching the substrate 100 from the first surface 100a to the second surface 100b of the substrate 100 and depositing material.

[0056] In an example embodiment, the dummy isolation structure DIS may include a second insulating layer 123 and a second conductor 122 located on the second insulating layer 123. In an example embodiment, the second insulating layer 123 may include an electrically insulating material, such as silicon oxide, silicon nitride, air, or a combination thereof. In an example embodiment, the second conductor 122 may include a conductive material, such as undoped polysilicon, metal silicide, a metal-containing layer, or a combination thereof. After establishing a trench serving as the dummy isolation structure DIS, the second insulating layer 123 may be established along the inner surface of the trench, and the second conductor 122 may be established to fill the trench having the second insulating layer 123.

[0057] In example embodiments, the dummy isolation structure DIS may have the same structure and / or electrical insulating material as the pixel isolation structure PIS described above. In example embodiments, the dummy isolation structure DIS is connected to the pixel isolation structure PIS. In example embodiments, the dummy isolation structure DIS is integrally coupled to the pixel isolation structure PIS. In some example embodiments, the dummy isolation structure DIS may be part of the pixel isolation structure PIS.

[0058] In the example embodiment, the dummy isolation structure DIS is not disposed in the second dummy pixel region DPR2. In the example embodiment, the conductive contact 140 is not disposed in the second dummy pixel region DPR2.

[0059] Reference Figure 5B and Figure 5CSince the dummy isolation structure DIS is disposed within the dummy pixel DP in the first dummy pixel region DPR1, the distance DD1 between the dummy isolation structure DIS in the first dummy pixel region DPR1 and its adjacent pixel isolation structure PIS can be smaller than the distance AD ​​between adjacent pixel isolation structures PIS in the active pixel region APR. In an example embodiment, the distance DD1 between adjacent pixel isolation structures PIS in the first dummy pixel region DPR1 can be smaller than the distance AD ​​between adjacent pixel isolation structures PIS in the active pixel region APR. The distance DD2 between adjacent pixel isolation structures PIS in the second dummy pixel region DPR2 can be the same as the distance AD ​​between adjacent pixel isolation structures PIS in the active pixel region APR. The distance AD ​​between adjacent pixel isolation structures PIS can substantially correspond to the width of each unit pixel AP and DP. Since unit pixels AP and DP can have similar sizes and / or shapes, the distance between pixel isolation structures PIS in the region where the dummy isolation structure DIS is disposed (i.e., the first dummy pixel region DPR1) can be relatively small.

[0060] To suppress dark current generation, a negative voltage can be applied to the dummy pixel region DPR via the conductive contact 140. Therefore, there may be a need to isolate the dummy pixel region DPR from the active pixel region APR (where the active pixel AP, to which a ground voltage is applied, is located).

[0061] In the example embodiment, the dummy isolation structure DIS is located within a portion of the dummy pixel region DPR (such as a first dummy pixel region DPR1), effectively isolating the first dummy pixel region DPR1. In the example embodiment, by adjusting the layout of some regions, the isolation between the dummy pixel region DPR and the active pixel region APR can be improved without additional processing. Therefore, an image sensor with improved electrical characteristics can be provided.

[0062] In an example embodiment, the dummy isolation structure DIS may be disposed in each dummy pixel DP in the first dummy pixel region DPR1. In an example embodiment, the dummy isolation structure DIS may be disposed in some dummy pixels DP in the first dummy pixel region DPR1.

[0063] In an example embodiment, the photoelectric conversion element PD may be located in the substrate 100 of each active pixel AP. In an example embodiment, the photoelectric conversion element PD may be spaced apart from the first surface 100a of the substrate 100. The photoelectric conversion element PD may be an n-type impurity doped region. A well region 107 may be located in the substrate 100 of the active pixel AP. The well region 107 may be adjacent to the first surface 100a of the substrate 100. The well region 107 may be a p-type impurity doped region.

[0064] In an example embodiment, the isolation layer 105 may be adjacent to the first surface 100a of the substrate 100 and configured to reduce the conductivity between the first active portion ACT1 and the second active portion ACT2. The isolation layer 105 may be located in the well region 107. The first active portion ACT1 and the second active portion ACT2 may be located in each active pixel AP. The first active portion ACT1 and the second active portion ACT2 may be a portion of the well region 107. The first active portion ACT1 and the second active portion ACT2 may be spaced apart from each other in each active pixel AP and / or may have different sizes. In an example embodiment, refer to Figure 5A The second active part ACT2 can be located between the first active parts ACT1 in adjacent active pixels AP.

[0065] In an example embodiment, the transmission gate TG is located on the first active portion ACT1 in each active pixel AP, and in an example embodiment, the floating diffusion region FD is located in the first active portion ACT1 in each active pixel AP, and the floating diffusion region FD is adjacent to the first surface 100a of the substrate 100. In an example embodiment, the floating diffusion region FD is a region doped with impurities of the opposite conductivity type to the impurities doped in the well region 107. In an example embodiment, the floating diffusion region FD may be an n-type impurity doped region. In an example embodiment, the transmission gate TG may be located on the first surface 100a of the substrate 100 and / or adjacent to the floating diffusion region FD.

[0066] The logic transistor may be located in the second active portion ACT2 of the active pixel AP. The logic transistor may include at least one of the following: a reset transistor (see...) Figure 3 RX), source follower transistor (see RX), source follower transistor (see RX) Figure 3 (DX) and selection transistor (see Figure 3 (SX). Two adjacent active pixels (APs) can share a logic transistor.

[0067] Wiring structure 110 may be located on a first surface 100a of substrate 100. Wiring structure 110 may include at least one logic transistor, and wiring 113 and contact plugs 115 connected to the logic transistor. Interlayer insulating layers 111a, 111b, and / or 111c may be stacked on the first surface 100a of substrate 100. Interlayer insulating layers 111a, 111b, and / or 111c may cover transmission gate TG. A plurality of contact plugs 115 and / or a plurality of wirings 113 may be located in interlayer insulating layers 111a, 111b, and 111c. Logic transistors may be electrically connected to floating diffusion region FD via contact plugs 115.

[0068] The color filter CF and microlens 150 may be located on the first surface 100a of the substrate 100. An antireflective layer 132, a first upper insulating layer 134, and a second upper insulating layer 136 may be located between the second surface 100b of the substrate 100 and the color filter CF. The antireflective layer 132 prevents light reflection, allowing light incident on the second surface 100b of the substrate 100 to smoothly reach the photoelectric conversion element PD. The second upper insulating layer 136 may cover the conductive contact 140.

[0069] The color filter CF and microlens 150 may correspond to each active pixel AP. Depending on the unit pixel, the color filter CF may include a red color filter, a green color filter, or a blue color filter. The color filter CF may be arranged in two dimensions and may include a yellow color filter, a magenta color filter, and / or a cyan color filter. In an example embodiment, the color filter CF may include a white color filter.

[0070] The microlens 150 may have a convex shape and / or a predetermined radius of curvature. The microlens 150 may include a transparent resin configured to focus incident light onto each active pixel AP.

[0071] In an example embodiment, the pixel isolation structure PIS and the dummy isolation structure DIS may have substantially uniform widths along one direction. In an example embodiment, the width of the pixel isolation structure PIS and / or the width of the dummy pixel structure DIS may gradually decrease in the direction from the first surface 100a of the substrate 100 to the second surface 100b of the substrate 100.

[0072] The following describes a method for manufacturing an image sensor according to an example embodiment.

[0073] A substrate 100 may be provided with a first conductivity type (e.g., p-type). The substrate 100 may have a first surface 100a and a second surface 100b opposite to each other. The first surface 100a may be a front surface, and the second surface 100b may be a rear surface. The substrate 100 may have a structure in which a first conductivity type epitaxial layer is located on a first conductivity type bulk silicon substrate. In an example embodiment, the substrate 100 is a bulk semiconductor substrate including a first conductivity type well.

[0074] The isolation layer 105 may be located in the substrate 100 adjacent to the first surface 100a of the active pixel region APR, just like the first active portion ACT1 and the second active portion ACT2. The isolation layer 105 may be etched in the first surface 100a of the substrate 100 to form a shallow trench and / or an insulating material may be deposited in the shallow trench.

[0075] A pixel isolation structure (PIS) associated with an active pixel (AP) and a virtual isolation structure (DIS) associated with a virtual pixel (DP) can be established.

[0076] A deep trench can be formed by patterning the first surface 100a of the substrate 100 and filling the deep trench with insulating material and conductor to establish a pixel isolation structure (PIS) and a dummy isolation structure (DIS). Multiple active pixels (AP) and multiple dummy pixels (DP) can be arranged in a matrix shape along a first direction D1 and a second direction D2 that intersect each other.

[0077] The photoelectric conversion element PD can be located in the substrate 100 of the active pixel region APR. The photoelectric conversion element PD can be formed using a mask having an opening corresponding to the corresponding active pixel AP, and using the mask to dope the substrate 100 with a second conductivity type (e.g., n-type) impurity different from the first conductivity type impurity. Subsequently, the mask can be removed. A well region 107 of the first conductivity type can be formed before or after the formation of the photoelectric conversion element PD. A transmission gate TG can be formed on the first surface 100a of the substrate 100, and a floating diffusion region FD can be formed in the substrate 100.

[0078] A wiring structure 110 may be formed on a first surface 100a of substrate 100. The wiring structure 110 may include logic transistors, wiring 113 connected to the logic transistors, and contact plugs 115. Interlayer insulating layers 111a, 111b, and 111c may be stacked on the first surface 100a of substrate 100 and may cover the transmission gate TG. A plurality of contact plugs 115 and a plurality of wirings 113 may be located in the interlayer insulating layers 111a, 111b, and 111c.

[0079] A thinning process can be performed to remove a portion of the substrate 100 to reduce the vertical thickness of the substrate 100. The thinning process may include grinding or polishing the second surface 100b of the substrate 100 and performing isotropic and / or anisotropic etching processes. The top and bottom of the substrate 100 may be inverted to make the substrate 100 thinner. A portion of the substrate 100 can be removed by grinding or polishing, and isotropic and / or anisotropic etching processes can subsequently be performed to remove surface defects of the substrate 100.

[0080] As the second surface 100b of the substrate 100 is thinned, the surfaces of the pixel isolation structure PIS and the dummy isolation structure DIS are exposed. Therefore, the exposed surfaces of the pixel isolation structure PIS and the dummy isolation structure DIS can be located at the same horizontal height as the second surface 100 of the substrate 100.

[0081] An anti-reflective layer 132, a conductive contact 140, and / or a first upper insulating layer 134 and a second upper insulating layer 136 may be located on the second surface 100b of the substrate 100. A color filter CF and a microlens 150 may be located on the second upper insulating layer 136 corresponding to the corresponding active pixel region APR.

[0082] Figure 6 Figure 7 illustrates some example embodiments. Figure 5A Compared to example embodiments that include a dummy isolation structure DIS with a substantially linear shape in a plan view, Figure 6 An example embodiment is presented, including a dummy isolation structure that has a substantially cross shape in the plan view, and Figure 7A An example embodiment is presented, which includes a dummy isolation structure that has a substantially block shape in the plan view.

[0083] Figure 6 This is an illustration of an image sensor according to an example embodiment, and is Figure 4 A magnified view of part A. The comparison with the reference will be simplified or omitted. Figures 5A to 5C Descriptions of the same components.

[0084] Reference Figure 6 The image sensor may include a dummy isolation structure DISa having a substantially cross shape in the planar view. In an example embodiment, the pixel isolation structure PIS may be denser in the first dummy pixel region DPR1 compared to other regions (e.g., the second dummy pixel region DPR2 and the active pixel region APR). In an example embodiment, the shape and / or size of the dummy isolation structure DISa may vary and is not limited to a cross shape.

[0085] Figure 7A This is an illustration of an image sensor according to an example embodiment, and is Figure 4 A magnified view of part A. Figure 7B It is along Figure 7A The cross-sectional view taken from line III-III'. The comparison with the reference will be simplified or omitted. Figures 5A to 5C Descriptions of the same components.

[0086] Reference Figure 7AThe image sensor may include a dummy isolation structure DISb located between adjacent dummy pixels DP in a planar view. The dummy isolation structure DISb may be connected to a pixel isolation structure PIS between adjacent dummy pixels DP. In the planar view, the dummy isolation structure DISb may have a substantially block shape, located in the central region of the pixel isolation structure PIS between adjacent dummy pixels DP. The dummy isolation structure DISb may extend inward toward the interior of the adjacent dummy pixels DP. At least some of the dummy pixels DP in the first dummy pixel region DPR1 may include a central portion with a width narrower than the width of its peripheral portions.

[0087] Reference Figure 7B The distance DD3 between the dummy isolation structure DISb and the pixel isolation structure PIS in the first dummy pixel region DPR1 can be less than the distance AD ​​between adjacent pixel isolation structures PIS in the active pixel region APR. In other words, the distance DD3 between the pixel isolation structures PIS in the first dummy pixel region DPR1 can be less than the distance AD ​​between adjacent pixel isolation structures PIS in the active pixel region APR.

[0088] In an example embodiment, since the dummy isolation structure DISb is located in the central region between adjacent dummy pixels DP in the first dummy pixel region DPR1, a space can be formed between adjacent dummy pixels DP, providing an etched edge between the dummy pixels DP. In other embodiments, the pixel isolation structure PIS is etched into the substrate 100 from the first surface 100a toward the second surface 100b, and the etched edge between adjacent dummy pixels DP is not located in a region adjacent to the second surface 100b of the substrate 100. In the example embodiment, the central region between the dummy pixels DP is over-etched compared to the peripheral region of the dummy pixels DP.

[0089] Figure 8 This is an illustration of an image sensor according to an example embodiment, and is Figure 4 A magnified view of part A. The comparison with the reference will be simplified or omitted. Figures 5A to 5C and Figure 7A and

[0090] Figure 7B Descriptions of the same components.

[0091] Figure 8 An image sensor comprising two dummy isolation structures (identified as DIS and DISb) is presented. A first dummy pixel region DPR1 includes the dummy isolation structure DIS within a dummy pixel DP and a dummy isolation structure DISb located between adjacent dummy pixels DP. In an example embodiment, the dummy isolation structure DIS may have a linear shape, but the shape and / or size of the dummy isolation structure DIS may vary.

[0092] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth in the appended claims.

Claims

1. An image sensor, comprising: The substrate includes an active pixel region and a dummy pixel region; A conductive contact that is connected to a portion of the dummy pixel area; A pixel isolation structure configured to at least partially penetrate the substrate and surround active pixels in the active pixel region and dummy pixels in the dummy pixel region, wherein the pixel isolation structure is configured to reduce the conductivity between active pixels in the active pixel region and dummy pixels in the dummy pixel region; and A dummy isolation structure is located in the dummy pixel region between the conductive contact and the active pixel region, and is configured to at least partially penetrate the substrate of the dummy pixel region. Wherein, the distance between the dummy isolation structure in the dummy pixel region and its adjacent pixel isolation structure is less than the distance between adjacent pixel isolation structures in the active pixel region, and The pixel isolation structure includes a first conductor, the conductive contact is connected to the first conductor in the dummy pixel region, and the dummy isolation structure includes a second conductor.

2. The image sensor according to claim 1, wherein, The pixel isolation structure is an isolation trench located between the active pixel and the dummy pixel, and the isolation trench is at least partially filled with an electrically insulating material.

3. The image sensor according to claim 1, wherein, In the plan view, the dummy isolation structure is located in the dummy pixel region.

4. The image sensor according to claim 3, wherein, In a plan view, the dummy isolation structure has a substantially line shape, a substantially cross shape, or a substantially block shape.

5. The image sensor according to claim 1, in, The dummy pixel region located between the conductive contact and the active pixel region includes at least two adjacent dummy pixels, and The dummy isolation structure is located between the at least two adjacent dummy pixels.

6. The image sensor according to claim 5, wherein, The dummy isolation structure is connected to the pixel isolation structure between the adjacent dummy pixels.

7. The image sensor according to claim 1, in, The pixel isolation structure includes an electrically insulating material, and The virtual isolation structure also includes the electrical insulation material.

8. The image sensor according to claim 1, in, The pixel isolation structure further includes a first insulating layer, and the first conductor is located on the first insulating layer.

9. The image sensor according to claim 1, wherein, The conductive contact is configured to apply a negative voltage to the dummy pixel region.

10. The image sensor according to claim 1, in, The dummy isolation structure also includes a second insulating layer, and the second conductor is located on the second insulating layer.

11. An image sensor, comprising: Active pixel region, which includes active pixels; The first dummy pixel region includes dummy pixels; Second virtual pixel area; A conductive contact is connected to a portion of the first dummy pixel region, wherein the first dummy pixel region is located between the conductive contact and the active pixel region; A pixel isolation structure surrounding the active pixels of the active pixel region and the dummy pixels of the first dummy pixel region; and A dummy isolation structure, located in the first dummy pixel region, is configured to reduce the conductivity between the dummy pixel and the second dummy pixel region. Wherein, the distance between the dummy isolation structure in the first dummy pixel region and its adjacent pixel isolation structure is less than the distance between adjacent pixel isolation structures in the active pixel region, and The pixel isolation structure includes a first conductor, the conductive contact is connected to the first conductor in the first dummy pixel region, and the dummy isolation structure includes a second conductor.

12. The image sensor according to claim 11, further comprising: The substrate, wherein the active pixel region and the first dummy pixel region are located on the substrate; The pixel isolation structure is configured to at least partially penetrate the substrate and is configured to reduce the conductivity between the active pixel in the active pixel region and the dummy pixel in the first dummy pixel region.

13. The image sensor according to claim 12, wherein, The dummy isolation structure is configured to penetrate the substrate at least partially.

14. The image sensor according to claim 12, in, The pixel isolation structure includes an electrically insulating material, and The virtual isolation structure also includes the electrical insulation material.

15. The image sensor according to claim 11, wherein, The virtual isolation structure also includes an insulating layer.

16. The image sensor according to claim 11, wherein, In a plan view, the dummy isolation structure has a substantially line shape, a substantially cross shape, or a substantially block shape.

17. An image sensor, comprising: A substrate comprising at least two pixel regions, the at least two pixel regions comprising an active pixel region and a dummy pixel region; A conductive contact that is connected to at least a portion of the dummy pixel region; and A pixel isolation structure, located in the substrate, surrounds active pixels in the active pixel region and dummy pixels in the dummy pixel region, and is configured to reduce conductivity between the at least two pixel regions and has a lattice shape. The dummy pixel region includes a first dummy pixel region and a second dummy pixel region, wherein the first dummy pixel region is located between the conductive contact and the active pixel region. Wherein, the distance between the first adjacent portions of the pixel isolation structure in the first dummy pixel region is less than the distance between the second adjacent portions of the pixel isolation structure in the active pixel region. Wherein, the distance between the third adjacent portions of the pixel isolation structure in the second dummy pixel region is the same as the distance between the second adjacent portions of the pixel isolation structure in the active pixel region, and The pixel isolation structure includes a first conductor, and the conductive contact is connected to the first conductor in the dummy pixel region.

18. The image sensor according to claim 17, wherein, The pixel isolation structure is configured to penetrate the substrate at least partially.

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