Active Silicon On Package Semiconductor Packaging

Abstract

Systems and methods for providing a low profile stacked die semiconductor package, wherein a first semiconductor package is stacked with a second semiconductor package, and both semiconductor packages are conductively coupled to an active silicon substrate that communicatively couples the first semiconductor package to the second semiconductor package. The first semiconductor package may be conductively coupled to the active silicon substrate using a plurality of interconnects arranged in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may be conductively coupled to the active silicon substrate using a plurality of interconnects arranged in a second interconnect pattern having a second pitch, the second pitch being greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of bond wires.

Description

Technical Field

[0001] The present disclosure relates to the fabrication of stacked package semiconductors. Background Art

[0002] Package stacking (PoP) is an integrated circuit packaging technology in which multiple ball grid arrays (BGAs) are arranged vertically. PoP packaging beneficially reduces the board area occupied by each semiconductor package. PoP packaging also minimizes the track length between components that often interoperate. Minimizing track length provides faster signal propagation, reduced noise, and reduced channel cross-talk. In an assembly, PoP packaging permits testing of individual components before stacking rather than after stacking (e.g., chip stacking), thereby reducing reprocessing due to the use of only known good components in PoP packaging.

[0003] In a typical PoP integrated circuit, a memory package is stacked with a logic package such as a system on chip (SoC). Often, the stacked packages are stacked and then physically and conductively coupled via repackaging. Since most semiconductor packages generate heat when operating, the heat generated by the semiconductor packages in the stack must be dissipated through a relatively small area. Reduced heat transfer within the PoP package leads to the formation of hot spots within the stack and ultimately leads to premature failure of the PoP package. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Features and advantages of various embodiments of the claimed subject matter will become apparent as the following detailed description proceeds and when reference is made to the accompanying drawings, in which like reference numerals represent like parts, and in which:

[0005] Figure 1 is a cross-sectional elevation view of an illustrative package-on-silicon (PoS) semiconductor package according to at least one embodiment described herein, wherein a first semiconductor package and a second semiconductor package are conductively coupled to an active silicon substrate that communicatively couples the first semiconductor package to the second semiconductor package;

[0006] Figure 2 is a cross-sectional elevation view of an illustrative package-on-silicon (PoS) semiconductor package according to at least one embodiment described herein, the illustrative package-on-silicon (PoS) semiconductor package including a first semiconductor package and a second semiconductor package stacked and physically coupled using an interposer disposed between an upper surface of the first semiconductor package and a lower surface of the second semiconductor package;

[0007] Figure 3is a cross-sectional elevation view of an illustrative package-on-silicon (PoS) semiconductor package according to at least one embodiment described herein, the illustrative package-on-silicon (PoS) semiconductor package comprising a stacked first semiconductor package physically coupled to at least one second semiconductor package, the at least one second semiconductor package being communicatively coupled to an active silicon substrate via a plurality of bond wires;

[0008] Figure 4A depicts an illustrative process according to at least one embodiment described herein for coupling a first semiconductor package to an active semiconductor substrate;

[0009] Figure 4B depicts an illustrative process according to at least one embodiment described herein for encapsulating a first semiconductor package in a molding compound;

[0010] Figure 4C depicts an illustrative process according to at least one embodiment described herein, wherein an active silicon substrate has been thinned to expose through silicon vias;

[0011] Figure 4D depicts an illustrative process according to at least one embodiment described herein, wherein a mold compound proximate to conductive members has been removed, thereby exposing the conductive members, and solder balls have been physically and conductively coupled to at least some of the conductive members;

[0012] Figure 4E depicts an illustrative process according to at least one embodiment described herein, wherein the interposer has been physically coupled to the upper surface of the first semiconductor package by a high thermal conductivity epoxy flux;

[0013] Figure 4F depicts an illustrative process according to at least one embodiment described herein, wherein solder balls have been reflowed over conductive bumps disposed on a lower surface of an active silicon substrate;

[0014] Figure 4G depicts an illustrative process according to at least one embodiment described herein, wherein a package-on-silicon (PoS) semiconductor package has been singulated;

[0015] Figure 4H depicts an illustrative process according to at least one embodiment described herein, wherein an active silicon substrate of a singulated package-on-silicon (PoS) semiconductor package has been conductively coupled to a substrate by reflowing solder balls disposed on a lower surface of the active silicon substrate;

[0016] Figure 5Adepicts an illustrative process according to at least one embodiment described herein for coupling a first semiconductor package to an active semiconductor substrate;

[0017] Figure 5B depicts an illustrative process according to at least one embodiment described herein for conductively coupling a second semiconductor package to an active silicon substrate via a plurality of bond wires and encapsulating the resulting package-on-silicon (PoS) semiconductor package in a molding compound;

[0018] Figure 5C depicts an illustrative process according to at least one embodiment described herein, wherein an active silicon substrate has been thinned to expose through silicon vias (TSVs);

[0019] Figure 5D depicts an illustrative process according to at least one embodiment described herein, wherein solder balls have been reflowed over conductive bumps disposed on a lower surface of an active silicon substrate;

[0020] Figure 5E depicts an illustrative process according to at least one embodiment described herein, wherein a package-on-silicon (PoS) semiconductor package has been diced;

[0021] Fig. 5F depicts an illustrative process according to at least one embodiment described herein, wherein an active silicon substrate of a singulated package-on-silicon (PoS) semiconductor package has been conductively coupled to a substrate by reflowing solder balls disposed on a lower surface of the active silicon substrate;

[0022] Figure 6 is a cross-sectional elevation view of another illustrative package-on-silicon (PoS) semiconductor package according to at least one embodiment described herein, wherein a heat spreader is conductively coupled to a first semiconductor package and a gap exists between the heat spreader and a lower surface of a stacked second semiconductor package;

[0023] Figure 7 is a high-level logic flow diagram of an illustrative method of manufacturing an active package-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein;

[0024] Figure 8 is a high-level logic flow diagram of an illustrative method of manufacturing an active package-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein;

[0025] Fig. 9 is a high-level logic flow diagram of an illustrative method of manufacturing an active package-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein;

[0026] Fig.10is a high-level logical flow diagram of an illustrative method of fabricating an active package-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein.

[0027] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. DETAILED DESCRIPTION

[0028] The systems and methods disclosed herein provide a package-on-silicon (PoS) semiconductor package, wherein a first semiconductor package and a second semiconductor package are stacked on and conductively coupled to an active silicon substrate. The active silicon substrate communicatively couples the first semiconductor package to the second semiconductor package. Typically, the second semiconductor package is disposed above the first semiconductor package, and the first semiconductor package is directly conductively coupled to the active silicon substrate using a plurality of interconnects arranged in a first pattern.

[0029] In embodiments where the footprint of the second semiconductor package extends beyond the footprint of the first semiconductor package, a plurality of conductive members (e.g., copper clad pillars) may extend between conductive structures arranged on the upper surface of the active silicon substrate in a second pattern and conductive structures disposed on the lower surface of the second semiconductor package, and conductively couple the conductive structures arranged on the upper surface of the active silicon substrate in the second pattern to the conductive structures disposed on the lower surface of the second semiconductor package. In such embodiments, the interconnect pitch (i.e., spacing and geometric arrangement) of the first pattern may have a greater density than the interconnect pitch of the second pattern. In such embodiments, the conductive members may be formed on the surface of the active silicon substrate before conductively coupling the second semiconductor package to the conductive members.

[0030] In other embodiments, a plurality of bonding wires may conductively couple the second semiconductor package to the active silicon substrate. In such embodiments, pads or lands disposed across the surface of the active silicon substrate in a second pattern receive each of at least some of the bonding wires conductively coupled to the second semiconductor package. The active silicon substrate includes various conductors, electronic components, logic devices, and / or semiconductor devices for communicatively coupling the first semiconductor package to the second semiconductor package. In such embodiments, the interconnect pitch of the first pattern of interconnects coupling the first semiconductor package to the active silicon substrate may have a greater density than the interconnect pitch of the second pattern of pads or similar conductive structures coupling the second semiconductor package to the active silicon substrate. In such embodiments, pads or other conductive structures may be formed on the surface of the active silicon substrate prior to conductively coupling the second semiconductor package to the conductive member.

[0031] In other embodiments, an interposer may be disposed between an upper surface of the first semiconductor package and a lower surface of the second semiconductor package. In an embodiment, the bottom surface of the interposer may be physically coupled to the first semiconductor package, for example, using a highly thermally conductive epoxy. The second semiconductor package is conductively coupled to an upper surface of the interposer. In some implementations, conductive landing points, pads, or similar structures disposed across all or a portion of the lower surface of the interposer may be conductively coupled to conductive structures extending from a surface of the active silicon substrate. In some implementations, bonding wires may conductively couple conductive landing points, pads, or similar structures disposed across all or a portion of the upper surface of the interposer to conductive structures disposed across the surface of the active silicon substrate in a second pattern.

[0032] A package-on-silicon (PoS) semiconductor package is provided. The PoS semiconductor package may include: an active silicon substrate having: an upper surface; a lower surface; and a plurality of conductive structures disposed across the upper surface; wherein the plurality of conductive structures include: a first portion of the conductive structures disposed across the upper surface of the active silicon substrate in a first pattern; and a second portion of the conductive structures disposed across the upper surface of the active silicon substrate in a second pattern; a first semiconductor package having an upper surface, a lower surface, and a plurality of conductive bumps disposed across the lower surface of the first semiconductor package in the first pattern; wherein the plurality of conductive bumps communicatively couple the first semiconductor package to the first portion of the conductive structures disposed on the active silicon substrate; and a second semiconductor package having an upper surface and a lower surface; the second semiconductor package being disposed such that at least a portion of the first semiconductor package is disposed between the lower surface of the second semiconductor package and the upper surface of the active silicon substrate; and the second semiconductor package being communicatively coupled to at least some of the second portions of the conductive structures disposed on the active silicon substrate via a plurality of conductive members, wherein the active silicon substrate communicatively couples the first semiconductor package to the second semiconductor package.

[0033] A method for manufacturing a package-on-silicon (PoS) semiconductor package is provided. The method may include: conductively coupling each of a plurality of conductive structures disposed on a lower surface of a first semiconductor package to a corresponding portion of a first portion of a conductive structure disposed across an upper surface of an active silicon substrate in a first mode; conductively coupling each of a plurality of conductive structures disposed on a second semiconductor package to a corresponding portion of a second portion of a conductive structure disposed across an upper surface of the active silicon substrate in a second mode; wherein the second semiconductor package is operably coupled to the active silicon substrate such that at least a portion of the first semiconductor package is disposed between at least a portion of the lower surface of the second semiconductor package and an upper surface of the active silicon substrate; and communicatively coupling the first semiconductor package to the second semiconductor package via the active silicon substrate.

[0034] An electronic device incorporating a package-on-silicon (PoS) semiconductor package is provided. The electronic device may include: a substrate having a package-on-silicon (PoS) semiconductor package conductively coupled thereto, the PoS semiconductor package including: an active silicon substrate having a plurality of conductive structures; wherein the plurality of conductive structures may include: a first portion of the conductive structure disposed across at least a portion of an upper surface of the active silicon substrate in a first pattern; and a second portion of the conductive structure disposed across at least a portion of the upper surface of the active silicon substrate in a second pattern; a first semiconductor package having an upper surface, a lower surface, and a plurality of conductive bumps disposed across at least a portion of the lower surface of the first semiconductor package in the first pattern; wherein the plurality of conductive bumps communicatively couple the first semiconductor package to the first portion of the conductive structure disposed on the upper surface of the active silicon substrate; and a second semiconductor package having an upper surface and a lower surface; the second semiconductor package disposed above the upper surface of the first semiconductor package; and the second semiconductor package communicatively coupled to at least some of the second portion of the conductive structure disposed on the upper surface of the active silicon substrate via a plurality of conductive members; wherein the active silicon substrate communicatively couples the first semiconductor package to the second semiconductor package.

[0035] A package-on-silicon (PoS) semiconductor package manufacturing system is provided. The system may include: a component for conductively coupling each of a plurality of conductive structures disposed on a lower surface of a first semiconductor package to a corresponding portion of a first portion of conductive structures disposed across an upper surface of an active silicon substrate in a first pattern; a component for conductively coupling each of a plurality of conductive structures disposed on a second semiconductor package to a corresponding portion of a second portion of conductive structures disposed across an upper surface of the active silicon substrate in a second pattern; wherein the second semiconductor package is operably coupled to the active silicon substrate such that at least a portion of the first semiconductor package is disposed between at least a portion of the lower surface of the second semiconductor package and an upper surface of the active silicon substrate; and the first semiconductor package is communicatively coupled to the second semiconductor package via the active silicon substrate.

[0036] As used herein, the terms "top," "bottom," "upper," "lower," "lowermost," and "uppermost" when used with respect to one or more elements are intended to convey relative, rather than absolute, physical configurations. Thus, an element described as the "uppermost element" or "top element" in a device may conversely form the "lowermost element" or "bottom element" in the device when the device is inverted. Similarly, an element described as the "lowermost element" or "bottom element" in a device may conversely form the "uppermost element" or "top element" in the device when the device is inverted.

[0037] As used herein, the term "logical association" when used with reference to multiple objects, systems, or elements is intended to convey the existence of a relationship between the objects, systems, or elements, such that access to one object, system, or element exposes the remaining objects, systems, or elements that are "logically associated" or "logically associated" with the accessed object, system, or element. There are example "logical associations" between relational databases, where access to an element in a first database can provide information and / or data from one or more elements in multiple additional databases, each of which has an identifying relationship with the accessed element. In another example, if "A" is logically associated with "B", accessing "A" will expose information and / or data from "B" or otherwise extract information and / or data from "B", and vice versa.

[0038] Figure 1 is a cross-sectional elevation view of an illustrative package-on-silicon (PoS) semiconductor package 100 in accordance with at least one embodiment described herein, wherein a first semiconductor package 110 and a second semiconductor package 150 are stacked and conductively coupled to an active silicon substrate 130 that communicatively couples the first semiconductor package 110 to the second semiconductor package 150. The first semiconductor package 110 is conductively coupled to the active silicon substrate 130 using a plurality of interconnects 140 arranged across an upper surface of the active silicon substrate 130 in a first pattern 142. The second semiconductor package 150 is also conductively coupled to the active silicon substrate 130 using a plurality of conductive structures 160 (e.g., conductive pillars) extending from the upper surface of the active silicon substrate 130 and arranged across the upper surface of the active silicon substrate 130 in a second pattern 162. In an embodiment, the density of the first interconnect pattern 142 is greater than the density of the second interconnect pattern 162. In an embodiment, the inter-interconnect distance in the first interconnect pattern 142 (ie, the distance between interconnects 140 ) is smaller than the inter-interconnect distance in the second interconnect pattern 162 (ie, the distance between conductive structures 160 ).

[0039] The active silicon substrate 130 communicatively couples the first semiconductor package 110 to the second semiconductor package 150. In an embodiment, landing pads, pads, or similar conductive elements 132 may be disposed on, across, or around all or a portion of the lower surface of the active silicon substrate 130. Conductive materials such as conductive paste or solder balls 134 may communicatively couple the active silicon substrate 130 to an underlying organic substrate 180, such as a printed circuit board. The active silicon substrate 130 may include any number of conductive couplings, connections, and / or configurable circuits, electrical components, conductive structures, logic elements, and / or semiconductor devices. The active silicon substrate 130 may include any number and / or combination of conductive and / or dielectric layers. The active silicon substrate 130 communicatively couples the first semiconductor package 110 to the second semiconductor package 150. The active silicon layer 130 may have a height of less than about 50 micrometers (μm); about 75 μm; about 100 μm; about 125 μm; about 150 μm; about 175 μm; or about 200 μm. The conductive element 132 that conductively couples the active silicon layer 130 to the underlying organic substrate may have a height of less than about 50 micrometers (μm); about 75 μm; about 100 μm; about 125 μm; about 150 μm; about 175 μm; or about 200 μm.

[0040] In an embodiment, the first semiconductor package 110 is conductively coupled to the active silicon substrate 130 using interconnects 140 arranged in a first interconnect pattern 142. In an embodiment, landing pads, pads, bumps, or similar conductive elements 140 arranged in the first interconnect pattern 142 may be disposed on, around, or across an upper surface of the active silicon substrate 130. In an embodiment, the landing pads, pads, bumps, or similar conductive elements forming the first interconnect pattern 142 may be spaced apart by a distance of less than about 100 micrometers (μm); less than about 80 μm; less than about 60 μm; less than about 50 μm; less than about 40 μm; less than about 30 μm; less than about 20 μm; or less than about 10 μm.

[0041] In an embodiment, the second semiconductor package 150 is conductively coupled to the active silicon substrate using conductive members 160 arranged in a second interconnection pattern 162. In an embodiment, the conductive members 160 arranged in the second interconnection pattern 162 may be disposed on, around, or across the upper surface of the active silicon substrate 130. In an embodiment, the conductive members 160 forming the second interconnection pattern 162 may be spaced apart by a distance greater than about 100 micrometers (μm); greater than about 120 μm; greater than about 140 μm; greater than about 150 μm; greater than about 170 μm; greater than about 190 μm; greater than about 200 μm; or greater than about 220 μm. In some implementations, the conductive members 160 may be formed on, around, or across the upper surface of the active silicon substrate 130 using any currently or future developed deposition technology. In some implementations, the conductive member 160 may include, but is not limited to, a copper-plated member that is conductively coupled to the upper surface of the active silicon substrate 130. In an embodiment, the conductive member 160 may have a height (i.e., may be projected a certain distance from the upper surface of the active silicon substrate 130): about 50 micrometers (μm); about 60 μm; about 70 μm; about 80 μm; about 90 μm; about 100 μm; about 110 μm; about 120 μm; about 130 μm; about 140 μm; or about 150 μm.

[0042] The first semiconductor package 110 may include any number and / or combination of semiconductor dies and / or stacked semiconductor dies having a first high-density interconnect pattern 142 disposed across all or a portion of a bottom surface of the first semiconductor package 110. In an embodiment, a plurality of microbumps 140 may provide the first interconnect pattern 142 on the bottom surface of the first semiconductor package 110. In an embodiment, the first semiconductor package 110 may include a system-on-chip (SoC) semiconductor package, such as from Intel. ® ,Cor. (Santa Clara, Calif.) ® SoC. The first semiconductor package 110 may include one or more semiconductor packages used in a rack-mounted, desktop, or portable processor-based device. In at least some implementations, one or more materials may underflow 190 in a space between a bottom surface of the first semiconductor package 110 and an upper surface of the active silicon substrate 130. In an embodiment, the first semiconductor package 110 may have a height of less than: about 50 micrometers (μm); about 75 μm; about 100 μm; about 125 μm; about 150 μm; or about 200 μm.

[0043] The second semiconductor package 150 may include any number and / or combination of semiconductor dies and / or stacked semiconductor dies having a second interconnect pattern 162 disposed across all or a portion of a peripheral portion of a bottom surface of the second semiconductor package 150 that protrudes and / or extends beyond the periphery of the first semiconductor package 110. In an embodiment, the second semiconductor package 150 may include, but is not limited to: one or more memory and / or storage semiconductor packages; one or more graphics / image processor semiconductor packages; and / or one or more wired or wireless communication interface semiconductor packages.

[0044] As in Figure 1 As depicted in FIG, the lower surface of the second semiconductor package 150 may be physically attached, coupled, and / or bonded to the upper surface of the first semiconductor package using one or more chemically active or thermosetting adhesives (such as a high thermal conductivity adhesive 170 that promotes heat flow upward through the PoS package). In an embodiment, the high thermal conductivity adhesive 170 may have a height (i.e., a depth measured from the lower surface of the second semiconductor package 150 to the upper surface of the first semiconductor package 110) less than: about 5 micrometers (μm); about 10 μm; about 15 μm; about 20 μm; about 25 μm; or about 30 μm.

[0045] In an embodiment, the second semiconductor package 150 may include a plurality of conductive features, such as a plurality of solder balls 152, which when reflowed conductively couple the second semiconductor package 150 to a conductive member 160 extending from the upper surface of the active silicon substrate. In an embodiment, a mold compound 112 may be inserted, deposited, flowed, or otherwise disposed between the lower surface of the second semiconductor package 150 and the upper surface of the active silicon substrate 130.

[0046] Figure 2 is a cross-sectional elevation view of an illustrative package-on-silicon (PoS) semiconductor package 200 according to at least one embodiment described herein, which includes a first semiconductor package 110 and a second semiconductor package 150 stacked and physically coupled using an interposer 210 disposed between an upper surface of the first semiconductor package 110 and a lower surface of the second semiconductor package 150. The first semiconductor package 110 is conductively coupled to an active silicon substrate 130 using a plurality of interconnects 140 disposed across an upper surface of the active silicon substrate 130 in a first pattern 142. The second semiconductor package 150 includes a ball grid array package conductively coupled to a plurality of landing points, pads, or similar conductive features 232 disposed on, around, or across an upper surface of the interposer 210. The interposer 210 includes a plurality of conductive features, such as a plurality of solder balls 222, which when reflowed conductively couple the interposer 210 (and, therefore, the second semiconductor package 150) to a conductive member 160 extending from an upper surface of the active silicon substrate 130.

[0047] The interposer 210 translates the contact pattern or pitch on the lower surface of the second semiconductor package 150 into the second interconnect pattern 162, thereby beneficially enabling the use of BGA and similar second semiconductor packages 150 in the PoS semiconductor package 200. In some implementations, the interposer 210 includes an organic pitch redistribution layer 220 sandwiched between an upper conductive layer 230 and a lower conductive layer 240, the upper conductive layer 230 including and / or incorporating conductive features 232, the lower conductive layer 240 including and / or incorporating a plurality of solder balls 222 for conductively coupling the interposer 210 to the conductive member 160. As shown in Figure 2 As depicted in FIG. 1 , the lower surface of interposer 210 may be physically attached, coupled, and / or bonded to the upper surface of the first semiconductor package using one or more chemically active or thermosetting adhesives, such as high thermal conductivity adhesive 170, which facilitates heat flow laterally and upward through PoS package 200. In an embodiment, interposer 210 may have a height of less than: about 20 micrometers (μm); about 30 μm; about 40 μm; about 50 μm; about 60 μm; about 70 μm; or about 80 μm.

[0048] Figure 3 is a cross-sectional elevation view of an illustrative package-on-silicon (PoS) semiconductor package 300 according to at least one embodiment described herein, which includes a stacked first semiconductor package 110 physically coupled to at least one second semiconductor package 150, the at least one second semiconductor package 150 being communicatively coupled to an active silicon substrate 130 via a plurality of bond wires 310A-310n (collectively referred to as “bond wires 310”). As shown in Figure 3 As depicted in FIG. 1 , the first semiconductor package 110 is conductively coupled to the active silicon substrate 130 using a plurality of interconnects 140 arranged across the upper surface of the active silicon substrate 130 in a first pattern 142. Figure 3 As depicted in the drawings, at least one second semiconductor package 150 may include a plurality of second semiconductor devices 150A-150n (collectively referred to as “second semiconductor packages or devices 150”), each of the plurality of second semiconductor devices 150A-150n being physically attached or coupled to an upper surface of the first semiconductor package 110 using one or more chemically activated or thermosetting adhesives 170.

[0049] As in Figure 3As depicted in FIG. 1 , each of the second semiconductor devices 150A and 150B is conductively coupled to the active silicon substrate 130 via a plurality of bonding wires 310A-310n, each of which extends from a conductive feature disposed on the upper surface of the second semiconductor package or device 150 to a corresponding conductive pad 320A-320n disposed on, across, or around the upper surface of the active silicon substrate 130 using a second interconnect pattern. In an embodiment, such as in FIG. Figure 3 As depicted in FIG. 1 , the underflow material 340 may be disposed between the lower surface of the active silicon substrate 130 and the upper surface of the organic substrate 180 to which the PoS semiconductor package 300A is coupled. Figure 3 As depicted in , the mold compound 330 may be at least partially disposed around the first semiconductor package 110 and the second semiconductor package 150 .

[0050] Figures 4A-4H An illustrative process is depicted for fabricating a package-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein. Figure 4A An illustrative process 400A is depicted for coupling a first semiconductor package 110 to an active silicon substrate 130 in accordance with at least one embodiment described herein. Figure 4A , the active semiconductor substrate 130 may include a plurality of devices, such as electrical components, conductors, logic elements, and semiconductor devices 410, such as semiconductor transistors. A plurality of through silicon vias (TSVs) 414A-414n may extend into the active silicon substrate 130. A plurality of conductive elements 412 may extend upward from the upper surface of the active silicon substrate 130. In an embodiment, each of some or all of the conductive elements 412 may include a nickel pillar 416 with a thin solder bump 418 mounted on the top. In an embodiment, the conductive elements 412 may be arranged using a first interconnect pattern 142.

[0051] A plurality of conductive structures 160A-160n (collectively referred to as "conductive structures 160") are formed, deposited, or otherwise disposed on the upper surface of the active silicon substrate 130 using a second interconnect pattern 162. In an embodiment, the conductive structures 160 may be formed using any currently available or future developed material deposition process, such as electroplating or photolithographic deposition. In an embodiment, the conductive structures 160 may be preformed or attached to the upper surface of the active silicon substrate 130, for example, via solder or via a conductive adhesive. The conductive structures 160 may be formed using any conductive material, such as: copper or a copper-containing alloy; aluminum or an aluminum-containing alloy; a conductive polymer; or a combination thereof. In an embodiment, the conductive structures 160 may have the same or different heights. The conductive structures 160 may have a height greater than: about 50 micrometers (μm); about 75 μm; about 100 μm; about 125 μm; about 150 μm; about 175 μm; or about 200 μm.

[0052] The first semiconductor package 110 includes electronic components, circuits, conductors, logic elements, and semiconductor devices 430, such as semiconductor transistors. The first semiconductor package 110 also includes a plurality of conductive elements 432 arranged or disposed on the lower surface of the first semiconductor package 110 using a first interconnect pattern 142. In an embodiment, each conductive element of some or all of the conductive elements 432 may include a nickel pillar 436 topped with a thin solder bump 438. Epoxy flux 420 may be used to facilitate conductive coupling of the first semiconductor package 110 to the active silicon substrate 130.

[0053] In an embodiment, solder 438 attached to conductive element 432 of first semiconductor package 110 melts and combines with solder 418 attached to conductive element 412 of active silicon substrate 130 to form interconnect 140 that conductively couples first semiconductor package 110 to active silicon substrate 130. In some implementations, cured epoxy flux 420 remains between the lower surface of first semiconductor package 110 and the upper surface of active silicon substrate 130 to provide an underfill for first semiconductor package 110.

[0054] Figure 4B An illustrative process 400B is depicted for encapsulating a first semiconductor package 110 in a mold compound 112 in accordance with at least one embodiment described herein. Figure 4B As depicted in FIG. 1 , the mold compound 112 may be partially or completely disposed around the first semiconductor package 110. In an embodiment, a top surface of the mold compound may be approximately flush with an upper surface of the first semiconductor package 110. In an embodiment, the conductive structure 160 may be covered by and / or encapsulated in the mold compound 112.

[0055] Figure 4CAn illustrative process 400C is depicted in accordance with at least one embodiment described herein, wherein an active silicon substrate 130 has been thinned to expose through silicon vias (TSVs) 412A-412n (collectively, “TSVs 412”). Each of at least some of the TSVs 412 terminates in a respective conductive bump 415A-415n (collectively, “conductive bumps 415”) disposed on a lower surface of the active silicon substrate 130. The active silicon substrate 130 may be thinned using any currently available or future developed thinning method or process, such as chemical / mechanical planarization (CMP). In an embodiment, the conductive bumps 415 may be disposed, deposited, or otherwise formed proximate to each of the TSVs 412 using any currently available or future developed deposition technique, process, or method. For example, the conductive element 415 may be photolithographically deposited or electroplated on the lower surface of the active silicon substrate 130.

[0056] Figure 4D An illustrative process 400D is depicted in accordance with at least one embodiment described herein, wherein the mold compound 112 proximate to the conductive members 160 has been removed, thereby exposing the conductive members 160, and the solder balls 450 have been physically and conductively coupled to at least some of the conductive members 160. In an embodiment, the mold compound 112 proximate to at least some of the conductive members 160 may be removed using any currently available or future developed material removal technique, process, or method. For example, the mold compound 112 proximate to the ends of some or all of the conductive members 160 may be removed via laser ablation.

[0057] In an embodiment, a shallow through mold interconnect (TMI) is formed over each of the conductive members 160, exposing the distal (referenced to the active silicon substrate 130) end of the respective conductive member. The TMI and conductive members 160 are cleaned, and solder paste is applied or printed onto the upper surface of the mold compound 112 and reflowed into the TMI, forming solder balls 450, which are physically and conductively coupled to the respective conductive members 160.

[0058] Figure 4E An illustrative process 400E is depicted in which an interposer 210 has been physically coupled to an upper surface of a first semiconductor package 110 by a high thermal conductivity epoxy flux 170, in accordance with at least one embodiment described herein. The interposer 210 includes an organic pitch redistribution layer 220 sandwiched between an upper conductive layer 230 and a lower conductive layer 240 conductively coupled to solder balls 250 formed on ends of conductive members 160.

[0059] Figure 4FAn illustrative process 400F is depicted in which solder balls 460 have been reflowed onto conductive bumps 415 disposed on the lower surface of active silicon substrate 130 in accordance with at least one embodiment described herein. Figure 4F Reflowed solder balls 460 are depicted in FIG. 4 , but any similar conductive element may be disposed proximate each of at least some of the conductive bumps 415 disposed on the lower surface of the active silicon substrate 130 .

[0060] Figure 4G An illustrative process 400G is depicted in which a package on silicon (PoS) semiconductor package has been cut according to at least one embodiment described herein. The PoS semiconductor package 400G can be cut using any currently available or future developed cutting technology, method, or process. For example, in some implementations, the PoS semiconductor package 400G can be cut using a mechanical or abrasive saw.

[0061] Figure 4H An illustrative process 400H is depicted in accordance with at least one embodiment described herein, wherein a singulated package-on-silicon (PoS) semiconductor package has been conductively coupled to a substrate 480 by reflowing solder balls 460 disposed on a lower surface of an active silicon substrate 130. In an embodiment, an underfill material 470 may flow between the lower surface of the active silicon substrate 130 and an upper surface of the substrate 480. In an embodiment, the substrate 480 may include a printed circuit board having multiple layers of a high-density substrate.

[0062] Figures 5A-5F An illustrative process according to at least one embodiment described herein for fabricating a package-on-silicon (PoS) semiconductor package is depicted in which a plurality of bond wires 310 communicatively couple a second semiconductor package 150 to an active silicon substrate 130 . Figure 5A An illustrative process 500A is depicted for coupling a first semiconductor package 110 to an active semiconductor substrate 130 in accordance with at least one embodiment described herein. Figure 5A , the active semiconductor substrate 130 may include a plurality of devices, such as electrical components, conductors, logic elements, and semiconductor devices 410, such as semiconductor transistors. A plurality of through silicon vias (TSVs) 414A-414n may extend into the active silicon substrate 130. A plurality of conductive elements 412 may extend upward from the upper surface of the active silicon substrate 130. In an embodiment, each of some or all of the conductive elements 412 may include a nickel pillar 416 with a thin solder bump 418 mounted on top. In an embodiment, the conductive elements 412 may be arranged using a first interconnect pattern 142.

[0063] A plurality of conductive pads 320A-320n (collectively referred to as "conductive pads 320") are formed, deposited, or otherwise disposed on the upper surface of the active silicon substrate 130 using the second interconnect pattern 162. In an embodiment, the conductive pads 320 may be formed using any currently available or future developed material deposition process, such as electroplating or photolithographic deposition. The conductive pads 320 may be formed using any conductive material, such as: copper or copper-containing alloys; aluminum or aluminum-containing alloys; conductive polymers; or combinations thereof.

[0064] The first semiconductor package 110 includes electronic components, circuits, conductors, logic elements, and semiconductor devices 430, such as semiconductor transistors. The first semiconductor package 110 also includes a plurality of conductive elements 432 arranged or disposed on the lower surface of the first semiconductor package 110 using a first interconnect pattern 142. In an embodiment, each conductive element of some or all of the conductive elements 432 may include a nickel pillar 436 topped with a thin solder bump 438. Epoxy flux 420 may be used to facilitate conductive coupling of the first semiconductor package 110 to the active silicon substrate 130.

[0065] In an embodiment, solder 438 attached to conductive element 432 of first semiconductor package 110 melts and combines with solder 418 attached to conductive element 412 of active silicon substrate 130 to form interconnect 140 that conductively couples first semiconductor package 110 to active silicon substrate 130. In some implementations, cured epoxy flux 420 remains between the lower surface of first semiconductor package 110 and the upper surface of active silicon substrate 130 to provide an underfill for first semiconductor package 110.

[0066] Figure 5BAn illustrative process 500B is depicted for conductively coupling a second semiconductor package 150 to an active silicon substrate 130 via a plurality of bond wires 310A-310n (collectively, “bond wires 310”) and encapsulating the resulting package-on-silicon (PoS) semiconductor package in a mold compound 330, in accordance with at least one embodiment described herein. The second semiconductor package 150 may include one or more semiconductor packages physically coupled to an upper surface of the first semiconductor package 110 using a bonding agent, such as a high thermal conductivity (Hi-K) epoxy 170. A first end of each of the plurality of bond wires 310 is conductively coupled to a respective conductive pad 510A-510n (collectively, “conductive pad 510”) disposed on, across, or around at least a portion of an upper surface of the second semiconductor package 150. A second end of each of the plurality of bond wires 310 is conductively coupled to a corresponding conductive pad 320A- 320n disposed on the upper surface of the active silicon substrate 130 using a second interconnection pattern.

[0067] Likewise Figure 5B , the mold compound 330 may be disposed on, around, or across at least a portion of the upper surface of the active silicon substrate 130, such that the mold compound 330 at least partially surrounds and / or covers the stacked first semiconductor package 110, the second semiconductor package 150, and the bonding wires 310. In an embodiment, the mold compound may include a high thermal conductivity mold compound 330. In such an embodiment, the high thermal conductivity mold compound 330 may have a thermal conductivity greater than: about 2 Watts / meter-Kelvin (W / mK); about 3 W / mK; about 4 W / mK; about 5 W / mK; about 7 W / mK; about 10 W / mK; or about 15 W / mK.

[0068] Figure 5CAn illustrative process 500C is depicted in accordance with at least one embodiment described herein, wherein an active silicon substrate 130 has been thinned to expose through silicon vias (TSVs) 412A-412n (collectively, “TSVs 412”). Each of at least some of the TSVs 412 terminates in a respective conductive bump 415A-415n (collectively, “conductive bumps 415”) disposed on a lower surface of the active silicon substrate 130. The active silicon substrate 130 may be thinned using any currently available or future developed thinning method or process, such as chemical / mechanical planarization (CMP). In an embodiment, the conductive bumps 415 may be disposed, deposited, or otherwise formed proximate to each of the TSVs 412 using any currently available or future developed deposition technique, process, or method. For example, the conductive element 415 may be photolithographically deposited or electroplated on the lower surface of the active silicon substrate 130.

[0069] Figure 5D An illustrative process 500D is depicted in which solder balls 460 have been reflowed onto conductive bumps 415 disposed on the lower surface of active silicon substrate 130 in accordance with at least one embodiment described herein. Figure 5D Reflowed solder balls 460 are depicted in FIG. 4 , but any similar conductive element may be disposed proximate each of at least some of the conductive bumps 415 disposed on the lower surface of the active silicon substrate 130 .

[0070] Figure 5E An illustrative process 500E is depicted in accordance with at least one embodiment described herein, wherein a package on silicon (PoS) semiconductor package has been diced. The PoS semiconductor package may be diced using any currently available or future developed dicing technique, method, or process. For example, in some implementations, the PoS semiconductor package may be diced using a mechanical or abrasive saw.

[0071] Fig. 5F An illustrative process 500F is depicted in which an active silicon substrate of a singulated package-on-silicon (PoS) semiconductor package has been conductively coupled to a substrate 480 by reflowing solder balls 460 disposed on a lower surface of the active silicon substrate 130. In an embodiment, in accordance with at least one embodiment described herein, an underfill material 470 may flow between the lower surface of the active silicon substrate 130 and an upper surface of the substrate 480. In an embodiment, the substrate 480 may include a printed circuit board having multiple layers of a high-density substrate.

[0072] Figure 6is a cross-sectional elevation view of another illustrative package-on-silicon (PoS) semiconductor package 600 according to at least one embodiment described herein, wherein a heat sink 610 is conductively coupled to a first semiconductor package 110 and a gap exists between the heat sink 610 and a lower surface of a stacked second semiconductor package 150. Figure 6 , in an embodiment, the second semiconductor package 150 may not be directly physically or thermally coupled to the first semiconductor package 110. In an example, the active silicon substrate 130 communicatively couples and physically connects the first semiconductor package 110 to the second semiconductor package 150 disposed above the first semiconductor package 110. In such an implementation, the first semiconductor package 110 includes a plurality of interconnects 140 arranged in a first interconnect pattern 142, which are coupled to the active semiconductor substrate 130. In such an implementation, a plurality of conductive structures 160 arranged in a second interconnect pattern 162 communicatively couples the second semiconductor package 150 to the active silicon substrate 130. The first interconnect pattern 142 may have a greater interconnect density than the second interconnect pattern 162.

[0073] The heat sink 610 may be thermally conductively coupled to at least a portion of the upper surface of the first semiconductor package 110. In an embodiment, the heat sink 610 may distribute thermal energy (i.e., heat) more evenly across the upper surface of the first semiconductor package 110. In an embodiment, the heat sink 610 may help dissipate heat generated by the first semiconductor package 110 to the surrounding environment around the PoS semiconductor package 100. In an embodiment, there may be an air gap 620 between the heat sink 610 and the lower surface of the second semiconductor package 150 to facilitate air flow across the heat sink 610 and to facilitate convective heat transfer between the heat sink 610 and the surrounding environment around the PoS semiconductor package 100. In an embodiment, the heat sink 610 may include or incorporate any number of surface features (e.g., points, depressions, fins, blades, etc.) to extend the surface area and / or enhance convection over the surface of the heat sink 610.

[0074] Figure 7 7 is a high-level logic flow diagram of an illustrative method 700 for fabricating an active package-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein. The PoS semiconductor package includes a first semiconductor package 110 conductively coupled to an active silicon substrate 130 via a plurality of interconnects 140 arranged in a first interconnect pattern 142. The PoS semiconductor package also includes a second semiconductor package 150 conductively coupled to the active silicon substrate 130 via a plurality of conductive members 160 or bond wires 310 arranged in a second interconnect pattern 162. The active silicon substrate 130 communicatively couples the first semiconductor package 110 to the second semiconductor package 150. The method 700 begins at 702.

[0075] At 704, the first semiconductor package 110 is conductively coupled to the active silicon substrate 130 using a plurality of interconnects 140 arranged in a first interconnect pattern 142. The first interconnect pattern 142 includes a plurality of interconnects 140 arranged at a first pitch (eg, interconnect spacing). In an embodiment, the first pitch may be less than 50 micrometers (μm).

[0076] At 706, the second semiconductor package 150 is conductively coupled to the active silicon substrate 130. In an embodiment, the second semiconductor package 150 may be conductively coupled to the active silicon substrate 130 using a plurality of conductive members 160 extending from a surface of the active silicon substrate 130 and arranged in a second interconnect pattern 162. In an embodiment, the second semiconductor package or device 150 may be conductively coupled to the active silicon substrate 130 using a plurality of bond wires 310 conductively coupled to a plurality of conductive pads 320 disposed across an upper surface of the active silicon substrate 130 in a second interconnect pattern 162. The second interconnect pattern 162 includes a plurality of interconnects 160 or a plurality of conductive pads 320 arranged on a second pitch (e.g., an interconnect / conductive pad pitch). In an embodiment, the second pitch may be greater than 150 micrometers (μm).

[0077] At 708 , the active silicon substrate 130 communicatively couples the first semiconductor package 110 and the second semiconductor package 150 to facilitate bidirectional exchange of data and / or information between the first semiconductor package 110 and the second semiconductor package 150 . The method 700 ends at 710 .

[0078] Figure 8 is a high-level logic flow diagram of an illustrative method 800 for fabricating an active package-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein. The method 800 may be performed in conjunction with Figure 7 The PoS semiconductor package includes a first semiconductor package 110 conductively coupled to an active silicon substrate 130 via a plurality of interconnects 140. The method 800 starts at 802.

[0079] At 804, the bottom fill material 190 may flow in the space formed between the lower surface of the first semiconductor package 110 and the upper surface of the active silicon substrate 130. In an embodiment, the bottom fill material 190 may include any number and / or combination of materials that are flowable and curable to a semi-rigid or rigid final state. In an embodiment, the bottom fill material 190 may include a non-conductive material having a high thermal conductivity. For example, the bottom fill material 190 may have a thermal conductivity greater than: about 1 Watt / meter-Kelvin (W / mK); about 2 W / mK; about 3 W / mK; about 5 W / mK; about 10 W / mK; about 12 W / mK; about 15 W / mK; or about 20 W / mK. The method 800 ends at 806.

[0080] Fig. 9 is a high-level logic flow diagram of an illustrative method 900 for fabricating an active-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein. The method 900 may be performed in conjunction with Figure 7 Method 700 and / or Figure 8 The PoS semiconductor package includes a second semiconductor package 150 disposed above the first semiconductor package 110 such that at least a portion of a lower surface of the second semiconductor package 150 overlaps at least a portion of an upper surface of the first semiconductor package 110. The method 900 starts at 902.

[0081] At 904, the second semiconductor package 150 is physically coupled to the first semiconductor package 110. In an embodiment, the lower surface of the second semiconductor package 150 may be bonded to the upper surface of the first semiconductor package 110 using an adhesive material 170. In some implementations, the adhesive material may include an epoxy-based adhesive material having a high thermal conductivity. For example, the adhesive material 170 may have a thermal conductivity greater than: about 1 Watt / meter-Kelvin (W / mK); about 2 W / mK; about 3 W / mK; about 5 W / mK; about 10 W / mK; about 12 W / mK; about 15 W / mK; or about 20 W / mK. The method 900 ends at 906.

[0082] Fig.10 is a high-level logic flow diagram of an illustrative method 1000 for fabricating an active-on-silicon (PoS) semiconductor package in accordance with at least one embodiment described herein. The method 1000 may be performed in conjunction with Figure 7 The method 700 described in detail in Figure 8 Method 800 and / or Fig. 9In one embodiment, the PoS semiconductor package may include an interposer 210 disposed between a lower surface of the second semiconductor package 150 and an upper surface of the first semiconductor package 110 . The method 1000 starts at 1002 .

[0083] At 1004, the interposer 210 is disposed between the lower surface of the second semiconductor package 150 and the upper surface of the first semiconductor package 110. In an embodiment, the interposer 210 includes a plurality of conductive features, such as a plurality of solder balls 222, which when reflowed conductively couple the interposer 210 (and, therefore, the second semiconductor package 150) to the conductive members 160 extending from the upper surface of the active silicon substrate 130.

[0084] The interposer 210 converts the contact pattern or pitch on the lower surface of the second semiconductor package 150 into the second interconnect pattern 162. In some implementations, the interposer 210 includes an organic pitch redistribution layer 220 sandwiched between an upper conductive layer 230 including and / or incorporating conductive features 232 and a lower conductive layer 240 including and / or incorporating a plurality of solder balls 222 for conductively coupling the interposer 210 to the conductive member 160.

[0085] At 1006 , the second semiconductor package 150 is conductively coupled to the interposer 210 .

[0086] At 1008, the interposer 210 is conductively coupled to the active silicon substrate 130. In an embodiment, the lower surface of the interposer 210 may be physically attached, coupled, and / or bonded to the upper surface of the first semiconductor package 110 using one or more chemically active or thermosetting adhesives, such as a high thermal conductivity adhesive 170, which facilitates heat flow laterally and upward through the PoS semiconductor package. The method 1000 ends at 1010.

[0087] although Figures 7 to 10 Various operations according to one or more embodiments are illustrated, but it is understood that they are not Figures 7 to 10 All operations described in are necessary for other embodiments. In fact, this article fully considers that in other embodiments of the present disclosure, Figures 7 to 10 The operations depicted in the figure and / or other operations described herein may be combined in a manner not specifically shown in any figure, but still fully comply with the present disclosure. Thus, claims for features and / or operations not specifically shown in a figure are deemed to be within the scope and content of the present disclosure.

[0088] As used in the application and claims, a list of items followed by the term "and / or" may mean any combination of the listed items. For example, the phrase "A, B, and / or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. As used in the application and claims, a list of items followed by the term "at least one of..." may mean any combination of the listed items. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0089] Thus, the present disclosure is directed to systems and methods for providing a low-profile stacked die semiconductor package, wherein a first semiconductor package is stacked with a second semiconductor package, and both semiconductor packages are conductively coupled to an active silicon substrate that communicatively couples the first semiconductor package to the second semiconductor package. The first semiconductor package may be conductively coupled to the active silicon substrate using a plurality of interconnects arranged in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may be conductively coupled to the active silicon substrate using a plurality of interconnects arranged in a second interconnect pattern having a second pitch, the second pitch being greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of bond wires.

[0090] The following examples relate to additional embodiments. The following examples of the present disclosure may include subject matter such as at least one apparatus, method, at least one machine-readable medium for storing instructions that, when executed, cause a machine to perform actions based on the method, components for performing actions based on the method, and / or a system for improving and enhancing lateral heat distribution across an upper surface of a first semiconductor package in a PoP semiconductor package and improving and enhancing heat flow from the first semiconductor package to a second semiconductor package within the PoP semiconductor package.

[0091] According to Example 1, a package-on-silicon (PoS) semiconductor package is provided. The PoS semiconductor package may include: an active silicon substrate having: an upper surface; a lower surface; and a plurality of conductive structures disposed across the upper surface; wherein the plurality of conductive structures include: a first portion of the conductive structures disposed across the upper surface of the active silicon substrate in a first pattern; and a second portion of the conductive structures disposed across the upper surface of the active silicon substrate in a second pattern; a first semiconductor package having an upper surface, a lower surface, and a plurality of conductive bumps disposed across the lower surface of the first semiconductor package in a first pattern; wherein the plurality of conductive bumps communicatively couple the first semiconductor package to the first portion of the conductive structures disposed on the active silicon substrate; and a second semiconductor package having an upper surface and a lower surface; the second semiconductor package is disposed such that at least a portion of the first semiconductor package is disposed between the lower surface of the second semiconductor package and the upper surface of the active silicon substrate; and the second semiconductor package is communicatively coupled to at least some of the second portions of the conductive structures disposed on the active silicon substrate via a plurality of conductive members, wherein the active silicon substrate communicatively couples the first semiconductor package to the second semiconductor package.

[0092] Example 2 may include elements of Example 1, wherein the first pattern includes conductive structures disposed on a first pitch of 50 micrometers (μm) or less; and wherein the second pattern includes conductive structures disposed on a second pitch of 150 μm or more.

[0093] Example 3 may include elements of either of Examples 1 or 2, wherein the one or more adhesives physically couple a lower surface of the second semiconductor package to at least a portion of an upper surface of the first semiconductor package.

[0094] Example 4 may include the elements of any of Examples 1 to 3, wherein a lower surface of the second semiconductor package extends beyond at least a portion of an edge of an upper surface of the first semiconductor package.

[0095] Example 5 may include elements of any one of Examples 1 to 4, wherein the plurality of conductive bumps on the lower surface of the second semiconductor package include a plurality of conductive bumps disposed around a portion of the second semiconductor package that extends beyond an upper surface of the first semiconductor package; and wherein the plurality of conductive members include a plurality of conductive pillars that communicatively couple at least some of the plurality of conductive bumps to at least some of the second portions of the conductive structure disposed on the upper surface of the active silicon substrate, the plurality of conductive bumps disposed around a portion of the second semiconductor package that extends beyond an upper surface of the first semiconductor package.

[0096] Example 6 may include elements of any of Examples 1 to 5, and the PoS semiconductor package may further include an interposer disposed between an upper surface of the first semiconductor package and a lower surface of the second semiconductor package, the interposer including: a plurality of conductive pads disposed across the upper surface of the interposer; a plurality of conductive structures disposed across at least a portion of the lower surface of the interposer; and a plurality of conductors that communicatively couple at least some of the plurality of conductive pads disposed on the upper surface of the interposer to at least some of the plurality of conductive structures disposed on the lower surface of the interposer.

[0097] Example 7 may include elements of any one of Examples 1 to 6, wherein each conductive bump of at least some of the plurality of conductive bumps disposed on the lower surface of the second semiconductor package is physically and communicatively coupled to a corresponding conductive pad of the plurality of conductive pads disposed across the upper surface of the interposer; and wherein the interposer includes an adhesive disposed across at least a portion of the lower surface of the interposer for physically coupling the second semiconductor package and the interposer to the first semiconductor package.

[0098] Example 8 may include the elements of any of Examples 1 to 7, wherein a lower surface of the interposer extends beyond at least a portion of an edge of an upper surface of the first semiconductor package.

[0099] Example 9 may include elements of any one of Examples 1 to 8, wherein the plurality of conductive structures on the lower surface of the interposer include a plurality of conductive bumps disposed around a portion of the organic interposer that extends beyond an upper surface of the first semiconductor package; and wherein the plurality of conductive members include a plurality of conductive pillars that communicatively couple each of at least some of the conductive bumps to a corresponding portion of a second portion of a conductive structure disposed on the upper surface of the active silicon substrate, the conductive bumps disposed around a portion of the interposer that extends beyond an upper surface of the first semiconductor package.

[0100] Example 10 may include elements of any one of Examples 1 to 9, wherein the plurality of conductive structures communicatively coupled to the second semiconductor package includes a plurality of bonding wires communicatively coupled to the second semiconductor package; and wherein each bonding wire of at least some of the plurality of bonding wires is communicatively coupled to a corresponding portion of a second portion of a conductive structure disposed on a surface of the active silicon substrate.

[0101] According to Example 11, a method for manufacturing a package-on-silicon (PoS) semiconductor package is provided. The method may include: conductively coupling each of a plurality of conductive structures disposed on a lower surface of a first semiconductor package to a corresponding portion of a first portion of a conductive structure disposed across an upper surface of an active silicon substrate in a first mode; conductively coupling each of a plurality of conductive structures disposed on a second semiconductor package to a corresponding portion of a second portion of a conductive structure disposed across an upper surface of an active silicon substrate in a second mode; wherein the second semiconductor package is operably coupled to the active silicon substrate so that at least a portion of the first semiconductor package is disposed between at least a portion of the lower surface of the second semiconductor package and an upper surface of the active silicon substrate; and communicatively coupling the first semiconductor package to the second semiconductor package via the active silicon substrate.

[0102] Example 12 may include elements of Example 11, and the method may further include disposing an underfill material between a lower surface of the first semiconductor package and an upper surface of the active silicon substrate.

[0103] Example 13 may include elements of either of Examples 11 or 12, wherein causing each of a plurality of conductive structures disposed on a second semiconductor package to be conductively coupled to a corresponding portion of a second portion of conductive structures disposed across an upper surface of the active silicon substrate in a second pattern may include conductively coupling a second semiconductor package having a plurality of conductive structures disposed on a lower surface of the second semiconductor package in a second pattern to a second portion of conductive structures disposed on an upper surface of the active silicon substrate.

[0104] Example 14 may include elements of any of Examples 11 to 13, and the method may further include adhesively coupling at least a portion of a lower surface of the second semiconductor package to at least a portion of an upper surface of the first semiconductor package.

[0105] Example 15 may include elements of any one of Examples 11 to 14, wherein adhesively coupling at least a portion of the lower surface of the second semiconductor package to at least a portion of the upper surface of the first semiconductor package may include: adhesively coupling at least a portion of the lower surface of the second semiconductor package to at least a portion of the upper surface of the first semiconductor package such that at least a portion of the lower surface of the second semiconductor package extends beyond at least a portion of an edge of the upper surface of the first semiconductor package.

[0106] Example 16 may include elements of any one of Examples 11 to 15, wherein causing each of a plurality of conductive structures disposed on the second semiconductor package to be conductively coupled to a corresponding portion of a second portion of a conductive structure disposed across an upper surface of the active silicon substrate in a second pattern may include causing each of at least some of the plurality of conductive structures to be conductively coupled to a corresponding portion of a second portion of a conductive structure disposed on an upper surface of the active silicon substrate, the plurality of conductive structures being disposed around a portion of a lower surface of the second semiconductor package that extends beyond an upper surface of the first semiconductor package.

[0107] Example 17 may include elements of any one of Examples 11 to 16, wherein conductively coupling each of at least some of the plurality of conductive structures to a corresponding portion of a second portion of a conductive structure disposed on an upper surface of the active silicon substrate, the plurality of conductive structures disposed around a portion of a lower surface of the second semiconductor package that extends beyond an upper surface of the first semiconductor package, may include conductively coupling each of at least some of the plurality of conductive structures to a corresponding portion of a second portion of a conductive structure disposed on an upper surface of the active silicon substrate in a second pattern, the plurality of conductive structures disposed around a portion of a lower surface of the second semiconductor package that extends beyond an upper surface of the first semiconductor package, via a conductive pillar.

[0108] Example 18 may include elements of any one of Examples 11 to 17, and the method may further include: disposing an interposer between an upper surface of the first semiconductor package and a lower surface of the second semiconductor package, the interposer comprising: a plurality of conductive pads disposed across the upper surface of the interposer; a plurality of conductive structures disposed across at least a portion of the lower surface of the interposer; and a plurality of conductors that communicatively couple at least some of the plurality of conductive pads disposed on the upper surface of the interposer to at least some of the plurality of conductive structures on the lower surface of the interposer.

[0109] Example 19 may include elements of any one of Examples 11 to 18, wherein conductively coupling the second semiconductor package to a second portion of the conductive structure disposed on the upper surface of the active silicon substrate may further include: conductively coupling each of at least some of the plurality of conductive structures disposed on the lower surface of the second semiconductor package in a second pattern to a corresponding conductive pad of the plurality of conductive pads disposed across the upper surface of the interposer; and conductively coupling each of at least some of the plurality of conductive structures disposed across at least a portion of the lower surface of the interposer to a corresponding portion of the second portion of the conductive structure disposed on the upper surface of the active silicon substrate.

[0110] Example 20 may include elements of any of Examples 11 to 19, and the method may further include adhesively coupling a lower surface of the interposer to at least a portion of an upper surface of the first semiconductor package to physically couple the interposer and the second semiconductor package to the first semiconductor package.

[0111] Example 21 may include elements of any one of Examples 11 to 20, wherein the lower surface of the interposer is adhesively coupled to at least a portion of the upper surface of the first semiconductor package, and may also include: adhesively coupling the lower surface of the interposer to at least a portion of the upper surface of the first semiconductor package such that at least a portion of the lower surface of the interposer extends beyond at least a portion of an edge of the upper surface of the first semiconductor package.

[0112] Example 22 may include elements of any one of Examples 11 to 21, wherein conductively coupling each of at least some of a plurality of conductive structures disposed across at least a portion of a lower surface of the interposer to a corresponding portion of a second portion of conductive structures disposed on an upper surface of the active silicon substrate may include conductively coupling each of at least some of the plurality of conductive structures to a second portion of conductive structures disposed on the upper surface of the active silicon substrate in a second pattern via a conductive pillar, the plurality of conductive structures disposed around a portion of the lower surface of the interposer that extends beyond an upper surface of the first semiconductor package.

[0113] Example 23 may include elements of any one of Examples 11 to 22, wherein conductively coupling the second semiconductor package to a second portion of a conductive structure disposed on an upper surface of the active silicon substrate may include conductively coupling the second semiconductor package to a second portion of a conductive structure disposed on an upper surface of the active silicon substrate via each of at least some of a plurality of bonding wires.

[0114] According to Example 24, an electronic device is provided. The electronic device may include: a substrate having a package-on-silicon (PoS) semiconductor package conductively coupled thereto, the PoS semiconductor package including: an active silicon substrate having a plurality of conductive structures; wherein the plurality of conductive structures include: a first portion of the conductive structure disposed across at least a portion of an upper surface of the active silicon substrate in a first pattern; and a second portion of the conductive structure disposed across at least a portion of the upper surface of the active silicon substrate in a second pattern; a first semiconductor package having an upper surface, a lower surface, and a plurality of conductive bumps disposed across at least a portion of the lower surface of the first semiconductor package in a first pattern; wherein the plurality of conductive bumps communicatively couple the first semiconductor package to the first portion of the conductive structure disposed on the upper surface of the active silicon substrate; and a second semiconductor package having an upper surface and a lower surface; the second semiconductor package disposed above the upper surface of the first semiconductor package; and the second semiconductor package communicatively couples to at least some of the second portions of the conductive structure disposed on the upper surface of the active silicon substrate via a plurality of conductive members; wherein the active silicon substrate communicatively couples the first semiconductor package to the second semiconductor package.

[0115] Example 25 may include the elements of Example 24, wherein the first pattern includes conductive structures disposed on a first pitch of 50 micrometers (μm) or less; and wherein the second pattern includes conductive structures disposed on a second pitch of 150 μm or more.

[0116] Example 26 may include elements of any of Examples 24 or 25, wherein the one or more adhesives physically couple the lower surface of the second semiconductor package to at least a portion of the upper surface of the first semiconductor package.

[0117] Example 27 may include the elements of any of Examples 24 to 26, wherein a lower surface of the second semiconductor package extends beyond at least a portion of an edge of an upper surface of the first semiconductor package.

[0118] Example 28 may include elements of any one of Examples 24 to 27, wherein the plurality of conductive bumps on the lower surface of the second semiconductor package include a plurality of conductive bumps disposed around a portion of the second semiconductor package that extends beyond an upper surface of the first semiconductor package; and wherein the plurality of conductive members include a plurality of conductive pillars that communicatively couple at least some of the plurality of conductive bumps to at least some of a second portion of a conductive structure disposed on the active silicon substrate, the plurality of conductive bumps disposed around a portion of the second semiconductor package that extends beyond an upper surface of the first semiconductor package.

[0119] Example 29 may include elements of any one of Examples 24 to 28, and the electronic device may further include: an interposer disposed between an upper surface of the first semiconductor package and a lower surface of the second semiconductor package, the interposer comprising: a plurality of conductive pads disposed across the upper surface of the interposer; a plurality of conductive structures disposed across at least a portion of the lower surface of the interposer; and a plurality of conductors that communicatively couple at least some of the plurality of conductive pads disposed on the upper surface of the interposer to at least some of the plurality of conductive structures disposed on the lower surface of the interposer.

[0120] Example 30 may include elements of any one of Examples 24 to 29, wherein a plurality of conductive bumps disposed on a lower surface of the second semiconductor package are communicatively coupled to corresponding conductive pads of a plurality of conductive pads disposed across an upper surface of the interposer; and wherein the interposer further comprises an adhesive disposed across at least a portion of the lower surface of the interposer for physically coupling the interposer and the second semiconductor package to the first semiconductor package.

[0121] Example 31 may include elements of any of Examples 24 to 30, wherein a lower surface of the interposer extends beyond at least a portion of an edge of an upper surface of the first semiconductor package.

[0122] Example 32 may include elements of any one of Examples 24 to 31, wherein the plurality of conductive structures on the lower surface of the interposer include a plurality of conductive bumps disposed around a portion of the organic interposer that extends beyond an upper surface of the first semiconductor package; and wherein the plurality of conductive members include a plurality of conductive pillars that communicatively couple at least some of the conductive bumps to corresponding portions of a second portion of the conductive structures disposed on the upper surface of the active silicon substrate, the conductive bumps disposed around a portion of the organic interposer that extends beyond an upper surface of the first semiconductor package.

[0123] Example 33 may include elements of any one of Examples 24 to 32, wherein the plurality of conductive structures communicatively coupled to the second semiconductor package includes a plurality of bonding wires communicatively coupled to the second semiconductor package; and wherein each bonding wire of at least some of the plurality of bonding wires is communicatively coupled to each conductive structure of at least some of the second portions of the conductive structures disposed on the upper surface of the active silicon substrate.

[0124] According to Example 34, a package-on-silicon (PoS) semiconductor package manufacturing system is provided. The system may include: a component for conductively coupling each of a plurality of conductive structures disposed on a lower surface of a first semiconductor package to a corresponding portion of a first portion of a conductive structure disposed across an upper surface of an active silicon substrate in a first mode; a component for conductively coupling each of a plurality of conductive structures disposed on a second semiconductor package to a corresponding portion of a second portion of a conductive structure disposed across an upper surface of the active silicon substrate in a second mode; wherein the second semiconductor package is operably coupled to the active silicon substrate such that at least a portion of the first semiconductor package is disposed between at least a portion of the lower surface of the second semiconductor package and an upper surface of the active silicon substrate; and communicatively coupling the first semiconductor package to the second semiconductor package via the active silicon substrate.

[0125] Example 35 may include elements of Example 34, and the system may additionally include: means for disposing a molding compound around at least a portion of a perimeter of the first semiconductor package.

[0126] Example 36 may include elements of any of Examples 34 or 35, wherein the component for causing each of a plurality of conductive structures disposed on the second semiconductor package to be conductively coupled to a corresponding portion of a second portion of the conductive structure disposed across the upper surface of the active silicon substrate in a second pattern may include: a component for causing the second semiconductor package having a plurality of conductive structures disposed on a lower surface of the second semiconductor package in a second pattern to be conductively coupled to a second portion of the conductive structure disposed on the upper surface of the active silicon substrate.

[0127] Example 37 may include elements of any of Examples 34 to 36, and the system may further include means for physically coupling at least a portion of a lower surface of the second semiconductor package to at least a portion of an upper surface of the first semiconductor package.

[0128] Example 38 may include elements of any one of Examples 34 to 37, wherein the component for physically coupling at least a portion of the lower surface of the second semiconductor package to at least a portion of the upper surface of the first semiconductor package may include: a component for physically coupling at least a portion of the lower surface of the second semiconductor package to at least a portion of the upper surface of the first semiconductor package such that at least a portion of the lower surface of the second semiconductor package extends beyond at least a portion of an edge of the upper surface of the first semiconductor package.

[0129] Example 39 may include elements of any one of Examples 34 to 38, wherein the component for causing each of a plurality of conductive structures disposed on the second semiconductor package to be conductively coupled to a corresponding portion of a second portion of a conductive structure disposed across an upper surface of the active silicon substrate in a second pattern may include: a component for causing each of at least some of the plurality of conductive structures to be conductively coupled to a corresponding portion of a second portion of a conductive structure disposed on an upper surface of the active silicon substrate, the plurality of conductive structures being disposed around a portion of a lower surface of the second semiconductor package that extends beyond an upper surface of the first semiconductor package.

[0130] Example 40 may include elements of any one of Examples 34 to 39, wherein the means for conductively coupling each of at least some of the plurality of conductive structures to a corresponding portion of a second portion of a conductive structure disposed on an upper surface of the active silicon substrate (the plurality of conductive structures disposed around a portion of a lower surface of the second semiconductor package that extends out of an upper surface of the first semiconductor package) may include conductively coupling each of at least some of the plurality of conductive structures to a corresponding portion of a second portion of a conductive structure disposed on an upper surface of the active silicon substrate in a second pattern via a conductive pillar, the plurality of conductive structures disposed around a portion of a lower surface of the second semiconductor package that extends out of an upper surface of the first semiconductor package.

[0131] Example 41 may include the elements of any of Examples 34 to 40, and the system may further include: means for disposing an interposer between an upper surface of the first semiconductor package and a lower surface of the second semiconductor package, the interposer comprising: a plurality of conductive pads disposed across an upper surface of the interposer;

[0132] a plurality of conductive structures disposed across at least a portion of a lower surface of the interposer; and a plurality of conductors communicatively coupling at least some of a plurality of conductive pads disposed on an upper surface of the interposer to at least some of the plurality of conductive structures on the lower surface of the interposer.

[0133] Example 42 may include elements of any one of Examples 34 to 41, wherein the component for conductively coupling the second semiconductor package to the second portion of the conductive structure disposed on the upper surface of the active silicon substrate may also include: a component for conductively coupling each of at least some of the plurality of conductive structures disposed on the lower surface of the second semiconductor package in a second pattern to a corresponding conductive pad of the plurality of conductive pads disposed across the upper surface of the interposer; and a component for conductively coupling each of at least some of the plurality of conductive structures disposed across at least a portion of the lower surface of the interposer to a corresponding portion of the second portion of the conductive structure disposed on the upper surface of the active silicon substrate.

[0134] Example 43 may include elements of any of Examples 34 to 42, and the system may further include: a component for physically coupling a lower surface of the interposer to at least a portion of an upper surface of the first semiconductor package to physically couple the interposer and the second semiconductor package to the first semiconductor package.

[0135] Example 44 may include elements of any one of Examples 34 to 43, wherein the component for physically coupling the lower surface of the interposer to at least a portion of the upper surface of the first semiconductor package may also include: a component for physically coupling the lower surface of the interposer to at least a portion of the upper surface of the first semiconductor package such that at least a portion of the lower surface of the interposer extends beyond at least a portion of an edge of the upper surface of the first semiconductor package.

[0136] Example 45 may include elements of any one of Examples 34 to 44, wherein the means for conductively coupling each of at least some of the plurality of conductive structures disposed across at least a portion of the lower surface of the interposer to a corresponding portion of a second portion of the conductive structure disposed on the upper surface of the active silicon substrate may include means for conductively coupling each of at least some of the plurality of conductive structures to the second portion of the conductive structure disposed on the upper surface of the active silicon substrate in a second pattern via a conductive pillar, the plurality of conductive structures disposed around a portion of the lower surface of the interposer that extends beyond the upper surface of the first semiconductor package.

[0137] Example 46 may include elements of any one of Examples 34 to 45, wherein the means for conductively coupling the second semiconductor package to the second portion of the conductive structure disposed on the upper surface of the active silicon substrate may include means for conductively coupling the second semiconductor package to the second portion of the conductive structure disposed on the upper surface of the active silicon substrate via each of at least some of the plurality of bonding wires.

[0138] The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Therefore, the claims are intended to cover all such equivalents.

Claims

1. A package-on-silicon (PoS) semiconductor package, comprising: An active silicon substrate, the active silicon substrate comprising a semiconductor device and having: upper surface; lower surface; as well as a plurality of conductive structures disposed across the upper surface; wherein the plurality of conductive structures include: a first portion of conductive structures disposed across the upper surface of the active silicon substrate in a first pattern, the first portion of conductive structures having a first density; and a second portion of the conductive structure disposed across the upper surface of the active silicon substrate in a second pattern, the second portion of the conductive structure having a second density, wherein the first density is greater than the second density; a first semiconductor package having an upper surface, a lower surface, and a plurality of conductive bumps disposed across the lower surface of the first semiconductor package in the first pattern; wherein the plurality of conductive bumps communicatively couple the first semiconductor package to the first portion of a conductive structure disposed on the active silicon substrate; and a second semiconductor package having an upper surface and a lower surface; disposing the second semiconductor package such that at least a portion of the first semiconductor package is disposed between the lower surface of the second semiconductor package and the upper surface of the active silicon substrate; and the second semiconductor package being communicatively coupled to at least some of the second portions of conductive structures disposed on the active silicon substrate via a plurality of conductive members, wherein the active silicon substrate communicatively couples the first semiconductor package to the second semiconductor package; wherein the first pattern comprises conductive structures disposed at a first pitch of 50 micrometers (μm) or less; and wherein the second pattern includes conductive structures arranged at a second pitch of 150 μm or more, and an interposer disposed between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package, the interposer comprising: a plurality of conductive pads disposed across an upper surface of the interposer; a plurality of conductive structures disposed across at least a portion of a lower surface of the interposer; and a plurality of conductors that communicatively couple at least some of the plurality of conductive pads disposed on the upper surface of the interposer to at least some of the plurality of conductive structures disposed on the lower surface of the interposer; wherein the interposer includes an adhesive disposed across at least a portion of the lower surface of the interposer for physically coupling the second semiconductor package and the interposer to the upper surface of the first semiconductor package; and wherein the adhesive has a high thermal conductivity, and wherein the thickness of the first semiconductor package is much greater than the thickness of the adhesive, The interposer includes an organic pitch redistribution layer that converts a contact pattern or pitch on a lower surface of the second semiconductor package into a second pattern of a second portion of a conductive structure. 2 . The package-on-silicon semiconductor package of claim 1 , wherein one or more adhesives physically couple the lower surface of the interposer to at least a portion of the upper surface of the first semiconductor package. 3 . The package-on-silicon semiconductor package of claim 2 , wherein the lower surface of the second semiconductor package protrudes beyond at least a portion of an edge of the upper surface of the first semiconductor package.

4. The silicon-on-package semiconductor package of claim 3: wherein a plurality of conductive bumps are disposed on the lower surface of the second semiconductor package, and the plurality of conductive bumps are disposed around the portion of the second semiconductor package extending out of the upper surface of the first semiconductor package; and The plurality of conductive members include a plurality of conductive pillars that communicatively couple at least some of the plurality of conductive bumps to at least some of the second portions of the conductive structure disposed on the upper surface of the active silicon substrate, the plurality of conductive bumps being disposed around the portion of the second semiconductor package that extends out of the upper surface of the first semiconductor package.

5. The package-on-silicon semiconductor package of claim 1: Wherein each conductive bump of at least some of the plurality of conductive bumps disposed on the lower surface of the second semiconductor package is physically and communicatively coupled to a corresponding conductive pad of the plurality of conductive pads disposed across the upper surface of the interposer. 6 . The package-on-silicon semiconductor package of claim 5 , wherein the lower surface of the interposer protrudes beyond at least a portion of an edge of the upper surface of the first semiconductor package.

7. The package-on-silicon semiconductor package as claimed in claim 6; wherein the plurality of conductive structures on the lower surface of the interposer include a plurality of conductive bumps disposed around the portion of the organic interposer extending beyond the upper surface of the first semiconductor package; and The plurality of conductive members include a plurality of conductive pillars that communicatively couple each of at least some of the conductive bumps to a corresponding portion of the second portion of the conductive structure disposed on the upper surface of the active silicon substrate, the conductive bumps being disposed around the portion of the interposer that protrudes out of the upper surface of the first semiconductor package.

8. The package-on-silicon semiconductor package of claim 1: wherein the plurality of conductive members communicatively coupled to the second semiconductor package comprises a plurality of bond wires communicatively coupled to the second semiconductor package; and Wherein each bonding wire of at least some of the plurality of bonding wires is communicatively coupled to a corresponding portion of the second portion of a conductive structure disposed on the surface of the active silicon substrate.

9. A method for manufacturing a package-on-silicon (PoS) semiconductor package, comprising: conductively coupling each of a plurality of conductive structures disposed on a lower surface of a first semiconductor package to a corresponding portion of a first portion of conductive structures disposed across an upper surface of an active silicon substrate in a first pattern, the first portion of the conductive structures having a first density, and the active silicon substrate including a semiconductor device; conductively coupling each of a plurality of conductive structures disposed on a second semiconductor package to a corresponding portion of a second portion of conductive structures disposed across the upper surface of the active silicon substrate in a second pattern via a plurality of conductive members, the second portion of the conductive structures having a second density, wherein the first density is greater than the second density; wherein the second semiconductor package is operatively coupled to the active silicon substrate such that at least a portion of the first semiconductor package is disposed between at least a portion of a lower surface of the second semiconductor package and the upper surface of the active silicon substrate; as well as communicatively coupling the first semiconductor package to the second semiconductor package via the active silicon substrate; An interposer is disposed between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package, the interposer comprising: a plurality of conductive pads disposed across an upper surface of the interposer; a plurality of conductive structures disposed across at least a portion of a lower surface of the interposer; and a plurality of conductors that communicatively couple at least some of the plurality of conductive pads disposed on the upper surface of the interposer to at least some of the plurality of conductive structures disposed on the lower surface of the interposer; wherein the interposer includes an adhesive disposed across at least a portion of the lower surface of the interposer for physically coupling the second semiconductor package and the interposer to the upper surface of the first semiconductor package; and wherein the adhesive has a high thermal conductivity, and wherein the thickness of the first semiconductor package is much greater than the thickness of the adhesive, The interposer includes an organic pitch redistribution layer that converts a contact pattern or pitch on a lower surface of the second semiconductor package into a second pattern of a second portion of a conductive structure.

10. The method of claim 9, further comprising: An underfill material is disposed between a lower surface of the first semiconductor package and an upper surface of the active silicon substrate.

11. The method of claim 9, wherein causing each of a plurality of conductive structures disposed on a second semiconductor package to conductively couple to a corresponding portion of a second portion of conductive structures disposed across the upper surface of the active silicon substrate in a second pattern comprises: conductively coupling a second semiconductor package having a plurality of conductive structures disposed on the lower surface of the second semiconductor package in the second pattern to a plurality of conductive pads disposed across an upper surface of the interposer; as well as A plurality of conductive structures disposed across at least a portion of a lower surface of the interposer are conductively coupled to the second portion of conductive structures disposed on the upper surface of the active silicon substrate.

12. The method of claim 11, further comprising: At least a portion of the lower surface of the interposer is adhesively coupled to at least a portion of the upper surface of the first semiconductor package.

13. The method of claim 12, wherein adhesively coupling at least a portion of the lower surface of the interposer to at least a portion of the upper surface of the first semiconductor package comprises: Adhesively coupling at least the portion of the lower surface of the interposer to at least the portion of the upper surface of the first semiconductor package such that at least a portion of the lower surface of the second semiconductor package extends beyond at least a portion of an edge of the upper surface of the first semiconductor package.

14. The method of claim 13, wherein causing each of a plurality of conductive structures disposed on a second semiconductor package to conductively couple to a corresponding portion of a second portion of conductive structures disposed across the upper surface of the active silicon substrate in a second pattern comprises: Conductively couple each of at least some of a plurality of conductive structures to a corresponding portion of the second portion of a conductive structure disposed on the upper surface of the active silicon substrate, the conductive structure being disposed around a portion of the lower surface of the second semiconductor package that extends beyond the upper surface of the first semiconductor package.

15. The method of claim 14, wherein causing each of at least some of a plurality of conductive structures disposed around the portion of the lower surface of the second semiconductor package that extends beyond the upper surface of the first semiconductor package to be conductively coupled to a corresponding portion of the second portion of the conductive structure disposed on the upper surface of the active silicon substrate comprises: Each of at least some of the plurality of conductive structures is conductively coupled to a corresponding portion of the second portion of the conductive structure disposed on the upper surface of the active silicon substrate in the second pattern via a conductive pillar, the plurality of conductive structures being disposed around the portion of the lower surface of the second semiconductor package that protrudes beyond the upper surface of the first semiconductor package.

16. The method of claim 9, wherein conductively coupling a second semiconductor package to a second portion of a conductive structure disposed on the upper surface of the active silicon substrate further comprises: conductively coupling each of at least some of the plurality of conductive structures disposed on the lower surface of the second semiconductor package in the second pattern to a corresponding conductive pad of the plurality of conductive pads disposed across the upper surface of the interposer; as well as Each conductive structure of at least some of the plurality of conductive structures disposed across at least a portion of the lower surface of the interposer is conductively coupled to a corresponding portion of the second portion of conductive structures disposed on the upper surface of the active silicon substrate.

17. The method of claim 16, further comprising: The lower surface of the interposer is adhesively coupled to at least a portion of an upper surface of the first semiconductor package such that the interposer and the second semiconductor package are physically coupled to the first semiconductor package.

18. The method of claim 17, wherein adhesively coupling the lower surface of the interposer to at least a portion of an upper surface of the first semiconductor package further comprises: The lower surface of the interposer is adhesively coupled to at least a portion of an upper surface of the first semiconductor package such that at least a portion of the lower surface of the interposer extends beyond at least a portion of an edge of the upper surface of the first semiconductor package.

19. The method of claim 18, wherein causing each of at least some of the plurality of conductive structures disposed across at least a portion of the lower surface of the interposer to be conductively coupled to a corresponding portion of the second portion of conductive structures disposed on the upper surface of the active silicon substrate comprises: Each of at least some of the plurality of conductive structures is conductively coupled to a second portion of a conductive structure disposed on the upper surface of the active silicon substrate in the second pattern via a conductive pillar, the plurality of conductive structures being disposed around the portion of the lower surface of the interposer that extends beyond the upper surface of the first semiconductor package.

20. The method of claim 9, wherein conductively coupling a second semiconductor package to a second portion of a conductive structure disposed on the upper surface of the active silicon substrate comprises: A second semiconductor package is conductively coupled to a second portion of a conductive structure disposed on the upper surface of the active silicon substrate via each bond wire of at least some of the plurality of bond wires.

21. An electronic device comprising: A substrate having a package-on-silicon (PoS) semiconductor package conductively coupled thereto, the PoS semiconductor package comprising: an active silicon substrate having a plurality of conductive structures; wherein the plurality of conductive structures include: a first portion of conductive structures disposed in a first pattern across at least a portion of an upper surface of the active silicon substrate, the first portion of conductive structures having a first density; and a second portion of the conductive structure disposed across at least a portion of the upper surface of the active silicon substrate in a second pattern, the second portion of the conductive structure having a second density, wherein the first density is substantially greater than the second density; a first semiconductor package having an upper surface, a lower surface, and a plurality of conductive bumps disposed across at least a portion of the lower surface of the first semiconductor package in the first pattern; wherein the plurality of conductive bumps communicatively couple the first semiconductor package to the first portion of a conductive structure disposed on the upper surface of the active silicon substrate; and a second semiconductor package having an upper surface and a lower surface; the second semiconductor package is disposed over the upper surface of the first semiconductor package; and the second semiconductor package being communicatively coupled to at least some of the second portions of conductive structures disposed on the upper surface of the active silicon substrate via a plurality of conductive members; wherein the active silicon substrate communicatively couples the first semiconductor package to the second semiconductor package, wherein the first pattern includes conductive structures disposed on a first pitch of 50 micrometers (μm) or less; and wherein the second pattern includes conductive structures disposed on a second pitch of 150 μm or more; and an interposer disposed between the upper surface of the first semiconductor package and the lower surface of the second semiconductor package, the interposer comprising: a plurality of conductive pads disposed across an upper surface of the interposer; a plurality of conductive structures disposed across at least a portion of a lower surface of the interposer; and a plurality of conductors that communicatively couple at least some of the plurality of conductive pads disposed on the upper surface of the interposer to at least some of the plurality of conductive structures disposed on the lower surface of the interposer; wherein the interposer includes an adhesive disposed across at least a portion of the lower surface of the interposer for physically coupling the second semiconductor package and the interposer to the upper surface of the first semiconductor package; and wherein the adhesive has a high thermal conductivity, and wherein the thickness of the first semiconductor package is much greater than the thickness of the adhesive, The interposer includes an organic pitch redistribution layer that converts a contact pattern or pitch on a lower surface of the second semiconductor package into a second pattern of a second portion of a conductive structure.

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