Display panel and method of manufacturing the same

Abstract

A display panel and a method for manufacturing the display panel are provided, wherein the display panel includes: a substrate layer; a signal line, which is arranged on the substrate layer, and the signal line includes: a first layer, which includes aluminum; and a second layer, which is directly arranged on the first layer, and the second layer includes a niobium-titanium alloy; a first thin-film transistor, which is connected to the signal line; a second thin-film transistor, which is arranged on the substrate layer; a capacitor, which is electrically connected to the second thin-film transistor; and a light-emitting element, which is electrically connected to the second thin-film transistor.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0122876, filed on October 16, 2018, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0002] Exemplary embodiments of the invention relate generally to display panels, and more particularly, to display panels and methods of manufacturing display panels having signal lines that result in more stable display panels with faster signal transmission speeds. Background Art

[0003] The display device includes a driving circuit (e.g., a gate driving circuit and a data driving circuit) for controlling a plurality of signal lines and a plurality of pixels. Each pixel includes a display element and a pixel driving circuit for controlling the display element. The pixel driving circuit includes a plurality of thin film transistors systematically connected to each other.

[0004] A recent trend in display devices is to increase resolution and / or eliminate the border around the display. The elimination of the border around the display reduces the space used for various signal lines in the display. The reduction in space used for various signal lines in the display may lead to increased failures and / or reduced speed.

[0005] The above information disclosed in this Background section is only for understanding the background of the inventive concept and therefore it may contain information that does not constitute prior art. Summary of the invention

[0006] The display panel constructed according to the exemplary embodiment of the invention has an improved signal transmission speed. In addition, the method of manufacturing the display panel according to the exemplary embodiment of the invention provides a reduced failure rate.

[0007] Additional features of the inventive concepts will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the inventive concepts.

[0008] According to one or more exemplary embodiments of the invention, a display panel includes: a base layer; a signal line, which is arranged on the base layer, the signal line includes: a first layer, which includes aluminum; and a second layer, which is directly arranged on the first layer, the second layer includes a niobium-titanium alloy; a first thin film transistor, which is connected to the signal line; a second thin film transistor, which is arranged on the base layer; a capacitor, which is electrically connected to the second thin film transistor; and a light-emitting element, which is electrically connected to the second thin film transistor.

[0009] The first thin film transistor may include a first polysilicon pattern, a first control electrode, a first input electrode, and a first output electrode. The first polysilicon pattern may be disposed on the substrate layer. The first control electrode may overlap the first polysilicon pattern and may be connected to a signal line. Each of the first input electrode and the first output electrode may be connected to the first polysilicon pattern.

[0010] The first control electrode may have substantially the same stack structure as the signal line.

[0011] The second thin film transistor may include a second polysilicon pattern, a second control electrode, a second input electrode, and a second output electrode. The second polysilicon pattern may be disposed on the substrate layer. The second control electrode may overlap the second polysilicon pattern and may be disposed on a layer different from the layer under the first control electrode. Each of the second input electrode and the second output electrode may be connected to the second polysilicon pattern.

[0012] The capacitor may include: a first electrode disposed on substantially the same layer as a layer under the signal line; and a second electrode disposed on substantially the same layer as a layer under the second control electrode. The first electrode may have substantially the same stack structure as the signal line.

[0013] The second control electrode and the second electrode may include: a first layer including an aluminum-nickel-lanthanum alloy; and a second layer disposed directly on the first layer and including a niobium-titanium alloy.

[0014] The first layer may further include nickel and lanthanum. The content of nickel relative to the first layer may be in the range of about 0.01 at % to about 0.05 at %, and the content of lanthanum relative to the first layer may be in the range of about 0.02 at % to about 0.05 at %.

[0015] The content of titanium with respect to the second layer may be in a range from about 5 at % to about 50 at %, and the content of niobium with respect to the second layer may be in a range from about 50 at % to about 95 at %.

[0016] The signal line may have a line width in a range from about 3 μm to about 5 μm.

[0017] The thickness of the first layer can be from about To about In the range of about To about within the range.

[0018] The display panel may further include a third layer disposed on the second layer, and the third layer may include titanium.

[0019] The first layer may have a thickness from about To about The second layer may have a thickness in the range from about To about The third layer may have a thickness in the range from about To about The thickness is within the range of .

[0020] The signal line may include at least one of a data line, a gate line, a control signal line, a power line, and a connection line.

[0021] According to one or more exemplary embodiments of the invention, a display panel includes: a base layer; a first thin film transistor, arranged on the base layer; a second thin film transistor, electrically connected to the first thin film transistor; and a light emitting element, connected to the second thin film transistor, wherein the first thin film transistor includes: a first polysilicon pattern, arranged on the base layer; a first control electrode, overlapping the first polysilicon pattern, the first control electrode including: a first layer including an aluminum-nickel-lanthanum alloy; and a second layer directly arranged on the first layer, the second layer including a niobium-titanium alloy; and a first input electrode and a first output electrode, each of the first input electrode and the first output electrode being connected to the first polysilicon pattern.

[0022] The first thin film transistor may further include a third layer directly disposed on the second layer, the third layer including titanium.

[0023] According to one or more exemplary embodiments of the invention, a method for manufacturing a display panel includes the following steps: forming a semiconductor pattern on a base layer; forming a signal line on the base layer by forming a first layer containing aluminum, directly forming a second layer on the first layer, and patterning the first layer and the second layer, the second layer containing a niobium-titanium alloy; forming a control electrode on the base layer, the control electrode overlapping the semiconductor pattern; forming an input electrode and an output electrode on the base layer, each of the input electrode and the output electrode being connected to the semiconductor pattern; and forming a light-emitting element on the base layer.

[0024] The step of forming the signal line may further include forming a third layer on the second layer and patterning the third layer. The third layer may include titanium. The first layer, the second layer, and the third layer are patterned substantially simultaneously through a single etching process.

[0025] The first layer may further include nickel and lanthanum, the content of nickel may be in a range from about 0.01 at % to about 0.05 at % relative to the first layer, and the content of lanthanum may be in a range from about 0.02 at % to about 0.05 at % relative to the first layer.

[0026] The content of titanium with respect to the second layer may be in a range from about 5 at % to about 50 at %, and the content of niobium with respect to the second layer may be in a range from about 50 at % to about 95 at %.

[0027] The step of forming a semiconductor pattern may include: forming a polysilicon pattern, and doping an area of ​​the polysilicon pattern that does not overlap with the control electrode with impurities, and the method of manufacturing a display panel may also include annealing the polysilicon pattern at a temperature range from about 400°C to about 500°C after forming the signal line.

[0028] The method may further include the steps of forming an insulating layer on the base layer to cover the polysilicon pattern; forming a through hole in the insulating layer to expose a region of the polysilicon pattern that does not overlap the control electrode; and cleaning the region of the polysilicon pattern exposed by the through hole.

[0029] The step of forming the signal line on the base layer may include forming at least one of a data line, a gate line, a control signal line, a power line, and a connection line.

[0030] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the inventive concept.

[0032] Figure 1 is a perspective view showing an exemplary embodiment of a display panel constructed according to the principles of the invention.

[0033] Figure 2 yes Figure 1 A plan view of the display panel.

[0034] Figure 3 The invention is constructed according to the principle of Figure 1 A cross-sectional view of an exemplary embodiment of a portion of a pixel.

[0035] Figure 4 is a cross-sectional view schematically illustrating an exemplary embodiment of a signal line constructed according to the principles of the invention.

[0036] Figure 5 is a graph showing a change in resistance of a signal line caused by a heat treatment process according to an exemplary embodiment of the invention.

[0037] Fig. 6A is a diagram showing SEM images of a signal line obtained before and after a cleaning process according to an exemplary embodiment of the invention.

[0038] Figure 6Bis a diagram showing a difference in an enlarged shape of a signal line caused by a difference in niobium and titanium content in a post-cleaning state according to an exemplary embodiment of the invention.

[0039] Figure 7 is a cross-sectional view schematically showing a signal line constructed according to an exemplary embodiment of the invention.

[0040] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Figure 8F , Figure 8G , Figure 8H and Fig.8I is a cross-sectional view illustrating a process of manufacturing a display panel constructed according to an exemplary embodiment of the invention.

[0041] It should be noted that these drawings are intended to illustrate the general characteristics of the methods, structures and / or materials used in certain example embodiments and are intended to supplement the written description provided below. However, these drawings are not drawn to scale and may not accurately reflect the precise structure or performance characteristics of any given embodiment and should not be interpreted as defining or limiting the range or nature of the values ​​contained by the example embodiments. For example, the relative thickness and position of molecules, layers, regions and / or structural elements may be reduced or exaggerated for clarity. The use of similar or identical reference numerals in the various drawings is intended to indicate the presence of similar or identical elements or features. DETAILED DESCRIPTION

[0042] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. "Embodiment" and "implementation" as used herein are interchangeable words for non-limiting examples of devices or methods using one or more inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other cases, well-known structures and devices are shown in block diagram form to avoid making various exemplary embodiments unnecessarily obscure. In addition, although various exemplary embodiments may be different, they do not have to be exclusive. For example, without departing from the inventive concept, the specific shape, construction and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0043] Unless otherwise stated, the exemplary embodiments shown should be understood as providing exemplary features of different details of some ways in which the inventive concept can be implemented in practice. Therefore, without departing from the inventive concept, unless otherwise stated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged.

[0044] In the accompanying drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the exemplary embodiments may be implemented differently, a specific process sequence may be performed differently from the sequence described. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the order described. In addition, the same reference numerals represent the same elements.

[0045] When an element, such as a layer, is referred to as being "on," "connected to," or "bonded to" another element or layer, the element or layer may be directly on, directly connected to, or directly bonded to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on," "directly connected to," or "directly bonded to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection with or without intervening elements. In addition, the DR1 axis, the DR2 axis, and the DR3 axis are not limited to three axes, such as the x-axis, the y-axis, and the z-axis, of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ for example. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0047] For descriptive purposes, spatially relative terms such as "under," "below," "below," "above," "above," "higher," "side" (e.g., as in "sidewall"), etc., may be used herein to describe the relationship of one element to another element shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, the spatially relative terms are intended to include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "under" or "beneath" other elements or features will subsequently be positioned as "above" the other elements or features. Thus, the exemplary term "under," may include both above and below orientations. In addition, the device may be otherwise positioned (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0048] The terms used herein are for the purpose of describing a particular embodiment, and are not intended to be limiting. Unless the context clearly indicates otherwise, as used herein, the singular forms "one", "an" and "said" are also intended to include plural forms. In addition, when the terms "include" and / or "comprise" or their variations are used in this specification, it is indicated that there are described features, integral bodies, steps, operations, elements, components and / or their groups, but one or more other features, integral bodies, steps, operations, elements, components and / or their groups are not excluded from existence or addition. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms, and are not used as terms of degree, and are thus used to explain the inherent deviations of the measured values, calculated values ​​and / or values ​​provided that will be recognized by those of ordinary skill in the art.

[0049] Various exemplary embodiments are described herein with reference to cross-sectional views and / or exploded views as schematic diagrams of idealized exemplary embodiments and / or intermediate structures. In this way, variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the exemplary embodiments disclosed herein should not necessarily be interpreted as being limited to the shapes of the specific illustrated regions, but rather include deviations in shapes due to, for example, manufacturing. In this way, the regions shown in the drawings may actually be schematic, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are not necessarily intended to be restrictive.

[0050] As is customary in the art, in terms of functional blocks, units and / or modules, some exemplary embodiments are described and shown in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be optionally driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform other functions. In addition, without departing from the scope of the inventive concept, each block, unit and / or module of some exemplary embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the inventive concept.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which this disclosure is a part. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly so defined herein.

[0052] Figure 1 is a perspective view showing an exemplary embodiment of a display panel DP constructed according to the principles of the invention. Figure 2 yes Figure 1 A plan view of the display panel DP. Figure 2 The interconnection structure among the pixels PX, the driving circuit GDC and the signal lines SGL of the display panel DP is schematically shown.

[0053] The display panel DP may have a front surface DP-FS parallel to the first direction axis DR1 and the second direction axis DR2. The normal direction of the front surface DP-FS of the display panel DP (i.e., the thickness direction of the display panel DP) may be referred to as a third direction axis DR3. In each layer constituting the display panel DP, the top surface or the front surface may be distinguished from the bottom or the rear surface based on the third direction axis DR3. Hereinafter, the first direction to the third direction may be directions respectively indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, and will be identified with the same reference numerals as the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively.

[0054] like Figure 1 As shown in , the display panel DP or its front surface DP-FS may include a display area DP-DA in which pixels PX displaying an image are arranged, and a non-display area DP-NDA adjacent to the display area DP-DA. The non-display area DP-NDA may be an area in which no pixels PX are arranged. Some of the signal lines SGL and / or the drive circuits GDC may be arranged in the non-display area DP-NDA.

[0055] like Figure 1 As shown in , the display area DP-DA may be generally rectangular or quadrilateral. The non-display area DP-NDA may surround the display area DP-DA. However, exemplary embodiments are not limited thereto, and the shapes of the display area DP-DA and the non-display area DP-NDA may be variously changed in a complementary manner. For example, the non-display area DP-NDA may be provided only in two areas of the front surface DP-FS that are opposite to each other in the first direction DR1. In an exemplary embodiment, the display area DP-DA may be circular.

[0056] like Figure 2 As shown in , the display panel DP may include a driving circuit GDC, a plurality of signal lines SGL, a plurality of signal pads DP-PD, and a plurality of pixels PX.

[0057] According to the display color of the pixel, the pixel PX can be classified into multiple groups. For example, the pixel PX can include a red pixel, a green pixel, and a blue pixel. In an exemplary embodiment, the pixel PX can also include a white pixel. Even when some pixels PX are included in different groups, the pixel driving circuits of the pixels PX can also be the same.

[0058] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a plurality of gate signals and sequentially output the gate signals to a plurality of gate lines GL to be described below. In addition, the gate driving circuit may be configured to output other control signals to the driving circuit of the pixel PX.

[0059] The gate driving circuit may include a plurality of thin film transistors formed by the same method as that for the driving circuit of the pixel PX, or formed by, for example, a low temperature polysilicon (LTPS) or low temperature polycrystalline oxide (LTPO) process.

[0060] The signal line SGL may include any line capable of transmitting an electrical signal in a display, including a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each gate line GL may be connected to a corresponding pixel PX in the pixels PX, and each data line DL may be connected to a corresponding pixel PX in the pixels PX. The power line PL may be connected to the pixel PX. The control signal line CSL may be used to provide a control signal to a gate drive circuit. The signal pads DP-PD may be connected to the corresponding signal lines SGL in the signal lines SGL. The signal lines SGL may also include a light emitting signal line.

[0061] In the exemplary embodiment shown, each pixel PX may be a light-emitting pixel. For example, the pixel PX may include an organic light-emitting diode or a quantum dot light-emitting diode used as a light-emitting device. The light-emitting layer of the organic light-emitting diode may include an organic light-emitting material. The light-emitting layer of the quantum dot light-emitting diode may include quantum dots and quantum rods. For simplicity, the following description will refer to an example in which an organic light-emitting pixel is used as a pixel PX.

[0062] The pixel PX may include an organic light emitting diode and a pixel driving circuit for driving the organic light emitting diode. The organic light emitting diode may be a top emission diode or a bottom emission diode. The pixel driving circuit may include at least a switching thin film transistor, a driving thin film transistor, and a capacitor. A high power voltage may be provided to the driving thin film transistor, and a low power voltage may be provided to one electrode of the organic light emitting diode. The driving thin film transistor may control a driving current passing through the organic light emitting diode according to the amount of charge stored in the capacitor. The switching thin film transistor may output a data signal applied to the data line in response to a gate signal applied to the gate line. The capacitor may be charged to a voltage level corresponding to the data signal received from the switching thin film transistor.

[0063] In an exemplary embodiment, the pixel driving circuit may be configured to have six or seven thin film transistors including a switch thin film transistor and a drive thin film transistor. However, the exemplary embodiment is not limited thereto, and in any given exemplary embodiment, the structure of the pixel driving circuit may be changed differently. In addition, the design of the signal line SGL may also be changed according to the structure of the pixel driving circuit.

[0064] Figure 3 The invention is constructed according to the principle of Figure 1FIG. 1 is a cross-sectional view of an exemplary embodiment of a portion of a pixel PX. Figure 3 1 shows a vertical cross section of a portion of a pixel PX in which a switching thin film transistor T1 (hereinafter, a first thin film transistor), a driving thin film transistor T2 (hereinafter, a second thin film transistor), a capacitor Cst, and an organic light emitting diode OLED are disposed. Figure 3 A vertical cross section of a portion including the gate line GL is further shown in FIG.

[0065] like Figure 3 As shown in , the display panel DP may include a base layer BL and some elements (e.g., a circuit device layer DP-CL, a display device layer DP-OLED, and a thin encapsulation layer TFE) disposed on the base layer BL. In an exemplary embodiment, the thin encapsulation layer TFE may be replaced with an encapsulation substrate (e.g., a metal substrate or a glass substrate). The display panel DP may also include functional layers such as an anti-reflection layer and a refractive index adjustment layer. The circuit device layer DP-CL may include a circuit device and at least a plurality of insulating layers. In an exemplary embodiment, the insulating layer may include an organic layer and / or an inorganic layer as will be described below.

[0066] The circuit device may include a signal line, a pixel driving circuit, etc. The circuit device layer may be formed by forming an insulating layer, a semiconductor layer, and a conductive layer using a coating or deposition process, and then patterning the insulating layer, the semiconductor layer, and the conductive layer using a photolithography process. The display device layer DP-OLED may include a light emitting element. The display device layer DP-OLED may also include an organic layer formed of the same material as the pixel defining layer PDL.

[0067] The base layer BL may be formed of a synthetic resin film (or referred to as a synthetic resin layer) or include a synthetic resin film. The synthetic resin layer may include a thermosetting resin. The synthetic resin layer may be a polyimide resin layer, but exemplary embodiments are not limited to a specific material. The synthetic resin layer may include at least one of an acrylic resin, a methacrylate resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a polyurethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In exemplary embodiments, the base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0068] At least one inorganic layer may be formed on the top surface of the base layer BL. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. For example, the at least one inorganic layer may include a plurality of inorganic layers of a multilayer structure. The multilayer inorganic layer may constitute a buffer layer BFL to be described below. The buffer layer BFL may prevent or limit foreign matter from entering the display panel DP. In addition, the buffer layer BFL may improve the adhesion of the conductive pattern or the semiconductor pattern compared to the case where the conductive pattern or the semiconductor pattern is directly formed on the base layer BL.

[0069] The first semiconductor pattern PS1 and the second semiconductor pattern PS2 may be disposed on the buffer layer BFL. Each of the first semiconductor pattern PS1 and the second semiconductor pattern PS2 may be formed of or include polycrystalline silicon. However, exemplary embodiments are not limited thereto, and in exemplary embodiments, each of the first semiconductor pattern PS1 and the second semiconductor pattern PS2 may be formed of or include at least one of various semiconductor materials (e.g., silicon semiconductor material and oxide semiconductor material), and may have one of a polycrystalline structure and an amorphous structure.

[0070] Each of the first semiconductor pattern PS1 and the second semiconductor pattern PS2 may include an input region (or a first portion), an output region (or a second portion), and a channel region (or a third portion) between the input region and the output region. The channel region of the first semiconductor pattern PS1 may be defined as facing the first control electrode GE1 to be described below, and the channel region of the second semiconductor pattern PS2 may be defined as facing the second control electrode GE2 to be described below. The input region and the output region may be doped with impurities and may have a higher conductivity than that of the channel region. For example, the input region and the output region may be doped to have n-type conductivity. The following description will refer to an example in which the first semiconductor pattern PS1 and the second semiconductor pattern PS2 are n-type, but the first semiconductor pattern PS1 and the second semiconductor pattern PS2 may be p-type. Alternatively, one of the first semiconductor pattern PS1 and the second semiconductor pattern PS2 may be p-type and the other may be n-type.

[0071] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may be disposed on the plurality of pixels PX (eg, Figure 1 and Figure 2 ) are stacked together and may cover the first semiconductor pattern PS1 and the second semiconductor pattern PS2. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure.

[0072] The first control electrode GE1 may be disposed on the first insulating layer 10. The first control electrode GE1 may overlap the channel region of the first semiconductor pattern PS1. The gate line GL and the first electrode CE1 of the capacitor Cst may be disposed on the first insulating layer 10. The first control electrode GE1, the gate line GL, and the first electrode CE1 may be formed by the same process and thus may have the same stacked structure. Figure 3, but when viewed in a plan view, the first control electrode GE1 may be connected to the gate line GL. The gate line GL may be used to provide a turn-on signal to the first thin film transistor T1.

[0073] The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the first control electrode GE1, the gate line GL and the first electrode CE1. The second insulating layer 20 may overlap with the plurality of pixels PX. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single layer structure or a multi-layer structure.

[0074] The second control electrode GE2 may be disposed on the second insulating layer 20. The second control electrode GE2 may overlap the channel region of the second semiconductor pattern PS2. The second electrode CE2 of the capacitor Cst may be disposed on the second insulating layer 20. The second control electrode GE2 and the second electrode CE2 may be formed by the same process and may have the same stacked structure. In an exemplary embodiment, the second control electrode GE2 may be disposed at the same level as the first control electrode GE1, or on the same layer as the first control electrode GE1.

[0075] The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the second control electrode GE2 and the second electrode CE2. The third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10, the second insulating layer 20, and the third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. In the exemplary embodiment shown, the third insulating layer 30 may be a single-layer silicon oxide layer.

[0076] The connection signal line and the input / output electrode may be disposed on the third insulating layer 30. The first input electrode DE1 and the first output electrode SE1 may be disposed on the third insulating layer 30 and may be connected to the input region and the output region of the first semiconductor pattern PS1 through the first through hole (which may also be referred to as a contact hole) CH1 and the second through hole CH2, respectively. The second input electrode DE2 and the second output electrode SE2 may be disposed on the third insulating layer 30 and may be connected to the input region and the output region of the second semiconductor pattern PS2 through the third through hole CH3 and the fourth through hole CH4, respectively. The first through holes CH1, CH2, CH3, and CH4 may penetrate the first through third insulating layers 10, 20, and 30.

[0077] The first connection signal line CNL1 and the second connection signal line CNL2 may be disposed on the third insulating layer 30. The first connection signal line CNL1 may be connected to the gate line GL through the fifth through hole CH5, and the second connection signal line CNL2 may be connected to the second electrode CE2 through the sixth through hole CH6. The first connection signal line CNL1 may be connected to another thin film transistor of the pixel driving circuit.

[0078] The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the connection signal line and the input / output electrode. The material of the fourth insulating layer 40 may not be limited. The connection electrode CNE may be disposed on the fourth insulating layer 40. The connection electrode CNE may be directly or indirectly connected to the second output electrode SE2 through the seventh contact hole CH7 penetrating the fourth insulating layer 40, or may be electrically connected to the second output electrode SE2 through another connection signal line. The fifth insulating layer 50 (or passivation layer) may be disposed on the fourth insulating layer 40 to cover the connection electrode CNE. The fifth insulating layer 50 may be an organic layer, and may have a single-layer structure or a multi-layer structure.

[0079] In the illustrated exemplary embodiment, at least one of the fourth insulating layer 40 and the fifth insulating layer 50 may be a single polyimide resin layer. However, the exemplary embodiment is not limited thereto, and in an exemplary embodiment, the fourth insulating layer 40 and the fifth insulating layer 50 may include at least one of acrylic resin, methacrylate resin, polyisoprene resin, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyamide resin, and perylene resin.

[0080] The organic light emitting diode OLED may be disposed on the fifth insulating layer 50. The anode AE ​​of the organic light emitting diode OLED may be disposed on the fifth insulating layer 50. The anode AE ​​may be connected to the connection electrode CNE through an eighth contact hole CH8 penetrating the fifth insulating layer 50. The pixel defining layer PDL may be disposed on the fifth insulating layer 50.

[0081] The pixel defining layer PDL may have an opening OP formed to expose at least a portion of the anode AE. The opening OP of the pixel defining layer PDL may define a light emitting area PXA of the pixel. For example, when viewed in a plan view, a plurality of pixels PX (eg, Figure 1 ) may be regularly arranged in the display panel DP. An area having pixels PX may be defined as a pixel area, and each pixel area may include a light emitting area PXA and a non-light emitting area NPXA adjacent to the light emitting area PXA. The non-light emitting area NPXA may surround the light emitting area PXA.

[0082] The hole control layer HCL may be commonly disposed in the light emitting region PXA and the non-light emitting region NPXA. A common layer such as the hole control layer HCL may be commonly disposed in a plurality of pixels PX (eg, see Figure 1 and Figure 2 ). The hole control layer HCL may include a hole transport layer and a hole injection layer.

[0083] The organic light emitting layer EML may be disposed on the hole control layer HCL. The organic light emitting layer EML may be partially disposed only on a region corresponding to the opening OP. That is, the organic light emitting layers EML may be respectively disposed in the pixels PX and may have respective boundaries spaced apart from each other.

[0084] In the illustrated exemplary embodiment, the organic light emitting layer EML is shown as having a patterned structure, but in an exemplary embodiment, the organic light emitting layer EML may be commonly disposed in a plurality of pixels PX. Here, the organic light emitting layer EML may be configured to emit white light or blue light. In addition, the organic light emitting layer EML may have a multi-layer structure.

[0085] The electron control layer ECL may be disposed on the organic light emitting layer EML. The electron control layer ECL may include an electron transport layer and an electron injection layer. The cathode CE may be disposed on the electron control layer ECL. The electron control layer ECL and the cathode CE may be disposed together in a plurality of pixels PX.

[0086] The thin encapsulation layer TFE may be disposed on the cathode CE. The thin encapsulation layer TFE may be disposed to cover a plurality of pixels PX together. In the illustrated exemplary embodiment, the thin encapsulation layer TFE may directly cover the cathode CE. In an exemplary embodiment, a cover layer may be further disposed to cover the cathode CE. In an exemplary embodiment, the stacked structure of the organic light emitting diode OLED may have a structure that is formed by flipping the cathode CE such as Figure 3 The shapes shown are obtained.

[0087] The thin encapsulation layer TFE may include at least an inorganic layer or an organic layer. In an exemplary embodiment, the thin encapsulation layer TFE may include two inorganic layers and an organic layer therebetween. In an exemplary embodiment, the thin encapsulation layer TFE may include a plurality of inorganic layers and a plurality of organic layers alternately stacked.

[0088] The inorganic encapsulation layer may protect the organic light emitting diode OLED from moisture or oxygen, and the organic encapsulation layer may protect the organic light emitting diode OLED from foreign objects (e.g., dust particles). The inorganic encapsulation layer may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but the exemplary embodiment is not limited thereto. The organic encapsulation layer may include an acrylic organic layer, but the exemplary embodiment is not limited thereto.

[0089] and Figure 3 , the fourth insulating layer 40 and the connecting electrode CNE may be omitted. The fifth insulating layer 50 may cover the second output electrode SE2, and the anode AE ​​may be directly or indirectly connected to the second output electrode SE2. According to the equivalent circuit of the present exemplary embodiment, the second thin film transistor T2 may be directly connected to the organic light emitting diode OLED. However, the exemplary embodiment is not limited thereto. In the exemplary embodiment, another thin film transistor may be further provided between the second thin film transistor T2 and the organic light emitting diode OLED when viewed in the equivalent circuit diagram.

[0090] Figure 4 is a cross-sectional view schematically illustrating an exemplary embodiment of a signal line CL- 1 according to inventive principles.

[0091] Will refer to Figure 4 The signal line CL-1 according to the illustrated exemplary embodiment described may be used as Figure 3 The gate line GL of the signal line CL-1 may have a double-layer stacked structure. The signal line CL-1 may include a first layer CL1 and a second layer CL2, the first layer CL1 includes aluminum, and the second layer CL2 is directly disposed on the first layer CL1 or directly contacts the first layer CL1 and includes a niobium-titanium alloy. In an exemplary embodiment, the second layer CL2 may be made of a niobium-titanium alloy.

[0092] Since the first layer CL1 includes aluminum, the signal line CL-1 can have a reduced resistance compared to a conventional molybdenum-based signal line. The resistance of the metal line can be reduced by increasing the thickness or line width of the metal line. However, in the case where the signal line has a thickness greater than a critical thickness, the base layer BL (e.g., see Figure 3 ) may be damaged (e.g., bent or broken) due to tension. In the case where the line width increases, additional areas may be required to maintain the required distance between signal lines or to set widened signal lines. That is, the area of ​​the non-display area DP-NDA will increase.

[0093] In the case where the signal line CL-1 is formed of or includes aluminum, the thickness and line width of the signal line CL-1 may be reduced. According to exemplary embodiments, damage to the base layer BL may be prevented or reduced, and the area of ​​the non-display area DP-NDA may be reduced. Therefore, the display panel constructed according to the exemplary embodiments may realize a borderless design or minimize the non-display area.

[0094] According to a display panel with high resolution, the signal line CL-1 may have a line width of 3 μm or less due to a small distance between pixels. Therefore, due to the narrow line width, a short circuit failure may occur in the pixel driving circuit. On the other hand, if the line width is greater than 5 μm, it is difficult to achieve a borderless design. In an exemplary embodiment, the signal line CL-1 of the double-layer stacked structure may be formed to have a line width in a range from about 3 μm to about 5 μm, and therefore, the above-mentioned problem does not occur.

[0095] The first layer CL1 may be formed of or include an aluminum-nickel-lanthanum alloy. In this case, it may be possible to prevent or suppress the hillock formation phenomenon in the signal line CL-1. Specifically, at a high temperature of about 400°C, a hillock formation phenomenon may occur in the aluminum layer. For example, an aluminum wire may thermally expand due to thermal stress at a high temperature and may have a protruding portion or a cracked portion. Therefore, if aluminum is used for the signal line CL-1, the electrical characteristics or physical characteristics of the signal line CL-1 may be degraded due to the thermal environment in subsequent processes. However, according to an exemplary embodiment of the invention, an aluminum-nickel-lanthanum alloy is used for the signal line CL-1, and the signal line CL-1 may have improved heat resistance and may prevent or reduce the hillock formation problem.

[0096] The content of aluminum relative to the first layer CL1 may be in the range of from about 99.90 at% to about 99.99 at%. The content of nickel relative to the first layer CL1 may be in the range of from about 0.01 at% to about 0.05 at%, and the content of lanthanum relative to the first layer CL1 may be in the range of from about 0.02 at% to about 0.05 at%. The composition of the aluminum alloy may be formed using ICP, XPS, and SIMS methods. As used herein, at% means atom%.

[0097] In the case where the content of nickel and lanthanum is less than the above at% range, it may be difficult to achieve good heat resistance, and thus, a hillock formation problem may occur. Also, if the content of nickel and lanthanum is higher than the above at% range, it may be difficult to reduce the resistance of the signal line CL-1 and prevent or reduce process failures occurring in the dry etching process.

[0098] The thickness of the first layer CL1 can be from about To about If the thickness of the first layer CL1 is less than The first layer CL1 will have a high resistance. If the thickness of the first layer CL1 is greater than The manufacturing cost will increase, and further, it may take a lot of time to perform the etching process. In addition, process failure may occur in the patterning process. However, the exemplary embodiments are not limited to the above thickness range of the first layer CL1, and the thickness of the first layer CL1 may be changed within a range that can be predicted by those skilled in the art based on the size of the display panel DP and / or the composition ratio of the material of the first layer CL1.

[0099] Since the second layer CL2 is directly disposed on the first layer CL1, the hillock formation problem occurring in the signal line CL-1 can be more effectively prevented or reduced because since the second layer CL2 covers the top surface of the first layer CL1, there is no space for the first layer CL1 to expand.

[0100] Hereinafter, a difference between a comparative example including the second layer CL2 made of titanium or titanium nitride and the second layer CL2 made of a niobium-titanium alloy is described in the illustrated exemplary embodiment.

[0101] In the case where the second layer CL2 is made of only titanium, when a heat treatment process is performed on the first semiconductor pattern PS1 and the second semiconductor pattern PS2 at a temperature ranging from about 400° C. to about 500° C., diffusion of aluminum and titanium occurs at an interface between the first layer CL1 and the second layer CL2. Therefore, an alloy of aluminum and titanium is formed, and the resistance of the signal line CL-1 is sharply increased.

[0102] When titanium nitride is used as the second layer CL2, due to the low film growth rate, contamination materials such as particles may be introduced into the interface between the first layer CL1 and the second layer CL2 during the deposition process of the second layer CL2, thereby deteriorating the performance of the signal line CL-1.

[0103] On the other hand, according to the exemplary embodiment shown, niobium-titanium alloy is used as the second layer CL2. Therefore, no diffusion occurs or limited diffusion occurs between the materials constituting the first layer CL1 and the second layer CL2, and therefore, the signal line can have a low resistance. Therefore, the signal line can be formed to have a small thickness and a small line width. In addition, in the case of using niobium-titanium alloy as the second layer CL2, the second layer CL2 can be grown at a large film growth rate. Therefore, it can be possible to prevent or suppress the contamination material from entering the interface between the first layer CL1 and the second layer CL2, and it can be possible to prevent or reduce the degradation of the physical characteristics or electrical characteristics of the signal line CL-1.

[0104] The thickness of the second layer CL2 can be to The thickness of the second layer CL2 is less than In the case where the second layer CL2 is thicker than 100 mm, all of the second layer CL2 may be etched away during the cleaning process as will be described below, and in this case, the first layer CL1 may come into contact with or react with the cleaning solution. That is, the first layer CL1 may be damaged, and the second layer CL2 may not function as a capping layer. In the case of , the manufacturing cost will increase, and it will take a lot of time to perform the etching process. In addition, process failure may occur in the patterning process. The thickness of each layer can be measured using a transmission electron microscope (TEM) or using a focused ion beam (FIB).

[0105] Figure 5 is a graph showing a change in resistance of a signal line caused by a heat treatment process according to an exemplary embodiment of the invention. Figure 5 The resistance values ​​of the signal line CL-1 measured before and after the heat treatment process according to the Nb / Ti ratio of the second layer CL2 are shown. The second layer CL2 having five different Nb / Ti ratios (at%) of about 95:5, 90:10, 80:20, 50:50 and 0:100 was used in the experiment.

[0106] like Figure 5 As shown in , when the heat treatment process is not performed on the signal line CL-1, the signal line CL-1 has a substantially constant resistance value of about 4 μΩ / cm regardless of the difference in the niobium-titanium ratio. After the heat treatment process, the signal line CL-2 has a slightly increased resistance value as the titanium ratio increases, and is controlled to be an acceptable value of about 4 μΩ / cm or more until the titanium ratio reaches about 50 at%. However, when the titanium ratio is about 100 at%, the resistance increases to a high value of about 8 μΩ / cm or more.

[0107] according to Figure 5 According to the experimental results shown in , the second layer CL2 may be provided to have a titanium ratio ranging from about 5 at % to about 50 at %. Figure 5 It is shown that when the titanium content is less than about 50 at%, the diffusion between aluminum and titanium can be effectively prevented or limited during the heat treatment process. When the titanium content is higher than about 50 at%, the resistance value will increase due to the alloy of aluminum and titanium formed by diffusion between aluminum and titanium.

[0108] According to an exemplary embodiment of the invention, the niobium content may be less than about 95 at %. For example, the niobium content may be in a range from about 50 at % to about 95 at %.

[0109] At increased niobium content, niobium pentoxide (Nb pentoxide) can be formed during the heat treatment process by chemical reaction between niobium and oxygen. 2 O 5). If niobium oxide is formed, it will increase the resistance value of the signal line CL-1. Therefore, strict process control may be required to limit oxygen in the heat treatment process.

[0110] like Figure 5 As shown in , in the case where the niobium content is less than about 95at%, the heat treatment process does not cause a large change in the resistance value of the signal line, and this result indicates that the niobium is not oxidized. Therefore, according to an exemplary embodiment of the invention, strict process control may not be required to limit oxygen during the heat treatment process. In the case where the niobium content is higher than about 95at%, the resistance value of the signal line CL-1 may be increased by the oxidation process without strict process control for limiting oxygen.

[0111] Table 1 below shows the results obtained by performing a cleaning process on the second layer CL2 having a titanium content of about 5 at%, 10 at%, 20 at%, and 50 at% using a spray method. The cleaning process was performed at room temperature for 1000 seconds (600 seconds for a sample having a Ti content of about 50 at%). Hydrogen fluoride (HF) and ammonium fluoride (NH 4 F) (eg, a buffered oxide etchant solution) is used as the cleaning solution.

[0112] [Table 1]

[0113]

[0114]

[0115] Fig. 6A is a diagram showing SEM images of a signal line CL- 1 obtained before and after a cleaning process according to an exemplary embodiment of the invention. Figure 6B TABLE 1 is a graph showing the difference in the enlarged shape of the signal line CL-1 obtained after the cleaning process when there is a difference in the niobium and titanium content given in Table 1. The cleaning process is performed by a method of spraying a cleaning solution onto the display panel DP and immersing the display panel DP in the cleaning solution. Fig. 6A and Figure 6B , and both the cross-sectional view and the plan view of the signal line CL-1 are shown. Fig. 6A The cross-sectional view of FIG. 1 shows a second layer CL2 and an insulating layer IL sequentially stacked on the first layer CL1. Figure 6B The second layer CL2 and the insulating layer IL are shown in a plan view of FIG. In an exemplary embodiment, the insulating layer IL may be one of the first to third insulating layers 10, 20, and 30, but the exemplary embodiment is not limited thereto.

[0116] Referring to Table 1, the higher the titanium content in the second layer CL2, the higher the etching rate of the second layer CL2. Figure 6B It is shown that an increase in the titanium content leads to rapid etching and a decrease in the thickness of the second layer CL2. In the case where the titanium content is higher than about 50 at%, all of the second layer CL2 may be removed during the cleaning process due to the high etching rate, and therefore, the cleaning solution may contact and react with the first layer CL1, thereby causing damage to the first layer CL1. In order to avoid this problem, it is necessary to increase the thickness of the second layer CL2. However, in an exemplary embodiment, the second layer CL2 may be formed to have a titanium content lower than about 50 at%, and therefore, the thickness of the second layer CL2 may be reduced. That is, the thickness of the signal line CL-1 may be reduced and the first layer CL1 may be prevented or limited from being affected by the cleaning solution.

[0117] So far, an example has been described in which the second layer CL2 is made of the niobium-titanium alloy, but exemplary embodiments are not limited thereto. For example, the second layer CL2 may also include other materials.

[0118] Figure 7 2 is a cross-sectional view schematically showing a signal line CL-2 according to an exemplary embodiment of the invention. The signal line CL-2 may have a three-layer stacked structure. For example, the signal line CL-2 may include a first layer CL1 containing aluminum, a second layer CL2 directly disposed on or in direct contact with the first layer CL1 and containing a niobium-titanium alloy, and a third layer CL3 directly disposed on or in direct contact with the second layer CL2 and containing titanium.

[0119] Since the third layer CL3 is disposed on the second layer CL2, during the cleaning process, the second layer CL2 is not etched unless the third layer CL3 thereon is removed. Therefore, compared with the signal line CL-1 of the double-layer stacked structure, the thickness of the second layer CL2 can be reduced. This can reduce the amount of expensive niobium used and reduce process costs.

[0120] The thickness of the second layer CL2 can be from about To about If the thickness of the second layer CL2 is less than about Then, the second layer CL2 may be formed to have a large thickness variation, which may cause process failure, and there may be a mixing problem caused by the diffusion of aluminum atoms of the first layer CL1 and titanium atoms of the third layer CL3. In addition, during the cleaning process, the second layer CL2 may be removed so that the first layer CL1 contacts or reacts with the cleaning solution. That is, the first layer CL1 may be damaged, and the second layer CL2 may not function as a capping layer. If the second layer CL2 is formed to have approximately Or thicker, there may be other technical difficulties such as increased manufacturing cost, long etching time, and failure in the patterning process.

[0121] The thickness of the third layer CL3 can be from about To about If the thickness of the third layer CL3 is less than about The third layer CL3 is removed quickly during the cleaning process, and in this case, the second layer CL2 is exposed to the cleaning solution at an early stage. Therefore, the second layer CL2 is etched by the cleaning solution, so that the first layer CL1 contacts or reacts with the cleaning solution. That is, the first layer CL1 is damaged, and the third layer CL3 cannot function as a cover layer. If the thickness of the third layer CL3 is greater than about There may be other technical difficulties such as increased manufacturing cost, long etching time, and failures in the patterning process.

[0122] Since the third layer CL3 is formed of only titanium, the third layer CL3 may have a high etching rate in a cleaning process. Therefore, the sum of the thicknesses of the second layer CL2 and the third layer CL3 in the three-layer stack structure may be greater than Figure 4 The thickness of the second layer CL2 in the double-layer stack structure shown in FIG. Therefore, during the cleaning process, it may be possible to prevent or limit exposure of the first layer CL1 to the cleaning solution.

[0123] In addition to the above differences, Figure 4 The description can be applied to Figure 7 Therefore, the exemplary embodiments shown in FIG. 1 and FIG. 2 may be omitted and not repeated. Figure 4 Elements of the same or similar reference numerals are indicated Figure 7 to avoid redundancy in the description of the elements.

[0124] In an exemplary embodiment, the conductive pattern can be connected to the reference Figure 3 The gate line GL is formed by the same process as described above, and in this case, the conductive pattern may have the same Figure 4 and Figure 7 The signal lines CL-1 and CL-2 shown in FIG. Figure 3 ) and the first electrode CE1 may have the same stack structure (eg, a double-layered structure or a triple-layered structure) as the gate line GL.

[0125] In an exemplary embodiment, Figure 4 and Figure 7 The signal line CL-1 and the signal line CL-2 shown in FIG. 1 can be used as connection signal lines for connecting the conductive patterns to each other. Figure 4 and Figure 7Although not shown in the cross-sectional view of FIG. 1 , the connecting signal line can be used as part of the pixel driving circuit. For example, the connecting signal line can connect the thin film transistors to each other.

[0126] The connecting signal line may be disposed on the second insulating layer 20 and may have a Figure 4 and Figure 7 The same stacking structure of the signal line CL-1 and the signal line CL-2 shown in FIG. 1 is shown in FIG. 2. In addition, the conductive pattern can be formed by the same process as that used for the related connection signal line, and in this case, the conductive pattern can have the same Figure 4 and Figure 7 The signal lines CL-1 and CL-2 shown in FIG. 1 have the same stacked structure. The second control electrode GE2 (eg, see Figure 3 ) and the second electrode CE2 may have the same stack structure as the connection signal line disposed on the second insulating layer 20.

[0127] Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E , Figure 8F , Figure 8G , Figure 8H and Fig.8I 1 is a cross-sectional view showing a process of manufacturing a display panel DP according to an exemplary embodiment of the invention. Fig. 8A , Figure 8B , Figure 8C , Fig.8D , Fig. 8E and Figure 8F Each of the Figure 3 For simplicity of description, the previous reference Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Fig. 6A , Figure 6B and Figure 7 The described elements may be denoted by the same reference numerals without repeating their repeated descriptions.

[0128] like Fig. 8A As shown in , an inorganic layer may be formed on the base layer BL. In an exemplary embodiment, a plurality of inorganic layers may be formed by depositing corresponding inorganic materials. For example, the buffer layer BFL may be formed by sequentially forming a silicon oxide layer and a silicon nitride layer.

[0129] like Fig. 8AAs shown in FIG. 1 , a first preliminary semiconductor pattern PS1-P and a second preliminary semiconductor pattern PS2-P may be formed on a buffer layer BFL. The first preliminary semiconductor pattern PS1-P and the second preliminary semiconductor pattern PS2-P may be formed by forming a semiconductor layer and patterning the semiconductor layer. Before or after patterning the semiconductor layer, a crystallization process may be performed to change the crystal structure of the semiconductor layer.

[0130] like Fig. 8A As shown in FIG. 1 , a first insulating layer 10 may be formed on the buffer layer BFL. The first insulating layer 10 may be formed by a deposition, coating, or printing method. The method of forming the first insulating layer 10 may vary in consideration of the material of the first insulating layer 10 .

[0131] Afterwards, if Figure 8B As shown in FIG. 1 , the first layer CL1 and the second layer CL2 may be continuously formed on the first insulating layer 10 in a manner of reducing the interval between each process. The first layer CL1 may be formed by depositing aluminum. In an exemplary embodiment, the first layer CL1 may be formed by depositing an aluminum-nickel-lanthanum alloy.

[0132] The second layer CL2 may be formed by depositing a niobium-titanium alloy. The deposition process of the first layer CL1 and the second layer CL2 may be performed using a plasma deposition process, but the exemplary embodiment is not limited thereto. In an exemplary embodiment, the first layer CL1 and the second layer CL2 may be deposited or formed using one of various methods known to those skilled in the art.

[0133] Afterwards, if Figure 8C As shown in , the first layer CL1 and the second layer CL2 may be patterned. As a result of the patterning, a gate line GL, a first control electrode GE1, and a first electrode CE1 may be formed by the first layer CL1 and the second layer CL2. The patterning may be performed using one of a conventional wet etching method and a dry etching method. In an exemplary embodiment, a dry etching process may be used to pattern the first layer CL1 and the second layer CL2. According to an exemplary embodiment of the invention, the first layer CL1 and the second layer CL2 may be etched at one time, and therefore, the manufacturing process may be simplified.

[0134] Reference Fig.8D , a third layer CL3 may be further formed on the second layer CL2. The first layer CL1, the second layer CL2, and the third layer CL3 may be formed continuously. In an exemplary embodiment, the third layer CL3 may be formed by depositing a titanium layer using a plasma deposition method, but the exemplary embodiment is not limited thereto. For example, the third layer CL3 may be deposited or formed using one of various methods known to those skilled in the art.

[0135] Afterwards, if Fig. 8EAs shown in , the first layer CL1, the second layer CL2, and the third layer CL3 may be patterned. As a result of the patterning, the gate line GL, the first control electrode GE1, and the first electrode CE1 may be formed by the first layer CL1, the second layer CL2, and the third layer CL3. The patterning may be performed using one of a conventional wet etching method and a dry etching method. In an exemplary embodiment, a dry etching process may be used to pattern the first layer CL1, the second layer CL2, and the third layer CL3. According to an exemplary embodiment of the invention, the first layer CL1, the second layer CL2, and the third layer CL3 may be etched at one time, and therefore, the manufacturing process may be simplified.

[0136] Afterwards, if Figure 8F As shown in FIG. 1 , a second insulating layer 20 may be formed on the first insulating layer 10. The second insulating layer 20 may be formed by a deposition, coating, or printing process. Next, a second control electrode GE2 and a second electrode CE2 may be formed on the second insulating layer 20. The second control electrode GE2 and the second electrode CE2 may have a single-layer structure or a multi-layer structure. FIG. 8B to FIG. 8E In the case of the process, the second control electrode GE2 and the second electrode CE2 may be formed to have a double-layer structure.

[0137] Next, the first initial semiconductor pattern PS1-P and the second initial semiconductor pattern PS2-P may be doped using the first control electrode GE1 and the second control electrode GE2 as a mask being used to form the first semiconductor pattern PS1 and the second semiconductor pattern PS2. Therefore, the first semiconductor pattern PS1 and the second semiconductor pattern PS2 may include a portion overlapping the first control electrode GE1 and the second control electrode GE2 and used as a channel region, and doped portions located on both sides of the channel region and used as an input region and an output region. In the exemplary embodiment shown, an n-type dopant (i.e., a group V element) may be used for the doping process.

[0138] Thereafter, a heat treatment process may be performed. The heat treatment process may be performed to heat treat the first semiconductor pattern PS1 and the second semiconductor pattern PS2 in a temperature range from about 400° C. to about 500° C. (specifically, at 450° C.). As a result of the heat treatment process, the dopants injected into the input region and the output region may be uniformly diffused. As described above, in the case where the conductive pattern includes a niobium-titanium alloy layer, even when the heat treatment process is performed at a high temperature, a hillock formation phenomenon may be prevented or reduced from occurring in the aluminum-containing layer.

[0139] Next, if Figure 8GAs shown in , a third insulating layer 30 may be formed on the second insulating layer 20. The third insulating layer 30 may be formed by a deposition, coating or printing method. Thereafter, the first through hole CH1 to the sixth through hole CH6 may be formed. Portions of the first semiconductor pattern PS1 and the second semiconductor pattern PS2 exposed by the first through hole CH1, CH2, CH3 and CH4 may be oxidized. A cleaning process may be performed to remove an oxide layer on the first semiconductor pattern PS1 and the second semiconductor pattern PS2, which may enable the contact resistance of the first semiconductor pattern PS1 and the second semiconductor pattern PS2 to be reduced. In an exemplary embodiment, a cleaning process may be performed to remove a silicon dioxide layer formed near the first through hole CH1, CH2, CH3 and CH4.

[0140] A cleaning solution may be provided near the fifth through hole CH5 and the sixth through hole CH6, but the niobium-titanium layer may prevent the cleaning solution from reacting with the aluminum-containing layer. The niobium layer may prevent the aluminum layer from being reacted with certain elements (e.g., HF or NH 4 F) Damage.

[0141] Afterwards, if Figure 8H As shown in , a conductive pattern may be formed on the third insulating layer 30 by a deposition process. For example, a first input electrode DE1, a first output electrode SE1, a second input electrode DE2, a second output electrode SE2, a first connection signal line CNL1, and a second connection signal line CNL2 may be formed. The conductive pattern may have a three-layer structure of Ti / Al / Ti.

[0142] Afterwards, if Fig.8I As shown in , subsequent processes may be further performed to manufacture a display panel. For example, a fourth insulating layer 40 may be formed, and a seventh contact hole CH7 may be formed. A connection electrode CNE may be formed on the fourth insulating layer 40. A fifth insulating layer 50 may be formed, and an eighth contact hole CH8 may be formed. Next, an organic light emitting diode OLED may be formed on the fifth insulating layer 50.

[0143] The anode AE ​​may be formed on the fifth insulating layer 50. The anode AE ​​may be connected to the connection electrode CNE through the eighth contact hole CH8. The pixel defining layer PDL may be formed on the fifth insulating layer 50 to expose a central portion of the anode AE.

[0144] Thereafter, a hole control layer HCL, an emission layer EML, an electron control layer ECL and a cathode CE may be sequentially formed. A thin encapsulation layer TFE may be formed on the cathode CE. The organic encapsulation layer and / or the inorganic encapsulation layer may be formed by, for example, a deposition process or an inkjet printing process.

[0145] According to an exemplary embodiment of the invention, a display panel may include a signal line having reduced resistance and improved signal transmission speed. Therefore, a signal delay problem in a high-resolution display panel may be reduced.

[0146] The signal line may include a first layer including aluminum or an aluminum alloy, and the signal line may have reduced resistance. In an exemplary embodiment, the first layer of the signal line may be formed of or include an aluminum nickel lanthanum alloy to suppress or prevent a hillock formation phenomenon.

[0147] The signal line may further include a niobium-titanium alloy layer directly disposed on the aluminum layer or the aluminum alloy layer to more effectively suppress or prevent hillock formation in the signal line. In addition, by performing a cleaning process, the niobium-titanium alloy layer may be prevented or limited from reacting with a cleaning solution, the aluminum layer or the aluminum alloy.

[0148] Although certain exemplary embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Therefore, the inventive concept is not limited to such embodiments, but is limited to the broader scope of the appended claims and various obvious modifications and equivalent arrangements as are apparent to those of ordinary skill in the art.

Claims

1. A display panel, comprising: Base layer; A signal line is arranged on the base layer, the signal line comprising: a first layer comprising aluminum; and a second layer directly arranged on the first layer, the second layer being made of a niobium-titanium alloy; A first thin film transistor connected to the signal line; A second thin film transistor is disposed on the base layer; a capacitor electrically connected to the second thin film transistor; and The light emitting element is electrically connected to the second thin film transistor.

2. The display panel according to claim 1, wherein: The first thin film transistor comprises: A first polysilicon pattern is disposed on the base layer; a first control electrode overlapping the first polysilicon pattern and connected to the signal line; and A first input electrode and a first output electrode, each of the first input electrode and the first output electrode being connected to the first polysilicon pattern.

3. The display panel according to claim 2, wherein: The first control electrode has the same stacking structure as the signal line.

4. The display panel according to claim 2, wherein: The second thin film transistor comprises: a second polysilicon pattern, disposed on the base layer; a second control electrode overlapping the second polysilicon pattern and disposed on a layer different from a layer under the first control electrode; a second input electrode and a second output electrode, each of the second input electrode and the second output electrode being connected to the second polysilicon pattern.

5. The display panel according to claim 4, wherein: The capacitor comprises: a first electrode disposed on the same layer as a layer under the signal line; and a second electrode disposed on the same layer as the layer below the second control electrode, and Wherein, the first electrode has the same stacking structure as the signal line.

6. The display panel according to claim 5, wherein: The second control electrode and the second electrode include: a first layer comprising an aluminum-nickel-lanthanum alloy; and A second layer is disposed directly on the first layer and includes a niobium-titanium alloy.

7. The display panel according to claim 1, wherein: The first layer also includes: Nickel, the nickel having a content ranging from 0.01 at % to 0.05 at % relative to the first layer; and Lanthanum, the lanthanum content relative to the first layer is in the range of 0.02 at % to 0.05 at %.

8. The display panel according to claim 7, wherein: The content of titanium relative to the second layer is in the range of 5 at % to 50 at %, and The content of the niobium relative to the second layer is in the range of from 50 at % to 95 at %.

9. A display panel, comprising: Base layer; A signal line is arranged on the base layer, A first thin film transistor, disposed on the base layer; a second thin film transistor, electrically connected to the first thin film transistor; as well as a light emitting element connected to the second thin film transistor, Wherein, the first thin film transistor comprises: A first polysilicon pattern is disposed on the base layer; A first control electrode overlapped with the first polysilicon pattern, the first control electrode comprising: a first layer comprising an aluminum-nickel-lanthanum alloy; and a second layer directly disposed on the first layer, the second layer being made of a niobium-titanium alloy; and a first input electrode and a first output electrode, each of the first input electrode and the first output electrode being connected to the first polysilicon pattern, Wherein, the signal line has the same stacking structure as the first control electrode.

10. A method for manufacturing a display panel, the method comprising the following steps: forming a semiconductor pattern on the base layer; forming a signal line on the base layer by forming a first layer including aluminum, forming a second layer directly on the first layer, and patterning the first layer and the second layer, the second layer being made of a niobium-titanium alloy; forming a control electrode on the base layer, wherein the control electrode overlaps the semiconductor pattern; forming an input electrode and an output electrode on the base layer, each of the input electrode and the output electrode being connected to the semiconductor pattern; as well as A light emitting element is formed on the base layer.

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