Electronic chip packaging structure and method thereof

By opening a groove on the finished carrier and installing the chip into the substrate to the carrier groove, combining the three-piece insulating high-temperature material lamination process and milling stamping and segmentation process, the problem of high cost of the existing molding packaging process is solved, and the production cost is reduced and production efficiency is improved.

CN111081561BActive Publication Date: 2025-06-06WUHAN CUIYAN TECHNOLOGY CO LTD
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Patent Information

Application Number
CN201911006540.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2019-06-25
Filing Date
2019-10-22
Publication Date
2025-06-06
Estimated Expiration
2039-10-22

AI Technical Summary

Technical Problem

The existing molding and packaging process leads to high production costs, mainly due to the expensive substrate material, large substrate consumption, long process time and low cutting efficiency of non-rectangular appearance finished products.

Method used

An electronic chip packaging method is adopted, including using a slot to open a finished product carrier, installing the chip to the substrate and bonding it to the slot of the finished product carrier, making the finished product carrier through a three-piece insulating high-temperature resistant material lamination process, and dividing the finished product carrier by means of insulating, milling or stamping to form the final product.

Benefits of technology

It effectively reduces production costs, improves production efficiency, reduces the consumption of substrate materials, and realizes large-scale mass production.

✦ Generated by Eureka AI based on patent content.

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Abstract

The purpose of the present invention is to provide an electronic chip packaging method to effectively reduce the production cost of the entire process in view of the cost disadvantage of the prior art. The present invention provides an electronic chip packaging method, which is characterized by comprising the following steps: a. obtaining a finished carrier and opening a groove on the finished carrier; b. installing the chip on a substrate; c. installing the substrate with the chip into the groove.
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Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to an electronic chip packaging structure and a method thereof. Background Art

[0002] At present, electronic chips are generally packaged using a molding packaging process. Molding packaging can ensure the mechanical strength, airtightness and electrical connection performance of the finished electronic device. One or more electronic chips are molded into an electronic device.

[0003] The continuous development of the molding packaging process has produced many branches of technical processes. These include BGA packaging process and LGA packaging process. Both of these packaging processes lead the pins of the chip through the substrate circuit to the bottom contact points of the electronic device formed after the molding package. The purpose of the BGA packaging process is to weld these contact points, so solder balls are added to the contact points; and the purpose of the LGA packaging process is to connect these contact points with the contacts of the connector. In order to obtain excellent mechanical strength and electrical connection performance, more and more electronic products are also manufactured using packaging processes similar to BGA and LGA. There are only some differences in the appearance size and the location layout of the contact points from the traditional BGA and LGA, and the process essence is almost exactly the same.

[0004] The specific process steps of this type of molding packaging process are as follows:

[0005] 1. Select a substrate material with high glass transition temperature (generally required to be about 175-230°C), high dimensional stability and low moisture absorption, good electrical performance and high reliability. Form a conductive circuit on this substrate.

[0006] 2. Bind or flip-chip or SMT one or more chips to the aforementioned substrate. Multiple substrates share a large-size substrate panel to improve production efficiency. Figure 1 shown.

[0007] 3. Place the substrate panel into the injection mold and inject the plastic sealant. Generally, epoxy resin mixture is used as the plastic sealant. Figure 2 shown.

[0008] 4. After the plastic encapsulation material attached to the substrate panel is solidified, it is cut according to the designed size specifications to form the final electronic device or electronic product.

[0009] In order to meet the requirements of the above process, the production cost is relatively high. The reasons are as follows:

[0010] 1. In order to make each component reach the appropriate performance index, the selected materials are relatively expensive. In order to obtain a substrate with a higher glass transition temperature, high dimensional stability and low moisture absorption, BT resin or ceramic must be used to produce the substrate. This makes the cost of the substrate very expensive.

[0011] 2. The process requirements for injecting plastic encapsulation materials require that the entire substrate surface be used as the bottom surface for injecting plastic encapsulation materials. This increases the consumption of the substrate. Taking TF cards and IoT cards as examples, their minimum necessary substrate area is only the area of ​​the contact point area. However, due to the molding packaging process, the entire bottom surface is used for the substrate.

[0012] 3. The injection molding process of electronic chip molding packaging takes a long time. If the area of ​​the electronic product or device is large, the efficiency of the substrate panel formation will be basically offset.

[0013] 4. For the cutting of non-rectangular finished products, currently both laser cutting and water jet cutting are required to complete the process, which is very inefficient.

[0014] Among the above reasons, the cost of the substrate accounts for more than half of the total production cost. Summary of the invention

[0015] The purpose of the present invention is to provide an electronic chip packaging method to effectively reduce the production cost of the entire process in view of the defects of the prior art.

[0016] The present invention provides an electronic chip packaging method, which is characterized by comprising the following steps:

[0017] a. Obtaining a finished carrier and opening a groove on the finished carrier;

[0018] b. Mounting the chip on the substrate;

[0019] c. Install the substrate with the chip into the slot.

[0020] In the step a, metal, ceramic or plastic packaging material is selected as the finished carrier of the electronic device or electronic product; if a metal material is selected as the finished carrier, the metal material is selected from a metal with a melting point higher than 300° C. and a low thermal expansion coefficient; a finished carrier and a groove of the required size are obtained by cutting or etching; the metal material is subjected to conductive insulation treatment; if ceramic or plastic packaging material is selected as the finished carrier, a groove is opened by injection molding;

[0021] In step a, the planar size of the groove on the finished carrier is larger than the planar size of the substrate; the groove is a step groove, wherein the substrate is arranged in the primary groove of the step groove, and the chip is arranged in the secondary groove of the step groove.

[0022] The step a comprises the following steps:

[0023] Three sheets of insulating high-temperature resistant materials with the same structural size are selected, and a first through hole is opened on the first sheet of insulating high-temperature resistant material, wherein the shape and size of the first through hole match the substrate; a second through hole is opened on the second sheet of insulating high-temperature resistant material, wherein the shape and size of the second through hole match the chip; a thermosetting adhesive / film is coated on the upper and lower surfaces of the second sheet of insulating high-temperature resistant material, and the first, second and third sheets of insulating high-temperature resistant materials are coaxially stacked from top to bottom, wherein the first through hole and the second through hole are coaxially arranged to form a groove; the first, second and third sheets of insulating high-temperature resistant materials are pressed into a whole by applying temperature and pressure to form a finished carrier.

[0024] The above technical solution also includes step d: using engraving, milling or stamping to divide the heated finished carrier into the desired shape to form a single final product, that is, a finished carrier is only provided with a substrate with a chip.

[0025] In the step b, one or more chip particles are bonded or flip-chip packaged or SMT-mounted onto the substrate.

[0026] In step b, the substrate may be glass fiber board, BT resin material, or high TG material. The above materials are commonly used circuit board materials, among which glass fiber board is the most common and has the lowest cost; high TG material has better dimensional stability than glass fiber board when the temperature changes; BT resin material has the best dimensional stability when the temperature changes and has the highest cost.

[0027] In step c, the substrate with the chip is bonded to the groove of the finished carrier using an adhesive that does not lose its adhesiveness at high temperatures, such as a thermosetting adhesive, AB adhesive, or anaerobic adhesive. The advantage of using adhesive is that it is easy to implement.

[0028] In step a, the plane size of the groove on the carrier is larger than the plane size of the substrate. The difference in the plane size between the groove and the substrate depends on the difference in thermal expansion coefficients between the components and the tolerance formed by production. The groove is a step groove. Since the chip protrudes from the plane of the substrate, a step groove is provided to provide installation space for the chip on the finished carrier. The primary groove of the step groove, that is, the first through hole, is a rectangular structure for placing the substrate; the secondary groove, that is, the second through hole, is a circular structure, which provides installation space for the chip on the carrier. The chip is arranged in the secondary groove.

[0029] In step c, the adhesive is applied to the side of the substrate with the chip and the edges of the substrate to effectively ensure the installation stability of the substrate and the carrier. The substrate coated with adhesive is placed in the groove of the carrier and pressure is applied. After at least 10 seconds, the substrate and the carrier are fixedly bonded; the side of the substrate with the chip faces the carrier groove.

[0030] The step c comprises placing the substrate coated with adhesive in the slot, heating and pressurizing the three sheets of insulating high temperature resistant materials with a laminator, and placing the three sheets of insulating high temperature resistant materials in a heating furnace for continuous heating after lamination. The substrate is placed in the carrier slot with the chip side facing the carrier slot.

[0031] In the step a, a plurality of evenly distributed grooves are formed on the finished product carrier; a substrate with a chip is placed in each groove;

[0032] In the step d, the heated finished carrier is divided by engraving, milling or punching to form a plurality of individual final products, that is, one finished carrier is provided with only one substrate with a chip.

[0033] The present invention also provides an electronic chip packaging structure, which is characterized by comprising a finished carrier, a substrate and a chip; a groove is provided on the finished carrier, and the chip is fixed on the substrate; the substrate is arranged in the groove; a side of the substrate with the chip faces the groove; the substrate and the finished carrier are fixedly connected and packaged by adhesive.

[0034] The finished carrier includes three sheets of insulating high-temperature resistant materials with the same structural size. A first through hole is opened on the first sheet of insulating high-temperature resistant material, wherein the shape and size of the first through hole match the substrate; a second through hole is opened on the second sheet of insulating high-temperature resistant material, wherein the shape and size of the second through hole match the chip; the upper and lower surfaces of the second sheet of insulating high-temperature resistant material are coated with thermosetting glue / film, the first, second and third sheets of insulating high-temperature resistant materials are coaxially stacked from top to bottom, wherein the first through hole and the second through hole are coaxially arranged to form a groove; the first, second and third sheets of insulating high-temperature resistant materials are pressed into a whole by applying temperature and pressure to form a finished carrier.

[0035] The chip includes one or more particles, which are mounted on the substrate through bonding, flip-chip packaging or SMT process.

[0036] The substrate can be made of glass fiber board, BT resin material, and high TG material. The above materials are commonly used circuit board materials, among which glass fiber board is the most common and has the lowest cost; high TG material has better dimensional stability than glass fiber board when the temperature changes; BT resin material has the best dimensional stability when the temperature changes and has the highest cost.

[0037] The adhesive is a thermosetting adhesive, AB adhesive or anaerobic adhesive. The substrate with the chip is bonded to the groove of the finished carrier by using an adhesive that does not lose its viscosity at high temperatures.

[0038] The plane size of the groove on the finished carrier is larger than the plane size of the substrate; the groove is a step groove, and the step groove includes a primary groove and a secondary groove extending sequentially into the interior of the finished carrier; the first through hole and the upper surface of the second insulating high temperature resistant material cooperate to form a primary groove, wherein the substrate is arranged in the primary groove of the step groove, the first through hole and the upper surface of the second insulating high temperature resistant material cooperate to form a secondary groove, and the chip is arranged in the secondary groove of the step groove. Since the chip protrudes from the plane of the substrate, a step groove is arranged to provide installation space for the chip on the finished carrier.

[0039] The adhesive is coated on the side of the substrate with the chip and the edges around the substrate, effectively ensuring the installation stability of the substrate and the carrier.

[0040] The finished carrier is made of metal, ceramic or plastic packaging material; the metal material is a metal with a melting point higher than 300°C and a low thermal expansion coefficient; a cutting or etching method is used to obtain a finished carrier and a groove of the required size; the metal material is subjected to conductive insulation treatment; if the finished carrier is made of ceramic or plastic packaging material, a groove is opened through an injection molding process.

[0041] The materials used in the present invention are all high temperature resistant and have good dimensional stability under temperature changes; sealing measures are adopted to prevent moisture from directly contacting the chip grains, which effectively plays a waterproof role and will not cause the size of the product to be forced to expand. The selection of the substrate material of the present invention does not need to be very harsh, and generally all substrate materials that can be reflow soldered can meet the requirements. The area of ​​the substrate of the present invention can be adjusted according to the required area of ​​the actual contact position, and it is not necessary for the bottom of the entire finished product to be a substrate. Taking TF cards and Internet of Things cards as examples, their minimum necessary substrate areas are the areas of the contact point areas respectively. The process of producing the carrier of the present invention and the bonding process of the carrier and the substrate can realize large-scale batch production, and the production method is very simple. Therefore, the present invention can effectively reduce the cost of packaging. The finished product carrier is made of insulating high temperature resistant materials. The product has good mechanical strength and a certain toughness, and is close to the material composition of the substrate, the bonding force between the two is strong, the thermal expansion coefficients of the two are basically the same, and it is not easy to deform after high and low temperature changes, and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of the prior art structure

[0043] Figure 2 This is a schematic diagram of the prior art packaging

[0044] Figure 3 It is a schematic diagram of the structure of the present invention

[0045] Figure 4 This is a schematic diagram of the finished carrier of the present invention.

[0046] Figure 5 This is a schematic diagram of the connection between the chip and the substrate of the present invention.

[0047] Figure 6 This is a schematic diagram of the substrate packaging of the present invention

[0048] Figure 7 It is a schematic diagram of the process of the present invention.

[0049] Figure 8 It is a process schematic diagram of the present invention.

[0050] Among them, 1-substrate, 2-chip, 3-injection mold, 4-finished product carrier, 5-slot, 6-pin, 7-metal wire, 8-thermosetting adhesive film, 9-insulating high temperature resistant material, 91-first piece of insulating high temperature resistant material, 92-second piece of insulating high temperature resistant material, 93-third piece of insulating high temperature resistant material, 10-first through hole, 11-second through hole, 12-final product. DETAILED DESCRIPTION

[0051] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments to facilitate a clear understanding of the present invention, but they do not constitute a limitation on the present invention.

[0052] As shown in the figure, the present invention provides two specific embodiments of packaging an Internet of Things card. However, it is not limited to Internet of Things cards. The same method can also be used to produce other products such as TF cards that originally use a molding packaging process. The steps of specific embodiment 1 are as follows:

[0053] 1. Select a 0.2 mm thick sheet of insulating high temperature resistant material 91, and punch the first through hole 10 (rectangular) of the slot 5, the positioning hole, and the exhaust hole on it.

[0054] 2. Select a 0.35mm thick sheet of insulating high temperature resistant material 92, and apply a 0.025mm thick heat curing adhesive / film on both sides, and then use a drilling machine or mold to open the second through hole 11 (circular) and positioning holes and exhaust holes of the groove 5 on it.

[0055] 3. Place the first insulating high temperature resistant material 91 of step 1 on the top, the second insulating high temperature resistant material 92 of step 2 in the middle, and place a 0.2 mm thick sheet material, i.e., the third insulating high temperature resistant material 93, below. Align the three materials according to the set position, stack them together, and slightly apply temperature and pressure to make the three materials initially become a whole (the heat curing glue / film is not completely cured). The first through hole and the second through hole are coaxially arranged to cooperate with the upper surface of the third insulating high temperature resistant material 93 to form a groove 5; the size of the groove 5 is not clearly defined with the substrate 1, and depends on the difference in thermal expansion coefficients between the components and the tolerance formed by production. The groove 5 is a step groove. Since the chip 2 protrudes from the plane of the substrate 1, a step groove is set to provide installation space for the chip 2 on the finished carrier 4. The first groove of the step groove, i.e., the first through hole, is a rectangular structure for placing the substrate 1; the second groove, i.e., the second through hole, is a circular structure to provide installation space for the chip 2 on the carrier. The chip 2 is arranged in the second groove.

[0056] 4. A circuit board with a printed circuit is selected as the substrate 1. One plane of the substrate 1 has at least 5 metal contacts for connecting with the socket contacts of the application device; one plane of the substrate 1 has at least 5 pins 6 for connecting with the IoT card chip 2. Each metal contact on both sides of the substrate 1 is connected to each pin 6 through a conductive line of a metal wire. There is no special requirement for the material of the substrate 1, as long as it can pass the reflow soldering. The plane size of the substrate 1 is slightly smaller than the plane size of the slot 5 of the carrier. Figure 5 The other side of the plane where the metal contacts of the substrate 1 are located is shown.

[0057] 5. Bind the chip 2 required for the IoT card to the side with at least 5 pins 6 on the substrate 1 by particle bonding or flip-chip packaging or SMT process. In this way, the chip 2 is connected to the pins 6 on the substrate 1 and finally connected to the metal contacts on the other side. Figure 5 The diagram shown is a schematic diagram of the chip 2 being bound.

[0058] 6. Place the substrate 1 processed in step 5 into the groove 5, and use a laminator to heat and pressurize the three sheets of insulating high temperature resistant materials 9 stacked with the substrate 1 for a period of time (180°C, preheat exhaust for 10s, then 30kg / cm 3 After the lamination is completed, the insulating high temperature resistant material 9 is placed in a heating furnace and heated at 180° C. for more than 60 minutes.

[0059] 7. The heated insulating high temperature resistant material 9 is finally divided into final products 12 by means of engraving, milling or punching to finally separate the assembled product of multiple products.

[0060] Effect of the invention:

[0061] 1. The Internet of Things card manufactured by the above method reduces the size of the substrate 1, expands the selection range of the substrate 1 material, and the process can be mass-produced, which greatly reduces the production cost. In this embodiment, the size of the substrate 1 is less than a quarter of that of the molding process.

[0062] 2. The finished carrier is made by three-layer material lamination process ( Figure 6 , Figure 7 ) is similar to the process of producing multi-layer circuit boards in PCB factories, so general PCB factories can achieve mass production without adding specific equipment; the plate-making mode is adopted, and formal lamination is performed after the substrate 1 is placed in the slot 5, which can greatly improve production efficiency.

[0063] The implementation steps of specific embodiment 2 are as follows:

[0064] 1. Select an aluminum alloy sheet with a thickness of about 0.8 mm, a low thermal expansion coefficient and a high hardness, namely, aviation aluminum sheet as the finished product carrier 4.

[0065] 2. Perform CNC processing on the aviation aluminum sheet. Mill a groove 5 on one of the planes of the aviation aluminum sheet, and make cuts around the plane. The semi-finished product of the Internet of Things card carrier as shown in the figure is obtained. The size of the groove 5 is not clearly limited to the size difference between the substrate 1, which depends on the difference in thermal expansion coefficients between the components and the tolerance formed by production. The groove 5 is a step groove. Since the chip 2 protrudes from the plane of the substrate 1, a step groove is set to provide installation space for the chip 2 on the finished carrier 4. The first-level groove of the step groove is a rectangular structure for placing the substrate 1; the second-level groove is a circular structure, which is easy to open and provides installation space for the chip 2 on the carrier. Chip 2 is set in the secondary groove.

[0066] 3. Then, the outer surface of the semi-finished IoT card carrier of step 2 is anodized to obtain a finished carrier. After anodization, the surface of the carrier is insulated and no longer conductive. Moreover, after anodization, the color of the carrier surface can be changed to any color such as gold, silver, black, etc. as needed.

[0067] 4. A circuit board with a printed circuit is selected as the substrate 1. One plane of the substrate 1 has at least 5 metal contacts for connecting with the socket contacts of the application device; one plane of the substrate 1 has at least 5 pins 6 for connecting with the IoT card chip 2. Each metal contact on both sides of the substrate 1 is connected to each pin 6 through a conductive line of a metal wire. There is no special requirement for the material of the substrate 1, as long as it can pass the reflow soldering. The plane size of the substrate 1 is slightly smaller than the plane size of the slot 5 of the carrier. Figure 5 The other side of the plane where the metal contacts of the substrate 1 are located is shown.

[0068] 5. Bind the chip 2 required for the IoT card to the side with at least 5 pins 6 on the substrate 1 by particle bonding or flip-chip packaging or SMT process. In this way, the chip 2 is connected to the pins 6 on the substrate 1 and finally connected to the metal contacts on the other side. Figure 5 The diagram shown is a schematic diagram of the chip 2 being bound.

[0069] 6. At a temperature of about 70°C, a heat-curing adhesive film 8 is attached to the substrate 1 with the chip 2. The heat-curing adhesive film 8 is attached to the side of the substrate 1 with the chip 2, and the edges of the substrate 1 are basically attached with the heat-curing adhesive film 8. Figure 6 shown.

[0070] 7. At a temperature of about 180°C, place the substrate 1 processed in step 6 into the carrier groove 5 and apply a certain pressure. After several tens of seconds, the substrate 1 and the carrier are completely bonded together. In the future, the two will not separate under a temperature environment below 300°C. The side of the substrate 1 with the chip 2 faces the carrier groove 5.

[0071] Effect of the invention:

[0072] 1. The Internet of Things card manufactured by the above method reduces the size of the substrate 1, expands the selection range of the substrate 1 material, and the process can be mass-produced, which greatly reduces the production cost. In this embodiment, the size of the substrate 1 is less than a quarter of that of the molding process.

[0073] 2. Because aluminum alloy is used as the carrier, the mechanical strength of the product is enhanced, especially the toughness of the product is enhanced, and the heat dissipation capacity is increased.

[0074] 3. The anodizing treatment of metal can be colorful, so the color of the product is no longer limited to the black of the molded package.

[0075] The contents not described in detail in this specification belong to the prior art known to professional and technical personnel in this field.

Claims

1. A method for packaging an electronic chip, Features The following steps are involved: a. Obtaining a finished carrier and opening a groove on the finished carrier; b. Mounting the chip on the substrate; c. Install the substrate with the chip into the slot; d. Use engraving, milling or stamping to divide the heated finished carrier into the desired shape to form a single final product, that is, a finished carrier is provided with only one substrate with a chip and the finished carrier meets the required size and shape; The step a comprises the following steps: Three sheets of insulating high-temperature resistant materials with the same structural size are selected, a first through hole is opened on the first sheet of insulating high-temperature resistant material, wherein the shape and size of the first through hole match the substrate; a second through hole is opened on the second sheet of insulating high-temperature resistant material, wherein the shape and size of the second through hole match the chip; a thermosetting adhesive / film is coated on the upper and lower surfaces of the second sheet of insulating high-temperature resistant material, and the first, second and third sheets of insulating high-temperature resistant materials are coaxially stacked from top to bottom, wherein the first through hole and the second through hole are coaxially arranged to form a groove; the first, second and third sheets of insulating high-temperature resistant materials are pressed into a whole by applying temperature and pressure to form a finished carrier; The step c comprises applying adhesive to the side of the substrate with the chip and the edges around the substrate; placing the substrate coated with adhesive into the groove of the carrier and applying pressure, and after at least 10 seconds, the substrate and the carrier are fixedly bonded; wherein the side of the substrate with the chip faces the carrier groove; The step c comprises: after the substrate is placed in the groove, heating and pressurizing the three sheets of insulating high temperature resistant materials with a laminator, and after the lamination is completed, placing the three sheets of insulating high temperature resistant materials in a heating furnace for continuous heating; wherein the side of the substrate with the chip faces the groove; In the step a, a plurality of evenly distributed grooves are formed on the finished product carrier; a substrate with a chip is placed in each groove; In the step d, the heated finished carrier is divided by engraving, milling or punching to form a plurality of individual final products.

2. The electronic chip packaging method according to claim 1, Features In the step a, the sheet-like insulating high temperature resistant material is an epoxy board, a glass fiber board or FR4.

3. The electronic chip packaging method according to claim 1, Features The step b includes binding or flip-chipping one or more chip particles or mounting them on the substrate using SMT technology; in the step b, the substrate can be made of glass fiber board, BT resin material, or high TG material.

4. The electronic chip packaging method according to claim 1, Features In the step a, metal, ceramic or plastic packaging material is selected as the finished product carrier of the electronic device or electronic product; If a metal material is selected as the finished carrier, the metal material is selected from metals with a melting point higher than 300°C and a low thermal expansion coefficient; a finished carrier and a slot of the required size are obtained by cutting or etching; the metal material is subjected to conductive insulation treatment; if ceramic or plastic packaging material is selected as the finished carrier, a slot is opened by injection molding; In step a, the planar size of the groove on the finished carrier is larger than the planar size of the substrate; the groove is a step groove, wherein the substrate is arranged in the primary groove of the step groove, and the chip is arranged in the secondary groove of the step groove.

5. An electronic chip packaging structure, Features It includes a finished product carrier, a substrate and a chip; the finished product carrier is provided with a groove, the chip is fixed on the substrate; the substrate is arranged in the groove; the side of the substrate with the chip faces the groove; the substrate and the finished product carrier are fixedly connected and packaged by adhesive; The heated finished carrier is divided by engraving, milling or punching to form a desired shape to form a single final product, that is, a finished carrier is provided with only one substrate with a chip and the finished carrier meets the desired size and shape; Three sheets of insulating high-temperature resistant materials with the same structural size are selected, a first through hole is opened on the first sheet of insulating high-temperature resistant material, wherein the shape and size of the first through hole match the substrate; a second through hole is opened on the second sheet of insulating high-temperature resistant material, wherein the shape and size of the second through hole match the chip; a thermosetting adhesive / film is coated on the upper and lower surfaces of the second sheet of insulating high-temperature resistant material, and the first, second and third sheets of insulating high-temperature resistant materials are coaxially stacked from top to bottom, wherein the first through hole and the second through hole are coaxially arranged to form a groove; the first, second and third sheets of insulating high-temperature resistant materials are pressed into a whole by applying temperature and pressure to form a finished carrier; Apply adhesive to the side of the substrate with the chip and the edges around the substrate; put the substrate coated with adhesive into the groove of the carrier and apply pressure, and after at least 10 seconds, the substrate and the carrier are fixedly bonded; the side of the substrate with the chip faces the carrier groove; After the substrate is placed in the groove, a laminator is used to heat and pressurize the three sheets of insulating high-temperature resistant materials. After the lamination is completed, the three sheets of insulating high-temperature resistant materials are placed in a heating furnace for continuous heating; the substrate is placed with the chip side facing the groove; A plurality of evenly distributed grooves are opened on the finished product carrier; a substrate with a chip is placed in each groove; The heated finished carrier is divided by engraving, milling or punching to form several individual final products.

Citation Information

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