Transistor and method for manufacturing the same

Abstract

Several of the described embodiments provide transistors with negative capacitance and methods of making the same. The transistor includes a gate structure having a ferroelectric layer. The ferroelectric layer is formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of the thickness of the ferroelectric layer.

Description

Technical Field

[0001] The present disclosure relates to a transistor and a method for manufacturing the same. Background Art

[0002] Field effect transistors (FETs) are used in a variety of semiconductor devices. Generally speaking, a field effect transistor includes a gate structure located above a channel region and between a source region and a drain region. The gate structure usually includes a gate dielectric layer on the channel region and a gate electrode on the gate dielectric layer.

[0003] One type of field effect transistor that is becoming increasingly popular is the negative capacitance field effect transistor (NCFET). Compared to conventional field effect transistors, the gate structure of a negative capacitance field effect transistor has negative capacitance. A negative capacitance field effect transistor has a number of advantages over other transistors. For example, a negative capacitance field effect transistor typically has a lower subthreshold swing than other transistors and can switch between conducting and non-conducting states faster than other transistors. Summary of the invention

[0004] According to one embodiment of the present disclosure, a transistor includes a substrate, a dielectric layer, a fin, first and second spacers, a gate dielectric layer, a ferroelectric layer, and a gate electrode. The dielectric layer is located on the substrate. The fin extends from the substrate, through the dielectric layer, and beyond the surface of the dielectric layer. The first and second spacers are located on the fin. The gate dielectric layer is located on the surface of the dielectric layer and on at least three sides of the fin. The ferroelectric layer is located on the gate dielectric layer and on at least three sides of the fin, the ferroelectric layer is separated from the fin and the first and second spacers by the gate dielectric layer, and the ferroelectric layer has a thickness less than or equal to 5 nanometers. The gate electrode is located on the ferroelectric layer.

[0005] According to one embodiment of the present disclosure, a method for manufacturing a transistor includes: forming a fin from a substrate; forming a dielectric layer on the substrate, the fin extending through the dielectric layer and exceeding a surface of the dielectric layer; forming a first spacer and a second spacer on the fin; forming a gate dielectric layer on at least three sides of the fin; forming a ferroelectric layer on the gate dielectric layer and on at least three sides of the fin, the ferroelectric layer being separated from the fin and the first spacer and the second spacer by the gate dielectric layer, the formation of the ferroelectric layer including forming a ferroelectric film having a first thickness, annealing the ferroelectric film, and reducing the thickness of the ferroelectric film to a second thickness less than the first thickness; and forming a gate electrode on the ferroelectric layer.

[0006] According to one embodiment of the present disclosure, a method for manufacturing a transistor includes: forming a first fin, the first fin extending from a substrate, the first fin including a channel region with a first width; forming a second fin, the second fin extending from the substrate, the second fin including a channel region with a second width; forming a first spacer and a second spacer on the first fin; forming a third spacer and a fourth spacer on the second fin; forming a gate dielectric layer on at least three sides of the first fin and at least three sides of the second fin; forming a ferroelectric layer on the gate dielectric layer and on at least three sides of the first fin, the ferroelectric layer being separated from the first fin and the first spacer and the second spacer by the gate dielectric layer; and forming a high dielectric constant dielectric layer on the gate dielectric layer and on at least three sides of the second fin, the ferroelectric layer being separated from the second fin and the third spacer and the fourth spacer by the gate dielectric layer.

[0007] According to one embodiment of the present disclosure, a method for manufacturing a transistor includes: forming a dielectric layer on a substrate; forming a fin extending from the substrate, passing through the dielectric layer and exceeding a surface of the dielectric layer; forming a first spacer and a second spacer on the fin; forming a gate dielectric layer on the surface of the dielectric layer and on at least three sides of the fin; forming a ferroelectric layer on the gate dielectric layer and on at least three sides of the fin, the ferroelectric layer being separated from the fin and the first spacer and the second spacer by the gate dielectric layer, the ferroelectric layer having a thickness less than or equal to 5 nanometers; and forming a gate electrode on the ferroelectric layer.

[0008] According to one embodiment of the present disclosure, a transistor includes a substrate, a first fin, a second fin, a first spacer, a second spacer, a third spacer, a fourth spacer, a gate dielectric layer, and a ferroelectric layer. The first fin extends from the substrate, and the first fin includes a source region, a drain region, and a channel region. The second fin extends from the substrate, and the second fin includes a source region, a drain region, and a channel region. The first spacer and the second spacer are located on the first fin. The third spacer and the fourth spacer are located on the second fin. The gate dielectric layer is located on at least three sides of the first fin and on at least three sides of the second fin. The ferroelectric layer is located on the gate dielectric layer, and the ferroelectric layer is separated from the first fin, the first spacer, and the second spacer by the gate dielectric layer, and the ferroelectric layer is separated from the second fin, the third spacer, and the fourth spacer by the gate dielectric layer.

[0009] According to one embodiment of the present disclosure, a transistor includes a substrate, a dielectric layer, a fin, a first spacer, a second spacer, a gate dielectric layer, a ferroelectric layer, and a gate electrode. The dielectric layer is located on the substrate. The fin is located on the substrate, and the fin extends through the dielectric layer. The first spacer and the second spacer are located on the fin. The gate dielectric layer is located on the dielectric layer and the fin. The ferroelectric layer is located on the gate dielectric layer, and the ferroelectric layer is separated from the fin and the first spacer and the second spacer by the gate dielectric layer. The gate electrode is located on the ferroelectric layer.

[0010] According to one embodiment of the present disclosure, a method for manufacturing a transistor includes: forming a fin on a substrate; forming a dielectric layer on the substrate, wherein the fin extends through the dielectric layer and exceeds the dielectric layer; forming a first spacer and a second spacer on the fin; forming a gate dielectric layer on the dielectric layer and on at least three sides of the fin; forming a ferroelectric layer on the gate dielectric layer, wherein the ferroelectric layer is separated from the fin and the first spacer and the second spacer by the gate dielectric layer; and forming a gate electrode on the ferroelectric layer.

[0011] According to one embodiment of the present disclosure, a method for manufacturing a transistor includes: forming a first fin on a substrate, the first fin including a channel region with a first width; forming a second fin on the substrate, the second fin including a channel region with a second width; forming a first spacer and a second spacer on the first fin; forming a third spacer and a fourth spacer on the second fin; forming a first dielectric layer on at least three sides of the first fin and at least three sides of the second fin; forming a ferroelectric layer on the first dielectric layer, the ferroelectric layer being separated from the first fin and the first spacer and the second spacer by the first dielectric layer; and forming a second dielectric layer on the first dielectric layer, the ferroelectric layer being separated from the second fin and the third spacer and the fourth spacer by the second dielectric layer.

[0012] According to one embodiment of the present disclosure, a method for manufacturing a transistor includes: forming a fin on a substrate; forming a first spacer and a second spacer on the fin; forming a gate dielectric layer on the dielectric layer and on at least three sides of the fin and on the first spacer and the second spacer; forming a ferroelectric layer on the gate dielectric layer, the ferroelectric layer being separated from the fin and the first spacer and the second spacer by the gate dielectric layer; and forming a gate electrode on the ferroelectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The embodiments of the present disclosure are best understood by the following detailed description with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased to facilitate discussion.

[0014] Figure 1 is an enlarged view of a component according to some embodiments;

[0015] Figure 2 According to some embodiments, Figure 1 a cross-sectional view of the elements of the shaft shown;

[0016] Figure 3 According to some embodiments, Figure 1 a cross-sectional view of the elements of the shaft shown;

[0017] FIG. 4A to FIG. 4C is a diagram showing a method according to some embodiments Figure 1 A cross-sectional view of a method for manufacturing a component;

[0018] FIG. 5A to FIG. 5F is a cross-sectional view illustrating a method for manufacturing a gate structure of a transistor having a first channel width according to some embodiments;

[0019] FIG. 6A to FIG. 6F is a cross-sectional view illustrating a method for manufacturing a gate structure of a transistor with a second channel width according to some embodiments.

[0020]

Explanation of symbols

[0021] 10: Substrate

[0022] 11: Shallow Trench Isolation Area

[0023] 12: Transistor

[0024] 14: Fins

[0025] 16, 60, 62: Gate structure

[0026] 17: Surface

[0027] 18: Source region

[0028] 19: Gap wall

[0029] 20: Drain region

[0030] 21: Interlayer dielectric

[0031] 22: First side

[0032] 24: Second side

[0033] 26: Upper surface

[0034] 28: Gate dielectric layer

[0035] 30: Ferroelectric layer

[0036] 32: Gate electrode

[0037] 34: Channel area

[0038] 36: Contact Etch Stop Layer

[0039] 40: First surface

[0040] 42: Second Surface

[0041] 44, 46: Side

[0042] 50: Inner surface

[0043] 52: Ferroelectric film

[0044] 54, 58: Groove

[0045] 56: Protective layer

[0046] 64: High dielectric constant dielectric layer

[0047] 8: Components

[0048] t1, t2: thickness

[0049] w1: first width

[0050] w2: channel width

[0051] w3: first channel width

[0052] w4: Second channel width DETAILED DESCRIPTION

[0053] The following disclosure provides many different embodiments or examples to implement different features of a given subject matter. Specific examples of components and configurations are described below to simplify the present description. Of course, these are merely examples and are not intended to be limiting. For example, in the description, a first feature formed on or above a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which other features are formed between the first and second features, so that the first feature and the second feature may not be in direct contact. In addition, the embodiments of the present disclosure may repeat reference symbols and / or letters in multiple examples. This repetition is for the purpose of simplicity and does not essentially specify the relationship between the multiple embodiments and / or configurations discussed.

[0054] Additionally, spatial relative terms such as "beneath," "below," "lower," "above," "upper," etc. may be used herein to concisely describe the relationship of one element or feature to another element or feature as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted likewise.

[0055] Electronic components continue to become smaller and include more complex circuits. Therefore, there is a need to shrink electronic components to have smaller sizes. Unfortunately, it is difficult to manufacture negative capacitance field effect transistors with reduced sizes. As previously described, a negative capacitance field effect transistor includes a gate structure with negative capacitance. In order to allow the gate structure to have negative capacitance, a ferroelectric layer is included in the gate structure. As the size of the negative capacitance field effect transistor is reduced, existing methods for manufacturing negative capacitance field effect transistors are generally unable to properly form the ferroelectric layer. For example, when the ferroelectric layer is thin (e.g., between 2 nanometers and 3 nanometers), existing methods often cannot properly form the crystalline structure of the ferroelectric layer. As another example, when the ferroelectric layer is thin and the transistor has a large channel width (e.g., greater than or equal to 100 nanometers), existing methods often cannot form the ferroelectric layer at all. Therefore, existing methods are generally unable to manufacture negative capacitance field effect transistors with reduced sizes.

[0056] Embodiments disclosed herein are directed to transistors with negative capacitance and methods for manufacturing the same. According to various embodiments disclosed herein, the size of the transistor can be enlarged or reduced. Therefore, the transistor disclosed herein is suitable for use in transistors that require a variety of sizes.

[0057] Figure 1 is an enlarged view of element 8 according to some embodiments. Figure 2 According to some embodiments, Figure 1 A cross-section of an element 8 of the shaft is shown. Figure 3 According to some embodiments, Figure 1 A cross-sectional view of the shaft element 8 is shown. Figures 1 to 3 To facilitate understanding.

[0058] Device 8 includes substrate 10, shallow trench isolation (STI) region 11, and transistor 12. As will be discussed in further detail below, multiple layers within device 8 are shown. Figure 1 Various components of element 8 are not shown.

[0059] Substrate 10 provides support for transistor 12. Substrate 10 may include a silicon substrate and / or other elemental semiconductors, such as germanium. Alternatively or additionally, substrate 10 may include a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and / or indium phosphide. In addition, substrate 10 may include a silicon on insulator (SOI) structure. Substrate 10 may also include an epitaxial layer and / or may be strained to enhance performance. Substrate 10 may also include a variety of doping configurations depending on the design of transistor 12, such as a P-type substrate and / or an N-type substrate.

[0060] In one embodiment, various other electronic components are fabricated in or on the substrate 10. For example, transistors, resistors, capacitors, etc. may be fabricated in or on the substrate 10 along with the transistor 12.

[0061] Shallow trench isolation regions 11 are formed on the substrate 10 and between the transistors 12. The shallow trench isolation regions 11 isolate the transistors 12 from each other and prevent leakage current between the transistors 12. The shallow trench isolation regions 11 can be made of silicon oxide or any other suitable dielectric material. In one embodiment, the shallow trench isolation regions 11 are made of a single dielectric layer.

[0062] The shallow trench isolation region 11 may be formed by a variety of semiconductor process technologies. For example, the shallow trench isolation region 11 may be formed by chemical vapor deposition (CVD), high-density plasma CVD, spin coating, sputtering, or other suitable methods. In one embodiment, the shallow trench isolation region 11 is formed after the fin 14 is formed. For example, in one embodiment, the fin 14 is formed from the substrate 10 by, for example, an etching or patterning process. Then, the shallow trench isolation region 11 is formed on the substrate 10 and adjacent to the fin 14 by, for example, a combination of deposition, chemical mechanical planarization (CMP), and etch back processes, such as Figure 1 shown.

[0063] Transistors 12 are formed on substrate 10. In one embodiment, each transistor 12 is a negative capacitance field effect transistor. Each transistor 12 includes fins 14, gate structures 16, spacers 19, and contact etch stop layers (CESL) 36. Interlayer dielectrics (ILD) 21 are formed on transistors 12. As will be discussed in further detail below, to illustrate the multiple layers within device 8, Figure 1 Portions of the gate structure 16 , the spacer 19 , the contact etch stop layer 36 , and the interlayer dielectric 21 are not shown.

[0064] Although Figure 1 and Figure 2 Two transistors 12 are shown, but device 8 may include any number of transistors. For example, device 8 may include an array of multiple transistors arranged in multiple columns and rows.

[0065] The fins 14 are formed on the substrate 10 and extend between the shallow trench isolation regions 11. Figure 1 and Figure 2As shown, the fin 14 extends from the substrate 10 and is between the shallow trench isolation regions 11 and exceeds the upper surface 17 of the shallow trench isolation regions 11 , so that a portion of the fin 14 is located above the upper surface 17 of the shallow trench isolation regions 11 .

[0066] In one embodiment, the fin 14 is made of a semiconductor material, such as silicon, germanium, silicon carbide, indium phosphide, gallium arsenide, indium arsenide, or a combination thereof. In one embodiment, the fin 14 is made of the same material as the substrate 10 .

[0067] The fins 14 may be formed by various semiconductor process technologies. For example, the fins 14 may be formed by chemical vapor deposition, high-density plasma CVD, spin coating, sputtering, or other suitable methods. As another embodiment, the fins 14 may be formed by etching or patterning the substrate 10 .

[0068] In one embodiment, each fin 14 has a substantially uniform width. Figure 1 and Figure 2 As shown, each fin 14 has a first width w1. In one embodiment, the first width w1 is between 5 nanometers and 15 nanometers. It should be noted that the first width w1 is not limited to the foregoing, and in other embodiments may be smaller or larger than the given example. For example, the element 8 may be reduced so that the first width w1 is between 2 nanometers and 3 nanometers, or the element 8 may be enlarged so that the first width w1 is between 25 nanometers and 50 nanometers. In another embodiment, each fin 14 has a variable width. For example, in one embodiment, each fin 14 has a width that varies from a width less than the first width w1 to a width greater than the first width w1.

[0069] In one embodiment, each fin 14 has the same width. Figure 1 and Figure 2 As shown, each fin 14 has a first width w1. In another embodiment, the fins 14 have different widths from each other.

[0070] In one embodiment, if it is best to Figure 1 and Figure 2 As shown, the cross-section of the fins 14 each has a rectangular shape. However, other shapes are possible. For example, the cross-section of the fins 14 can have a diamond shape, a circle, etc.

[0071] Each fin 14 includes a source region 18 and a drain region 20. Figure 3 As shown, the source region 18 and the drain region 20 are located on opposite sides of the gate structure 16 .

[0072] The source region 18 and the drain region 20 are doped regions and may have any type of doping profile depending on the design of the transistor 12. For example, the source region 18 and the drain region 20 may be n-type or p-type doped regions with any degree of doping concentration. It should be noted that the positions of the source region 18 and the drain region 20 may be interchanged.

[0073] Source region 18 and drain region 20 may be formed using a variety of semiconductor processing techniques. For example, one or more dopant species, such as phosphorus, boron, etc., may be implanted into fin 14 to form source region 18 and drain region 20; or source 18 and drain 20 may be epitaxially grown.

[0074] The gate structure 16 is formed on the shallow trench isolation region 11 and on the fin 14. The gate structure 16 surrounds one or more sides of the fin 14. In one embodiment, as best shown in FIG. Figure 1 and Figure 2 As shown, the gate structure 16 is located on three different sides of the fin 14. That is, the gate structure 16 is formed on the first side 22, the second side 24 opposite the first side 22, and the upper surface 26 of the fin 14. The gate structure 16 includes a gate dielectric layer 28, a ferroelectric layer 30, and a gate electrode 32. As will be discussed in further detail below, for the multiple layers shown in the device 8, Figure 1 Portions of the gate structure 16 , the spacer 19 , the contact etch stop layer 36 , and the interlayer dielectric 21 are not shown.

[0075] The gate dielectric layer 28 is formed on the shallow trench isolation region 11 and the fin 14. The gate dielectric layer 28 electrically isolates the gate electrode 32 from the fin 14. In one embodiment, the gate dielectric layer 28 has an amorphous structure. However, the gate dielectric layer 28 may also have a crystalline structure.

[0076] In one embodiment, if it is best to Figure 1 and Figure 2 As shown, the gate dielectric layer 28 is formed on the first side 22 , the second side 24 opposite to the first side 22 , and the upper surface 26 of the fin 14 .

[0077] The gate dielectric layer 28 may be made of a variety of different dielectric materials. For example, the gate dielectric layer 28 may include nitride; silicon oxide; a high-k dielectric material selected from one or more of hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium oxysilicon nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), and / or hafnium zirconium oxide (HfZrO); combinations thereof; and / or other suitable materials.

[0078] In one embodiment, the gate dielectric layer 28 is a single dielectric layer. In another embodiment, the gate dielectric layer 28 includes a plurality of dielectric layers. For example, the gate dielectric layer 28 may include a first dielectric layer made of a first material, a second dielectric layer made of a second material, and a third dielectric layer made of a third material. The materials of the first, second and third dielectric layers may be selected from any of the dielectric materials described in the previous paragraph.

[0079] The gate dielectric layer 28 may be formed by various semiconductor processing techniques, such as chemical vapor deposition, high density plasma chemical vapor deposition, spin coating, sputtering, or other suitable methods.

[0080] The ferroelectric layer 30 is formed on the gate dielectric layer 28. The ferroelectric layer 30 is a material layer having ferroelectric properties, such as reversible electrical polarization. For example, the ferroelectric layer 30 may be made of HfSiO x ), aluminum oxide (Al2O3), hafnium zirconium oxide (HfZrO x ), doped hafnium zirconium oxide, lanthanum oxide (LaO x ), titanium dioxide (TiO2), hafnium dioxide, barium strontium titanate (BaSrTiO x ), lead zirconium titanate (PbZr x Ti y O z ), a combination thereof with various ratios, or any other suitable material. In one embodiment, the ferroelectric layer 30 has a crystalline structure. For example, the ferroelectric layer 30 may have an orthorhombic crystalline structure.

[0081] In one embodiment, if it is best to Figure 1 and Figure 2 As shown, the ferroelectric layer 30 is formed on the first side 22 , the second side 24 opposite to the first side 22 , and the upper surface 26 of the fin 14 .

[0082] The ferroelectric layer 30 has a thickness t1. In one embodiment, the ferroelectric layer 30 is a thin film. For example, in one embodiment, the thickness t1 is less than or equal to 5 nanometers. In one embodiment, the thickness t1 is between 2 nanometers and 3 nanometers. It should be noted that the thickness t1 is not limited to the above, and in other embodiments, it can be less than or greater than the given example. For example, the thickness t1 can be greater than 5 nanometers.

[0083] The following will refer to Figure 4A , Figure 4B and Figure 4C The fabrication of the ferroelectric layer 30 is discussed in more detail.

[0084] The gate electrode 32 is formed on the ferroelectric layer 30. Figure 3 As shown, gate electrode 32 is located directly over a channel region 34 extending between source region 18 and drain region 20 .

[0085] The channel region 34 has a channel width w2. In one embodiment, the channel region 34 has a narrow width (i.e., the channel region 34 is a short channel). For example, in one embodiment, the channel width w2 is less than or equal to 50 nanometers. As will be discussed in more detail below, the narrow width of the channel region 34 is beneficial in manufacturing the ferroelectric layer 30 to have a desired thickness and phase. It should be noted that the channel width w2 is not limited to the foregoing, and in other embodiments may be less than or greater than the examples given.

[0086] The channel region 34 can be made of a variety of materials. For example, the channel region 34 can be a silicon, silicon germanium, or germanium channel. In addition, the channel region 34 can be strained to increase performance, or relaxed. In one embodiment, the channel region 34 is a high mobility channel.

[0087] In one embodiment, if it is best to Figure 1 and Figure 2 As shown, the gate structure 16 is shared between the transistors 12. In this embodiment, the gate structure 16 is located above the two fins 14. In another embodiment, each transistor 12 includes its own gate structure. In this embodiment, a separate gate structure is formed above each transistor 12.

[0088] The gate electrode 32 is made of a conductive material. For example, the gate electrode 32 may be made of doped polysilicon; a metal such as hafnium, zirconium, titanium, tantalum, titanium nitride, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, copper, and / or tungsten; a combination thereof; or a multilayer thereof.

[0089] The gate electrode 32 may be formed by various semiconductor processing techniques. For example, the gate electrode 32 may be formed by chemical vapor deposition, high density plasma chemical vapor deposition, spin coating, sputtering, or other suitable methods.

[0090] The gate structure 16 (specifically, the gate dielectric layer 28, the ferroelectric layer 30, and the gate electrode 32), the source region 18, the drain region 20, and the channel region 34 are configured to provide negative capacitance. Negative capacitance provides a number of advantages over other types of transistors. For example, the negative capacitance of the gate structure 16 allows the transistor 12 to have a lower subthreshold swing than other types of transistors. As a result, the transistor 12 can switch between conducting and non-conducting states faster than other types of transistors.

[0091] The spacer 19 is formed on the upper surface 26 of the fin 14 and is located on the opposite side of the gate electrode 32. Figure 3As shown, the first spacer is located on the side of the first surface 40 of the gate electrode 32; and the second spacer is located on the side of the second surface 42 of the gate electrode 32 opposite to the first surface 40. The spacer 19 protects the sidewalls of the gate electrode 32. As discussed in more detail below, the spacer 19 is used during the fabrication of the gate dielectric layer 28, the ferroelectric layer 30, and the gate electrode 32 of the gate structure 16.

[0092] In one embodiment, the spacer 19 is made of a dielectric material. For example, the spacer 19 may be made of a nitride; a low-K dielectric material such as silicon oxynitride (SiO x N y ), silicon nitride (Si3N4), silicon monoxide (SiO), silicon oxycarbonitride (SiONC) and silicon oxycarbide (SiOC); combinations thereof; and / or other suitable materials.

[0093] A contact etch stop layer 36 is formed on the upper surface 26 of the fin 14 and on the opposite side of the gate electrode 32. Figure 3 As shown, a first contact etch stop layer is located on a side of a first surface 40 of the gate electrode 32; and a second contact etch stop layer is located on a side of a second surface 42 of the gate electrode 32 opposite the first surface 40. The contact etch stop layer 36 protects the fin 14. As will be discussed in more detail below, the contact etch stop layer 36 is used during the fabrication of the gate dielectric layer 28, the ferroelectric layer 30, and the gate electrode 32 of the gate structure 16.

[0094] In one embodiment, the contact etch stop layer 36 is made of a dielectric material. For example, the contact etch stop layer 36 may be made of a nitride; a low-K dielectric material such as silicon oxynitride (SiO x N y ), silicon nitride (Si3N4), silicon monoxide (SiO), silicon oxycarbonitride (SiONC) and silicon oxycarbide (SiOC); combinations thereof; and / or other suitable materials.

[0095] In one embodiment, if it is best to Figure 3 As shown, the contact etch stop layer 36 extends in a first direction along the upper surface 26 of the fin 14 , and the spacer 19 extends in a second direction transverse to the first direction along the sidewall of the gate electrode 32 .

[0096] The interlayer dielectric 21 is formed on the spacer 19 and the contact etch stop layer 36. In one embodiment, the interlayer dielectric 21 is also formed on the transistor 12. That is, the interlayer dielectric 21 can be directly formed on the gate structure 16.

[0097] In one embodiment, the interlayer dielectric 21 is used to form an interconnect layer. For example, the interlayer dielectric 21 can be used to electrically isolate the source region 18, the drain region 20 and / or the gate electrode 32 from being electrically coupled to other various electronic components (e.g., contact pads, transistors, capacitors, resistors, processors, etc.) and / or other interconnect layers. The interlayer dielectric 21 with the conductive dielectric is sometimes referred to as a metal layer.

[0098] The interlayer dielectric 21 can be made of a variety of dielectric materials. For example, the interlayer dielectric 21 can be made of nitride; low-K dielectric materials such as silicon oxynitride (SiO x N y ), silicon nitride (Si3N4), silicon monoxide (SiO), silicon oxycarbonitride (SiONC) and silicon oxycarbide (SiOC); combinations thereof; and / or other suitable materials.

[0099] The interlayer dielectric 21 may be formed by various semiconductor processing techniques, such as chemical vapor deposition, high density plasma chemical vapor deposition, spin coating, sputtering, or other suitable methods.

[0100] It should be noted that in order to show the various layers within the element 8, Figure 1 Not shown are portions of the gate dielectric layer 28, portions of the ferroelectric layer 30, the spacer 19, the contact etch stop layer 36, and the interlayer dielectric 21. Figure 1 and Figure 3 , can be collected Figure 1 The side 44 of the gate dielectric layer 28, the side 46 of the ferroelectric layer 30, the spacer 19, the contact etch stop layer 36 and the interlayer dielectric 21 are not shown. Figure 1 The first surface 40 of the gate electrode 32 is exposed.

[0101] As previously discussed, it is generally difficult to manufacture negative capacitance field effect transistors with reduced dimensions. As the dimensions of negative capacitance field effect transistors are reduced, existing methods of manufacturing negative capacitance field effect transistors generally fail to properly form the ferroelectric layer. For example, when the ferroelectric layer is thin (e.g., between 2 nanometers and 3 nanometers), existing methods often fail to properly form the crystalline structure of the ferroelectric layer. FIG. 4A to FIG. 4C FIG. 8 is a cross-sectional view illustrating a method for manufacturing the element 8 according to some embodiments. It should be noted that: FIG. 4A to FIG. 4C Display and Figure 3 The same cross-sectional view is shown. Also note that FIG. 4A to FIG. 4C The steps shown may be performed on each transistor 12 .

[0102] As per FIG. 4A to FIG. 4CThe method described can produce a ferroelectric layer (such as ferroelectric layer 30) regardless of its thickness. FIG. 4A to FIG. 4C The method described can produce a thin ferroelectric layer with a thickness between 2 nm and 3 nm. It should be noted that the thickness of the ferroelectric layer 30 is not limited to the above, and in other embodiments can be less or greater than the given example.

[0103] exist Figure 4A In, as per Figures 1 to 3 As discussed, the fin 14, the source region 18, the drain region 20, the channel region 34, the spacer 19, the contact etch stop layer 36, the interlayer dielectric 21, and the gate dielectric layer 28 are formed on the substrate 10. The gate dielectric layer 28 is formed on the inner surface 50 of the spacer 19 and the upper surface 26 of the fin 14.

[0104] After forming the fin 14, the source region 18, the drain region 20, the channel region 34, the spacer 19, the contact etch stop layer 36, the interlayer dielectric 21 and the gate dielectric layer 28, a ferroelectric film 52 is formed on the gate dielectric layer 28. The ferroelectric film 52 forms a trench 54. Figure 4C As discussed, the ferroelectric film 52 is used to form the ferroelectric layer 30. In one embodiment, when the ferroelectric film 52 is formed on Figure 4A When the ferroelectric film 52 is on the gate dielectric layer 28 in the embodiment of the present invention, the ferroelectric film 52 is in an amorphous state.

[0105] The ferroelectric film 52 has a thickness t2. In one embodiment, the thickness t2 is greater than the thickness t1 of the ferroelectric layer 30. For example, in one embodiment, when the thickness t1 of the ferroelectric layer 30 is less than or equal to 5 nanometers, the thickness t2 is greater than 5 nanometers. In one embodiment, the thickness t2 is greater than 5 nanometers and less than 15 nanometers. It should be noted that the thickness t2 is not limited to the above, and in other embodiments, it can be less than or greater than the given example. For the ferroelectric film 52, having a large thickness ensures that the ferroelectric film 52 properly covers the gate dielectric layer 28. In addition, as will be described in accordance with Figure 4B As discussed, the ferroelectric film 52 having a large thickness ensures that the ferroelectric film 52 has an appropriate phase after annealing.

[0106] The ferroelectric film 52 may be made of any suitable material to form a layer having ferroelectric properties. For example, the ferroelectric film 52 may be made of hafnium silicon oxide (HfSiO x ), aluminum oxide (Al2O3), hafnium zirconium oxide (HfZrO x ), doped hafnium zirconium oxide, lanthanum oxide (LaO x ), titanium dioxide (TiO2), hafnium dioxide (HfO2), barium strontium titanate (BaSrTiO x ), lead zirconium titanate (PbZr x Ti y O z), combinations thereof, or any other suitable materials.

[0107] The ferroelectric film 52 may be formed by various semiconductor processing techniques, such as chemical vapor deposition, high density plasma chemical vapor deposition, spin coating, sputtering, atomic layer deposition (ALD), or other suitable methods.

[0108] Once the ferroelectric film 52 is formed, a protective layer 56 is formed on the ferroelectric film 52 and in the trench 54. The protective layer 56 prevents the ferroelectric film 52 from being damaged during the annealing process. Figure 4B Let's discuss.

[0109] In one embodiment, the protection layer 56 is made of a conductive material, such as hafnium, zirconium, titanium, tantalum, titanium nitride, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, copper, and / or tungsten, combinations thereof, or multiple layers thereof.

[0110] Whether the material layer has ferroelectric properties depends on many factors, such as the elements contained in the material layer, the ratio of the elements contained in the material layer, and the phase of the material layer. As mentioned above, the ferroelectric film 52 can be made of any suitable material to form a layer having ferroelectric properties [e.g., hafnium silicon oxide (HfSiO x ), aluminum oxide (Al2O3), hafnium zirconium oxide (HfZrO x ), lanthanum oxide (LaO x ), titanium dioxide (TiO2), hafnium dioxide (HfO2), barium strontium titanate (BaSrTiO x ), lead zirconium titanate (PbZr x Ti y O z ), combinations thereof, or any other suitable material]. In addition, each material used for the ferroelectric film 52 may have varying element ratios. For example, the ferroelectric film 52 may be made of HfZrO2 or Hf x Zr 1-x O2, where x can be equal to 0 to 0.5. Figure 4B In the process, an annealing process is performed to change the phase of the ferroelectric film 52 so that the ferroelectric film 52 has ferroelectric properties. In particular, as discussed above, when the ferroelectric film 52 is formed on Figure 4A When the gate dielectric layer 28 is formed in the ferroelectric film 52, the ferroelectric film 52 is in an amorphous state. Figure 4BIn the embodiment, the ferroelectric film 52 is annealed to change the phase of the ferroelectric film 52 from an amorphous state to a crystalline state. For example, the ferroelectric film 52 may be annealed in a gas environment (e.g., an oxygen environment) between 650 and 900 degrees Celsius. In one embodiment, the ferroelectric film 52 is annealed using a spike annealing process, wherein the ferroelectric film 52 is heated to between 750 and 900 degrees Celsius and maintained for 25 to 35 seconds. Once the ferroelectric film 52 is annealed, the ferroelectric film 52 is annealed. Figure 4B The ferroelectric film 52 is crystalline and has ferroelectric properties.

[0111] It should be noted that due to the large thickness t2 of the ferroelectric film 52, the phase of the ferroelectric film 52 can be easily changed from an amorphous state to a crystalline state by an annealing process. If the ferroelectric film 52 is a thin film (e.g., having a thickness between 2 nanometers and 3 nanometers), the ferroelectric film 52 may not be changed from an amorphous state to a crystalline state by an annealing process. In this case, the ferroelectric film 52 will not have ferroelectric properties.

[0112] exist Figure 4C In the embodiment, the protective layer 56 and a portion of the ferroelectric film 52 are removed. A portion of the ferroelectric film 52 is removed to thin the ferroelectric film 52 to a desired thickness to form the ferroelectric layer 30. For example, the thickness t2 of the ferroelectric film 52 is reduced to Figure 3 The ferroelectric layer 30 is shown to have a thickness t1. The ferroelectric layer 30 forms a trench 58.

[0113] The protective layer 56 and a portion of the ferroelectric film 52 may be removed using a variety of semiconductor processing techniques. For example, the protective layer 56 and a portion of the ferroelectric film 52 may be removed using a masking and etching technique. In one embodiment, the upper surface of the interlayer dielectric 21, the gate dielectric layer 28, and a portion of the ferroelectric film 52 used to form the ferroelectric layer 30 are masked. The remaining portion of the ferroelectric film 52 and the protective layer 56 are exposed. Next, an etching process is performed to remove the exposed portion of the ferroelectric film 52 and the entire protective layer 56. In one embodiment, a single etching process is used to remove the exposed portion of the ferroelectric film 52 and the entire protective layer 56. In another embodiment, a first etching process is used to remove the entire protective layer 56, and then a second etching process is used to remove the exposed portion of the ferroelectric film 52. The ferroelectric film 52 is etched until a desired thickness is reached (for example, until the ferroelectric film 52 has a thickness less than or equal to 5 nanometers) to form the ferroelectric layer 30.

[0114] As discussed above, in one embodiment, the channel region 34 has a narrow width (eg, the channel region 34 is a short channel). For example, in one embodiment, the channel width w2 is less than or equal to 50 nanometers. The narrow width of the channel region 34 ensures that Figure 4CIn the thinning process, the ferroelectric film 52 will not be excessively thinned or completely removed. If the channel region 34 is too wide (for example, the channel region 34 is a long channel having a width greater than or equal to 100 nanometers), the ferroelectric film 52 will often be excessively thinned or completely removed due to the loading effect in, for example, the etch-back process. That is, the etch-back process may be greatly accelerated due to the large size of the channel region 34 and thin the ferroelectric film 52 beyond the required thickness. It should be noted that the given example of the width of the channel region 34 is not limited to the foregoing, and in other embodiments, it may be less than or greater than the given example.

[0115] Once the ferroelectric film 52 is thinned to a desired thickness to form the ferroelectric layer 30, a gate electrode 32 is formed in the trench 58. Thus, the following is obtained: Figure 3 The gate structure 16 is shown.

[0116] As above Figures 1 to 3 As discussed, various semiconductor processing techniques may be used to form the gate electrode 32. For example, the gate electrode 32 may be formed by chemical vapor deposition, high density plasma chemical vapor deposition, spin coating, sputtering, or other suitable methods.

[0117] As previously discussed, if the channel region 34 has a large width, the ferroelectric film 52 will often be over-thinned or completely removed during, for example, an etch-back process. Fortunately, when the channel region 34 has a large width, in order to make the transistor 12 have a negative capacitance, the ferroelectric layer 30 is not necessary. Instead, the ferroelectric layer 30 can be replaced by a high dielectric constant (K) dielectric layer. Thus, the same method as in accordance with FIG. 4A to FIG. 4C The different processes are used to manufacture the gate structure of a transistor having a channel region 34 with a large width. FIG. 5A to FIG. 5F as well as 6A to 6F The invention discloses a method for manufacturing a gate structure of a transistor with a narrow channel width and a gate structure of a transistor with a large channel width according to some embodiments. The gate structure of the transistor with a large channel width includes a high-K dielectric layer instead of a ferroelectric layer.

[0118] FIG. 5A to FIG. 5F FIG. 4 is an enlarged cross-sectional view illustrating a method for manufacturing a gate structure 60 of a transistor having a first channel width w3 according to some embodiments. 6A to 6F FIG. 1 is an enlarged cross-sectional view illustrating a method for manufacturing a gate structure 62 of a transistor having a second channel width w4 according to some embodiments. It should be noted that: FIG. 5A to FIG. 5F as well as 6A to 6F Display and Figure 3 The same cross-sectional view is shown. It should also be noted that FIG. 5A to FIG. 5F and 6A to 6F The cross-sectional view shown is enlarged and the substrate 10 is not shown.

[0119] In one embodiment, the first channel width w3 is smaller than the second channel width w4. For example, in one embodiment, the first channel width w3 is less than or equal to 50 nanometers, and the second channel width w4 is greater than or equal to 100 nanometers. It should be noted that the first channel width w3 and the second channel width w4 are not limited to the above, and in other embodiments, they can be smaller or larger than the given example.

[0120] In one embodiment, FIG. 5A to FIG. 5F and 6A to 6F The steps shown are used to manufacture two different transistors on the same substrate. For example, in one embodiment, FIG. 5A to FIG. 5F The steps shown are used to manufacture a first transistor on a substrate 10, and 6A to 6F The steps shown are used to manufacture the second transistor on the substrate 10. In this embodiment, FIG. 5A to FIG. 5F The steps shown are similar to 6A to 6F The steps shown are performed simultaneously. In addition, as will be discussed in more detail below, FIG. 5A to FIG. 5F Some of the manufacturing steps performed in 6A to 6F Therefore, refer to FIG. 5A to FIG. 5F and 6A to 6F It is helpful. It should be noted that FIG. 5A to FIG. 5F and 6A to 6F The steps shown can also be used to manufacture two different transistors on two different substrates, and FIG. 5A to FIG. 5F The steps shown can be used with 6A to 6F The steps shown are performed separately.

[0121] exist Figure 5A and Fig. 6A In, similar to Figure 4A , forming fins 14, source regions 18, drain regions 20, channel regions 34, spacers 19, contact etching stop layers 36, interlayer dielectrics 21, and gate dielectric layers 28 on substrate 10. As described above, substrate 10 is not shown in FIG. FIG. 5A to FIG. 5F as well as 6A to 6F The fin 14, the source region 18, the drain region 20, the channel region 34, the spacer 19, the contact etch stop layer 36, the interlayer dielectric 21, and the gate dielectric layer 28 have been previously fabricated according to Figure 4A It has been discussed before and will not be discussed again here.

[0122] After forming the fin 14 , the source region 18 , the drain region 20 , the channel region 34 , the spacer 19 , the contact etch stop layer 36 , the interlayer dielectric 21 , and the gate dielectric layer 28 , a high-K dielectric layer 64 is formed on the gate dielectric layer 28 .

[0123] The high-K dielectric layer 64 may be made of a variety of different dielectric materials with a high dielectric constant, such as hafnium dioxide, zirconium dioxide, hafnium silicon oxide (HfSiO), hafnium oxysilicide nitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), and / or hafnium zirconium oxide (HfZrO), combinations thereof, and / or other suitable materials.

[0124] The high-K dielectric layer 64 may be formed by various semiconductor processing techniques, such as chemical vapor deposition, high-density plasma chemical vapor deposition, spin coating, sputtering, atomic layer deposition or other suitable methods.

[0125] exist Figure 5B In the embodiment, the high-K dielectric layer 64 is removed to expose the gate dielectric layer 28. In one embodiment, the high-K dielectric layer 64 is completely removed.

[0126] The high-K dielectric layer 64 may be removed by various semiconductor processing techniques. For example, the high-K dielectric layer 64 may be removed by photolithography, masking, and etching techniques.

[0127] exist Figure 6B In FIG. 6 , the high-K dielectric layer 64 is not removed. The gate structure 62 is Figure 6B Still remains the same.

[0128] exist Figure 5C In, continue Figure 5B The high-K dielectric layer 64 is removed to form a ferroelectric film 52 on the gate dielectric layer 28. In addition, a protective layer 56 is formed on the ferroelectric film 52. The ferroelectric film 52 and the protective layer 56 are previously manufactured according to Figure 4A In one embodiment, when Figure 5C When the ferroelectric film 52 is formed on the gate dielectric layer 28, the ferroelectric film 52 is in an amorphous state.

[0129] exist Figure 6C In, due to Figure 6B The high-K dielectric layer 64 is not removed, and the ferroelectric film 52 is formed on the high-K dielectric layer 64. Then, a protective layer 56 is formed on the ferroelectric film 52. The ferroelectric film 52 and the protective layer 56 are previously manufactured according to Figure 4A In one embodiment, when Figure 6C When the ferroelectric film 52 is formed on the high-K dielectric layer 64, the ferroelectric film 52 is in an amorphous state.

[0130] As previously discussed, in one embodiment, FIG. 5A to FIG. 5F The steps shown are similar to 6A to 6F The steps shown are performed simultaneously. In this embodiment, Figure 5C The ferroelectric film 52 is formed with Figure 6CThe formation of the ferroelectric film 52 can be performed in a single step. For example, a single deposition process can be used to form Figure 5C The ferroelectric film 52 in the formation Figure 6C The ferroelectric film 52 in. Figure 5C The formation of the protective layer 56 in Figure 6C The formation of the protective layer 56 in can also be similarly performed in a single step.

[0131] exist Figure 5D and Fig.6D In the process, an annealing process is performed to change the phase of the ferroelectric film 52 from an amorphous state to a crystalline state, so that the ferroelectric film 52 has ferroelectric properties. Figure 5D and Fig.6D The ferroelectric film 52 has ferroelectric properties. Figure 4B It has been discussed before and will not be discussed again here.

[0132] As previously discussed, in one embodiment, FIG. 5A to FIG. 5F The steps shown are similar to 6A to 6F The steps shown are performed simultaneously. In this embodiment, Figure 5D The annealing process and Fig.6D The annealing process may be a single annealing process. For example, Figure 5D The ferroelectric film 52 of the gate structure 60 is Fig.6D The ferroelectric film 52 of the gate structure 62 may be heated at the same time.

[0133] exist Figure 5E In the embodiment, the protective layer 56 and a portion of the ferroelectric film 52 are removed. The portion of the ferroelectric film 52 is removed to thin the ferroelectric film 52 to a desired thickness to form the ferroelectric layer 30. For example, the thickness t2 of the ferroelectric film 52 is reduced to the thickness t1 of the ferroelectric layer 30. The removal of the protective layer 56 and the thinning of the ferroelectric film 52 have been previously described in accordance with Figure 4C What has been discussed will no longer be discussed.

[0134] exist Fig. 6EIn one embodiment, the protective layer 56 and the ferroelectric film 52 are removed to expose the high-K dielectric layer 64. In one embodiment, the protective layer 56 and the ferroelectric film 52 are completely removed. The protective layer 56 and the ferroelectric film 52 can be removed using a variety of semiconductor processing techniques. For example, the protective layer 56 and the ferroelectric film 52 can be removed using photolithography, masking, and etching techniques. In one embodiment, the upper surfaces of the interlayer dielectric 21, the gate dielectric layer 28, and the high-K dielectric layer 64 are masked; and the ferroelectric film 52 and the protective layer 56 are exposed. Next, an etching process is performed to remove the protective layer 56 and the ferroelectric film 52 and expose the high-K dielectric layer 64. In one embodiment, a single etching process is used to remove the protective layer 56 and the ferroelectric film 52. In another embodiment, the protective layer 56 is first removed using a first etching process, and then the ferroelectric film 52 is removed using a second etching process.

[0135] As previously discussed, in one embodiment, FIG. 5A to FIG. 5F The steps shown are similar to 6A to 6F The steps shown are performed simultaneously. In this embodiment, Figure 5E The protective layer 56 and part of the ferroelectric film 52 are removed and Fig. 6E The removal of the protective layer 56 and the ferroelectric film 52 can be performed in a single step. For example, a single etching process can be used to remove Figure 5E The protective layer 56 and part of the ferroelectric film 52 are removed Fig. 6E The protective layer 56 and the ferroelectric film 52 are formed.

[0136] exist Fig. 5F In the embodiment, once the ferroelectric film 52 is thinned to a desired thickness to form the ferroelectric layer 30, a gate electrode 32 is formed on the ferroelectric layer 30. Fig. 5F The gate structure 60 shown is substantially similar to Figure 3 The gate structure 16 is shown. The fabrication of the gate electrode 32 has been discussed above and will not be discussed again here.

[0137] exist Fig. 6F Once the protection layer 56 and the ferroelectric film 52 are removed, the gate electrode 32 is formed on the high-K dielectric layer 64. The gate structure 62 is similar to the gate structure 60 except that the ferroelectric layer 30 in the gate structure 60 is replaced by the high-K dielectric layer 64.

[0138] As previously discussed, in one embodiment, FIG. 5A to FIG. 5F The steps shown are similar to 6A to 6F The steps shown are performed simultaneously. In this embodiment, Fig. 5F The formation of the middle gate electrode 32 and Fig. 6F The formation of the middle gate electrode 32 can be performed in a single step. For example, a single deposition process can be used to form Fig. 5F The gate electrode 32 and Fig. 6F The gate electrode 32 is formed on the substrate.

[0139] Several of the described embodiments provide transistors with negative capacitance and methods for making the same. In one or more embodiments, the transistor includes a ferroelectric layer formed by forming a thick ferroelectric film, annealing the ferroelectric film to have a desired phase, and thinning the ferroelectric film to a desired thickness of the ferroelectric layer. This process ensures that the ferroelectric layer will have ferroelectric properties regardless of the thickness of the ferroelectric layer. In one or more embodiments, the ferroelectric layer is replaced with a high-K dielectric layer. The high-K dielectric layer ensures that the transistor has negative capacitance even when the transistor has a large channel width. Therefore, the size of the transistor can be enlarged or reduced as needed while still having negative capacitance. Therefore, the transistors and methods disclosed herein are suitable for applications requiring transistors of various sizes.

[0140] According to one embodiment disclosed herein, a transistor includes a substrate; a dielectric layer located on the substrate; a fin extending from the substrate, through the dielectric layer and beyond a surface of the dielectric layer; first and second spacers located on the fin; a gate dielectric layer located on the surface of the dielectric layer and on at least three sides of the fin; a ferroelectric layer located on the gate dielectric layer and on at least three sides of the fin; and a gate electrode located on the ferroelectric layer. The ferroelectric layer is separated from the fin and the first and second spacers by the gate dielectric layer.

[0141] In one embodiment, the ferroelectric layer has a thickness less than or equal to 5 nanometers. In one embodiment, the transistor further includes source and drain regions, which are located in the fin, and the ferroelectric layer is located between the source and drain regions. In one embodiment, the transistor further includes a contact etch stop layer, which is located on the fin, the contact etch stop layer extends along a first direction, and the first and second spacers extend along a second direction transverse to the first direction. In one embodiment, the fin is located between the substrate and the first and second spacers. In one embodiment, a portion of the gate dielectric layer, a portion of the ferroelectric layer, and a portion of the gate electrode are located between the first and second spacers. In one embodiment, the first and second spacers are separated by a distance less than or equal to 50 nanometers.

[0142] According to one embodiment disclosed herein, a method includes forming a dielectric layer on a substrate; forming a fin extending from the substrate, through the dielectric layer and beyond a surface of the dielectric layer; forming first and second spacers on the fin; forming a gate dielectric layer on the surface of the dielectric layer and on at least three sides of the fin; forming a ferroelectric layer on the gate dielectric layer and on at least three sides of the fin; and forming a gate electrode on the ferroelectric layer. The ferroelectric layer is separated from the fin and the first and second spacers by the gate dielectric layer.

[0143] In one embodiment, a manufacturing method includes forming a fin from a substrate; forming a dielectric layer on the substrate, the fin extending through the dielectric layer and beyond the surface of the dielectric layer; forming first and second spacers on the fin; forming a gate dielectric layer on at least three sides of the fin; forming a ferroelectric layer on the gate dielectric layer and on at least three sides of the fin, the ferroelectric layer being separated from the fin and the first and second spacers by the gate dielectric layer, the formation of the ferroelectric layer including forming a ferroelectric film having a first thickness; annealing the ferroelectric film; and reducing the thickness of the ferroelectric film to a second thickness less than the first thickness; and forming a gate electrode on the ferroelectric layer.

[0144] In one embodiment, the first thickness is greater than 5 nanometers, and the second thickness is less than or equal to 5 nanometers. In one embodiment, the manufacturing method further includes forming a source and a drain region in the fin, the source and the drain region are aligned with the first and second spacers, respectively. In one embodiment, a portion of the gate dielectric layer, a portion of the ferroelectric layer, and a portion of the gate electrode are located between the first and second spacers. In one embodiment, the ferroelectric layer has a thickness less than or equal to 5 nanometers.

[0145] According to one embodiment disclosed herein, a method includes forming a dielectric layer on a substrate; forming a first fin, the first fin extending from the substrate, through the dielectric layer and beyond the surface of the dielectric layer; forming a second fin, the second fin extending from the substrate, through the dielectric layer and beyond the surface of the dielectric layer; forming first and second spacers on the first fin; forming third and fourth spacers on the second fin; forming a gate dielectric layer on the surface of the dielectric layer, on at least three sides of the first fin, and on at least three sides of the second fin; forming a ferroelectric layer on the gate dielectric layer and on at least three sides of the first fin; and forming a high-K dielectric layer on the gate dielectric layer and on at least three sides of the second fin; and forming a gate electrode on the ferroelectric layer and on the high-K dielectric layer. The first fin includes a channel region having a first width. The second fin includes a channel region having a second width. The ferroelectric layer is separated from the first fin and the first and second spacers by the gate dielectric layer. The ferroelectric layer is separated from the second fin and the third and fourth spacers by the gate dielectric layer.

[0146] In one embodiment, a manufacturing method includes forming a first fin, which extends from a substrate and includes a channel region having a first width; forming a second fin, which extends from the substrate and includes a channel region having a second width; forming first and second spacers on the first fin; forming third and fourth spacers on the second fin; forming a gate dielectric layer on at least three sides of the first fin and on at least three sides of the second fin; forming a ferroelectric layer on the gate dielectric layer and on at least three sides of the first fin, the ferroelectric layer being separated from the first fin and the first and second spacers by the gate dielectric layer; and forming a high-K dielectric constant dielectric layer on the gate dielectric layer and on at least three sides of the second fin, the ferroelectric layer being separated from the second fin and the third and fourth spacers by the gate dielectric layer.

[0147] In one embodiment, the second width is greater than the first width. In one embodiment, the first width is less than or equal to 50 nanometers, and the second width is greater than or equal to 100 nanometers. In one embodiment, forming the ferroelectric layer includes forming a ferroelectric film having a first thickness; annealing the ferroelectric film; and reducing the thickness of the ferroelectric film to a second thickness less than the first thickness. In one embodiment, the manufacturing method further includes forming a ferroelectric layer on at least three sides of the second fin, the ferroelectric layer being separated from the second fin and the third and fourth spacers by a gate dielectric layer. In one embodiment, the manufacturing method further includes removing a portion of the ferroelectric layer located on the second fin. In one embodiment, the manufacturing method further includes forming a high-k dielectric layer on at least three sides of the first fin, the high-k dielectric layer being separated from the first fin and the first and second spacers by a gate dielectric layer; and removing a plurality of portions of the high-k dielectric layer located on the first fin prior to the formation of the ferroelectric layer. In one embodiment, the ferroelectric layer has a thickness less than or equal to 5 nanometers. In one embodiment, the manufacturing method further includes forming an interlayer dielectric on the first and second spacers and the third and fourth spacers.

[0148] The multiple embodiments described above may be combined to provide further embodiments. These and other changes may be made to the embodiments in accordance with the above detailed description. In general, in the following claims, the words used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, these claims are not limited to the embodiments disclosed herein.

[0149] The features of some embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a benchmark to design or improve other processes and structures to achieve the same purpose and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such equal construction does not depart from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and variations here without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A transistor, characterized in that: The transistor contains: a substrate; a dielectric layer located on the substrate; a first fin extending from the substrate, through the dielectric layer and beyond a surface of the dielectric layer; a second fin extending from the substrate, through the dielectric layer and beyond a surface of the dielectric layer; A first spacer and a second spacer are located on the first fin; A third spacer and a fourth spacer are located on the second fin; a first gate dielectric layer disposed on the surface of the dielectric layer and on at least three sides of the first fin; a second gate dielectric layer disposed on the surface of the dielectric layer and on at least three sides of the second fin; a ferroelectric layer located on the first gate dielectric layer and on the at least three sides of the first fin, the ferroelectric layer being separated from the first fin and the first and second spacers by the first gate dielectric layer, the ferroelectric layer having a thickness less than or equal to 5 nanometers; A high-k dielectric layer is located on the second gate dielectric layer and on the at least three sides of the second fin, and the high-k dielectric layer is separated from the second fin and the third and fourth spacers by the second gate dielectric layer; a first gate electrode disposed on the ferroelectric layer; and A second gate electrode is located on the high-k dielectric layer.

2. The transistor according to claim 1, wherein The transistor also contains: A source region and a drain region are located in the first fin, and the ferroelectric layer is located between the source region and the drain region.

3. The transistor according to claim 1, wherein The transistor also contains: A contact etching stop layer is located on the first fin. The contact etching stop layer extends along a first direction. The first spacer and the second spacer extend along a second direction transverse to the first direction.

4. The transistor according to claim 1, wherein The first fin is located between the substrate and the first spacer and the second spacer.

5. The transistor according to claim 1, wherein The first gate dielectric layer, a portion of the ferroelectric layer, and the first gate electrode are located between the first spacer and the second spacer.

6. The transistor according to claim 1, wherein The first spacer and the second spacer are spaced apart from each other by a distance which is less than or equal to 50 nanometers.

7. A method for manufacturing a transistor, characterized in that: The method includes: forming a fin from a substrate; forming a dielectric layer on the substrate, wherein the fin extends through the dielectric layer and exceeds a surface of the dielectric layer; forming a first spacer and a second spacer on the fin; forming a gate dielectric layer on at least three sides of the fin; A ferroelectric layer is formed on the gate dielectric layer and on the at least three sides of the fin, wherein the ferroelectric layer is separated from the fin and the first spacer and the second spacer by the gate dielectric layer, wherein forming the ferroelectric layer comprises: forming a ferroelectric film having a first thickness; annealing the ferroelectric film; and reducing the thickness of the ferroelectric film to a second thickness that is less than the first thickness; as well as A gate electrode is formed on the ferroelectric layer.

8. The method according to claim 7, characterized in that The first thickness is greater than 5 nanometers, and the second thickness is less than or equal to 5 nanometers.

9. The method according to claim 7, characterized in that The method also includes: A source region and a drain region are formed in the fin, and the source region and the drain region are aligned with the first spacer and the second spacer respectively.

10. The method according to claim 7, characterized in that A portion of the gate dielectric layer, a portion of the ferroelectric layer, and a portion of the gate electrode are located between the first spacer and the second spacer.

11. The method according to claim 7, characterized in that The ferroelectric layer has a thickness less than or equal to 5 nanometers.

12. A method for manufacturing a transistor, characterized in that: The method includes: Forming a first fin, the first fin extending from a substrate, the first fin comprising a channel region having a first width; forming a second fin extending from the substrate, the second fin comprising a channel region having a second width; forming a first spacer and a second spacer on the first fin; forming a third spacer and a fourth spacer on the second fin; forming a gate dielectric layer on at least three sides of the first fin and at least three sides of the second fin; forming a ferroelectric layer on the gate dielectric layer and the at least three sides of the first fin, wherein the ferroelectric layer is separated from the first fin and the first and second spacers by the gate dielectric layer; as well as A high-k dielectric layer is formed on the gate dielectric layer and the at least three sides of the second fin. The ferroelectric layer is separated from the second fin and the third and fourth spacers by the gate dielectric layer.

13. The method according to claim 12, characterized in that The second width is greater than the first width.

14. The method according to claim 13, characterized in that The first width is less than or equal to 50 nanometers, and the second width is greater than or equal to 100 nanometers.

15. The method according to claim 12, characterized in that Forming the ferroelectric layer comprises: forming a ferroelectric film having a first thickness; annealing the ferroelectric film; and The thickness of the ferroelectric film is reduced to a second thickness that is smaller than the first thickness.

16. The method according to claim 12, characterized in that The method also includes: The ferroelectric layer is formed on the at least three sides of the second fin, and the ferroelectric layer is separated from the second fin and the third and fourth spacers by the gate dielectric layer.

17. The method according to claim 16, characterized in that The method also includes: Portions of the ferroelectric layer located on the second fin are removed.

18. The method according to claim 12, characterized in that The method also includes: Forming the high-k dielectric layer on the at least three sides of the first fin, the high-k dielectric layer being separated from the first fin and the first and second spacers by the gate dielectric layer; as well as Before forming the ferroelectric layer, a plurality of portions of the high-k dielectric layer located on the first fin are removed.

19. The method of claim 12, wherein: The ferroelectric layer has a thickness less than or equal to 5 nanometers.

20. The method of claim 12, wherein: The method also includes: An inter-layer dielectric is formed on the first spacer, the second spacer, the third spacer, and the fourth spacer.

21. A method for manufacturing a transistor, characterized in that: The method includes: forming a dielectric layer on a substrate; forming a fin extending from the substrate, through the dielectric layer and beyond a surface of the dielectric layer; forming a first spacer and a second spacer on the fin; forming a gate dielectric layer on the surface of the dielectric layer and on at least three sides of the fin; A ferroelectric layer is formed on the gate dielectric layer and on the at least three sides of the fin, the ferroelectric layer is separated from the fin and the first spacer and the second spacer by the gate dielectric layer, the ferroelectric layer has a thickness less than or equal to 5 nanometers, wherein forming the ferroelectric layer comprises: forming a ferroelectric film having a first thickness; annealing the ferroelectric film; and reducing the thickness of the ferroelectric film to a second thickness that is smaller than the first thickness; as well as A gate electrode is formed on the ferroelectric layer.

22. The method according to claim 21, characterized in that The method also includes: A source region and a drain region are formed in the fin, and the ferroelectric layer is located between the source region and the drain region.

23. The method of claim 21, wherein: The method also includes: A contact etching stop layer is formed on the fin, the contact etching stop layer extends along a first direction, and the first spacer and the second spacer extend along a second direction transverse to the first direction.

24. The method of claim 21, wherein: The fin is located between the substrate and the first spacer and the second spacer.

25. The method of claim 21, wherein: A portion of the gate dielectric layer, a portion of the ferroelectric layer, and a portion of the gate electrode are located between the first spacer and the second spacer.

26. The method of claim 21, wherein: The first spacer and the second spacer are spaced apart from each other by a distance which is less than or equal to 50 nanometers.

27. A transistor, characterized in that: The transistor contains: a substrate; A first fin extending from the substrate, the first fin comprising a source region, a drain region, and a channel region; A second fin extending from the substrate, the second fin comprising a source region, a drain region, and a channel region; A first spacer and a second spacer are located on the first fin; A third spacer and a fourth spacer are located on the second fin; a first gate dielectric layer disposed on at least three sides of the first fin; a second gate dielectric layer disposed on at least three sides of the second fin; A ferroelectric layer is located on the first gate dielectric layer and the second gate dielectric layer, the ferroelectric layer is separated from the first fin and the first and second spacers by the first gate dielectric layer, and the ferroelectric layer is separated from the second fin and the third and fourth spacers by the second gate dielectric layer; A high-k dielectric layer is located on the second gate dielectric layer and on the at least three sides of the second fin, and the high-k dielectric layer is separated from the second fin and the third and fourth spacers by the second gate dielectric layer; a first gate electrode disposed on the ferroelectric layer; and A second gate electrode is located on the high-k dielectric layer.

28. The transistor according to claim 27, characterized in that The transistor also contains: An interlayer dielectric is located on the first spacer, the second spacer, the third spacer, and the fourth spacer.

29. The transistor according to claim 27, characterized in that The first gate electrode is located on the at least three sides of the first fin.

30. The transistor according to claim 29, characterized in that The first gate dielectric layer, a first portion of the ferroelectric layer, and the first gate electrode are located between the first spacer and the second spacer, and The second gate dielectric layer, a second portion of the ferroelectric layer, and the second gate electrode are located between the third spacer and the fourth spacer.

31. The transistor according to claim 27, characterized in that The ferroelectric layer has a thickness less than or equal to 5 nanometers.

32. The transistor according to claim 27, characterized in that The ferroelectric layer is located between the source region and the drain region of the first fin and between the source region and the drain region of the second fin.

33. The transistor according to claim 27, characterized in that The first fin is located between the substrate and the first spacer and the second spacer, and the second fin is located between the substrate and the third spacer and the fourth spacer.

34. The transistor according to claim 27, characterized in that The first spacer and the second spacer are spaced apart from each other by a distance that is less than or equal to 50 nanometers, and the third spacer and the fourth spacer are spaced apart from each other by a distance that is less than or equal to 50 nanometers.

35. A transistor, characterized in that: The transistor contains: a substrate; a dielectric layer located on the substrate; a first fin, located on the substrate, the first fin extending through the dielectric layer; a second fin, located on the substrate, the second fin extending through the dielectric layer; A first spacer and a second spacer are located on the first fin; A third spacer and a fourth spacer are located on the second fin; a first gate dielectric layer, located on the dielectric layer and the first fin; a second gate dielectric layer, located on the dielectric layer and the second fin; a high-k dielectric layer located on the second gate dielectric layer and on at least three sides of the second fin; A ferroelectric layer is located on the first gate dielectric layer, and the ferroelectric layer is separated from the first fin and the first spacer and the second spacer by the first gate dielectric layer; a first gate electrode disposed on the ferroelectric layer; and A second gate electrode is located on the high-k dielectric layer.

36. The transistor according to claim 35, characterized in that The ferroelectric layer has a thickness less than or equal to 5 nanometers.

37. The transistor according to claim 35, characterized in that The transistor also contains: A source region and a drain region are located in the first fin, and the ferroelectric layer is located between the source region and the drain region.

38. The transistor according to claim 35, characterized in that The transistor also contains: A contact etching stop layer is located on the first fin. The contact etching stop layer extends along a first direction. The first spacer and the second spacer extend along a second direction transverse to the first direction.

39. The transistor according to claim 35, characterized in that The first fin is located between the substrate and the first spacer and the second spacer.

40. The transistor according to claim 35, characterized in that The first gate dielectric layer, a portion of the ferroelectric layer, and the first gate electrode are located between the first spacer and the second spacer.

41. A method for manufacturing a transistor, characterized in that: The method includes: forming a fin on a substrate; forming a dielectric layer on the substrate, the fin extending through the dielectric layer and beyond the dielectric layer; forming a first spacer and a second spacer on the fin; forming a gate dielectric layer on the dielectric layer and on at least three sides of the fin; A ferroelectric layer is formed on the gate dielectric layer, wherein the ferroelectric layer is separated from the fin and the first spacer and the second spacer by the gate dielectric layer, wherein forming the ferroelectric layer comprises: forming a ferroelectric film having a first thickness; annealing the ferroelectric film; and reducing the thickness of the ferroelectric film to a second thickness that is smaller than the first thickness; as well as A gate electrode is formed on the ferroelectric layer.

42. The method of claim 41, wherein: The first thickness is greater than 5 nanometers, and the second thickness is less than or equal to 5 nanometers.

43. The method of claim 41, wherein: The method also includes: A source region and a drain region are formed in the fin, and the source region and the drain region are aligned with the first spacer and the second spacer respectively.

44. The method of claim 41, wherein: A portion of the gate dielectric layer, a portion of the ferroelectric layer, and a portion of the gate electrode are located between the first spacer and the second spacer.

45. The method of claim 41, wherein: The ferroelectric layer has a thickness less than or equal to 5 nanometers.

46. ​​A method for manufacturing a transistor, characterized in that: The method includes: Forming a first fin on a substrate, the first fin comprising a channel region having a first width; forming a second fin on the substrate, the second fin comprising a channel region having a second width; forming a first spacer and a second spacer on the first fin; forming a third spacer and a fourth spacer on the second fin; forming a first dielectric layer on at least three sides of the first fin and at least three sides of the second fin; forming a ferroelectric layer on the first dielectric layer, wherein the ferroelectric layer is separated from the first fin and the first and second spacers by the first dielectric layer; and A second dielectric layer is formed on the first dielectric layer. The ferroelectric layer is separated from the second fin, the third spacer and the fourth spacer by the second dielectric layer.

47. The method of claim 46, wherein: The second width is greater than the first width.

48. The method of claim 47, wherein: The first width is less than or equal to 50 nanometers, and the second width is greater than or equal to 100 nanometers.

49. The method of claim 46, wherein: Forming the ferroelectric layer comprises: forming a ferroelectric film having a first thickness; annealing the ferroelectric film; and The thickness of the ferroelectric film is reduced to a second thickness that is smaller than the first thickness.

50. The method of claim 46, wherein: Forming the ferroelectric layer includes forming the ferroelectric layer on the second fin so that the ferroelectric layer is separated from the second fin and the third and fourth spacers by the second dielectric layer, and removing a plurality of portions of the ferroelectric layer on the second fin.

51. The method of claim 46, wherein: Forming the second dielectric layer includes forming the second dielectric layer on the first fin so that the second dielectric layer is separated from the first fin and the first and second spacers by the first dielectric layer, and removing a plurality of portions of the second dielectric layer on the first fin before forming the ferroelectric layer.

52. The method of claim 46, wherein: The ferroelectric layer has a thickness less than or equal to 5 nanometers.

53. The method of claim 46, wherein: The method also includes: An inter-layer dielectric is formed on the first spacer, the second spacer, the third spacer, and the fourth spacer.

54. The method of claim 46, wherein: The first dielectric layer is a gate dielectric layer, and the second dielectric layer is a high dielectric constant dielectric layer.

55. A method for manufacturing a transistor, characterized in that: The method includes: forming a fin on a substrate; forming a first spacer and a second spacer on the fin; forming a gate dielectric layer on the dielectric layer, on at least three sides of the fin, and on the first spacer and the second spacer; A ferroelectric layer is formed on the gate dielectric layer, wherein the ferroelectric layer is separated from the fin and the first spacer and the second spacer by the gate dielectric layer, wherein forming the ferroelectric layer comprises: forming a ferroelectric film having a first thickness; annealing the ferroelectric film; and reducing the thickness of the ferroelectric film to a second thickness that is smaller than the first thickness; as well as A gate electrode is formed on the ferroelectric layer.

56. The method of claim 55, wherein: The ferroelectric layer has a thickness less than or equal to 5 nanometers.

57. The method of claim 55, wherein: The method also includes: A source region and a drain region are formed in the fin, and the ferroelectric layer is located between the source region and the drain region.

58. The method of claim 55, wherein: The fin is located between the substrate and the first spacer and the second spacer.

59. The method of claim 55, wherein: A portion of the gate dielectric layer, a portion of the ferroelectric layer, and a portion of the gate electrode are located between the first spacer and the second spacer.

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