Groove and method for forming same, method for preparing capacitor and capacitor

Abstract

The present invention provides a groove and a method for forming the groove, a method for preparing a capacitor and a capacitor. The method for preparing the capacitor includes: providing an initial structure, the initial structure including a substrate layer, an insulating layer and a storage node contact plug located on the substrate layer, and a first supporting structure layer; etching the first supporting structure layer to form a first hole; forming a sacrificial layer in the first hole; forming a second supporting structure layer on the surface of the first supporting structure layer and the sacrificial layer; etching the second supporting structure layer to form a second hole, the sacrificial layer being exposed to the second hole; removing the sacrificial layer; and sequentially depositing a lower electrode layer, a dielectric layer, and an upper electrode layer to form the capacitor. The method of one embodiment of the present invention can reduce the etching difficulty of a high aspect ratio structure by setting and removing the sacrificial layer, and solve the problem of high resistance impedance or even circuit breakage caused by the reduction of the lower contact point area due to insufficient etching.

Description

Technical Field

[0001] The invention relates to a capacitor, in particular to a method for manufacturing a capacitor capable of reducing the etching difficulty of a structure with a high aspect ratio. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory widely used in multi-computer systems. As one of the necessary structures in DRAM, capacitors have functions such as voltage adjustment and filtering in the circuit and are widely used in integrated circuits. With the development of the manufacturing process, the aspect ratio of the columnar capacitor structure is getting higher and higher. When etching to form capacitor holes, the capacitor holes will appear wide at the top and narrow at the bottom, that is, the area of ​​the lower contact point exposed at the bottom of the columnar capacitor structure becomes smaller; and the smaller area of ​​the lower contact point will cause the columnar capacitor and the lower contact point to produce high resistance impedance (High Resistance), and the smaller area of ​​the lower contact point may also cause insufficient etching (under etch), that is, the columnar capacitor structure and the lower contact point are disconnected. Summary of the invention

[0003] A main object of the present invention is to provide a method for forming a groove, comprising:

[0004] Providing a substrate, on which a first dielectric layer is disposed;

[0005] Etching the first dielectric layer to form a first hole;

[0006] forming a sacrificial layer in the first hole;

[0007] forming a second dielectric layer on the first dielectric layer and the sacrificial layer;

[0008] etching the second dielectric layer to form a second hole, wherein the sacrificial layer is exposed in the second hole; and

[0009] The sacrificial layer is removed, and the first hole and the second hole are connected to form the groove.

[0010] According to an embodiment of the present invention, the first dielectric layer and the second dielectric layer include one or more of a silicon nitride film and a silicon oxide film.

[0011] An embodiment of the present invention provides a groove, which is manufactured by the above method, and the aspect ratio of the groove is greater than 8:1.

[0012] An embodiment of the present invention provides a method for manufacturing a capacitor, comprising:

[0013] Providing an initial structure, the initial structure comprising a substrate layer, an insulating layer and a storage node contact plug located on the substrate layer, and a first supporting structure layer disposed on the insulating layer and the storage node contact plug;

[0014] Etching the first supporting structure layer to form a first hole, wherein the storage node contact plug is exposed in the first hole;

[0015] forming a sacrificial layer in the first hole;

[0016] forming a second supporting structure layer on the surfaces of the first supporting structure layer and the sacrificial layer;

[0017] Etching the second supporting structure layer to form a second hole, wherein the sacrificial layer is exposed in the second hole;

[0018] removing the sacrificial layer; and

[0019] The capacitor is formed by depositing a lower electrode layer, a dielectric layer and an upper electrode layer in sequence.

[0020] According to one embodiment of the present invention, the dry etching gas includes O2, C4F6, CHF3, CH2F2, the etching pressure is 5-30mtorr, the operating frequency and power are 2MHZ, 4000-8000W, 60MHZ, 100-2000W, and the etching time is 10-40 seconds.

[0021] According to an embodiment of the present invention, the sacrificial layer is made of amorphous solid material.

[0022] According to an embodiment of the present invention, the sacrificial layer is removed by a wet etching process.

[0023] According to one embodiment of the present invention, the solution used for the wet etching is a mixed solution of hydrofluoric acid and ammonia water, or a mixed solution of hydrofluoric acid and tetramethylammonium hydroxide.

[0024] According to one embodiment of the present invention, the first supporting structure layer includes a supporting layer and a dielectric layer; the second supporting structure layer includes a plurality of supporting layers and a plurality of dielectric layers, and each of the dielectric layers is sandwiched between two of the supporting layers.

[0025] An embodiment of the present invention provides a capacitor, which is manufactured by any of the above methods, wherein the first hole and the second hole form a capacitor hole, and the depth-to-width ratio of the capacitor hole is greater than 8:1.

[0026] An embodiment of the present invention provides a semiconductor storage device including the above capacitor.

[0027] An embodiment of the present invention provides a semiconductor structure, comprising:

[0028] substrate;

[0029] An insulating layer, disposed on the substrate;

[0030] A storage node contact plug is disposed in the insulating layer and connected to the substrate;

[0031] A first supporting structure layer is disposed on the insulating layer, a first hole is opened in the first supporting structure layer, and the storage node contact plug is exposed in the first hole;

[0032] a sacrificial layer disposed in the first hole and covering the storage node contact plug; and

[0033] The second supporting structure layer is disposed on the first supporting structure layer. A second hole is opened in the second supporting structure layer, and the sacrificial layer is exposed to the second hole.

[0034] The method of one embodiment of the present invention can reduce the difficulty of etching a high aspect ratio structure by setting and removing a sacrificial layer, and solve the problem of high resistance impedance or even circuit breakage caused by a smaller lower contact point area due to insufficient etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Various objects, features and advantages of the present invention will become more apparent by considering the following detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present invention and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0036] Figures 1 to 10 FIG. 1 is a schematic diagram of a structure of a capacitor during a method for manufacturing a capacitor according to an embodiment of the present invention.

[0037] The reference numerals are described as follows:

[0038] Substrate 10;

[0039] Storage node contact plug 20;

[0040] Insulation layer 30;

[0041] A first supporting layer 41;

[0042] A second supporting layer 42;

[0043] A third supporting layer 43;

[0044] A top support layer 44;

[0045] A first dielectric layer 51;

[0046] A second dielectric layer 52;

[0047] A third dielectric layer 53;

[0048] Sacrificial layer 60;

[0049] First hole 91;

[0050] A second hole 92;

[0051] Lower electrode layer 100;

[0052] Capacitor dielectric layer 200;

[0053] The upper electrode layer 300 . DETAILED DESCRIPTION

[0054] Typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various changes in different embodiments, all of which do not depart from the scope of the present invention, and the descriptions and illustrations therein are essentially used for illustrative purposes rather than for limiting the present invention. Among them, the terms such as "bottom", "upper surface", "vertical" and the like that indicate orientation involved in the present invention are only for the purpose of explanation in conjunction with the accompanying drawings, and are not intended to limit the technical solution of the present invention.

[0055] An embodiment of the present invention provides a method for manufacturing a capacitor, which can reduce the difficulty of capacitor etching and solve the problem of high resistance impedance or even circuit breakage caused by insufficient etching resulting in a smaller lower contact point area.

[0056] like Figures 1 to 10 As shown, a method for manufacturing a capacitor according to an embodiment of the present invention comprises:

[0057] Providing an initial structure, the initial structure comprising a substrate 10, an insulating layer 30 and a storage node contact plug 20 located on the substrate 10, and a first supporting structure layer covering the insulating layer 30 and the storage node contact plug 20;

[0058] Etching the first supporting structure layer to form a first hole 91 , wherein the storage node contact plug 20 is exposed in the first hole 91 ;

[0059] Filling and forming a sacrificial layer 60 in the first hole 91;

[0060] forming a second supporting structure layer on the surface of the first supporting structure layer and the sacrificial layer 60;

[0061] Etching the second support structure layer to form a second hole 92 , wherein the sacrificial layer 60 is exposed in the second hole 92 ;

[0062] removing the sacrificial layer 60 so that the storage node contact plug 20 is exposed to the second hole 92 ; and

[0063] A lower electrode layer 100 , a capacitor dielectric layer 200 and an upper electrode layer 300 are formed in the second hole 92 .

[0064] In one embodiment, if Figure 1 As shown, the storage node contact plug 20 is a contact layer for connecting the capacitor, which is disposed in the insulating layer 30, and its first surface is in contact with the substrate 10, and its second surface is exposed to the first hole 91, that is, the storage node contact plug 20 is disposed in the height or thickness direction of the insulating layer 30 ( Figure 1 The insulating layer 30 is penetrated in the vertical direction of the insulating layer 30.

[0065] In one embodiment, an insulating layer 30 may be first deposited on the substrate 10, a through hole may be opened in the insulating layer 30, the through hole may be arranged along the height direction of the insulating layer 30, and the substrate 10 may be exposed to the through hole, and a storage node contact plug 20 may be filled in the through hole so that a first surface of the storage node contact plug 20 is in contact with the substrate 10, and a second surface is flush with an upper surface of the insulating layer 30; then a first supporting structure layer may be deposited on the insulating layer 30 and the storage node contact plug 20 to obtain an initial structure for manufacturing a capacitor.

[0066] The first supporting structure layer may include a first supporting layer 41 and a first dielectric layer 51. The first supporting layer 41 is disposed on the surface of the storage node contact plug 20 and the insulating layer 30, and the first dielectric layer 51 is located on the first supporting layer 41. The material of the first supporting layer 41 includes but is not limited to silicon nitride, and its thickness may be 10 to 80 nm, such as 20 nm, 40 nm, 60 nm, 70 nm, etc. The first dielectric layer 51 is an oxide layer, and its material may include one or more of phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) and fluorine-doped silicate glass (FSG), and the thickness of the first dielectric layer 51 may be 300 to 1000 nm, such as 400 nm, 500 nm, 700 nm, 900 nm, etc.

[0067] In one embodiment, if Figure 2 As shown, a photoresist layer 70 is formed on the first dielectric layer 51, and the first supporting structure layer is etched to form a first hole 91. The first hole 91 penetrates the first supporting structure layer along the height or thickness direction of the first supporting structure layer, so that the second surface of the storage node contact plug 20 is exposed to the first hole 91, that is, the second surface of the storage node contact plug 20 is the bottom surface of the first hole 91.

[0068] In one embodiment, C4F6, O2, NF3, etc. are used as etching gases, and the first dielectric layer 51 is etched under the conditions of a pressure of 5-30 mTorr, an operating frequency and power of 2 MHZ, 4000-8000W, 60 MHZ, 500-1500W.

[0069] In one embodiment, C4F8, C4F6, O2, CH2F2, etc. are used as etching gases, and the first supporting layer 41 is etched under the conditions of a pressure of 5 to 50 mTorr, an operating frequency and a power of 2 MHZ, 1000 to 5000 W, 27 MHZ, 50 to 300 W, 60 MHZ, 200 to 1000 W.

[0070] The first hole 91 obtained by etching the first supporting structure layer can be arranged perpendicular to the insulating layer 30 due to its small depth-to-width ratio, so that the lateral size of its bottom opening is basically consistent with the upper opening, so that the second surface of the storage node contact plug 20 can be fully exposed to the first hole 91.

[0071] In one embodiment, if Figure 3 As shown, a sacrificial layer 60 is formed in the first hole 91 by deposition, and the material of the sacrificial layer 60 can be a material that can be removed by wet etching, such as SOC (Spin on carbon), but the material of the sacrificial layer 60 in the present invention is not limited to SOC. The present invention does not specifically limit the deposition method of the sacrificial layer 60, for example, it can be chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0072] In one embodiment, the reaction gas used to deposit the sacrificial layer 60 includes silane (SiH4) and an inert gas, and the inert gas can be one or more of He, Ne, Ar, Kr, Xe, and Rn; wherein the gas flow rate of silane can be 200sccm to 2000sccm, the gas flow rate of the inert gas can be 2000sccm to 20000sccm, and the height of the sacrificial layer can be 500 to 1500nm.

[0073] The sacrificial layer 60 is filled in the first hole 91 , and the upper surface of the first dielectric layer 51 can be kept flush with the upper surface of the sacrificial layer 60 by CMP (chemical mechanical polishing), so that the height of the sacrificial layer 60 is equal to the height of the first supporting structure layer.

[0074] In one embodiment, if Figure 4 As shown, a second supporting structure layer is formed on the first dielectric layer 51 and the sacrificial layer 60, and the second supporting structure layer may include a second supporting layer 42, a second dielectric layer 52, a third supporting layer 43, a third dielectric layer 53 and a top supporting layer 44 stacked in sequence. The second supporting layer 42 covers the first dielectric layer 51 and the sacrificial layer 60, the second dielectric layer 52 is directly located on the second supporting layer 42, the third supporting layer 43 is directly located on the second dielectric layer 52, the third dielectric layer 53 is directly located on the third supporting layer 43, and the top supporting layer 44 is directly located on the third dielectric layer 53. In the second supporting structure layer, the supporting layers and the dielectric layers are alternately arranged, and the dielectric layer is sandwiched between the two supporting layers.

[0075] The second dielectric layer 52 and the third dielectric layer 53 may be oxide layers, for example, but not limited to silicon dioxide layers, and the heights of the second dielectric layer 52 and the third dielectric layer 53 may be 300 to 1000 nm, for example, 400 nm, 500 nm, 700 nm, 900 nm, etc. By adjusting the heights of the second dielectric layer 52 and the third dielectric layer 53, capacitors of corresponding heights may be obtained.

[0076] The second support layer 42 , the third support layer 43 , and the top support layer 44 may be made of nitride, such as silicon nitride, and may have a height of 50 to 200 nm, such as 70 nm, 100 nm, 120 nm, 150 nm, 170 nm, etc.

[0077] In one embodiment, if Figure 5 As shown, the second supporting structure layer is etched to form a second hole 92, which penetrates the second supporting structure layer along the height or thickness direction of the second supporting structure layer, so that the upper surface of the sacrificial layer 60 is exposed to the second hole 92, that is, the upper surface of the sacrificial layer 60 is the bottom surface of the second hole 92.

[0078] In one embodiment, the second supporting structure layer is etched by a dry etching process to form a second hole 92, and the dry etching gas includes O2, C4F6, CHF3, and CH2F2, wherein the gas flow rate of oxygen can be 10sccm~80sccm, the gas flow rate of C4F6 can be 10sccm~80sccm, the gas flow rate of CHF3 can be 10sccm~80sccm, and the gas flow rate of CH2F2 can be 10sccm~80sccm; the etching pressure can be 5~30mt, the operating frequency and power can be 2MHZ, 4000~8000W, 60MHZ, 100~2000W, and the etching time can be 10sec~40sec.

[0079] In another embodiment, C4F8, C4F6, O2, CH2F2, etc. are used as etching gases, and the top support layer 44 is etched under the conditions of pressure of 5-50mTorr, operating frequency and power of 2MHZ, 1000-5000W, 27MHZ, 50-300W, 60MHZ, 200-1000W.

[0080] In another embodiment, C4F6, O2, NF3, etc. are used as etching gases, and the third dielectric layer 53 is etched under the conditions of a pressure of 5-30 mTorr, an operating frequency and power of 2 MHZ, 4000-8000W, 60 MHZ, 500-1500W.

[0081] In another embodiment, C4F6, O2, C4F8, NF3, CH2F2, etc. are used as etching gases to etch the third supporting layer 43.

[0082] In another embodiment, C4F6, O2, NF3, etc. are used as etching gases, and the second dielectric layer 52 is etched under the conditions of a pressure of 5-30 mTorr, an operating frequency and a power of 2 MHZ, 4000-8000W, 60 MHZ, 500-2000W.

[0083] In another embodiment, O2, CHF3, CH2F2, etc. are used as etching gases, and the second supporting layer 42 is etched under the conditions of pressure of 5-50mTorr, operating frequency and power of 2MHZ, 200-1000W, 27MHZ, 50-300W, 60MHZ, 200-1000W, and the sacrificial layer 60 is used as an etching stop layer.

[0084] In one embodiment, the sacrificial layer 60 may be removed by a wet etching process so that the storage node contact plug 20 is exposed to the second hole 92, thereby obtaining Figure 6 The structure shown.

[0085] A manufacturing method according to an embodiment of the present invention opens a first hole 91 in an initial structure to fully expose a storage node contact plug 20, forms a sacrificial layer 60 in the first hole 91, and removes the sacrificial layer 60 after forming a second hole 92, so that the first hole 91 is connected to the second hole 92 to form a capacitor hole, and the storage node contact plug 20 is fully exposed to the capacitor hole, so that in a capacitor structure with a high aspect ratio, the area of ​​the lower contact point exposed at the bottom of the capacitor hole is maintained at a large level.

[0086] In one embodiment, the solution used for wet etching is a mixed solution of diluted hydrofluoric acid (DHF) and ammonia water (NH 4 OH). At room temperature, the concentration of the diluted hydrofluoric acid may be 100 to 500:1.

[0087] In another embodiment, the solution used for wet etching is a mixed solution of diluted hydrofluoric acid and tetramethylammonium hydroxide (TMAH), wherein the concentration of the tetramethylammonium hydroxide may be 1% to 10% at a temperature of 35° C. to 65° C.

[0088] In one embodiment, if Figure 7 As shown, the lower electrode layer 100 can be formed in the second hole 92 by chemical vapor deposition process. The lower electrode layer 100 has a U-shaped structure, with its bottom surface covering the storage node contact plug 20 at the bottom of the second hole 92 and its side surface covering the sidewall of the second hole 92.

[0089] In one embodiment, for example, an opening can be formed in the top support layer 44 to expose the third dielectric layer 53 between the top support layer 44 and the third support layer 43, and the third dielectric layer 53 can be removed by a wet etching process. The second dielectric layer 52 and the first dielectric layer 51 can be removed in the same manner, so that a plurality of cavities are formed between two adjacent support layers and the lower electrode, forming a structure such as Figure 8 The structure shown.

[0090] In one embodiment, the capacitor dielectric layer 200 is formed on the top support layer 44 and the lower electrode layer 100 by chemical vapor deposition process, that is, the capacitor dielectric layer 200 covers the top support layer 44 and the lower electrode layer 100. In addition, the capacitor dielectric layer 200 is formed on the inner wall of the cavity (that is, on the support layer and the lower electrode layer 100 surrounding the cavity), so that the side of the lower electrode layer 100 is sandwiched between the two capacitor dielectric layers 200 or the capacitor dielectric layer 200 and the support layer, forming a Fig. 9 The structure shown.

[0091] In one embodiment, the material of the capacitor dielectric layer 200 includes a high-k material.

[0092] In one embodiment, the upper electrode layer 300 can be formed on the capacitor dielectric layer 200 located on the surface of the capacitor structure by chemical vapor deposition process, the upper electrode layer 300 fills the second hole 92 and covers the capacitor dielectric layer 200 located on the top support layer 44, and at the same time, the upper electrode layer 300 is filled in the cavity surrounded by the capacitor dielectric layer 200, so as to form Fig.10 The capacitor structure shown.

[0093] In the present invention, there is no particular limitation on the materials of the upper electrode layer 300 and the lower electrode layer 100 . For example, both the upper electrode layer 300 and the lower electrode layer 100 can be made of titanium nitride (TiN).

[0094] In the capacitor structure manufactured in one embodiment of the present invention, each support layer (the first support layer 41 , the second support layer 42 , the third support layer 43 and the top support layer 44 ) plays a supporting and blocking role.

[0095] In the capacitor structure manufactured in one embodiment of the present invention, the aspect ratio of the capacitor hole is greater than 8:1, such as 10:1, 20:1, 40:1, etc.

[0096] A manufacturing method according to an embodiment of the present invention increases the capacitor height and improves the etching profile, and the capacitor thus manufactured can be applied to dynamic random access memory.

[0097] In the method of one embodiment of the present invention, the height of the capacitor structure obtained can be adjusted by adjusting the single-layer height of each dielectric layer or the number of dielectric layers in the second supporting structure layer.

[0098] The method of one embodiment of the present invention can reduce the difficulty of etching a high aspect ratio structure by setting and removing a sacrificial layer, solve the problem of high resistance impedance or even short circuit caused by a smaller lower contact point area due to insufficient etching, and produce a vertical capacitor and reduce the tilt effect of the capacitor.

[0099] like Figure 5 As shown, an embodiment of the present invention provides a semiconductor structure that can be used as an intermediate structure for preparing a capacitor structure. The semiconductor structure includes a substrate 10, an insulating layer 30, a storage node contact plug 20, a first supporting structure layer, a sacrificial layer 60 and a second supporting structure layer.

[0100] Among them, the insulating layer 30 is arranged on the substrate 10; the storage node contact plug 20 is embedded in the insulating layer 30 and connected to the substrate 10; the first supporting structure layer is arranged on the insulating layer 30, a first hole is opened in the first supporting structure layer, and the storage node contact plug 20 is exposed to the first hole; the sacrificial layer 60 is arranged in the first hole and covers the storage node contact plug 20; the second supporting structure layer is arranged on the first supporting structure layer, a second hole 92 is opened in the second supporting structure layer, and the sacrificial layer 60 is exposed to the second hole 92.

[0101] In one embodiment, the first supporting structure layer may include a first supporting layer 41 and a first dielectric layer 51 . The first supporting layer 41 is disposed on surfaces of the storage node contact plugs 20 and the insulating layer 30 , and the first dielectric layer 51 is located on the first supporting layer 41 .

[0102] In one embodiment, the second supporting structure layer is disposed on the first dielectric layer 51 and the sacrificial layer 60 , and the second supporting structure layer may include a second supporting layer 42 , a second dielectric layer 52 , a third supporting layer 43 , a third dielectric layer 53 and a top supporting layer 44 stacked in sequence.

[0103] Unless otherwise defined, the terms used in the present invention have the meanings commonly understood by those skilled in the art.

[0104] The embodiments described in the present invention are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Those skilled in the art may make various other substitutions, changes and improvements within the scope of the present invention. Therefore, the present invention is not limited to the above embodiments, but is only limited by the claims.

Claims

1. A method for forming a groove, comprising: Providing a substrate, on which a first dielectric layer is disposed; Etching the first dielectric layer to form a first hole; forming a sacrificial layer in the first hole; forming a second dielectric layer on the first dielectric layer and the sacrificial layer; Etching the second dielectric layer to form a second hole, wherein the sacrificial layer is exposed to the second hole; as well as The sacrificial layer is removed, and the first hole and the second hole are connected to form the groove.

2. A groove made by the method according to claim 1, wherein the aspect ratio of the groove is greater than 8:

1.

3. A method for manufacturing a capacitor, comprising: Providing an initial structure, the initial structure comprising a substrate layer, an insulating layer and a storage node contact plug located on the substrate layer, and a first supporting structure layer disposed on the insulating layer and the storage node contact plug; Etching the first supporting structure layer to form a first hole, wherein the storage node contact plug is exposed in the first hole; forming a sacrificial layer in the first hole; forming a second supporting structure layer on the surfaces of the first supporting structure layer and the sacrificial layer; Etching the second supporting structure layer to form a second hole, wherein the sacrificial layer is exposed in the second hole; removing the sacrificial layer; as well as The capacitor is formed by depositing a lower electrode layer, a dielectric layer, and an upper electrode layer in sequence.

4. The method according to claim 3, wherein: The gases used to etch the first supporting structure layer include O2, C4F6, CHF3, and CH2F2, the etching pressure is 5 to 30 mtorr, the operating frequency and power are 2 MHZ, 4000 to 8000 W, 60 MHZ, 100 to 2000 W, and the etching time is 10 to 40 seconds.

5. The method according to claim 1 or 3, wherein: The sacrificial layer is made of amorphous solid material.

6. The method according to claim 5, wherein: The sacrificial layer is removed by a wet etching process, and the solution used for the wet etching process is a mixed solution of hydrofluoric acid and ammonia water, or a mixed solution of hydrofluoric acid and tetramethylammonium hydroxide.

7. The method according to claim 3, wherein: The first supporting structure layer includes a supporting layer and a dielectric layer; the second supporting structure layer includes a plurality of supporting layers and a plurality of dielectric layers, and each dielectric layer is sandwiched between two supporting layers.

8. A capacitor made by the method according to any one of claims 3 to 7, wherein: The first hole and the second hole form a capacitor hole, and the depth-to-width ratio of the capacitor hole is greater than 8:

1.

9. A semiconductor storage device comprising the capacitor according to claim 8.

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