Reduce band-to-band tunneling in semiconductor devices

Abstract

Disclosed are integrated circuit transistor structures that reduce band-to-band tunneling between the channel region and the source / drain regions of the transistor without adversely increasing the intrinsic resistance of the device. In exemplary embodiments, the structure includes one or more spacers configured to separate the source and / or drain from the channel region. The regions of the spacers(s) comprise semiconductor materials that provide a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacers comprise silicon, germanium, and carbon (e.g., for devices with a germanium channel). The proportions may be at least 10% silicon, at least 85% germanium, and at least 1% carbon by atomic percentage. Other embodiments are implemented using III-V materials.

Description

Background Technology

[0001] Semiconductor devices are electronic components that utilize the electronic properties of semiconductor materials such as silicon, germanium, and gallium arsenide. A field-effect transistor (FET) is a semiconductor device comprising three terminals: a gate, a source, and a drain. An FET uses an electric field applied through the gate to control the conductivity of a channel through which charge carriers (e.g., electrons or holes) flow from the source to the drain. In instances where the charge carriers are electrons, the FET is called an n-channel device, and in instances where the charge carriers are holes, the FET is called a p-channel device. Some FETs have a fourth terminal, called the body or substrate, which can be used to bias the transistor. Additionally, a metal-oxide-semiconductor FET (MOSFET) includes a gate dielectric between the gate and the channel. MOSFETs can also be known as metal-insulator-semiconductor FETs (MISFETs) or insulated-gate FETs (IGFETs). Complementary MOS (CMOS) structures use a combination of p-channel MOSFETs (PMOS) and n-channel MOSFETs (NMOS) to implement logic gates and other integrated circuits. When a MOSFET device is biased in the off state, such as in an n-MOS where the gate is held low and the drain is held high, a relatively large electric field exists in the channel-drain region, which can lead to a phenomenon known as band-to-band tunneling (BTBT). BTBT can cause several non-negligible problems. Attached Figure Description

[0002] As the following detailed description continues, and with reference to the accompanying drawings, in which similar figures depict similar parts, the features and advantages of the claimed subject matter will become apparent.

[0003] Figures 1a-1b each illustrate an exemplary cross-sectional view of an integrated circuit transistor structure configured according to certain embodiments of the present disclosure.

[0004] Figures 2a-2b Each illustration shows an exemplary cross-sectional view of another integrated circuit transistor structure configured according to certain other embodiments of this disclosure.

[0005] Figures 3a-3c Each illustration shows an exemplary cross-sectional view of another integrated circuit transistor structure configured according to certain other embodiments of this disclosure.

[0006] Figures 4a-4b Each illustration depicts a diagram of the conduction band energy and valence band energy according to an exemplary embodiment of the present disclosure.

[0007] Figure 5The illustrations depict methods for forming integrated circuit transistor structures to reduce band-to-band tunneling according to certain embodiments of the present disclosure.

[0008] Figure 6 The illustrations depict computing systems according to some embodiments of the present disclosure, which are implemented using integrated circuit structures and / or transistor devices formed by using the techniques disclosed herein.

[0009] While the detailed implementation below will continue with reference to illustrative embodiments, many alternatives, modifications and variations thereto will be apparent in light of this disclosure. Detailed Implementation

[0010] Techniques for reducing band-to-band tunneling in integrated circuit transistor devices are disclosed. According to some embodiments, the techniques can be implemented, for example, to reduce band-to-band tunneling or source-to-drain tunneling between the channel region and the source / drain region of the transistor without increasing the intrinsic resistance of the device. This can subsequently improve device performance and efficiency, and reduce off-state current. The techniques include epitaxially providing undoped or lightly doped semiconductor spacers, together with heavily doped semiconductor material in the source / drain regions. The source / drain semiconductor spacers are disposed in the source / drain recesses before depositing the heavily doped source / drain material, such that the source / drain spacers are located between the heavily doped source / drain regions and the channel region. As will be appreciated from this disclosure, the semiconductor material of the source / drain spacers is selected such that it increases the band offset against the conductive carrier without adversely affecting other bands. In embodiments, the spacers comprise semiconductor materials having a band gap larger than the channel band gap. Therefore, for example, in PMOS devices, the source / drain spacers comprise semiconductor materials that provide a relatively high conduction band offset (CBO) and a zero or otherwise relatively low valence band offset (VBO), and in NMOS devices, the source / drain spacers comprise semiconductor materials that provide a relatively high VBO and a zero or otherwise relatively low CBO. In some cases, the heavily doped source / drain material is identical to the source / drain spacer material except that the spacer material is undoped or only lightly doped relative to the subsequently deposited heavily doped source / drain material. In such cases, it is noted that the dopant can be adjusted via one or more process knobs, in a step-like or graded manner, during a continuous source / drain epitaxial deposition process. In other cases, the heavily doped source / drain material is compositionally different from the undoped or lightly doped source / drain spacer material (i.e., the spacer materials are compositionally different in addition to being doped differently). In any such case, the arrangement of the selected material provides a strip structure configured to reduce strip-to-strip tunneling without significantly affecting intrinsic resistance. Numerous configurations will become apparent from this disclosure.

[0011] General Overview

[0012] As previously explained, band-to-band tunneling (BTBT) can cause several non-trivial problems. For example, in the PMOS case of BTBT, there is hole tunneling from the drain to the channel, and in the NMOS case of BTBT, there is electron tunneling from the drain to the channel. This can produce undesirable effects in the device, including unacceptable levels of off-state current.

[0013] Therefore, techniques are provided herein to reduce the BBT (Block Band Bending) between the channel region and the source / drain region of a transistor. According to some embodiments, advantageously, a reduction in BBT can be achieved without adversely increasing the intrinsic resistance of the device. In embodiments, the integrated circuit transistor structure includes a heavily doped semiconductor material in the source / drain region, but with an undoped / lightly doped source / drain semiconductor spacer between the heavily doped source / drain semiconductor material and the channel region. The source / drain spacer material is a semiconductor material that increases the band offset of the target carrier, such as a semiconductor material with a band gap larger than the channel band gap. Therefore, for PMOS devices, the source / drain spacer material suppresses tunneling from the valence band of the drain to the conduction band of the channel, and for NMOS devices, the source / drain spacer material suppresses tunneling from the conduction band of the drain to the valence band of the channel. For example, in a PMOS device, the source / drain spacer comprises a semiconductor material that provides a relatively high CBO (Conduction Bore) and a relatively low VBO (Voltage Bore). Therefore, for example, in some embodiments, the semiconductor spacer material for PMOS devices provides a CBO of 0.1 eV or greater (e.g., ≥150 meV, or ≥180 meV, or ≥200 meV) while simultaneously providing a VBO of less than 50 meV (e.g., -0.045 to 0.045 meV, or -0.035 to 0.035 meV, or -0.025 to 0.025 meV, or -0.015 to 0.015 meV, or -0.01 to 0.01 meV). On the other hand, for NMOS devices, the source / drain spacer comprises a semiconductor material that provides a relatively low CBO and a relatively high VBO. Therefore, for example, in some embodiments, the semiconductor spacer material for NMOS devices provides a VBO of 0.1 eV or greater (e.g., ≥150 meV, or ≥180 meV, or ≥200 meV) while simultaneously providing a CBO of less than 50 meV (e.g., -0.045 to 0.045 meV, or -0.035 to 0.035 meV, or -0.025 to 0.025 meV, or -0.015 to 0.015 meV, or -0.01 to 0.01 meV). Such selection criteria provide a desirable strip structure.

[0014] It should be noted that such band properties can be temperature-dependent and therefore can be measured at appropriate temperatures, as will be appreciated. In some embodiments, for example, the band properties discussed herein are measured at temperatures in the range of approximately 300 Kelvin (K), and therefore approximately 300 + / - 5 K (e.g., 300 K or 302 K). Appropriate measurement temperatures may vary from embodiment to embodiment, and this disclosure is not intended to be limited to temperature. As will be appreciated therein, offsets may be scaled based on the measurement temperature.

[0015] In some exemplary cases, in addition to the following, the source / drain spacer material is compared with heavily doped source / drain materials (e.g., exceeding 1E18 cm⁻¹). 3 Same dopant concentration: source / drain spacer material is undoped or only lightly doped (e.g., less than 1E18cm). 3 The dopant concentration). For example, in one such exemplary embodiment with a germanium channel region, boron-doped silicon-germanium carbon (b-doped SiGe:C) is used for the heavily doped source / drain material, and the same SiGe:C composite is used in an undoped / lightly doped state (no or relatively low boron concentration) for the source / drain spacer. In some such cases, the germanium concentration is in the range of 80 to 90 atomic percent. In other exemplary cases, the heavily doped source / drain material is compositionally different from the source / drain spacer material (i.e., more than just differently doped). For example, in one such embodiment with a germanium channel region, boron-doped germanium is used for the heavily doped source / drain material, and undoped / lightly doped SiGe:C with a germanium concentration in the range of 80 to 90 atomic percent is used for the source / drain spacer. Note that a colon is used to include carbon because it is a relatively small amount relative to silicon and germanium (e.g., 4 atomic percent or less). For this reason, the colon can also be omitted (SiGeC).

[0016] As previously noted, the source / drain spacer is undoped or lightly doped relative to the highly doped source / drain regions. According to some embodiments, the highly doped source / drain material can be, for example, having a germanium concentration in the range of 80 to 100 atomic percent and exceeding 1E18 cm⁻¹. 3 Or 1E20cm 3 Or 1E21cm 3 Or 2E21cm 3 p-doped semiconductors with boron concentrations of [missing information]. In contrast, according to some embodiments, undoped or lightly doped source / drain spacer materials can be, for example, having a germanium concentration in the range of 80 to 90 atomic percent and less than 1E18 cm⁻¹. 3 Or 1E17cm 3 Or 1E16cm 3 p-doped SiGe:C with boron concentrations. Similar dopant concentrations can also be applied to n-doped transistor devices. As will be appreciated from this disclosure, any number of materials and doping schemes can be used in combination with the source / drain spacers, satisfying the selection criteria provided herein differently regarding band structures.

[0017] As will be further appreciated, the concentration of the elements constituting the spacers can vary from one embodiment to the next. For example, in some embodiments having source / drain spacers comprising SiGe:C, those spacers comprise 10 to 16 atomic percent silicon, 80 to 90 atomic percent germanium, and 1 to 4 atomic percent carbon. In a more general sense, the PMOS transistor configuration with a germanium channel according to the embodiments herein can be implemented using any material system arranged to provide a highly doped semiconductor source / drain region combined with an undoped / lightly doped source / drain semiconductor spacer material that provides a CBO of 0.1 eV or greater and a VBO of less than 0.04 eV (e.g., -0.04 eV < VBO < +0.04 eV). Note that these offsets (CBO and VBO) of the source / drain spacers are relative to the channel region. In any such PMOS configuration, the high CBO of the selected source / drain semiconductor spacer material provides an increased bandgap at the channel / drain boundary, which reduces or prevents BBT, while the low VBO ensures that the device's intrinsic resistance remains low, as will be explained herein. Similarly, an NMOS transistor configuration with a germanium or III-V material channel according to the embodiments herein can be implemented using any material system arranged to provide a highly doped semiconductor source / drain region combined with an undoped / lightly doped semiconductor source / drain spacer material providing a VBO of 0.1 eV or greater and a CBO of less than 0.04 eV (e.g., 0.0 eV ± 0.04 eV). In any such NMOS configuration, the high VBO of the selected source / drain semiconductor spacer material provides an increased bandgap at the channel / drain boundary, which reduces or prevents BBT, while the low CBO ensures that the device's intrinsic resistance remains low, as will be explained herein.

[0018] According to embodiments, methods for implementing these technologies include forming a semiconductor body and at least a gate structure on that semiconductor body, thereby defining a channel region in the body below the gate structure. The semiconductor body may be planar or non-planar (e.g., a FinFET or nanowire channel configuration), and in some embodiments is germanium. The gate structure is disposed at least above the semiconductor body (in planar devices), but may also be disposed on opposite sidewalls of the semiconductor body (in FinFET devices) or completely surrounding the semiconductor body (in nanowire devices). The gate structure includes a gate dielectric, a gate electrode, and a gate spacer, and may be implemented in a gate-first or gate-later process. Note that in some embodiments, the gate dielectric may include a high-k gate dielectric. The method further includes etching source and drain recesses adjacent to the gate structure such that the source / drain recesses undercut the gate structure. Thus, each source / drain recess extends vertically downward into the substrate or semiconductor body on which it is formed, and laterally beneath the gate spacer and gate electrode (and gate dielectric). Undoped / lightly doped source / drain semiconductor spacer (S / D spacer) material is then deposited into the source / drain recesses, at least adjacent to the channel region, followed by deposition of heavily doped source / drain material. Note that this deposition process can be continuous, with the dopant concentration increasing from approximately zero fractions or steps to, for example, more than 1E18 cm⁻¹ during the deposition of the S / D spacer portion. 3This is used for the bulk of the highly doped S / D portion. As will be further understood, the thickness of the S / D spacer material deposition can vary, but in some embodiments it is in the range of 3 nm to 50 nm (e.g., 5 to 30 nm, or 5 to 25 nm, or 5 to 20 nm, or 3 to 10 nm). In some such cases, the thickness of the S / D spacer material deposition constitutes approximately 25% or less of the overall thickness of the total S / D structure (the overall thickness includes undoped / lightly doped S / D spacers and highly doped source / drain portions), and the highly doped S / D material constitutes approximately 50% to 95% of the overall thickness of the S / D structure. It is also noted that the highly doped S / D material deposition can be used to form so-called raised S / D regions, such that the S / D regions extend beyond the recess opening (above it) and above the channel region between them. Furthermore, recalling that for PMOS transistor devices, the S / D spacer semiconductor material is chosen to provide a relatively high CBO (e.g., exceeding 150 or 180 mAh) and a relatively low VBO (e.g., 0 eV, + / - 0.025 eV), and for NMOS transistor devices, the S / D spacer semiconductor material is chosen to provide a relatively high VBO (e.g., exceeding 150 or 180 mAh) and a relatively low CBO (e.g., 0 eV, + / - 0.025 eV). Numerous PMOS and NMOS transistor structures that satisfy these criteria can be formed.

[0019] Architecture

[0020] The transistor structures provided herein can be implemented using any number of material systems that meet the criteria provided herein regarding channel and source and / or drain materials. In some embodiments, the channel and source and / or drain materials are group IV semiconductor materials (e.g., silicon, germanium, SiGe, SiGe:C), while in other embodiments, the channel and source and / or drain materials are group III-V semiconductor materials (e.g., indium aluminum arsenide-InAlAs, indium arsenide phosphide-InAsP, indium gallium phosphide-InGaAsP, gallium antimonide-GaSb, gallium aluminum antimonide-GaAlSb, indium gallium antimonide-InGaSb, indium gallium antimonide phosphide-InGaPSb, indium gallium antimonide-InGaSb, indium gallium arsenide-InGaAs, and indium arsenide-InAs, or other group III-V semiconductor materials or compounds). Figures 1a-b, 2a-b, 3a-b and Table 1 illustrate various exemplary group IV semiconductor embodiments, and Figure 3c Table 2 illustrates various exemplary III-V semiconductor embodiments.

[0021] Figures 1a and 1b each illustrate exemplary cross-sectional views of integrated circuit transistor structures according to certain embodiments of the present disclosure. As can be seen, each of the exemplary structures 100 and 100' illustrates a PMOS transistor device comprising a semiconductor substrate 101 and a semiconductor body including a channel region 110. A gate stack or structure is formed over the channel region 110 and includes a gate dielectric 103 and a gate electrode 104. Additionally, a gate spacer 102 is provided to either side of the gate stack. As can be seen, the source recess is filled with a combination of undoped / lightly doped source / drain spacers 112 and a highly doped source region 106, and the drain recess is filled with a combination of undoped / lightly doped source / drain spacers 112 and a highly doped drain region 108. Other transistor features, such as source and drain contacts and insulating fill materials, local interconnects, and interconnect / metal layers, are not shown but will readily become apparent from the present disclosure. As will further appreciate in light of this disclosure, spacer 112, in conjunction with source region 106 and drain region 108, operates to provide an overall band structure or configuration (with respect to the channel region) that is configured to reduce band-to-band tunneling without adversely affecting the intrinsic resistance of transistor structure 100 or 100'. It will also be appreciated that the illustrated cross-section can be a planar channel architecture or a non-planar channel architecture. For example, for a non-planar fin-based or nanowire channel structure, the illustrated cross-section is obtained through and parallel to the fin / semiconductor body (and perpendicular to the gate). Due to the nature of the cross-section, multiple sides of the gate structure with respect to the non-planar semiconductor fin / body cannot be seen, but will again readily become apparent to those skilled in the art.

[0022] Substrate 101 can be any suitable semiconductor substrate, such as bulk silicon, bulk germanium, or bulk III-V material (e.g., deepened indium gallium-InGaAs, or gallium arsenide-GaAs) substrate. Alternatively, substrate 101 can be a multilayer structure, such as a semiconductor-on-insulator configuration (e.g., germanium-on-oxide, or GaAs-on-oxide), or a first semiconductor layer (e.g., germanium) on a second semiconductor layer (e.g., silicon or SiGe layer). In a more general sense, any number of substrate configurations can be used, and this disclosure is not intended to be limited to any particular type.

[0023] Note that the channel region 110 may be native to the substrate 101 (i.e., the channel region 110 is formed by and is part of the substrate 101), but may also be compositionally different from the underlying substrate (e.g., germanium fins or bodies 110 on an InGaAs substrate 101). This optional compositional difference is generally depicted in the figures as a dashed line between the channel region 110 and the substrate 101. In some such embodiments, the compositionally different semiconductor fins or bodies that will ultimately include the channel region 110 are epitaxially grown from the trench after the removal of the sacrificial native fins, in a so-called aspect ratio-based trapping (ART) fin formation process. An exemplary ART-based semiconductor fin formation technique is provided, for example, in U.S. Patent Application Publication 2014 / 0027860. In some such ART-based cases, alternative fin materials are provided as alternating layers of the desired channel material and sacrificial / inactive materials, as described in U.S. Patent Application Publication 2016 / 0260802. Such multilayer fins are particularly useful for forming nanowire transistors (e.g., during the final gate processing, before the deposition of the final gate material). In some ART-based applications, a first fin or wire assembly is formed using a first semiconductor material system (e.g., for p-type devices), and a second fin or wire assembly is formed using a second semiconductor material system (e.g., for n-type devices). Any number of fin formation processes can be used in the context of this disclosure, provided that suitable strip structures, as described differently herein, can be supplied to mitigate or otherwise reduce strip-to-strip tunneling.

[0024] The gate structure can be implemented using any suitable process and materials. For example, the gate structure can be formed during a metal gate replacement process (or so-called post-gate process), where a dummy gate material is initially supplied and then removed later in the process to make way for the final gate material. Alternatively, the gate structure can be formed during a so-called pre-gate process, where the desired final gate material is provided earlier in the process. In the illustrated embodiment, the gate dielectric 103 is provided between the gate spacer 102 and the gate electrode 104 to provide a U-shape in the illustrated cross-section. However, in other embodiments, the gate dielectric is only between the gate electrode 104 and the channel region 110, such that the gate spacer can directly contact the opposing sidewalls of the gate electrode 104. The gate stack can further include a hard mask on top of the gate electrodes (and any exposed gate dielectric). Any number of gate stack configurations can be used.

[0025] The gate spacer 102 may be, for example, silicon nitride or silicon dioxide. The gate dielectric 103 may be, for example, any suitable gate dielectric material, such as silicon dioxide or a high-k gate dielectric material. Examples of high-k gate dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when using a high-k material, an annealing process may be performed on the gate dielectric 103 to improve its quality. Furthermore, the gate electrode 104 may include, for example, a wide range of materials, such as polysilicon, silicon nitride, silicon carbide, or various suitable metals or metal alloys, such as aluminum, tungsten, titanium, tantalum, copper, titanium nitride, or tantalum nitride.

[0026] In some embodiments, the gate dielectric and / or gate electrode may comprise a multilayer structure of two or more material layers or components. For example, in one such embodiment, the gate dielectric is a bilayer structure having a first dielectric material (e.g., silicon dioxide) in contact with the channel region and a second dielectric material (e.g., hafnium oxide) in contact with the first dielectric material, the first dielectric material having a lower dielectric constant than the second dielectric material. Similarly, the gate electrode structure may include a central metal plug portion (e.g., tungsten) having one or more external work function layers and / or barrier layers (e.g., tantalum, tantalum nitride), and / or a resistance-reducing capping layer (e.g., copper, gold). In some embodiments, the gate dielectric and / or gate electrode may include a graded distribution (increasing or decreasing, as appropriate) of the concentration of one or more of these materials. Numerous different gate structure configurations can be used, as will be apparent from this disclosure.

[0027] In some embodiments fabricated using a post-gate process, the source / drain recess is formed adjacent to the channel region 110 after a dummy gate stack (e.g., polysilicon gate electrode 104, silicon dioxide gate dielectric 103, and silicon nitride gate spacer 102) has been provided. However, in other embodiments with a pre-gate process, the source / drain recess can be formed adjacent to the channel region after that final gate stack (e.g., tungsten gate electrode 104, hafnium dioxide gate dielectric 103, and silicon nitride gate spacer 102) has been provided. In any case, it is noted that the source / drain recess undercuts the gate structure such that the recess extends below the gate spacer 102 and the gate electrode 104. Any suitable etching can be used, including wet and / or dry etching, isotropic and / or anisotropic etching, and selective etching schemes. The degree of undercut will vary from one embodiment to the next, depending on factors such as the desired distance between the source and drain recesses (or the lateral length of the channel region 110) and the desired thickness of the spacer layer 112. In some cases, the thickness of the source layer 112 is less than 20%, or less than 15%, or less than 10%, or less than 5% of the overall thickness of the source / drain structure (i.e., the combined thickness of 112 and 106 for the source structure and 112 and 108 for the drain structure). Furthermore, it should be noted that while the recesses shown in Figures 1a-1b are provided with a rounded profile adjacent to the channel region, other embodiments may provide more facet-shaped or angular source / drain recesses, depending on factors such as the crystal orientation of the channel material and the etching process employed, as will be appreciated.

[0028] Source / drain spacer 112 is first deposited into the recess (before the heavily doped source / drain regions 106 / 108) to effectively provide a BTBT inhibitor between the channel region 110 and the corresponding source region 106 and drain region 108. As previously explained, spacer 112 comprises a semiconductor material selected to effectively increase the band offset against the target carriers (i.e., holes for PMOS devices or electrons for NMOS devices). Thus, for PMOS devices, and more specifically in this exemplary embodiment, the selected spacer 112 material has a relatively high CBO and a zero or otherwise relatively low VBO. As will be appreciated, these offsets (CBO and VBO) of spacer 112 are relative to the channel region 110. In an embodiment, the spacer material has a larger band gap than the channel material. In any such case, the selected spacer 112 material may also be subject to doping to provide the desired level of conductivity and / or polarity, particularly in embodiments in which the same material is used in the heavily doped source / drain regions 106 / 108.

[0029] In some embodiments, the source / drain semiconductor spacer material for the PMOS device is selected such that CBO exceeds a threshold of at least 150 millielectron volts (meV) or at least 180 meV, and VBO is less than a threshold of 20 meV or less than 10 meV or less than 5 meV (or otherwise relatively close to 0 meV). In some such embodiments having a germanium channel region, the selected semiconductor material for spacer 112 is silicon germanium carbon (SiGe:C), however, other semiconductor materials exhibiting the previously mentioned desired properties may also be used. In some such embodiments, the selected semiconductor spacer material composition may be one of, or otherwise comparable to, the following: Si 0.16 Ge 0.80 C 0.04 Si 0.15 Ge 0.83 C 0.02 Si 0.14 Ge 0.85 C 0.01 Si 0.13 Ge 0.85 C 0.02 Si 0.11 Ge 0.88 C 0.01 , or Si 0.10 Ge 0.89 C 0.01 Other exemplary embodiments will be apparent, such as any of those having a germanium concentration in the range of about 80 to 90 atomic percent, a silicon concentration in the range of about 10 to 16 atomic percent, and a carbon concentration in the range of about 1 to 4 atomic percent.

[0030] In some such embodiments having SiGe:C spacer 112, the channel can be, for example, bulk germanium (undoped / lightly doped), and the source / drain regions 106 / 108 are boron-doped germanium or SiGe or SiGe:C with a different germanium concentration than the spacer 112. The underlying substrate can be any number of materials, to name just a few, such as silicon, Ge, SiGe, or InGaAs. In this first example embodiment, as illustrated in FIG. 1a, the spacer 112 is undoped or relatively lightly doped compared to the relatively heavily doped source and drain regions 106 and 108. If the substrate is doped, the doping of the spacer 112 can be, for example, one or more orders of magnitude lower than that of the heavily doped source and drain regions 106 and 108.

[0031] As shown in the exemplary embodiment of FIG1a, spacer 112 is disposed below gate electrode 104. Note that spacer 112 does not need to be aligned with gate spacer 102. However, in Figure 1bIn this embodiment, spacer 112 is aligned with gate spacer 102. Such alignment is not required; more precisely, any degree of overlap between the source / drain spacer 112 and the gate electrode 104 and / or gate dielectric 103 can help mitigate BTBT. In embodiments where the gate dielectric 103 is also disposed on the sidewall of the gate 104, the spacer 112 may simply be below the gate dielectric 103. The overlap distance can vary from embodiment to embodiment, but in some cases it is in the range of 0.1 nm to 5 nm overlap between the gate electrode 104 and / or gate dielectric 103 and each source / drain spacer 112. Note that because the source / drain spacers 112 below the gate electrode 104 and / or gate dielectric 103 are lightly doped or undoped, most band bending will occur in the lightly / undoped regions, and it is desirable for band bending to occur in regions with high offset.

[0032] Figure 1a' illustrates an alternative embodiment for any of the embodiments provided herein, however, it is shown in the context of Figure 1a. Specifically, note that neither the source nor the drain region needs to have the spacers as provided herein; more precisely, in some embodiments, only the source region includes spacers and the drain region is a regular drain structure, while in other embodiments, only the drain region includes spacers and the source region is a regular source structure. The same alternative embodiments can be applied to the embodiments described herein. Figure 1b , 2a Any of the embodiments discussed in -b and 3a-c, and Figure 5 An exemplary method.

[0033] Figure 2a and 2b Each figure illustrates an exemplary cross-sectional view of another integrated circuit transistor structure according to certain embodiments of the present disclosure. As can be seen, structures 200 and 200' are similar to structures 100 and 100', respectively, except as follows: the highly doped source and drain regions 206 / 208 are formed from the same semiconductor material (same semiconductor composition, but regardless of dopant concentration) selected for the undoped / lightly doped spacers 212. Thus, for example, for the purposes of this particular discussion, undoped / lightly doped SiGe:C and heavily doped SiGe:C having the same germanium-silicon-carbon concentration can be considered compositionally identical, despite having different boron concentrations, while undoped / lightly doped SiGe:C and heavily doped SiGe are compositionally different. Regarding the similarity between Figures 1a-b and 2a-b, the previous related discussions regarding the gate structure (including gate electrode 104, gate dielectric 103, and gate spacer 102), channel region 110, and substrate 101 are equally applicable here.

[0034] In some such exemplary embodiments, for a PMOS device, both the source / drain spacer 212 and the source / drain regions 206 / 208 are formed of SiGe:C. However, the source / drain regions 206 / 208 are heavily doped SiGe:C, relative to the undoped / lightly doped SiGe:C spacer 212. As previously explained, the spacer 212 is deployed to separate the source regions 206 and 208 from the channel region 110 to suppress BTBT. In embodiments, the spacer material has a larger bandgap than the channel material (or simply the channel bandgap).

[0035] As in Figure 2a As shown in the exemplary embodiment, the source / drain spacer 212 is disposed below the gate electrode 204, but does not need to be aligned with the gate spacer 202. As explained with respect to Figures 1a-b, the source / drain spacer 212 does not need to be aligned with the gate spacer 202. Figure 2b In an exemplary embodiment, the source / drain spacer 212 is aligned with the gate spacer 202. Previous related discussions regarding the degree of overlap between the source / drain spacer 112 and the gate electrode 104 and / or the gate dielectric 103 are equally applicable herein.

[0036] Figure 3a and 3b Each illustration shows an exemplary cross-sectional view of an integrated circuit transistor structure according to other embodiments of the present disclosure. As can be seen, each of the exemplary structures 300 and 300' illustrates an NMOS transistor device comprising a semiconductor substrate 101 and a semiconductor body including a channel region 110. A gate stack or structure is formed over the channel region 110 and includes a gate dielectric 103 and a gate electrode 104. Additionally, a gate spacer 102 is provided on either side of the gate stack. As can be seen, the source recess is filled with a combination of undoped / lightly doped source / drain spacers 312 and a highly doped source region 306, and the drain recess is filled with a combination of undoped / lightly doped source / drain spacers 312 and a highly doped drain region 308. Regarding the similarity between Figures 1a-b and 3a-b, the previous related discussions concerning the gate structure (including gate electrode 104, gate dielectric 103, and gate spacer 102), channel region 110, and substrate 101 are equally applicable here.

[0037] Source / drain spacer 312 is first deposited into the recess to effectively provide a BTBT inhibitor between the channel region 110 and the corresponding source region 306 and drain region 308. As previously explained, spacer 312 comprises a semiconductor material selected to effectively increase the band offset against the target carriers (i.e., holes for PMOS devices or electrons for NMOS devices). Thus, for NMOS devices (such as this exemplary embodiment), the selected spacer 312 material has a relatively high VBO and a zero or otherwise relatively low CBO. As will be appreciated, these offsets (CBO and VBO) of spacer 312 are relative to the channel region 110. In embodiments, the spacer material has a larger band gap than the channel material. In any such case, the selected spacer 312 material may also be subject to doping to provide a desired level of conductivity and / or polarity, particularly in embodiments where that same material is used in the heavily doped source / drain regions 306 / 308.

[0038] In some embodiments, the source / drain semiconductor spacer material for the NMOS device is selected such that VBO exceeds a threshold of at least 150 millielectron volts (meV) or at least 180 meV, and CBO is less than a threshold of 10 meV or less than 5 meV (or otherwise relatively close to 0 meV). In some such embodiments having a germanium channel region, the selected semiconductor material for spacer 312 is silicon-germanium (SiGe) or silicon; however, other semiconductor materials exhibiting the previously mentioned desired properties may also be used. In some such embodiments, the selected semiconductor spacer 312 material composition may be one of, or otherwise comparable to, the following: Si 0.8 Ge 0.20 Si 0.85 Ge 0.15 Si 0.87 Ge 0.13 , or Si 0.90 Ge 0.10 Other exemplary embodiments will be apparent, such as those having a silicon concentration in the range of about 80 to 90 atomic percent and a germanium concentration in the range of about 10 to 20 atomic percent. In other embodiments, the source / drain spacer 312 may be all silicon. In some such embodiments having undoped or lightly doped SiGe or silicon spacers 312, the channel may be, for example, bulk germanium (undoped / lightly doped), and the heavily doped source / drain regions 306 / 308 are phosphorus-doped germanium, as in... Figure 3aAs shown in the exemplary embodiments. In other such exemplary embodiments, the heavily doped source / drain regions 306 / 308 are made of the same material as the source / drain spacer 312 (except for doping, as will be understood), as Figure 3b As shown in the image.

[0039] Table 1 illustrates several specific exemplary embodiments for both PMOS and NMOS configurations, using a group IV semiconductor material system including silicon and germanium. As will be appreciated with respect to Table 1, the polar dopant for the p-type source / drain regions (PMOS devices) is indicated as the first component in a given material, followed by a colon. For example, to name just a few types, exemplary p-type dopants for group IV source / drain materials include boron, gallium, and aluminum. Thus, for example, a boron-doped germanium source or drain region is represented as B:Ge, and a lightly boron-doped SiGe:C source or drain spacer is represented as B:SiGe:C. Similarly, to name just a few types, exemplary n-type dopants for group IV source / drain materials (NMOS devices) include phosphorus, arsenic, and antimony. Thus, for example, a phosphorus-doped silicon source or drain region is represented as P:Si, and a lightly phosphorus-doped SiGe:C source or drain spacer is represented as P:SiGe:C. As will further appreciate with respect to Table 1, although the channels in each of the examples are indicated as undoped, in other embodiments, the channels in any of these examples may be lightly doped (p-type or n-type, depending on factors such as desired performance, transistor type, and operating mode). Moreover, if the atomic percentages of a given component of the semiconductor material are provided as a range, then the explicitly stated exemplary embodiments include composites / alloys having any weighted values ​​within that given range. For example, source / drain spacers Si. x Ge y :C z Where 8 ≤ x ≤ 16, 80 ≤ y ≤ 90, and 1 ≤ z ≤ 4, then various exemplary embodiments include any SiGe:C alloy which is fully represented by (excluding dopants—if present—to provide n-type / p-type polarity) as follows: any first atomic percentage of silicon in the range of 8 to 16 atomic percentages, any second atomic percentage of germanium in the range of 80 to 90 atomic percentages, and any third atomic percentage of carbon in the range of 1 to 4 atomic percentages, wherein the first, second, and third atomic percentages are equal to 100 percent. Numerous variations in material systems and alternative embodiments will be appreciated in light of this disclosure.

[0040]

[0041]

[0042] Table 1: Exemplary Group IV material systems for reducing BTBT.

[0043] Although Figures 1a to 3b involve group IV semiconductor materials in the channel and source / drain regions, other embodiments are also available according to this disclosure. Figure 3c This involves III-V group semiconductor materials in the channel and source / drain regions. As can be seen, each of the exemplary structures 300” illustrates an NMOS transistor device comprising a semiconductor substrate 101 and a semiconductor body including a channel region 410. A gate stack or structure is formed over the channel region 410 and includes a gate dielectric 103 and a gate electrode 104. Additionally, a gate spacer 102 is provided to either side of the gate stack. As can be seen, the source recess is filled with a combination of undoped / lightly doped source / drain spacers 412 and a highly doped source region 406, and the drain recess is filled with a combination of undoped / lightly doped source / drain spacers 412 and a highly doped drain region 408. In general, the previous related discussions concerning transistor components and BTBT mitigation are equally applicable here, as will be appreciated. In a more general sense, given that this disclosure will make it apparent that different materials can be used in any of the various transistor components depicted, and that this disclosure is not intended to be limited to the specific exemplary embodiments provided herein.

[0044] Table 2 illustrates several specific exemplary embodiments for NMOS configurations using group IV semiconductor material systems including silicon and germanium. As will be appreciated with respect to Table 2, polar doping for the n-type or p-type source / drain regions is indicated as the first component in a given material, followed by a colon, as explained with respect to Table 1. Exemplary p-type dopants for group III-V source / drain materials include magnesium, beryllium, and carbon, and exemplary n-type dopants for group III-V source / drain materials include silicon and tellurium. As will also be appreciated with respect to Table 2, while the channel is indicated as undoped in each of the examples, in other embodiments, the channel in any of these examples may be lightly doped (p-type or n-type, depending on factors such as desired performance, transistor type, and operating mode). Moreover, if the atomic percentage of a given component of the semiconductor material is provided as a range, then the explicitly stated exemplary embodiments include compounds / alloys having any weighted value within that given range. For example, source / drain spacers In y Al 1-yAs, where 0.60 ≤ y ≤ 1.00, then various exemplary embodiments include any InAlAs complex, which is fully represented by (excluding dopants—if present—to provide n-type / p-type polarity) as follows: any first atomic percentage of indium in the range of 60 to 100 atoms; and any second atomic percentage of aluminum in the range of 0 to 40 atomic percentages of germanium, wherein the first and second atomic percentages are equal to 100 percent. It is also noted that 0 atomic percentage means that the particular element is not in the complex. Numerous variations of the material system and alternative embodiments will be appreciated in light of this disclosure.

[0045]

[0046]

[0047]

[0048]

[0049] Table 2: Exemplary III-V material systems for reducing BTBT.

[0050] Note that the broken bandgap contact mentioned for some examples in Table 2 means that the valence band of the spacer material is above the conduction band of the channel material. Because the valence band of the source / drain region is above the conduction band of the channel, the carrier can travel between the two materials with minimal (almost unmeasurable) or otherwise reduced resistance. This type of interface is sometimes referred to as a broken bandgap heterostructure. So, while other entries in Table 2 have n-type doped source / drain regions in contact with an n-type channel (meaning the channel is undoped or lightly p-doped), these specific examples have p-type doped source / drain regions in contact with an n-type channel. Furthermore, note that in these specific cases, the transistor is still an NMOS transistor, although the source / drain regions are p-type doped, a property unique to the broken bandgap material.

[0051] Figure 4a A set of plots 400 is shown illustrating the conduction band and valence band energies for various PMOS transistor devices, some configured according to embodiments of this disclosure. Each of the three top plots 402, 404, and 406 shows the conduction band energy as a function of the location of the source, channel, and drain regions (from left to right). The bottom plot 408 shows the valence band energy as a function of the location of the source, channel, and drain regions (from left to right).

[0052] More specifically, Figure 402 illustrates the conduction band energy for a standard integrated circuit transistor structure, i.e., a structure that does not employ source / drain spacers that promote the band structure as described herein (e.g., in a PMOS device, the source / drain spacers comprise semiconductor materials providing relatively high CBO and relatively low VBO). Figure 404 illustrates the conduction band energy for the integrated circuit transistor structure illustrated in Figures 1a-b, which, as described above, employs a lightly doped SiGe:C spacer 112 between the germanium channel and the heavily p-doped germanium source and drain regions 106, 108. Figure 406 illustrates the conduction band energy for... Figure 2a The conduction band energy of the integrated circuit transistor structure illustrated in Figure -b is described above, which employs a lightly doped SiGe:C spacer 210 between the germanium channel and the heavily doped SiGe:C source and drain regions 206, 208. The dopant is boron, but any number of dopants can be used, depending on the desired polarity and desired conductivity.

[0053] As can be seen in the comparison of Figures 404 and 406 with respect to Figure 402, the use of SiGe:C semiconductor material provides an increased band offset, corresponding to an increased conduction band offset (CBO) for the p-type carrier, which in turn eliminates or otherwise reduces undesirable tunneling (such as band-to-channel tunneling from drain to channel and source-to-drain tunneling). Figure 408 shows the valence band energy, which remains substantially the same at a relatively low level for all three cases (e.g., standard device structure, SiGe:C spacer with germanium source / drain case, and SiGe:C case for both spacer and source / drain). This indicates that the intrinsic resistance of the transistor device does not substantially increase when using SiGe:C spacers as provided in this exemplary case.

[0054] Figure 4b A set of plots 450 is shown, illustrating the conduction band and valence band energies for an NMOS transistor device according to certain embodiments of the present disclosure. Each of the three top plots 452, 454, and 456 shows the valence band energy as a function of the location of the source, channel, and drain regions (from left to right). The bottom plot 458 shows the conduction band energy as a function of the location of the source, channel, and drain regions (from left to right).

[0055] More specifically, Figure 452 illustrates the conduction band energy for a standard integrated circuit transistor structure, i.e., a structure that does not employ source / drain spacers that promote the band structure as presented differently herein (e.g., in NMOS devices, the source / drain spacers comprise semiconductor materials providing relatively high VBO and relatively low CBO). Figure 454 illustrates the conduction band energy for... Figure 3a The figure illustrates the valence band energy of an integrated circuit transistor structure, which, as described above, employs a lightly doped SiGe spacer 312 between the germanium channel and the heavily n-doped germanium source and drain regions 306, 308. Figure 456 shows the valence band energy of the integrated circuit transistor structure. Figure 3b The diagram illustrates the conduction band energy of an integrated circuit transistor structure, which, as described above, employs a lightly doped SiGe spacer 312 between the germanium channel and the heavily doped SiGe source and drain regions 306, 308. In this exemplary case, the dopant is phosphorus.

[0056] As can be seen in the comparison of Figures 454 and 456 with respect to Figure 452, the use of SiGe semiconductor material provides an increased band offset, corresponding to an increased valence band offset (CBO) for the n-type carrier, which in turn eliminates or otherwise reduces undesirable tunneling (such as band-to-channel tunneling from drain to channel, and source-to-drain tunneling). Figure 458 shows the conduction band energy, which remains substantially the same at a relatively low level for all three cases (e.g., standard device structure, SiGe spacer with germanium source / drain case, and SiGe case for both spacer and source / drain). This indicates that the intrinsic resistance of the transistor device does not substantially increase when using SiGe spacers as provided in this exemplary case.

[0057] method

[0058] Figure 5 The illustrations depict methods for fabricating or forming integrated circuit transistor structures to reduce band-to-band tunneling according to certain embodiments of the present disclosure. As can be seen, the exemplary methods include multiple stages and sub-processes, the sequence of which may vary from one embodiment to another. However, when considered in aggregate, these stages and sub-processes form certain processes for creating integrated circuit transistor structures with reduced band-to-band tunneling according to embodiments disclosed herein. Note that the methods can be used with either a gate-first process or a gate-later process. Numerous variations and alternative configurations will be apparent in light of this disclosure.

[0059] As in Figure 5As illustrated in the figure, in an embodiment, a method 500 for forming an integrated circuit transistor structure begins at operation 510, which involves forming a semiconductor body, for example, from germanium or III-V material. The semiconductor body may be planar (for planar transistor architectures), such as a bulk substrate or blanket. Alternatively, the semiconductor body may be non-planar, such as a fin. In any such case, a channel region may be formed within the semiconductor body, as will be appreciated. Next, at operation 520, a gate structure is formed and disposed at least above the semiconductor body. As previously explained, the gate structure is disposed above the semiconductor body (in planar devices), but may additionally be disposed on opposite sidewalls of the semiconductor body (in FinFET devices), or completely surrounding the semiconductor body (in gate-wound devices). In any such case, the gate structure generally includes a gate dielectric, a gate electrode, and opposing gate spacers, as previously explained.

[0060] As previously noted, one exemplary embodiment relates to a gate-before-gate process at 520, wherein the final gate material is provided prior to the formation of the source / drain structure. However, in other exemplary embodiments, a dummy gate material, such as silicon dioxide for the dummy gate dielectric and polysilicon for the dummy gate electrode, may be provided at 520. In such cases, the dummy gate material effectively serves as a position holder for the final gate material and can be removed later in the process, such as after the source / drain region has been formed at 550 and the dielectric fill material has been provided and planarized down to the dummy gate stack. Once the dummy gate stack is isolated (by applying a protective mask over the source / drain structure and dielectric fill material), the exposed dummy gate material can be removed using a suitable etching scheme and replaced by the final gate structure material, which may be the same material provided in the gate-before-gate process (e.g., a high-k gate dielectric, such as hafnium oxide, and a gate electrode, such as a tungsten plug having one or more titanium and / or titanium nitride layers for work function tuning). The method can then continue at 560, as will be discussed thereafter.

[0061] At operation 530, source and drain recesses are formed on either side of the gate structure to allow the formation of source and drain structures (including undoped / lightly doped source / drain spacers and heavily doped source / drain regions) therein, respectively. As previously explained, the source and drain recesses, according to some embodiments, represent at least one of each undercut gate electrode and / or gate dielectric, and can be supplied using any number of suitable etching schemes, including wet and / or dry isotropic and / or anisotropic etching.

[0062] At operation 540, undoped / lightly doped source / drain spacer material is epitaxially deposited into each of the source / drain recesses formed at 530. As previously explained, the source / drain spacers are configured to increase the band offset against the target carrier (p or n type) and provide the desired band structure: for PMOS, increasing CBO with little effect on VBO, and for NMOS, increasing VBO with little effect on CBO. Thus, the channel region of the semiconductor body is separated from the upcoming heavily doped source and drain regions by the corresponding source / drain spacers.

[0063] At operation 550, heavily doped source / drain material is epitaxially deposited into the source / drain recess and at least partially on the source / drain spacer material provided at 540. Note that in some embodiments, the heavily doped source / drain material may be the same material as the undoped / lightly doped spacer material, while in other embodiments, the heavily doped source / drain material is compositionally different from the undoped / lightly doped spacer material. As previously explained, compositional difference is intended to mean that the heavily doped source / drain material differs from the undoped / lightly doped spacer material beyond any difference in polarity-based doping supplied for the purpose of configuring a p-type or n-type device.

[0064] In some embodiments, the semiconductor material selected for the source / drain spacer is undoped or lightly doped silicon-germanium-carbon for use in PMOS devices with germanium channels, or undoped or lightly doped silicon-germanium for use in NMOS devices with germanium channels. In other embodiments, the semiconductor material selected for the source / drain spacer is undoped or lightly doped indium aluminum arsenide for use in NMOS devices with indium gallium arsenide channels. Tables 1 and 2 describe several other exemplary embodiments for group IV and group III-V source / drain spacer materials. In any such embodiment, the heavily doped source / drain regions may be of the same composition (but with desired impurities) or alternatively may be different in composition, as explained herein.

[0065] Note that one or more of the components of the source / drain structure provided herein can be hierarchical. In such cases, the S / D structure may include one or more hierarchical buffers or hierarchical segments. In some such cases, block portions with relatively fixed compositions may exist between the hierarchical portions. Any number of hierarchical schemes can be used.

[0066] At 560, the structure can be fabricated using standard or proprietary manufacturing techniques, which may include, for example, supplying filler material, planarization, contact structure formation, etc. One or more interconnect layers may be formed on the device layer, which includes transistors formed as provided herein. Numerous integrated circuit structures can be fabricated to include such transistors.

[0067] For example, one or more such integrated circuit transistors can be formed in the manufacture of, for example, processor or communication chips or memory chips or any other integrated circuit having transistors (including MOS transistors). Such integrated circuits can then be used in a wide variety of electronic devices and systems, to name just a few, such as desktop and laptop computers, smartphones, tablet computers, and test equipment. Numerous applications and functional circuits will be readily apparent.

[0068] Exemplary System

[0069] Figure 6 The illustration depicts a computing system 1000 according to some embodiments of the present disclosure, implemented using integrated circuit structures and / or transistor devices formed by using the techniques disclosed herein. As can be seen, the computing system 1000 houses a motherboard 1002. The motherboard 1002 may include a plurality of components, including but not limited to a processor 1004 and at least one communication chip 1006, each of which may be physically and electrically coupled to the motherboard 1002 or otherwise integrated therein. As will be appreciated, the motherboard 1002 may be, for example, any printed circuit board, whether it is a motherboard, a daughterboard mounted on a motherboard, or the sole board of the system 1000, etc.

[0070] Depending on its application, the computing system 1000 may include one or more other components that may or may not be physically and electrically coupled to the motherboard 1002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, optical discs (CDs), digital versatile discs (DVDs), etc.). Any component included in the computing system 1000 may include one or more integrated circuit structures or devices formed using the techniques disclosed according to exemplary embodiments. In some embodiments, multiple functions may be integrated into one or more chips (e.g., as noted, a communication chip 1006 may be part of or otherwise integrated into the processor 1004).

[0071] Communication chip 1006 enables wireless communication for transmitting data to and from computing system 1000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that transmit data using modulated electromagnetic radiation or through non-solid media. This term does not imply that the associated device does not contain any wires; however, in some embodiments they may not. Communication chip 1006 can implement any of a plurality of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE, Ev-Do, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. Computing system 1000 may include multiple communication chips 1006. For example, the first communication chip 1006 can be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1006 can be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0072] The processor 1004 of the computing system 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments, the processor's integrated circuit die includes on-board circuitry implemented using one or more integrated circuit structures or devices formed using the disclosed techniques, as described differently herein. The term "processor" can refer to any device or part of a device that processes, for example, electronic data from registers and / or memory to transform that electronic data into other electronic data that can be stored in registers and / or memory.

[0073] The communication chip 1006 may also include an integrated circuit die packaged within the communication chip 1006. According to some exemplary embodiments, the integrated circuit die of the communication chip includes one or more integrated circuit structures or devices formed using the techniques disclosed herein, as described differently. As will be appreciated in light of this disclosure, it is noted that multi-standard wireless capabilities can be directly integrated into the processor 1004 (e.g., the functionality of any chip 1006 is integrated into the processor 1004, rather than having a separate communication chip). Furthermore, it is noted that the processor 1004 can be a chipset with such wireless capabilities. In short, any number of processors 1004 and / or communication chips 1006 can be used. Similarly, any chip or chipset can have multiple functions integrated therein.

[0074] In various implementations, the computing system 1000 may be a laptop, netbook, notebook, smartphone, tablet device, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device or system that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques, as described differently herein. Note that the reference to computing system is intended to include computing devices, apparatus, and other structures configured for computing or processing information.

[0075] Other exemplary embodiments

[0076] The following examples pertain to other embodiments, from which numerous substitutions and configurations will become apparent.

[0077] Example 1 is an integrated circuit transistor structure comprising: a body including a first semiconductor material having a first bandgap; a gate structure at least above the body, the gate structure including a gate dielectric and a gate electrode between the body and the gate electrode; a source region and a drain region between the body; and a spacer between the body and one of the source or drain regions, the spacer extending below one or both of the gate electrode and the gate dielectric, the spacer including a second semiconductor material having a second bandgap larger than the first bandgap; wherein the second semiconductor material provides a conduction band offset (CBO) of 0.1 eV or higher relative to the first semiconductor material, and a valence band offset (VBO) relative to the first semiconductor material in the range of -0.05 eV to 0.05 eV.

[0078] Example 2 includes the subject matter of Example 1, wherein the spacer between the body and one of the source or drain regions is a first spacer, and the integrated circuit transistor structure further includes a second spacer between the body and the other of the source or drain regions, the second spacer extending beneath one or both of the gate electrode and the gate dielectric, the second spacer comprising a second semiconductor material.

[0079] Example 3 includes the subject of Example 1 or 2, wherein the spacer is undoped, and one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0080] Example 4 includes the subject of Example 1 or 2, wherein the spacers include those with a spacing of less than 1E18 cm. 3 The concentration of p-type impurities, and one of the source or drain regions includes a concentration exceeding 1E18 cm⁻¹. 3 The concentration of p-type impurities.

[0081] Example 5 includes the subject of Example 1 or 2, wherein the spacers include those with a spacing of less than 1E16 cm. 3 The concentration of p-type impurities, and one of the source or drain regions includes a concentration exceeding 1E18 cm⁻¹. 3 The concentration of p-type impurities.

[0082] Example 6 includes the subject of any of the previous examples, wherein said one of the source or drain regions includes a germanium concentration of more than 75 atomic percent.

[0083] Example 7 includes the subject of any of the preceding examples, wherein the source or drain region of said one includes a germanium concentration of more than 99 atomic percent.

[0084] Example 8 includes the subject of any of the previous examples, wherein said one of the source or drain regions includes silicon, germanium, and carbon.

[0085] Example 9 includes the subject of any of the previous examples, wherein, except that, one of the source or drain regions is compositionally identical to the spacer: one of the source or drain regions comprises a portion exceeding 1E18 cm 3 The concentration of p-type impurities, and said p-type impurities are either not included in the spacers or are present in 1E17 cm⁻¹. 3 The following concentrations are included in the spacer.

[0086] Example 10 includes the subject of any of the previous examples, wherein the CBO threshold is at least 180 millielectron volts (meV) and the VBO threshold is less than 10 meV.

[0087] Example 11 includes the subject of any of the previous examples, wherein the first semiconductor material is germanium, such that the body is a germanium body.

[0088] Example 12 includes the subject of any of the previous examples, wherein the body, gate structure, spacers, and source and drain regions are part of a p-type metal-oxide-semiconductor (PMOS) transistor.

[0089] Example 13 includes the subject of any of the previous examples, wherein the subject is undoped or lightly n-doped.

[0090] Example 14 includes the subject of any of the previous examples, wherein the spacers include silicon, germanium, and carbon.

[0091] Example 15 includes the subject of Example 14, wherein the spacer comprises approximately 10% to 16% silicon by atomic percentage, 80% to 90% germanium by atomic percentage, and 1% to 4% carbon by atomic percentage.

[0092] Example 16 is an integrated circuit transistor structure comprising: a body including a first semiconductor material having a first bandgap; a gate structure at least above the body, the gate structure including a gate dielectric and a gate electrode, the gate dielectric being between the body and the gate electrode; a source region and a drain region, the body being between the source region and the drain region; and a spacer between the body and one of the source region or the drain region, the spacer extending below one or both of the gate electrode and the gate dielectric, the spacer including a second semiconductor material having a second bandgap larger than the first bandgap; wherein the second semiconductor material provides a valence band offset (CBO) of 0.1 eV or higher relative to the first semiconductor material, and a conduction band offset (VBO) relative to the first semiconductor material in the range of -0.05 eV to 0.05 eV.

[0093] Example 17 includes the subject matter of Example 16, wherein the spacer between the body and one of the source or drain regions is a first spacer, and the integrated circuit transistor structure further includes a second spacer between the body and the other of the source or drain regions, the second spacer extending beneath one or both of the gate electrode and the gate dielectric, the second spacer comprising a second semiconductor material.

[0094] Example 18 includes the subject of Example 16 or 17, wherein the spacer is undoped, and one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of n-type impurities.

[0095] Example 19 includes the subject of Example 16 or 17, wherein the spacers comprise spaces smaller than 1E18 cm. 3 The concentration of n-type impurities, and one of the source or drain regions includes more than 1E18 cm⁻¹. 3 The concentration of n-type impurities.

[0096] Example 20 includes the subject of Example 16 or 17, wherein the spacers comprise spaces smaller than 1E16 cm. 3 The concentration of n-type impurities, and one of the source or drain regions includes more than 1E18 cm⁻¹. 3 The concentration of n-type impurities.

[0097] Example 21 includes the subject matter of Example 16 or 17, wherein one of the source or drain regions is a III-V semiconductor material or compound, and the first semiconductor material is different from the source and drain regions and is also a III-V semiconductor material or compound. In one such exemplary case, one of the source or drain regions includes at least two of indium (In), gallium (Ga), arsenic (As), and antimony (Sb), and the first semiconductor material is different from the source and drain regions and includes at least two of In, Ga, As, and Sb.

[0098] Example 22 includes the subject matter of Example 21, wherein one of the source or drain regions comprises an indium concentration of more than 50 atomic percent, and / or wherein the first semiconductor material comprises an indium concentration of more than 50 atomic percent.

[0099] Example 23 includes the subject matter of Example 21 or 22, wherein one of the source or drain regions further includes phosphorus.

[0100] Example 24 includes the subject matter of Example 21 or 22, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes In y Al 1-y As, where 0.51≤x≤0.55 and y≥0.6.

[0101] Example 25 includes the subject matter of Example 21 or 22, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes InAs. y P 1-y , where 0.51≤x≤0.55 and y≥0.1.

[0102] Example 26 includes the subject matter of Example 21 or 22, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes In y Ga 1-y As z P 1-z , where 0.51≤x≤0.55, 0.25≤y≤1.00, and 0.50≤z≤1.00.

[0103] Example 27 includes the subject matter of Example 21 or 22, wherein the first semiconductor material comprises InAs, and one of the source or drain regions comprises GaSb.

[0104] Example 28 includes the subject of Example 27, wherein the spacer and body provide a gap heterostructure, wherein one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0105] Example 29 includes the subject matter of Example 21 or 22, wherein the first semiconductor material comprises InAs, and one of the source or drain regions comprises Ga. x Al 1-x Sb, where 0.01≤x≤0.20.

[0106] Example 30 includes the subject of Example 29, wherein the spacer and body provide a gap heterostructure, wherein one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0107] Example 31 includes the subject matter of Example 21 or 22, wherein the first semiconductor material comprises InAs, and one of the source or drain regions comprises In... x Ga 1-x Sb, where 0.25≤x≤1.00.

[0108] Example 32 includes the subject of Example 31, wherein the spacer and body provide a gap heterostructure, wherein one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0109] Example 33 includes the subject matter of Example 21 or 22, wherein the first semiconductor material comprises GaSb, and one of the source or drain regions comprises In. x Ga 1-x P y Sb 1-y , where 0.25≤x≤1.00 and 0.00≤y≤0.10.

[0110] Example 34 includes the subject of Example 33, wherein the spacer and body provide a gap heterostructure, wherein one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0111] Example 35 includes the subject of any one of Examples 16 to 34, wherein the CBO threshold is at least 180 millielectron volts (meV) and the VBO threshold is less than 10 meV.

[0112] Example 36 includes the subject matter of any one of Examples 16 to 35, wherein the body, gate structure, spacer, and source and drain regions are part of an n-type metal-oxide-semiconductor (NMOS) transistor.

[0113] Example 37 includes the subject of any one of Examples 16 to 36, wherein the subject is undoped or lightly p-doped.

[0114] Example 38 includes the subject matter of any one of Examples 16 to 37, wherein the spacer comprises a group III-V semiconductor material or compound. In some such exemplary cases, the spacer comprises at least two of indium (In), gallium (Ga), arsenic (As), and antimony (Sb).

[0115] Example 39 includes the subject matter of Example 38, wherein, except that, one of the source or drain regions is compositionally identical to the spacer: the one of the source or drain regions comprises a length exceeding 1E18 cm 3 The concentration of impurities, and said impurities are either not included in said spacers or are present in 1E17cm. 3 The following concentrations are included in the spacer.

[0116] Example 40 includes the subject of Example 38, wherein one of the source or drain regions is compositionally different from the spacer in terms of any difference in impurity doping and beyond such difference.

[0117] Example 41 includes the subject of any one of Examples 16 to 20 and 35 to 37, wherein one of the source or drain regions is silicon or silicon and germanium, and the first semiconductor material is germanium.

[0118] Example 42 includes the subject matter of Example 41, wherein, except that, one of the source or drain regions is compositionally identical to the spacer: one of the source or drain regions comprises a portion exceeding 1E18 cm 3 The concentration of impurities, and said impurities are either not included in said spacers or are present in 1E17cm. 3 The following concentrations are included in the spacer.

[0119] Example 43 is a method of forming an integrated circuit transistor structure, comprising: providing a body comprising a first semiconductor material having a first bandgap; providing a gate structure at least above the body, the gate structure comprising a gate dielectric and a gate electrode, the gate dielectric being between the body and the gate electrode; providing a source region and a drain region, the body being between the source region and the drain region; and providing a spacer between the body and one of the source region or the drain region, the spacer extending below one or both of the gate electrode and the gate dielectric, the spacer comprising a second semiconductor material having a second bandgap larger than the first bandgap; wherein the second semiconductor material provides a conduction band offset (CBO) of 0.1 eV or higher relative to the first semiconductor material, and a valence band offset (VBO) relative to the first semiconductor material in the range of -0.05 eV to 0.05 eV.

[0120] Example 44 includes the subject matter of Example 43, wherein the spacer between the body and one of the source or drain regions is a first spacer, and the method further includes providing a second spacer between the body and the other of the source or drain regions, the second spacer extending beneath one or both of the gate electrode and the gate dielectric, the second spacer comprising a second semiconductor material.

[0121] Example 45 includes the subject of Example 43 or 44, wherein the spacer is undoped, and one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0122] Example 46 includes the subject of Example 43 or 44, wherein the spacers include those with a spacing of less than 1E18 cm. 3 The concentration of p-type impurities, and one of the source or drain regions includes a concentration exceeding 1E18 cm⁻¹. 3 The concentration of p-type impurities.

[0123] Example 47 includes the subject of Example 43 or 44, wherein the spacers include those with a spacing of less than 1E16 cm. 3 The concentration of p-type impurities, and one of the source or drain regions includes a concentration exceeding 1E18 cm⁻¹. 3 The concentration of p-type impurities.

[0124] Example 48 includes the subject of any one of Examples 43 to 47, wherein said one of the source or drain regions includes a germanium concentration of more than 75 atomic percent.

[0125] Example 49 includes the subject of any one of Examples 43 to 48, wherein one of the source or drain regions comprises a germanium concentration of more than 99 atomic percent.

[0126] Example 50 includes the subject of any one of Examples 43 to 49, wherein one of the source or drain regions comprises silicon, germanium, and carbon.

[0127] Example 51 includes the subject of any one of Examples 43 to 50, wherein, except that, one of the source or drain regions is compositionally identical to the spacer: the one of the source or drain regions comprises a portion exceeding 1E18 cm 3 The concentration of p-type impurities, and said p-type impurities are either not included in the spacers or are present in 1E17 cm⁻¹. 3 The following concentrations are included in the spacer.

[0128] Example 52 includes the subject of any one of Examples 43 to 51, wherein the CBO threshold is at least 180 millielectron volts (meV) and the VBO threshold is less than 10 meV.

[0129] Example 53 includes the subject matter of any one of Examples 43 to 52, wherein the first semiconductor material is germanium, such that the body is a germanium body.

[0130] Example 54 includes the subject of any one of Examples 43 to 53, wherein the body, gate structure, spacer, and source and drain regions are part of a p-type metal-oxide-semiconductor (PMOS) transistor.

[0131] Example 55 includes the subject of Example 54, wherein the subject is undoped or lightly n-doped.

[0132] Example 56 includes the subject of any one of Examples 43 to 55, wherein the spacers include silicon, germanium, and carbon.

[0133] Example 57 includes the subject of Example 56, wherein the spacer comprises approximately 10% to 16% silicon by atomic percentage, 80% to 90% germanium by atomic percentage, and 1% to 4% carbon by atomic percentage.

[0134] Example 58 is a method of forming an integrated circuit transistor structure, comprising: a body including a first semiconductor material having a first bandgap; a gate structure at least above the body, the gate structure including a gate dielectric and a gate electrode, the gate dielectric being between the body and the gate electrode; a source region and a drain region, the body being between the source region and the drain region; and a spacer between the body and one of the source region or the drain region, the spacer extending below one or both of the gate electrode and the gate dielectric, the spacer including a second semiconductor material having a second bandgap larger than the first bandgap; wherein the second semiconductor material provides a valence band offset (CBO) of 0.1 eV or higher relative to the first semiconductor material, and a conduction band offset (VBO) relative to the first semiconductor material in the range of -0.05 eV to 0.05 eV.

[0135] Example 59 includes the subject matter of Example 58, wherein the spacer between the body and one of the source or drain regions is a first spacer, and the method further includes a second spacer between the body and the other of the source or drain regions, the second spacer extending beneath one or both of the gate electrode and the gate dielectric, the second spacer comprising a second semiconductor material.

[0136] Example 60 includes the subject of Example 58 or 59, wherein the spacer is undoped, and one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of n-type impurities.

[0137] Example 61 includes the subject of Example 58 or 59, wherein the spacers include those with a spacing of less than 1E18 cm. 3 The concentration of n-type impurities, and one of the source or drain regions includes more than 1E18 cm⁻¹. 3 The concentration of n-type impurities.

[0138] Example 62 includes the subject of Example 58 or 59, wherein the spacers include those with a spacing of less than 1E16 cm. 3 The concentration of n-type impurities, and one of the source or drain regions includes more than 1E18 cm⁻¹. 3 The concentration of n-type impurities.

[0139] Example 63 includes the subject matter of any one of Examples 58 to 62, wherein one of the source or drain regions is a group III-V semiconductor material or compound, and the first semiconductor material is different from the source and drain regions and is also a group III-V semiconductor material or compound. In one such exemplary case, one of the source or drain regions includes at least two of indium (In), gallium (Ga), arsenic (As), and antimony (Sb), and the first semiconductor material is different from the source and drain regions and includes at least two of In, Ga, As, and Sb.

[0140] Example 64 includes the subject matter of Example 63, wherein one of the source or drain regions comprises an indium concentration of more than 50 atomic percent, and / or wherein the first semiconductor material comprises an indium concentration of more than 50 atomic percent.

[0141] Example 65 includes the subject matter of Example 63 or 64, wherein one of the source or drain regions further includes phosphorus.

[0142] Example 66 includes the subject matter of Example 63 or 64, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes In y Al 1-y As, where 0.51≤x≤0.55 and y≥0.6.

[0143] Example 67 includes the subject matter of Example 63 or 64, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes InAs. y P 1-y , where 0.51≤x≤0.55 and y≥0.1.

[0144] Example 68 includes the subject matter of Example 63 or 64, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes In y Ga 1-y As z P 1-z , where 0.51≤x≤0.55, 0.25≤y≤1.00, and 0.50≤z≤1.00.

[0145] Example 69 includes the subject matter of Example 63 or 64, wherein the first semiconductor material comprises InAs, and one of the source or drain regions comprises GaSb.

[0146] Example 70 includes the subject of Example 69, wherein the spacer and body provide a gap heterostructure, wherein one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0147] Example 71 includes the subject matter of Example 63 or 64, wherein the first semiconductor material comprises InAs, and one of the source or drain regions comprises Ga. x Al 1-x Sb, where 0.01≤x≤0.20.

[0148] Example 72 includes the subject of Example 71, wherein the spacer and body provide a gap heterostructure, wherein one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0149] Example 73 includes the subject matter of Example 63 or 64, wherein the first semiconductor material comprises InAs, and one of the source or drain regions comprises In... x Ga 1-x Sb, where 0.25≤x≤1.00.

[0150] Example 74 includes the subject of Example 73, wherein the spacer and body provide a gap heterostructure, wherein one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0151] Example 75 includes the subject matter of Example 63 or 64, wherein the first semiconductor material comprises GaSb, and one of the source or drain regions comprises In. x Ga 1-x P y Sb 1-y , where 0.25≤x≤1.00 and 0.00≤y≤0.10.

[0152] Example 76 includes the subject of Example 75, wherein the spacer and body provide a gap heterostructure, wherein one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0153] Example 77 includes the subject of any one of Examples 58 to 76, wherein the CBO threshold is at least 180 millielectron volts (meV) and the VBO threshold is less than 10 meV.

[0154] Example 78 includes the subject of any one of Examples 58 to 77, wherein the body, gate structure, spacer, and source and drain regions are part of an n-type metal-oxide-semiconductor (NMOS) transistor.

[0155] Example 79 includes the subject of any one of Examples 58 to 78, wherein the subject is undoped or lightly p-doped.

[0156] Example 80 includes the subject of any one of Examples 58 to 79, wherein the spacer includes at least two of indium (In), gallium (Ga), arsenic (As), and antimony (Sb).

[0157] Example 81 includes the subject matter of Example 80, wherein, except that, one of the source or drain regions is compositionally identical to the spacer: the one of the source or drain regions comprises a length exceeding 1E18 cm 3 The concentration of impurities, and said impurities are either not included in said spacers or are present in 1E17cm. 3 The following concentrations are included in the spacer.

[0158] Example 82 includes the subject of Example 80, wherein the one of the source or drain regions is compositionally different from the spacer in terms of any difference in impurity doping and beyond the difference.

[0159] Example 83 includes the subject of any one of Examples 58 to 62 and 77 to 79, wherein one of the source or drain regions is silicon or silicon and germanium, and the first semiconductor material is germanium.

[0160] Example 84 includes the subject matter of Example 83, wherein, except that, one of the source or drain regions is compositionally identical to the spacer: one of the source or drain regions comprises a portion exceeding 1E18 cm 3 The concentration of impurities, and said impurities are either not included in said spacers or are present in 1E17cm. 3 The following concentrations are included in the spacer.

[0161] Example 85 is an integrated circuit transistor structure comprising: a germanium body; a gate structure at least above the germanium body, the gate structure including a gate dielectric and a gate electrode, the gate dielectric being between the germanium body and the gate electrode and in direct contact with the germanium body; a source region and a drain region, the germanium body being between the source region and the drain region; and a spacer between the germanium body and one of the source region or the drain region, the spacer extending below one or both of the gate electrode and the gate dielectric, the spacer comprising silicon, germanium, and carbon.

[0162] Example 86 includes the subject of Example 85, wherein the spacer is undoped, and one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

[0163] Example 87 includes the subject of Example 85 or 86, wherein one of the source or drain regions comprises a germanium concentration of more than 75 atomic percent.

[0164] Example 88 includes the subject of any one of Examples 85 to 87, wherein one of the source or drain regions comprises a germanium concentration of more than 98 atomic percent.

[0165] Example 89 includes the subject of any one of Examples 85 to 88, wherein said one of the source or drain regions includes a germanium concentration of more than 99 atomic percent.

[0166] Example 90 includes the subject of any one of Examples 85 to 89, wherein one of the source or drain regions comprises silicon, germanium, and carbon.

[0167] Example 91 includes the subject of any one of Examples 85 to 90, wherein, except that, one of the source or drain regions is compositionally identical to the spacer: the one of the source or drain regions comprises a portion exceeding 1E18 cm 3 The concentration of p-type impurities, and said p-type impurities are either not included in the spacers or are present in 1E17 cm⁻¹. 3 The following concentrations are included in the spacer.

[0168] Example 92 includes the subject matter of any one of Examples 85 to 91, wherein the spacer and one of the source or drain regions comprise substantially equal concentrations of silicon, germanium, and carbon. For example, in some such embodiments, concentrations within 10 percent of the target concentration are considered substantially equal, while in other embodiments, concentrations within 5 percent of the target concentration are considered substantially equal, while in other embodiments, concentrations within 2.5 percent of the target concentration are considered substantially equal, and in other embodiments, concentrations within 1 percent of the target concentration are considered substantially equal. In still other embodiments, concentrations within 5 atomic percent of each other are considered substantially equal, or concentrations within 2.5 atomic percent of each other are considered substantially equal, or concentrations within 1 atomic percent of each other are considered substantially equal. As will be appreciated, the greater the target concentration, the greater the variation in atomic percentage from that target concentration can be while still maintaining substantially equal conditions. For example, if the target atomic percentage for a given component is relatively small (such as 4 atomic percentages), then the atomic percentages will be in the range of approximately 2 to 3 atomic percentages, or 5 to 6 atomic percentages (a variation of approximately 1 to 2 atomic percentages from the target concentration). In another exemplary case, if the target atomic percentage for a given component is relatively large (such as 50 atomic percentages), then the atomic percentages will be in the range of approximately 45 to 49 atomic percentages, or 51 to 55 atomic percentages (a variation of approximately 1 to 5 atomic percentages from the target concentration). In a more general sense, the concentration can be varied while still maintaining the desired equal range from one embodiment to the next (within a given range acceptable for a given application), as will be appreciated in light of this disclosure.

[0169] Example 93 includes the subject of any one of Examples 85 to 92, wherein each of the source or drain regions and the spacer comprises approximately 10% to 16% silicon by atomic percentage, 80% to 90% germanium by atomic percentage, and 1% to 4% carbon by atomic percentage.

[0170] Example 94 includes the subject of any one of Examples 85 to 93, wherein the integrated circuit transistor structure is a PMOS transistor structure.

[0171] Example 95 is an integrated circuit transistor structure comprising: a germanium body; a gate structure at least above the germanium body, the gate structure including a gate dielectric and a gate electrode, the gate dielectric being between the germanium body and the gate electrode and in direct contact with the germanium body; a source region and a drain region, the germanium body being between the source region and the drain region, the source region and the drain region comprising at least one of silicon and germanium and having a silicon concentration of 80 atomic percent or more; and a spacer between the germanium body and one of the source region or the drain region, the spacer extending below one or both of the gate electrode and the gate dielectric, the spacer being silicon or silicon-germanium having a silicon concentration of 80 atomic percent or more.

[0172] Example 96 includes the subject matter of Example 95, wherein the spacer is undoped, and one of the source or drain regions is doped with a dopant exceeding 1E18 cm⁻¹. 3 The concentration of n-type impurities.

[0173] Example 97 includes the subject of Example 95 or 96, wherein one of the source or drain regions comprises a silicon concentration of more than 95 atomic percentages.

[0174] Example 98 includes the subject of any one of Examples 95 to 97, wherein said one of the source or drain regions includes a silicon concentration of more than 98 atomic percentages.

[0175] Example 99 includes the subject of any one of Examples 95 to 98, wherein said one of the source or drain regions comprises a silicon concentration of more than 99 atomic percentages.

[0176] Example 100 includes the subject of any one of Examples 95 to 99, wherein one of the source or drain regions comprises silicon and germanium.

[0177] Example 101 includes the subject of any one of Examples 95 to 100, wherein, except that, one of the source or drain regions is compositionally identical to the spacer, the other being: the one of the source or drain regions is doped with a concentration exceeding 1E18 cm⁻¹. 3 The concentration of n-type impurities is specified, and the spacers are either undoped or doped with a concentration of at least 1E17 cm⁻¹. 3 The following concentrations of n-type impurities.

[0178] Example 102 includes the subject of any one of Examples 95 to 101, wherein the spacer and one of the source or drain regions comprises at least one of silicon and germanium in substantially equal concentrations.

[0179] Example 103 includes the subject of any one of Examples 95 to 102, wherein each of the source or drain regions and the spacer comprises approximately 10% to 20% germanium by atomic percentage and 80% to 90% germanium by atomic percentage.

[0180] The terms and expressions used herein are descriptive and non-limiting, and their use is not intended to exclude any equivalents (or portions thereof) of the features shown and described, and it is recognized that various modifications are possible within the scope of the claims. Therefore, the claims are intended to cover all such equivalents. Various features, aspects, and embodiments have been described herein. These features, aspects, and embodiments are readily combined with each other and are susceptible to variations and modifications, as will be understood by those skilled in the art. Therefore, this disclosure should be considered to cover such combinations, variations, and modifications. It is intended that the scope of this disclosure is not limited to the detailed description herein, but rather rather precisely by the claims appended herein. Future applications claiming priority to this application may claim protection for the disclosed subject matter in different ways and may generally include any set of one or more elements as not disclosed herein or otherwise shown.

Claims

1. An integrated circuit transistor structure, comprising: The body comprises a first semiconductor material having a first band gap; A gate structure at least above the body, the gate structure including a gate dielectric and a gate electrode, the gate dielectric being between the body and the gate electrode; A source region and a drain region, wherein the body is located between the source region and the drain region; as well as A spacer between the body and one of the source or drain regions, the spacer extending beneath one or both of the gate electrode and the gate dielectric, the spacer comprising a second semiconductor material having a second bandgap larger than the first bandgap; The second semiconductor material provides a conduction band offset (CBO) of 0.1 eV or higher relative to the first semiconductor material, and a valence band offset (VBO) relative to the first semiconductor material in the range of -0.05 eV to 0.05 eV.

2. The integrated circuit transistor structure of claim 1, wherein the spacer is undoped, and one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of p-type impurities.

3. The integrated circuit transistor structure of claim 1, wherein one of the source or drain regions comprises a germanium concentration of more than 75 atomic percent.

4. The integrated circuit transistor structure according to claim 1, wherein one of the source region or drain region comprises silicon, germanium, and carbon.

5. The integrated circuit transistor structure of claim 1, wherein, except that one of the source or drain regions is compositionally identical to the spacer: the one of the source or drain regions comprises a portion exceeding 1E18 cm 3 The concentration of p-type impurities, and said p-type impurities are either not included in the spacers or are present in 1E17 cm⁻¹. 3 The following concentrations are included in the spacer.

6. The integrated circuit transistor structure according to claim 1, wherein the first semiconductor material is germanium, such that the body is a germanium body.

7. The integrated circuit transistor structure according to any one of claims 1 to 6, wherein the spacer comprises silicon, germanium, and carbon.

8. The integrated circuit transistor structure of claim 7, wherein the spacer comprises 10% to 16% silicon by atomic percentage, 80% to 90% germanium by atomic percentage, and 1% to 4% carbon by atomic percentage.

9. An integrated circuit transistor structure, comprising: The body comprises a first semiconductor material having a first band gap; A gate structure at least above the body, the gate structure including a gate dielectric and a gate electrode, the gate dielectric being between the body and the gate electrode; A source region and a drain region, wherein the body is located between the source region and the drain region; as well as A spacer between the body and one of the source or drain regions, the spacer extending beneath one or both of the gate electrode and the gate dielectric, the spacer comprising a second semiconductor material having a second bandgap larger than the first bandgap; The second semiconductor material provides a valence band offset (CBO) of 0.1 eV or higher relative to the first semiconductor material, and a conduction band offset (VBO) in the range of -0.05 eV to 0.05 eV relative to the first semiconductor material.

10. The integrated circuit transistor structure of claim 9, wherein the spacer is undoped, and one of the source or drain regions comprises a length exceeding 1E18 cm. 3 The concentration of n-type impurities.

11. The integrated circuit transistor structure of claim 9, wherein one of the source or drain regions comprises at least two of indium (In), gallium (Ga), arsenic (As), and antimony (Sb), and the first semiconductor material is different from the source and drain regions and comprises at least two of In, Ga, As, and Sb.

12. The integrated circuit transistor structure of claim 11, wherein one of the source or drain regions comprises an indium concentration of more than 50 atomic percent, and wherein the first semiconductor material comprises an indium concentration of more than 50 atomic percent.

13. The integrated circuit transistor structure of claim 11, wherein one of the source or drain regions further comprises phosphorus.

14. The integrated circuit transistor structure of claim 11, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes In y Al 1-y As, where 0.51≤x≤0.55 and y≥0.

6.

15. The integrated circuit transistor structure of claim 11, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes InAs. y P 1-y , where 0.51≤x≤0.55 and y≥0.

1.

16. The integrated circuit transistor structure of claim 11, wherein the first semiconductor material comprises In x Ga 1-x As, and one of the source or drain regions includes In y Ga 1-y As z P 1-z , where 0.51≤x≤0.55, 0.25≤y≤1.00, and 0.50≤z≤1.

00.

17. The integrated circuit transistor structure of claim 11, wherein the first semiconductor material comprises InAs, and one of the source region or drain region comprises GaSb.

18. The integrated circuit transistor structure of claim 11, wherein the first semiconductor material comprises InAs, and one of the source or drain regions comprises Ga. x Al 1-x Sb, where 0.01≤x≤0.

20.

19. The integrated circuit transistor structure of claim 11, wherein the first semiconductor material comprises InAs, and one of the source or drain regions comprises In... x Ga 1-x Sb, where 0.25≤x≤1.

00.

20. The integrated circuit transistor structure of claim 11, wherein the first semiconductor material comprises GaSb, and one of the source or drain regions comprises In. x Ga 1-x P y Sb 1-y , where 0.25≤x≤1.00 and 0.00≤y≤0.

10.

21. The integrated circuit transistor structure according to any one of claims 9 to 20, wherein the spacer comprises at least two of indium (In), gallium (Ga), arsenic (As), and antimony (Sb).

22. The integrated circuit transistor structure of claim 21, wherein, except that one of the source or drain regions is compositionally identical to the spacer, the one of the source or drain regions comprises a portion exceeding 1E18 cm 3 The concentration of impurities, and said impurities are either not included in said spacers or are present in 1E17cm. 3 The following concentrations are included in the spacer.

23. The integrated circuit transistor structure of claim 21, wherein one of the source or drain regions is compositionally different from the spacer, transcending any difference in impurity doping.

24. The integrated circuit transistor structure according to claim 9 or 10, wherein one of the source region or drain region is silicon or silicon and germanium, and the first semiconductor material is germanium.

25. The integrated circuit transistor structure of claim 24, wherein, except that one of the source or drain regions is compositionally identical to the spacer, the other being: the one of the source or drain regions comprises a portion exceeding 1E18 cm 3 The concentration of impurities, and said impurities are either not included in said spacers or are present in 1E17cm. 3 The following concentrations are included in the spacer.

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