Apparatus for manufacturing semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor processing device includes: a chamber housing; an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer; an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring; and a ring voltage source configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform includes a positive voltage applied during a first period and a negative voltage applied during a second period, and wherein the magnitude of the negative voltage increases during the second period.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2018-0130882 filed on October 30, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to an apparatus for manufacturing a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] Semiconductor devices can be manufactured by various semiconductor processes. A chamber for performing a semiconductor process may include a chamber in which plasma is forcibly generated. As an example, an etching process may be performed to remove a portion of a wafer or some layers disposed on a wafer. When a semiconductor process using plasma is performed, free radicals and ions may be formed in the chamber. The free radicals and ions may be formed by bias power supplied to the chamber. Summary of the invention

[0005] An aspect of the inventive concept provides a semiconductor processing apparatus in which a semiconductor manufacturing process using plasma is performed and a plasma sheath is controlled to efficiently perform the semiconductor manufacturing process, and a method of manufacturing a semiconductor device.

[0006] According to one aspect of the inventive concept, a semiconductor processing device includes: a chamber housing; an electrostatic chuck disposed in the chamber housing, the electrostatic chuck being configured to hold a semiconductor wafer; an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring; and a ring voltage source configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each period of the non-sinusoidal periodic waveform includes a positive voltage applied during a first time period and a negative voltage applied during a second time period, and wherein the magnitude of the negative voltage increases during the second time period.

[0007] According to one aspect of the inventive concept, an apparatus for manufacturing a semiconductor device includes: a first bias electrode connected to a lower portion of an electrostatic chuck, the electrostatic chuck being configured to accommodate a semiconductor wafer, the first bias electrode being configured to receive a first bias power having a pulse signal; a second bias electrode disposed above the electrostatic chuck, the second bias electrode being configured to receive a second bias power; and an edge ring surrounding the electrostatic chuck, the edge ring being configured to receive a ring voltage synchronized with at least one of the first bias power and the second bias power, wherein a cycle of the ring voltage is divided into a first period, a second period, and a third period, and wherein the ring voltage has a constant positive voltage during the first period, and has a gradually increasing negative voltage during the second period.

[0008] According to one aspect of the inventive concept, an apparatus for manufacturing a semiconductor device includes: a bias power supply configured to supply bias power to an electrode in a semiconductor process chamber; a chuck voltage source configured to supply an electrostatic chuck voltage to an electrostatic chuck disposed in the semiconductor process chamber, the electrostatic chuck being configured to hold a semiconductor wafer; and a ring voltage source configured to supply a ring voltage to an edge ring surrounding the electrostatic chuck to control a thickness of a plasma sheath region, the ring voltage having a constant positive voltage during a first period of the ring voltage and having a gradually increasing negative voltage during a second period of the ring voltage.

[0009] According to one aspect of the inventive concept, a method for manufacturing a semiconductor device includes: placing a semiconductor wafer on an electrostatic chuck; inputting a first bias power as a pulse signal to a first bias electrode disposed above the electrostatic chuck; and inputting a second bias power to a second bias electrode connected to a lower portion of the electrostatic chuck, wherein a combination of the first bias power and the second bias power accelerates plasma particles toward the semiconductor wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0011] Figure 1 and Figure 2 An apparatus for manufacturing a semiconductor device according to an example embodiment of the inventive concept is shown;

[0012] Figure 3 yes Figure 2 Enlarged view of area A in the middle;

[0013] Figure 4 and Figure 5 An edge ring included in a semiconductor process chamber according to an example embodiment of the inventive concept is shown;

[0014] Figure 6 and Figure 7 The operation of a semiconductor process chamber according to an example embodiment of the inventive concept is shown;

[0015] Figure 8 and Fig. 9 is a graph illustrating the operation of a semiconductor process chamber according to an example embodiment of the inventive concept;

[0016] Fig.10 A semiconductor process chamber according to an example embodiment of the inventive concept is shown;

[0017] Fig.11A , Fig. 11B , Fig. 12Aand Fig. 12B are graphs respectively showing bias power and ring voltage input to a semiconductor process chamber; and

[0018] Figures 13 to 15 Operations of a semiconductor process chamber according to example embodiments of the inventive concepts are illustrated. DETAILED DESCRIPTION

[0019] Hereinafter, example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0020] Figure 1 and Figure 2 An apparatus including a semiconductor process chamber according to example embodiments of the inventive concepts is illustrated.

[0021] Reference Figure 1 , the plasma processing apparatus 10 according to the example embodiment may include a chamber housing 11, a gas supply unit 12, a bias power supply unit 13, a chuck voltage supply unit 14, a ring voltage supply unit 15, and a control device 16. For example, the gas supply unit 12 may be a gas source, the bias power supply unit 13 may be a bias power supply, the chuck voltage supply unit 14 may be a chuck voltage source, the ring voltage supply unit 15 may be a ring voltage source, and the control device 16 may be a controller. The chamber housing 11 may provide a space for performing a semiconductor process. For example, a process for manufacturing a semiconductor device may be performed in a chamber surrounded by the chamber housing 11. For example, the semiconductor process may be a process for manufacturing a semiconductor device. The gas supply unit 12, the bias power supply unit 13, the chuck voltage supply unit 14, the ring voltage supply unit 15, etc. may be disposed on the chamber housing 11.

[0022] The gas supply unit 12 can supply gas for performing a semiconductor process in a process chamber surrounded by the chamber housing 11, and the type of gas supplied to the process chamber can vary according to the type of semiconductor process. The bias power supply unit 13 is a circuit configured to supply bias power for performing a semiconductor process. In some embodiments, a plurality of bias power supply units 13 may be included in the device 10. As an example, a plurality of bias power supply units 13 may be respectively arranged at the upper and lower portions of the chamber housing 11. For example, a plurality of bias power supply units 13 may be respectively connected to the upper and lower portions of the chamber. In the case where the semiconductor process uses plasma, the gas supply unit 12 may supply hydrogen or an inert gas into the chamber, and hydrogen ions, free radicals, etc. (e.g., hydrogen plasma and / or inert gas plasma) may be formed by the bias power supplied by the bias power supply unit 13.

[0023] The chuck voltage supply unit 14 may input a chuck voltage to an electrostatic chuck (ECS) on which a semiconductor wafer, a mother substrate for a display, etc. as an object of a semiconductor process may be placed. Coulomb force is generated by the chuck voltage, and the semiconductor wafer, the mother substrate for a display, etc. may be fixed to the electrostatic chuck by the Coulomb force.

[0024] In the plasma processing apparatus 10 according to the example embodiment, an edge ring may be provided around the electrostatic chuck. For example, in a plan view, the edge ring may be separated from the electrostatic chuck by a predetermined distance to surround the side surface of the electrostatic chuck. The ring voltage supply unit 15 may supply a predetermined ring voltage to an electrode in the edge ring. The sheath region above the edge ring may have a thickness adjusted by the ring voltage.

[0025] The control device 16 can control the gas supply unit 12, the bias power supply unit 13, the chuck voltage supply unit 14, the ring voltage supply unit 15, etc. to perform a semiconductor manufacturing process in the chamber housing 11. As an example, the control device 16 can determine the flow rate of the gas supplied by the gas supply unit 12, the bias power applied to the chamber, the chuck voltage input to the electrostatic chuck, the ring voltage input to the edge ring, etc. In an example embodiment, the control device 16 can input ring voltages of various waveforms as well as simple pulse waves, sine waves, or DC voltages to the edge ring to prevent / reduce degradation of the field distribution (which varies according to the consumption of the edge ring) and to improve process efficiency by alleviating the charge accumulated on the edge ring. For example, the control device 16 can be a controller connected to the ring voltage supply unit 15. The ring voltage supply unit 15 can be a power supply that generates multiple DC power levels. For example, the controller 16 can control the multiple DC power levels generated by the ring voltage source 15 to output a series of electrical signals, such as Figure 8 , Fig. 9 , Fig. 11B and Fig. 12B As shown. For example, the controller 16 can send a control signal to the ring voltage source 15 to selectively output a series of electrical signals having a plurality of partitions, the plurality of partitions having corresponding voltage levels. Each corresponding voltage can be generated by selecting one of a plurality of DC power levels or a combination of DC power levels. For example, the ring voltage source 15 can include a switch and / or a modulator to select and / or combine DC power levels. For example, the ring voltage source 15 can include a positive DC power generator and a negative DC power generator.

[0026] refer to Figure 2The semiconductor processing apparatus 100 according to example embodiments may be an apparatus for performing a semiconductor process using plasma. The semiconductor processing apparatus 100 may include a chamber 110, a ring voltage supply unit 120, a chuck voltage supply unit 130, a first bias power supply unit 140, a second bias power supply unit 150, a gas supply unit 160, etc. For example, the semiconductor processing apparatus 100 may be Figure 1 The present invention provides an example of a semiconductor processing device 10 of the present invention, and some elements of the device 10 are not shown in the device 100, and vice versa. The bias power described in the present disclosure may be a corresponding bias voltage. For example, the first bias power and the second bias power may have a corresponding bias voltage. The ring voltage source 15 may be configured to supply voltages of different waveforms to the edge ring, and the waveform may be determined according to the bias voltage applied to the first bias electrode.

[0027] The chamber 110 may include an edge ring 111, an electrostatic chuck 112, a first bias electrode 113, a second bias electrode 114, a gas flow path 115, etc., which are disposed in the housing 101. A process object to be subjected to a semiconductor process may be placed on the electrostatic chuck 112. As an example, the process object may be a semiconductor wafer W. As an example, a plurality of protrusions 112A each having a pin shape and / or a round top may be provided on the top surface of the electrostatic chuck 112. The semiconductor wafer W may be placed on the protrusions 112A, and there may be a space between the top surface of the electrostatic chuck 112 and the bottom surface of the semiconductor wafer W. As an example, the space between the top surface of the electrostatic chuck 112 and the bottom surface of the semiconductor wafer W may be filled with helium or the like to cool the semiconductor wafer W. In some embodiments, the top surface of the electrostatic chuck 112 may be flat, and the semiconductor wafer W may contact the top surface of the electrostatic chuck 112. For example, the contact area of ​​the bottom surface of the semiconductor wafer W may be greater than half of the entire area of ​​the bottom surface of the semiconductor wafer W. In some embodiments, the cooling gas (eg, helium) may contact the bottom surface of the semiconductor wafer W. In a certain embodiment, the cooling gas may flow along a hole formed in the electrostatic chuck. In this case, the cooling gas may not contact the semiconductor wafer W.

[0028] In example embodiments, the semiconductor wafer W may be fixed to the top surface of the electrostatic chuck 112 by a Coulomb force generated by a chuck voltage supplied to the electrostatic chuck 112 by the chuck voltage supply unit 130. As an example, the chuck voltage supplied by the chuck voltage supply unit 130 may be a constant voltage, and the chuck voltage may have a magnitude of several hundred volts to several thousand volts.

[0029] A reaction gas may be introduced through the gas flow path to perform a semiconductor process. The first bias power supply unit 140 may supply a first bias power to a first bias electrode 113 disposed below the electrostatic chuck 112, and the second bias power supply unit 150 may supply a second bias power to a second bias electrode 114 disposed above the electrostatic chuck 112. Each of the first bias power supply unit 140 and the second bias power supply unit 150 may include a radio frequency (RF) power source configured to supply bias power.

[0030] Plasma 170 including ions 171, radicals 172, electrons 173, etc. may be generated by the reaction gas on the semiconductor wafer W (e.g., between the wafer and the second bias electrode 114) by the first bias power and the second bias power. The reaction gas may be converted into plasma 170 by the first bias power and the second bias power to increase reactivity. As an example, in the case where the semiconductor processing device 100 is an etching device, the ions 171, radicals 172, electrons 173, etc. of the plasma may be accelerated to the semiconductor wafer W by the first bias power, which is supplied to the first bias electrode 113 by the first bias power supply unit 140. At least some of the semiconductor substrate or layer included in the semiconductor wafer W may be etched by the ions 171, radicals 172, electrons 173, etc. of the plasma.

[0031] A self-bias voltage may be generated on the semiconductor wafer W by the first bias power supplied to the first bias electrode 113 and the second bias power supplied to the second bias electrode 114. In example embodiments, plasma 170 may be generated on the semiconductor wafer W by the self-bias voltage, and a plasma sheath region may be formed between the plasma 170 and the semiconductor wafer W.

[0032] The ions 171, radicals 172, electrons 173, etc. contained in the plasma 170 may be incident on the semiconductor wafer W through the plasma sheath region. The angle at which the ions 171, radicals 172, electrons 173, etc. are incident on the semiconductor wafer W may vary according to the thickness of the plasma sheath region, etc. As an example, the thickness of the plasma sheath region may increase or decrease from the center of the semiconductor wafer W toward the edge ring 111.

[0033] As an example, when the thickness of the plasma sheath region above the edge ring 111 is less than the thickness of the plasma sheath region above the semiconductor wafer W, the angle at which the ions 171, the radicals 172, the electrons 173, etc. are incident on the semiconductor wafer W may be distorted at a region adjacent to the boundary of the semiconductor wafer W. For example, the flow direction of particles (e.g., ions 171, radicals 172, and / or electrons 173) at an edge portion of the plasma 170 corresponding to the edge portion of the wafer W and / or corresponding to the edge ring 111 may not be parallel to the flow direction of particles at a center portion of the plasma 170 corresponding to the center of the wafer W. The angle at which the ions 171, the radicals 172, the electrons 173, etc. are incident on the semiconductor wafer W may not be in a direction at right angles to the top surface of the semiconductor wafer. For example, the particles of the plasma 170 may not be perpendicularly incident on the semiconductor wafer W at the edge portion. Therefore, the semiconductor process may not be effectively performed in the region adjacent to the boundary of the semiconductor wafer W. For example, when particles of plasma (eg, ions 171 , radicals 172 , and / or electrons 173 ) are vertically incident on the wafer W, an etching / deposition process may be performed more efficiently than when the plasma particles are incident on the wafer W at an oblique angle.

[0034] To address the above-mentioned problem, the ring voltage input to the edge ring 111 may be increased in such a manner that the thickness of the plasma sheath region increases over the edge ring 111. However, as the ring voltage increases, the edge ring 111 may be charged, and acceleration of ions 171, radicals 172, etc. toward the semiconductor wafer W may be reduced or prevented over the edge ring 111 and / or over the edge portion of the semiconductor wafer W.

[0035] In some examples, when the semiconductor process is an etching process, the edge ring 111 may also be etched from the upper portion of the edge ring 111 as the etching process is performed. Therefore, the thickness of the edge ring 111 may be reduced. In this case, the thickness of the plasma sheath region may also be reduced above the edge ring 111, and the angles at which the ions 171, radicals 172, electrons 173, etc. are incident on the semiconductor wafer W may be distorted. For example, the semiconductor process may not be accurately performed. When the magnitude of the voltage input to the edge ring is increased to compensate for the reduction in the thickness of the plasma sheath region caused by etching the edge ring 111, the above-mentioned problem (e.g., a charged edge ring) may occur.

[0036] In example embodiments, the above-mentioned problems may be solved by variously changing the voltage input to the edge ring 111. The ring voltage supply unit 120 may include a voltage generator configured to output voltages having various waveforms to electrodes included in the edge ring 111. As an example, the ring voltage supply unit 120 may supply a ring voltage having a predetermined period. The ring voltage may have a positive voltage in a first period and a negative voltage in a second period. In example embodiments, the ring voltage supply unit 120 may generate a negative voltage having a gradually increasing magnitude, for example, a ramp voltage having a gradually increasing absolute value and a negative sign, as the ring voltage in the second period, to adjust the thickness of the plasma sheath region above the edge ring 111 and improve the degradation of process efficiency, etc., caused by charging the edge ring 111.

[0037] The degree to which the edge ring 111 is charged may depend on the magnitude of the first bias power and the magnitude of the second bias power used to generate the plasma 170. In example embodiments, a change in the length of the second period included in the cycle of the ring voltage, a change in the magnitude of the ring voltage in the second period, etc. may be determined in consideration of at least one of the first bias power and the second bias power. For example, at least a portion of the change in the magnitude of the ring voltage may be greater than the first bias voltage. For example, an absolute value of at least a portion of the change in the magnitude of the ring voltage may be greater than an absolute value of the first bias voltage. Therefore, charging of the edge ring 111 may be effectively offset, and ions 171, etc. may be continuously accelerated toward the electrostatic chuck 112 to improve process efficiency.

[0038] In an example embodiment, each of the first bias power and the second bias power may be generated in the form of a pulse. As an example, the first bias power and the second bias power may be input to the first bias electrode 113 and the second bias electrode 114 after being synchronized with each other. For example, when the first bias power is input to the first bias electrode 113, the second bias power may also be input to the second bias electrode 114. When the first bias power is not input to the first bias electrode 113, the second bias power may also not be input to the second bias electrode 114.

[0039] When the first bias power and the second bias power are not input, when the ring voltage is input to the edge ring (regardless of the waveforms of the first bias power and the second bias power), the ions 171 may be concentrated on the edge ring 111. The ions 171 concentrated on the edge ring 111 may be discharged toward above the edge ring 111. Therefore, the edge ring 111 or a portion of the semiconductor wafer W adjacent to the edge ring 111 may be damaged, and / or the wear of the edge ring 111 may be accelerated by the discharge. The ions 171 concentrated on the edge ring 111 may distort the particle incident direction from above the edge ring 111 and / or above the edge portion of the wafer W. For example, the ions 171 concentrated on the edge ring 111 may deteriorate the quality of the plasma process.

[0040] In order to solve the above problem, in an example embodiment, at least one of the first bias power and the second bias power may be synchronized with the ring voltage. For example, when at least one of the first bias power and the second bias power is not input, the ring voltage may be generated so that the ions 171 are not input / incident to the edge ring 111. Therefore, the wear of the edge ring 111 and the damage of the semiconductor wafer W may be reduced to improve process efficiency and stability.

[0041] Figure 3 yes Figure 2 Magnified view of area A in the middle.

[0042] Reference Figure 3 , the semiconductor wafer W may be placed on the protrusion 112A formed on the top surface of the electrostatic chuck 112. Therefore, there may be a space between the bottom surface of the semiconductor wafer W and the top surface of the electrostatic chuck 112. Helium (He) may be introduced into the space to cool the semiconductor wafer W. Figure 3 In the illustrated embodiment, the plasma sheath region between the plasma and the semiconductor wafer W may be omitted. For example, the plasma sheath region may be formed between the plasma and the semiconductor wafer W.

[0043] The electrostatic chuck 112 may be disposed on the first bias electrode 113, and an electrode 112E to which an electrostatic chuck voltage is input may be disposed within the electrostatic chuck 112. For example, the electrostatic chuck 112 may contact the first through-hole electrode 113. For example, the electrostatic chuck 112 may include an electrode 112E and an insulating layer surrounding the electrode 112E. As an example, the electrostatic chuck voltage may be a direct current (DC) voltage or a pulse voltage. The edge ring 111 is disposed around the electrostatic chuck 112, and the ring electrode 111E may be embedded in the edge ring 111. As described above, the edge ring 111 may be formed of a dielectric material. For example, the edge ring 111 may include a ring electrode 111E and a dielectric material surrounding the ring electrode 111E.

[0044] In order to perform a semiconductor process, a plasma 170 may be generated above a semiconductor wafer W. Ions 171, radicals 172, charges 173, and the like contained in the plasma 170 may be accelerated to the semiconductor wafer W to perform a semiconductor process. A positive potential is formed above the edge ring 111, and when a negative voltage is input to a ring electrode 111E within the edge ring 111, the ions 171 may be accelerated to the edge ring 111. For example, the ions 171 may be incident on the edge ring 111, and the ions 171 may accumulate on the edge ring 111, so that the edge ring 111 may be positively charged. Therefore, even when a negative voltage is input to the ring electrode 111E, after the edge ring 111 is charged with the ions 171, the ions 171 may not be accelerated to the edge ring 111. For example, the ions 171 may be positive ions, such as Figure 2 and Figure 3 shown.

[0045] In an example embodiment, the ring voltage supply unit 120 may output various waveforms of ring voltages to the ring electrode 111E in such a manner that the ions 171 may be accelerated toward the edge ring 111 even when the edge ring 111 is positively charged. As an example, the ring voltage may have a waveform of a ramp voltage in which the absolute value of the ring voltage gradually increases during a period in which the ring voltage input to the ring electrode 111 has a negative voltage. Therefore, even when the edge ring 111 is positively charged, as the absolute value of the ring voltage gradually increases, the ions 171 may be incident toward the edge ring 111. For example, when a negative ring voltage is applied to the edge ring 111, the negative voltage may be gradually increased to compensate for the positive charge gradually accumulated on the edge ring 111, thereby maintaining a negative electric field toward the plasma sheath and / or plasma. For example, by sequentially increasing the negative ring voltage, negative ring voltages of different values ​​may be sequentially applied to the edge ring.

[0046] Figure 4 and Figure 5 An edge ring that may be included in a semiconductor process chamber according to example embodiments of the inventive concepts is illustrated.

[0047] Reference Figure 4 , an edge ring 111 according to an example embodiment may be disposed in a semiconductor process chamber to surround the periphery of a semiconductor wafer W. As an example, the edge ring 111 may be disposed around an electrostatic chuck on which the semiconductor wafer W is mounted, and may surround the periphery of the semiconductor wafer W. For example, the edge ring 111 may have a continuous single structure, such as Figure 4 shown.

[0048] The edge ring 111 may be formed of a dielectric material, and one or more electrodes may be embedded in the edge ring 111. A ring voltage supply unit of the semiconductor processing apparatus may input a predetermined ring voltage to the electrodes within the edge ring 111. In some embodiments, a ring voltage of a predetermined waveform such as a DC voltage, a sine wave, a pulse wave, etc. is input to the edge ring 111. In certain example embodiments, the ring voltage supply unit may generate a ring voltage of various waveforms different from the DC voltage, the sine wave, or the pulse wave, and input the ring voltage to the electrodes within the edge ring 111. When a plurality of electrodes are embedded in the edge ring 111, the plurality of electrodes may receive the ring voltage from the ring voltage supply unit together. For example, the plurality of electrodes embedded in the edge ring 111 may be electrically connected to each other.

[0049] Reference Figure 5 , the edge ring 111 may include a plurality of unit structures 111A to 111D separated from each other. Figure 5 In the illustrated embodiment, it is assumed that the edge ring 111 includes four unit structures 111A to 111D, but the number of the plurality of structures 111A to 111D may be variously changed.

[0050] Each of the plurality of unit structures 111A to 111D may be formed of a dielectric material and may include an electrode therein. The electrodes embedded in the plurality of unit structures 111A to 111D may receive the same ring voltage from the ring voltage supply unit. Therefore, a voltage of the same waveform may be input to the plurality of unit structures 111A to 111D separated from each other, and a semiconductor process may be uniformly performed on the semiconductor wafer W.

[0051] Plasma may be generated over the semiconductor wafer W while a semiconductor process is performed, and charges, ions, etc. may be accelerated to the semiconductor wafer W by voltages applied to the upper and lower portions of the semiconductor wafer W to perform an etching process, etc. However, a sheath region may exist over the edge ring 111 away from the center of the semiconductor wafer W, where the plasma potential is reduced.

[0052] Since a positive potential is generated above the edge ring 111, when a negative voltage is input to the electrode within the edge ring 111, the edge ring 111 itself may be charged. For example, the upper surface of the edge ring 111 may carry positive ions from the plasma formed above the edge ring 111. If the edge ring is charged, ions and the like may not be effectively accelerated above the edge ring 111 even when a negative voltage is input to the electrode within the edge ring 111. For example, the positive ions accumulated on the surface of the edge ring 111 may reduce the negative electric field from the electrode within the edge ring 111. Therefore, a semiconductor process may not be effectively performed in the edge region of the semiconductor wafer W.

[0053] In order to solve the above-mentioned problem, in the present inventive concept, a ramp voltage may be input to the edge ring 111 for a predetermined time. The ramp voltage may be a voltage with a negative sign whose absolute value increases. Therefore, even when the edge ring 111 itself is charged, ions with positive charge characteristics may be accelerated to the edge ring by the ramp voltage, and a semiconductor process may be effectively performed even in the edge region of the semiconductor wafer W. As an example, a ring voltage with a predetermined period may be input to the edge ring 111, and the ring voltage may have a waveform of the ramp voltage during a portion of the predetermined period.

[0054] Figure 6 and Figure 7 Operations of a semiconductor process chamber according to example embodiments of the inventive concepts are illustrated.

[0055] For example, Figure 6 is a graph showing the thickness distribution of the plasma sheath region in a semiconductor process chamber. Figure 6 , there may be a portion in which the thickness of the plasma sheath region in the semiconductor process chamber gradually decreases as the distance from the center of the semiconductor wafer becomes longer than a predetermined distance. As an example, the distance R from the center (at which the thickness of the plasma sheath region begins to decrease) may correspond to the radius of the semiconductor wafer. However, depending on the thickness of the edge ring, etc., the thickness of the plasma sheath region may increase at a position farther than the radius of the semiconductor wafer. When the magnitude of the ring voltage input to the edge ring increases, the distance R at which the thickness of the plasma sheath region decreases may increase at a position farther than the radius of the semiconductor wafer.

[0056] Reference Figure 7 , a plasma sheath region PS may be formed over the semiconductor wafer W and the edge ring 211 in the semiconductor process chamber 200. The semiconductor wafer W may be seated on a plurality of protrusions 212A disposed on the top surface of the electrostatic chuck 212, and a space between the semiconductor wafer W and the top surface of the electrostatic chuck 212 may be filled with helium or the like for cooling.

[0057] The plasma sheath region PS may have a first thickness D1 over the semiconductor wafer W and a second thickness D2 over the edge ring 211. As an example, the first thickness D1 and the second thickness D2 may be different from each other, and the second thickness D2 may vary according to the ring voltage input to the ring electrode 211E by the ring voltage supply unit 220, the thickness and height of the edge ring 211, etc. Figure 7 In the illustrated embodiment, the second thickness D2 may be smaller than the first thickness D1. Therefore, there may be a space in which the thickness of the plasma sheath region PS decreases as the distance from the center CW of the semiconductor wafer W becomes farther.

[0058] The ring voltage input to the edge ring 211 may have a positive voltage during a first period and a negative voltage during a second period. When the ring voltage increases, the second thickness D2 of the plasma sheath region PS may increase over the edge ring 211 to improve the process efficiency outside the semiconductor wafer W. For example, when the ring voltage increases, the electric field over the edge ring 211 and over the edge region of the wafer W may become parallel to the electric field formed over the center of the wafer W, and when the electric field is perpendicular to the top surface of the wafer W, the etching efficiency and / or quality of the plasma process may be improved. However, charging may easily occur only when the magnitude of the ring voltage increases (the edge ring 211 is positively charged during the second period in which the ring voltage has a negative voltage). For example, when a greater negative voltage is applied to the edge ring 211, the edge ring 211 may be positively charged with more positive ions 171. Therefore, the second thickness D2 of the plasma sheath region PS may not be adjusted over the edge ring 211, or the ions may not be accelerated by the ring voltage input to the edge ring, thereby reducing the process efficiency outside the semiconductor wafer W. For example, by reducing the effective voltage applied to the edge ring 211, the plasma process efficiency may be reduced due to the positive charges of the positive ions 171 accumulated on the top surface of the edge ring 211. As the ring voltage increases in magnitude, the second thickness D2 of the plasma sheath region PS may excessively increase, thereby reducing the process efficiency on the edge region of the semiconductor wafer W.

[0059] In order to solve the above problems, in an example embodiment, a ring voltage having various waveforms may be input to the edge ring 211 instead of simply increasing the size of the ring voltage. To this end, the ring voltage supply unit 220 may include a voltage generating circuit configured to supply a voltage, a modulator configured to determine a waveform, etc. For example, the modulator may transform the voltage generated from the voltage generating circuit into waveforms of different shapes.

[0060] Figure 8 and Fig. 9 is a graph illustrating operation of a semiconductor process chamber according to example embodiments of the inventive concepts.

[0061] refer to Figure 8, the ring voltage may have a first voltage VP (positive voltage) and a second voltage VN (negative voltage) during a single cycle. For example, the ring voltage may repeat a cycle including the first voltage VP and the second voltage VN multiple times (for example, when a plasma process is performed). When the ring voltage has the second voltage VN, the edge ring formed by the dielectric material may be charged by the positive potential generated above the edge ring, and the voltage of the edge ring may increase. For example, the edge ring may be positively charged by positive ions accumulated on the edge ring. Therefore, since the edge ring has a positive voltage even when the ring voltage has the second voltage VN, the ions may not be accelerated to the semiconductor wafer at the edge portion of the semiconductor wafer W. For example, the etching rate of the process may be reduced by the positive ions accumulated on the edge ring. In order to solve this problem, a voltage with a larger absolute value may be input to the edge ring. For example, a negative voltage stronger than the previous negative voltage may be applied to the edge ring to maintain the etching rate of the process when positive ions accumulate on the edge ring. However, when a strong negative voltage is applied to the edge ring, a slope of a plasma sheath region may increase in a region where the semiconductor wafer and the edge ring are adjacent to each other, and process efficiency may decrease due to the increased slope of the plasma sheath region.

[0062] Applying a deformed waveform to the edge ring electrode 211E may improve the process efficiency of the plasma chamber. Therefore, in example embodiments, voltages having various waveforms may be input to the edge ring rather than simply inputting a voltage having a larger absolute value to the edge ring. Fig. 9 In an example embodiment, the ring voltage may have a predetermined period TP. The period TP may be divided into a first period T1 and a second period T2. In the period TP, a ratio of the first period T1 and the second period T2 may vary according to an example embodiment. During the first period T1, the ring voltage may have a first voltage VP (positive voltage).

[0063] During the second time period T2 of the period TP, a ramp voltage that decreases from the first negative voltage VN1 to the second negative voltage VN2 may be input to the edge ring. During the second time period T2, the ring voltage may have a tendency of gradually increasing negative voltage over time, which also means that the ring voltage has a gradually increasing absolute value and negative sign. For example, the ring voltage source 220 may apply the first positive voltage VP to the edge ring electrode 211E during the first time period T1, and apply the first negative voltage VN1 to the edge ring electrode 211E at the start time of the second time period T2. The controller 16 may control the ring voltage source 220 to output a series of negative voltages of different levels (negative voltages of gradually / continuously increasing levels) during the second time period T2, so that the negative voltage level reaches the second negative voltage VN2 at the end of the second time period T2, as shown in FIG. Fig. 9 For example, the gradually / continuously increasing negative voltage level of the ring voltage may increase linearly, as Fig. 9 For example, three or more voltage levels may be applied to the edge ring electrode 211E during the second period T2. For example, the magnitude of the negative voltage may increase in arithmetic progression, such as Fig. 9 For example, a graph representing increasing negative voltage levels may have a substantially constant slope / gradient, such as Fig. 9 For example, the electrical signal applied to the edge ring electrode 211E may have a non-sinusoidal periodic waveform including a pulse portion (positive voltage pulse) and a trapezoidal portion, as shown in FIG. Fig. 9 For example, the difference between the first negative voltage VN1 and the second negative voltage VN2 may be about half of the first negative voltage VN1. For example, the difference between the first negative voltage VN1 and the second negative voltage VN2 may be between 25% and 70% of the magnitude of the first negative voltage VN1.

[0064] Since the ring voltage decreases from the first negative voltage VN1 to the second negative voltage VN2 in the second period T2, ions can be accelerated even when the edge ring is charged. As an example, the difference between the first negative voltage VN1 and the second negative voltage VN2 may be determined in consideration of a voltage corresponding to charges accumulated in the edge ring. Fig. 9 In the illustrated embodiment, in each second period T2 of each cycle TP, the difference between the first negative voltage VN1 and the second negative voltage VN2 is shown to be the same. However, in some embodiments, the difference between the first negative voltage VN1 and the second negative voltage VN2 may vary in each cycle TP. For example, at least one of the first negative voltage VN1 and the second negative voltage VN2 may be changed. In some embodiments, in the second period T2 of each cycle TP2, the downward trend / slope of the ring voltage may vary.

[0065] Fig.10 A semiconductor process chamber according to an example embodiment of the inventive concepts is illustrated.

[0066] Reference Fig.10 In the semiconductor process chamber 300 according to example embodiments, the chuck voltage supply unit 330 may input an electrostatic chuck voltage to the electrode 312E of the electrostatic chuck 312. A Coulomb force is generated between the electrostatic chuck 312 and the semiconductor wafer W by the electrostatic chuck voltage, and the semiconductor wafer W is fixed to the electrostatic chuck 312 by the Coulomb force.

[0067] The ring voltage supply unit 320 may input a ring voltage to an edge ring electrode 311E disposed in an edge ring 311 around the electrostatic chuck 312. The ring voltage is a voltage having a predetermined period, and the ring voltage supply unit 320 may input a ring voltage of various waveforms to the edge ring electrode 311E of the edge ring 311 when a plasma process is performed in a plasma chamber.

[0068] The first bias electrode 313 may be disposed below the electrostatic chuck 312. The first bias electrode 313 may be a pedestal and may be used as a bottom electrode to generate plasma. The first bias power supply unit 340 may input the first bias power to the first bias electrode 313. As an example, the first bias power supply unit 340 may input the first bias power to the first bias electrode 313 in the form of a pulse. For example, the first bias power supply unit 340 may repeatedly perform an operation to input and block the first bias power at a predetermined cycle.

[0069] For example, when the first bias power generated in the form of a pulse is blocked, the first bias power is not input to the first bias electrode 340, and ions contained in the plasma above the electrostatic chuck 312 may be concentrated on the edge ring 311 by the ring voltage input to the edge ring electrode 311E of the edge ring 311. The ions concentrated on the edge ring 311 may cause discharge above the edge ring 311, and may damage the edge ring 311 or a portion of the semiconductor wafer W adjacent to the edge ring 311.

[0070] In an exemplary embodiment, in order to solve the above problem, the ring voltage input to the edge ring electrode 311E of the edge ring 311 and the first bias power input to the first bias electrode 313 may be synchronized with each other. The synchronization of the first bias power and the ring voltage may be performed in various ways, which will be referred to below. Fig.11A , Fig. 11B , Fig. 12A and Fig. 12B Give a description.

[0071] Fig.11A , Fig. 11B , Fig. 12A and Fig. 12B is a graph showing bias power and ring voltage input to a semiconductor process chamber.

[0072] Reference Fig.11A , the first bias power may be input to the first bias electrode 313 in the form of pulses. Fig. 11B , the ring voltage input to the edge ring electrode 311E of the edge ring 311 may be synchronized with the first bias power. Fig. 11B As shown, the ring voltage may be a voltage having a predetermined period, and the period TP of the ring voltage may be the same as the period of the bias power.

[0073] The period TP of the ring voltage may be divided into a first period T1 and a second period T2. The ring voltage may have a positive voltage VP in the first period T1, and a negative voltage having a decreasing trend / slope from a first negative voltage VN1 to a second negative voltage VN2 in the second period T2. For example, the negative voltage may increase during the second period T2, as shown in FIG. Fig. 11BFor example, the ring voltage source 320 may apply a positive voltage VP to the edge ring electrode 311E during the first period T1, and apply a first negative voltage VN1 to the edge ring electrode 311E at the start time of the second period T2. The controller 16 may control the ring voltage source 320 to output a series of negative voltages of different levels (gradually / continuously increasing negative voltage levels) during the second period T2, so that the negative voltage level reaches VN2 at the end of the second period T2, as shown in FIG. Fig. 11B For example, the gradually / continuously increasing negative voltage level of the ring voltage may increase in a meandering shape, as shown in FIG. Fig. 11B For example, the slope of the curve representing increasing negative voltage levels may increase gradually / continuously, as shown in FIG. Fig. 11B For example, during the second period T2, three or more voltage levels different from each other may be applied to the edge ring electrode 311E. For example, the electrical signal applied to the edge ring electrode 311E may have the following characteristics: Fig. 11B The non-sinusoidal periodic waveform shown includes a pulse portion (positive voltage pulse) and a generally trapezoidal portion (eg, except that the top of the trapezoid is not linear, but increases continuously in magnitude from VN1 to VN2). However, the waveform of the ring voltage is not limited to Fig. 11B The waveform shown in FIG. 1 may be variously modified. For example, the difference between the first negative voltage VN1 and the second negative voltage VN2 may be about half of the first negative voltage VN1. For example, the difference between the first negative voltage VN1 and the second negative voltage VN2 may be between 25% and 70% of the magnitude of the first negative voltage VN1. Fig.11A and Fig. 11B In the example embodiment shown, the ring voltage can be synchronized to have a negative voltage when bias power is not input / applied. In some embodiments, the ring voltage can be synchronized to have a positive voltage when bias power is not input. For example, the bias power and the ring voltage can be synchronized with various phase differences.

[0074] Reference Fig. 12A , the first bias power may be input to the first bias electrode 313 in the form of pulses. Fig. 12B , the period TP of the ring voltage input to the edge ring 311 may be divided into a first period T1, a second period T2, and a third period T3. The ring voltage may have a positive voltage VP in the first period T1, and a voltage having a decreasing trend / slope from a first negative voltage VN1 to a second negative voltage VN2 in the second period T2. For example, the negative voltage applied to the edge ring 311 during the second period T2 may be about Fig. 11B The corresponding negative voltage is the same as described above. Fig. 12BIn the illustrated embodiment, the ring voltage may not be input to the electrode 311E of the edge ring 311 during the third period T3. In some embodiments, a DC voltage less than the positive voltage VP, and a first negative voltage VN1 and a second negative voltage VN2 may be applied to the edge ring 311 during the third period T3. For example, the electrical signal applied to the edge ring electrode 311E may have the following characteristics: Fig. 12B The non-sinusoidal periodic waveform shown includes a pulse portion (positive voltage pulse), a generally trapezoidal portion (eg, except that the top of the trapezoid is not linear, but increases continuously in size from VN1 to VN2), and a blank portion with no substantial electrical signal.

[0075] As an example, the third period T3 may correspond to a time when the first bias power is not input to the first bias electrode 313. For example, the ring voltage may be synchronized with the first bias power in the form of a pulse. When the first bias power is not input, the ring voltage may not be input to the edge ring 311. Therefore, when the ring voltage is not applied to the edge ring 311, ions, radicals, etc. may not be concentrated on the edge ring 311, which can reduce undesired discharge occurring from above the edge ring 311.

[0076] The first bias power may be synchronized with a second bias power input to a second bias electrode disposed at an upper portion of the semiconductor process chamber. For example, the second bias power may be input / applied when the first bias power is input / applied, and the second bias power may not be input / applied when the first bias power is not input / applied. For example, the ring voltage may be synchronized with the first bias power, and the second bias power may be generated in the form of a pulse. In some embodiments, when the first bias power is not applied to the first bias electrode, a ground voltage may be applied to the edge ring electrode.

[0077] Figures 13 to 15 Operations of a semiconductor process chamber according to example embodiments of the inventive concepts are illustrated.

[0078] Reference Figures 13 to 15 , a semiconductor process chamber 400 according to an example embodiment may include an electrostatic chuck 412 on which a semiconductor wafer W is seated, an edge ring 411 disposed around the electrostatic chuck 412 to surround the semiconductor wafer W, and a ring voltage supply unit 420 configured to input a ring voltage to an electrode 411E of the edge ring 411. As an example, the semiconductor wafer W may be disposed on a plurality of protrusions 412A formed on a top surface of the electrostatic chuck 412.

[0079] The plasma sheath region PS may be formed on the top surfaces of the semiconductor wafer W and the edge ring 411. The thickness of the plasma sheath region PS above the semiconductor wafer W may be different from the thickness of the plasma sheath region PS above the edge ring 411. The thickness of the plasma sheath region PS above the edge ring 411 may vary due to the ring voltage input to the edge ring 411 by the ring voltage supply unit 420. As an example, the plasma sheath region PS may have a first thickness D1 above the semiconductor wafer W and a second thickness D2 above the edge ring 411. When the ring voltage is relatively small, the second thickness D2 may be less than the first thickness D1. Therefore, as Fig.13 As shown, the incident direction of ions, radicals, etc. may be distorted / shifted from the vertical direction in the region above the edge of the semiconductor wafer W and the outside.

[0080] When the ring voltage is relatively large, the second thickness D2 may be greater than the first thickness D1, such as Fig.14 As shown. By inputting a relatively large ring voltage and appropriately determining the distance between the semiconductor wafer W and the edge ring 411, the ions and radicals can be controlled to be vertically incident on the edge region of the semiconductor wafer W. However, when the ring voltage is increased, the edge ring 411 is charged, so that, for example, after the edge ring 411 is positively charged, the ions, radicals, etc. may no longer be accelerated. When the ring voltage is reduced to solve this problem, the acceleration direction of the ions, radicals, etc. may be distorted from the vertical direction in the region above the edge of the semiconductor wafer W and outside, as shown. Fig.13 shown.

[0081] Therefore, in example embodiments, the ring voltage supply unit 420 may input a ring voltage of various waveforms to the edge ring 411. The ring voltage supply unit 420 may include: a circuit configured to adjust the size and waveform of the ring voltage. Therefore, the difference between the first thickness D1 and the second thickness D2 in the plasma sheath region PS may be significantly reduced, and ions and radicals may be controlled to be uniformly incident in the entire region of the semiconductor wafer W, such as Fig.15 shown.

[0082] As an example, the ring voltage supply unit 420 may input a ring voltage having a predetermined period to the edge ring 411. The ring voltage has a positive voltage in a first period of the period, and has a negative voltage with a decreasing trend in a second period of the period. Therefore, the absolute value of the ring voltage is not increased to reduce the difference between the second thickness D2 and the first thickness D1, and a negative voltage with a decreasing trend is input in the second period. Therefore, even if the edge ring 411 is charged, ions can be accelerated.

[0083] According to example embodiments, a positive voltage is input to an edge ring of a semiconductor process chamber in which a semiconductor process using plasma is performed in a first period of a cycle, and a negative voltage is input to the edge ring in a second period of the cycle. The ramp voltage input in the second period may have an absolute value that gradually increases. Therefore, even when the edge ring is charged, ions or the like may be accelerated to a wafer to effectively perform a semiconductor process.

[0084] Hereinafter, a method of manufacturing a semiconductor device according to an embodiment of the present disclosure will be described.

[0085] According to the method of manufacturing a semiconductor device, a substrate may be disposed on an electrostatic chuck 112 in a plasma chamber 110. The substrate may be a semiconductor wafer W or other substrates, for example, a crystalline silicon substrate, a crystalline germanium substrate, or a crystalline silicon germanium substrate. Before the substrate is disposed in the plasma chamber 110, various semiconductor patterns and various conductor patterns may be formed on the substrate to form circuits including transistors, capacitors, and / or switches through multiple manufacturing processes including multiple steps of a photolithography process. In the plasma chamber 110, a thin film layer formed on the substrate may be etched by using a plasma etching process. An etching mask pattern may be formed on the thin film layer, and the etching mask pattern may be maintained while etching the thin film in the plasma chamber. In some embodiments, an etching mask pattern may be etched when etching the thin film to form a pattern. The thin film may be an insulator film or a conductor film. When etching the thin film in the chamber 110, an electrical signal described in an embodiment of the present disclosure may be supplied to an edge ring and a bias electrode. After performing the etching process, one or more layers and / or patterns may be formed on the thin film layer to form additional patterns and / or circuits on the substrate. The resulting substrate may be cut and packaged to form a semiconductor device.

[0086] Although the present disclosure describes similar elements of an apparatus with different reference numerals, corresponding elements and / or devices may indicate the same elements and / or devices. For example, semiconductor processing apparatus 10 and 100 may indicate the same apparatus, edge rings 111, 211, 311, and 411 may indicate the same edge ring, electrostatic chucks 112, 212, 312, and 412 may indicate the same electrostatic chuck, bias electrodes 113 and 313 may indicate the same bias electrode, and ring voltage sources 15, 120, 220, 320, and 420 may indicate the same ring voltage source.

[0087] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor processing device, include: Cavity housing; an electrostatic chuck disposed in the chamber housing, the electrostatic chuck configured to hold a semiconductor wafer; a first bias electrode connected to a lower portion of the electrostatic chuck; a second bias electrode mounted above the electrostatic chuck; an edge ring surrounding the electrostatic chuck, the edge ring including a ring electrode disposed within the edge ring; as well as a ring voltage source configured to supply a ring voltage to the ring electrode, the ring voltage having a non-sinusoidal periodic waveform, wherein each cycle of the non-sinusoidal periodic waveform includes a positive voltage applied during a first period and a negative voltage applied during a second period, wherein the magnitude of the negative voltage increases during the second period, and The ring voltage source determines an increasing trend of the magnitude of the negative voltage during the second period based on at least one of a first bias power supplied to the first bias electrode and a second bias power supplied to the second bias electrode.

2. The semiconductor processing device according to claim 1, further comprising: include: The first bias power supply is configured to supply the first bias power to the first bias electrode, wherein the first bias power is synchronized with the ring voltage.

3. The semiconductor processing device according to claim 2, in, The negative loop voltage increased during the second period is greater than the magnitude of the bias voltage of the first bias power.

4. The semiconductor processing device according to claim 1, in, The edge ring includes a dielectric material in which the ring electrode is embedded.

5. The semiconductor processing apparatus according to claim 1, in, The edge ring is provided as a continuous single structure surrounding the electrostatic chuck.

6. The semiconductor processing apparatus according to claim 1, in, The edge ring includes a plurality of unit structures separated from each other, and The plurality of unit structures of the edge ring surround the electrostatic chuck.

7. The semiconductor processing apparatus according to claim 6, in, The plurality of unit structures of the edge ring respectively include a plurality of ring electrodes.

8. The semiconductor processing apparatus according to claim 7, in, The plurality of ring electrodes are electrically connected to each other.

9. The semiconductor processing apparatus according to claim 1, further comprising: include: a second bias power supply configured to supply the second bias power to the second bias electrode, At least a portion of a difference between a magnitude of the negative loop voltage increased during the second period and a second bias voltage of the second bias power is greater than a difference between the second bias voltage and a first bias voltage of the first bias power.

10. The semiconductor processing apparatus according to claim 1, in, The ring voltage source is configured to adjust a length of the first period and a length of the second period within the cycle.

11. The semiconductor processing apparatus according to claim 1, further comprising: include: A chuck voltage source is configured to input an electrostatic chuck voltage to an electrode disposed within the electrostatic chuck.

12. The semiconductor processing apparatus according to claim 1, in, In a plan view, the edge ring is separated from the electrostatic chuck by a predetermined distance.

13. An apparatus for manufacturing a semiconductor device, the apparatus include: a first bias electrode connected to a lower portion of an electrostatic chuck configured to accommodate a semiconductor wafer, the first bias electrode configured to receive a first bias power having a pulse signal; a second bias electrode disposed above the electrostatic chuck, the second bias electrode being configured to receive a second bias power; as well as an edge ring surrounding the electrostatic chuck, the edge ring configured to receive a ring voltage synchronized with at least one of the first bias power and the second bias power, The cycle of the ring voltage is divided into a first period, a second period and a third period, and The ring voltage has a constant positive voltage during the first period, and has a gradually increasing negative voltage during the second period.

14. The device according to claim 13, in, The edge ring is configured to receive a ground voltage during the third period.

15. The device according to claim 13, in, The second bias power is generated as a pulse signal synchronized with the first bias power, and The ring voltage is synchronized with the first bias power and the second bias power.

16. The device according to claim 15, in, The first bias power and the second bias power are input to the first bias electrode and the second bias electrode during the first period and the second period, and are not input to the first bias electrode and the second bias electrode during the third period.

17. The device according to claim 13, in, The absolute value of the ring voltage increases during the second period.

18. An apparatus for manufacturing a semiconductor device, the apparatus include: a bias power supply configured to supply bias power to an electrode disposed in a semiconductor process chamber; a chuck voltage source configured to supply an electrostatic chuck voltage to an electrostatic chuck disposed in the semiconductor process chamber, the electrostatic chuck being configured to hold a semiconductor wafer; as well as a ring voltage source configured to supply a ring voltage to an edge ring surrounding the electrostatic chuck to control a thickness of a plasma sheath region, the ring voltage having a constant positive voltage during a first period of the ring voltage and having a gradually increasing negative voltage during a second period of the ring voltage, The ring voltage source determines at least one of a change in length of the second time period and a change in magnitude of the ring voltage in the second time period based on the bias power.

19. The device according to claim 18, in, The ring voltage source is configured to supply a plurality of different values ​​of negative ring voltages to the edge ring during the second period.

20. The device according to claim 18, in, The ring voltage source is configured to supply a gradually increasing negative voltage of different waveforms according to the bias power.

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