High-density packaging lead frame structure

Abstract

The present invention discloses a high-density package leadframe structure, comprising a stacked base frame, at least one leadframe, and a plurality of conductive pads or protrusions for mounting chips. Each leadframe comprises a buffer layer and an RDL circuit layer stacked sequentially from the top surface of the base frame, with the pads or protrusions positioned on the upper surface of the RDL circuit layer of the leadframe furthest from the base frame. The buffer layer is a layer of low-CTE insulating material, and the RDL circuit layer is connected to the surface of the base frame via a conductive structure. By employing a metal-ceramic hybrid leadframe structure, the present invention significantly addresses the problem of high-density chip mounting due to the large difference in thermal expansion coefficient between silicon-based and metal substrates, while also overcoming defects such as warping and lack of uniformity.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a high-density packaging lead frame structure. Background Art

[0002] The lead frame is a fundamental material for semiconductor packaging. As the carrier of integrated circuit chips, it uses bonding materials (gold, aluminum, or copper wire) to achieve electrical connections between the chip's internal circuit terminals and external leads, forming a key structural component of the electrical circuit and acting as a bridge to connect to external wires. Its main functions include circuit connection, heat dissipation, and mechanical support.

[0003] The history of semiconductor packaging development demonstrates that packaging materials play a decisive role in the evolution of packaging technology, essentially establishing a pattern of "one generation of packaging, one generation of materials." Different semiconductor packaging methods require different lead frames, so the development trends of semiconductor packaging methods dictate the development trends of lead frames.

[0004] In general, semiconductor packaging, influenced by surface mount technology, has been continuously evolving towards thinner and smaller form factors in recent years. This has resulted in packages offering advantages such as high density, multi-functionality, superior performance, compact size, low power consumption, high speed, minimal latency, and decreasing costs. However, there has been a lack of a simple product form and process that can integrate the advantages of packages such as QFN, QFP, BGA, FC (Flip Chip), COL (Chip On Lead), and CSP, while also meeting the requirements of package design flexibility, high I / O, a high chip-to-package volume ratio, good heat dissipation and conductivity, and excellent reliability. Currently, a new metal-ceramic substrate based on a frame substrate is being developed, and mass production capabilities are now available.

[0005] However, traditional EMC pre-molded packaging easily delaminates from the metal frame. Both traditional etched lead frames and MIS lead frames have limited density, achieving a maximum line spacing of 75µm, and both require RDL design within the chip pad. For system-level packaging, because the CTE of metal is much greater than that of silicon, temperature fluctuations during packaging or extreme operating environments can easily cause stress and strain on the chip, leading to cracks, leakage, short circuits, and other defects. Ceramic capacitors and resistors, in particular, require delamination due to metal expansion and contraction. Using a BT substrate presents significant heat dissipation and cost issues. Ceramic substrates are significantly more expensive than metal substrates and, due to size limitations, are inherently brittle. Metal-ceramic frames are a revolutionary technology that breaks the constraints of traditional packaging formats, combining multiple advantages and features. They offer a significant challenge to traditional QFN, QFP, and BGA products, and are well-suited to various industry trends such as COL, FC, and copper wire ball bonding. MIS materials are relatively thin, but they are prone to warping and uniformity issues during the packaging process.

[0006] Therefore, there is an urgent need for a new type of packaging lead frame that can ensure high chip bonding density while overcoming warping and uniformity problems. Summary of the Invention

[0007] In order to solve the problems of the prior art, on the one hand, an embodiment of the present invention provides a high-density packaging lead frame structure, comprising a bottom frame, at least one lead frame and a plurality of conductive pads or protrusions for mounting chips, which are stacked in sequence; each lead frame comprises a buffer layer and an RDL circuit layer stacked in sequence from the top surface of the bottom frame, and the pads or protrusions are arranged on the upper surface of the RDL circuit layer of the lead frame farthest from the bottom frame; the buffer layer is a low CTE value insulating material layer, and the RDL circuit layer is connected to the surface of the bottom frame through a conductive structure.

[0008] As a further improvement of the embodiment of the present invention, the material of the buffer layer is a ceramic epoxy resin or a silicon dioxide resin with a low CTE value.

[0009] As a further improvement of an embodiment of the present invention, the conductive structure includes a conductive hole filled with copper paste, a conductive hole filled with a thermally conductive insulating material, or a copper column.

[0010] As a further improvement to the embodiment of the present invention, the buffer layer closest to the bottom frame is a discontinuous structure, and the bottom frame forms a step inside the frame.

[0011] As a further improvement of the embodiment of the present invention, a pad layer is provided on a surface of the bottom frame away from the buffer layer, for connecting the bottom frame and the substrate.

[0012] As a further improvement of an embodiment of the present invention, the surface of the pad layer is coated with a nickel-gold layer, a nickel-palladium-gold layer, an OSP layer, a silver layer, a nickel-silver-gold layer, a nickel-lead-tin alloy or a tin-silver alloy.

[0013] As a further improvement of the embodiment of the present invention, the at least one lead frame further includes an air guide groove, and the air flow channel formed by the air guide groove connects the bottom frame and the installed chip.

[0014] As a further improvement of the embodiment of the present invention, the bottom frame is a metal copper frame, an FR4 circuit board or a BT substrate.

[0015] On the other hand, the present invention also discloses a high-density packaging structure, comprising a substrate, a high-density packaging lead frame structure, and a chip arranged in sequence; the chip is connected to the substrate through the high-density packaging lead frame structure, and is electrically connected through the pads or protrusions.

[0016] As a further improvement of the embodiment of the present invention, the substrate is a ceramic epoxy resin or a silicon dioxide resin, or a silicon dioxide PI.

[0017] The present invention has the following beneficial effects:

[0018] 1. The present invention adopts a metal-ceramic hybrid frame. Through multiple layers of masking, exposure, pre-filling, lamination, drilling, electroplating, secondary exposure, secondary etching and surface treatment on a metal carrier, a ceramic substrate with a BGA structure is formed. This can achieve a higher number and density of I / Os than traditional substrates.

[0019] 2. The present invention can achieve a line width and spacing of 15um; if laser forming and direct copper electroplating are used, ceramic or silicon dioxide materials can achieve a multi-layer substrate with a line width and spacing of 12 / 12μm, which can realize two-layer, three-layer and four-layer multi-layer packaging.

[0020] 3. The present invention adopts a metal-ceramic hybrid frame, which greatly solves the problem of excessive difference in expansion coefficient between silicon-based and metal substrates, facilitating flip-chip mounting. It uses long copper pillars and then covers them with low CTE insulating materials to form multi-layer ultra-fine circuits, ensuring that the CTE value of the substrate approaches the silicon-based CTE value of the chip, thereby ensuring the reliability of the chip and ceramic passive components.

[0021] 4. When the present invention is combined with a chip, the chip does not require RDL design or a conventional packaging substrate, which simplifies the chip production process and reduces production costs;

[0022] 5. The ceramic resin or silicon dioxide resin insulation layer and substrate used in the present invention solve the problems of warping, flatness, and excessive expansion and contraction coefficient;

[0023] 6. The chip I / O number involved in the present invention is as high as 1000 in the same package form, further solving the problem of low I / O pin count of traditional lead frame;

[0024] 7. The present invention not only conducts heat out through each chip pin, but also can dissipate heat directly through the insulation layer, which greatly improves the consistency of heat dissipation and is conducive to solving the heat dissipation and high current problems of high-power chips. This structure not only has a large heat capacity of the copper pillars and lead frame, and a good heat dissipation effect, but also has a high heat dissipation coefficient of ceramic materials and good high-frequency performance. The heat dissipation effect, high-frequency performance, and reliability of EMC materials are far behind those of ceramic materials.

[0025] 8. The packaging structure of the present invention adopts a PNL fan-out structure. The inner fan-in design significantly shortens the length of the bonding wire, resulting in high packaging efficiency. In addition, it has higher strength and better stability than other types of fan-out packaging structures, while also having low cost.

[0026] 9. The lead frame package of the present invention has achieved BGA ball planting capability for the first time, supporting WB, FC and COL mounting as well as chip stacking and package stacking design;

[0027] 10. The structure of the present invention can also be implemented on other materials, such as FR4 circuit boards and BT substrates, and has a wide range of applications; the process is simple and the processing time is short. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive efforts.

[0029] Figure 1 1 is a schematic diagram of a high-density package lead frame structure provided by an embodiment of the present invention;

[0030] The example in the figure is represented as:

[0031] 1- bottom frame; 2- lead frame; 3- buffer layer; 4- RDL circuit layer; 5- bump; 6- conductive structure; 7- step; 8- pad layer; 9- substrate; 10- chip; 11- ceramic device; 12- air guide groove. DETAILED DESCRIPTION

[0032] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0033] The embodiment of the present invention provides a high-density package lead frame, such as Figure 1 As shown, it includes a bottom frame 1, a lead frame 2 and a plurality of conductive pads or protrusions 5 for mounting chips, which are stacked in sequence; each lead frame 2 includes a buffer layer 3 and an RDL circuit layer 4 stacked in sequence from the top surface of the bottom frame 1, and the pads or protrusions 5 are arranged on the upper surface of the RDL circuit layer 4 of the lead frame 2 farthest from the bottom frame 1.

[0034] The bottom frame 1 is a metal copper frame; in other optional implementations, the bottom frame may also be an FR4 circuit board or a BT substrate.

[0035] It should be noted that, in other optional embodiments, the number of lead frames 2 can be two or more, and accordingly, the high-density packaging lead frame includes a bottom frame, a first lead frame, a second lead frame and a plurality of conductive protrusions for mounting chips that are stacked in sequence; the first lead frame includes a first buffer layer and a first RDL circuit layer arranged on the top surface of the bottom frame, and the second lead frame includes a second buffer layer and a second RDL circuit layer arranged on the top surface of the bottom frame, that is, the high-density packaging lead frame includes a bottom frame, a first buffer layer, a first RDL circuit layer, a second buffer layer, a second RDL circuit layer and a plurality of conductive protrusions for mounting chips that are stacked in sequence.

[0036] The buffer layer 3 is an insulating material layer with a low CTE value, and the RDL circuit layer 4 is connected to the surface of the bottom frame 1 through the conductive structure 6 .

[0037] The buffer layer 3 is made of a low CTE ceramic epoxy resin or a silicon dioxide resin.

[0038] Specifically, the conductive structure 6 is a copper pillar. In other optional embodiments, it can also be a conductive hole filled with copper paste or a conductive hole filled with a thermally conductive insulating material.

[0039] Specifically, a structure such as the following is formed inside the frame of the bottom frame 1 in a direction extending to the buffer layer 3. Figure 1 As shown in the step 7 , the buffer layer 3 on the upper surface of the bottom frame 1 is a discontinuous structure, which aims to reduce warping and delamination caused by the inconsistent CTE values ​​between the metal copper and the buffer layer.

[0040] In other embodiments, when the number of lead frames is two or more and the high-density package lead frame is a multi-layer structure, a step is formed between the bottom frame and the buffer layer of the lead frame closest thereto.

[0041] A pad layer 8 is provided on the surface of the bottom frame 1 of the high-density package lead frame structure away from the buffer layer 3 , for connecting the bottom frame 1 and the substrate 9 .

[0042] Furthermore, the surface of the pad layer 8 is coated with a nickel-gold layer, a nickel-palladium-gold layer, an OSP layer, a silver layer, a nickel-silver-gold layer, a nickel-lead-tin alloy or a tin-silver alloy.

[0043] Preferably, the lead frame 2 further includes an air guide groove 12 , and the air flow channel formed by the air guide groove 12 connects the bottom frame 1 and the mounted chip 10 .

[0044] On the other hand, the present invention also discloses a high-density packaging structure, including a substrate 9, the above-mentioned high-density packaging lead frame structure, and a chip 10 arranged in sequence; the chip 10 is connected to the substrate 9 through the above-mentioned high-density packaging lead frame structure, and is electrically connected through a pad or a protrusion 5.

[0045] In an optional embodiment, the chip 10 may be a logic chip, an analog chip, or a memory chip; and the substrate 9 and the ceramic device 11 may also be connected via the lead frame structure.

[0046] In an embodiment of the present invention, the substrate is EMC or ceramic epoxy resin or silicon dioxide resin, or silicon dioxide PI.

[0047] The present invention has the following beneficial effects:

[0048] 1. The present invention adopts a metal-ceramic hybrid frame. Through multiple layers of masking, exposure, pre-filling, lamination, drilling, electroplating, secondary exposure, secondary etching and surface treatment on a metal carrier, a ceramic substrate with a BGA structure is formed. This can achieve a higher number and density of I / Os than traditional substrates.

[0049] 2. The present invention can achieve a line width and spacing of 15um; if laser forming and direct copper electroplating are used, ceramic or silicon dioxide materials can achieve a multi-layer substrate with a line width and spacing of 12 / 12μm, which can realize two-layer, three-layer and four-layer multi-layer packaging.

[0050] 3. The present invention adopts a metal-ceramic hybrid frame, which greatly solves the problem of excessive difference in expansion coefficient between silicon-based and metal substrates, facilitating flip-chip mounting. It uses long copper pillars and then covers them with low CTE insulating materials to form multi-layer ultra-fine circuits, ensuring that the CTE value of the substrate approaches the silicon-based CTE value of the chip, thereby ensuring the reliability of the chip and ceramic passive components.

[0051] 4. When the present invention is combined with a chip, the chip does not require RDL design or a conventional packaging substrate, which simplifies the chip production process and reduces production costs;

[0052] 5. The ceramic resin or silicon dioxide resin insulation layer and substrate used in the present invention solve the problems of warping, flatness, and excessive expansion and contraction coefficient;

[0053] 6. The chip I / O number involved in the present invention is as high as 1000 in the same package form, further solving the problem of low I / O pin count of traditional lead frame;

[0054] 7. The present invention not only conducts heat out through each chip pin, but also can dissipate heat directly through the insulation layer, which greatly improves the consistency of heat dissipation and is conducive to solving the heat dissipation and high current problems of high-power chips. This structure not only has a large heat capacity of the copper pillars and lead frame, and a good heat dissipation effect, but also has a high heat dissipation coefficient of ceramic materials and good high-frequency performance. The heat dissipation effect, high-frequency performance, and reliability of EMC materials are far behind those of ceramic materials.

[0055] 8. The packaging structure of the present invention adopts a PNL fan-out structure. The inner fan-in design significantly shortens the length of the bonding wire, resulting in high packaging efficiency. In addition, it has higher strength and better stability than other types of fan-out packaging structures, while also having low cost.

[0056] 9. The lead frame package of the present invention has achieved BGA ball planting capability for the first time, supporting WB, FC and COL mounting as well as chip stacking and package stacking design;

[0057] 10. The structure of the present invention can also be implemented on other materials, such as FR4 circuit boards and BT substrates, and has a wide range of applications; the process is simple and the processing time is short.

[0058] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present invention, and will not be described in detail here.

[0059] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A high-density package lead frame structure, characterized in that: The device comprises a bottom frame, at least one lead frame, and a plurality of conductive pads or bumps for mounting chips, which are stacked in sequence. Each lead frame comprises a buffer layer and an RDL circuit layer stacked in sequence from the top surface of the bottom frame. The pads or bumps are arranged on the upper surface of the RDL circuit layer of the lead frame farthest from the bottom frame. The buffer layer is a low CTE value insulating material layer, and the RDL circuit layer is connected to the surface of the bottom frame through a conductive structure. The bottom frame is provided with a pad layer on a surface away from the buffer layer, for connecting the bottom frame and the substrate; The at least one lead frame further includes an air guide groove, wherein an air flow channel formed by the air guide groove communicates with the bottom frame and the mounted chip.

2. The high-density packaging lead frame structure according to claim 1, characterized in that: The material of the buffer layer is a low CTE ceramic epoxy resin or a silicon dioxide resin.

3. The high-density packaging lead frame structure according to claim 1, characterized in that: The conductive structure includes a conductive hole filled with copper paste, a conductive hole filled with thermal conductive insulating material, or a copper column.

4. The high-density packaging lead frame structure according to claim 1, wherein: The buffer layer closest to the bottom frame is a discontinuous structure, and the bottom frame forms a step inside the frame.

5. The high-density packaging lead frame structure according to claim 4, characterized in that: The surface of the pad layer is coated with a nickel-gold layer, a nickel-palladium-gold layer, an OSP layer, a silver layer, a nickel-silver-gold layer, a nickel-lead-tin alloy or a tin-silver alloy.

6. The high-density packaging lead frame structure according to claim 1, characterized in that: The bottom frame is a metal copper frame, an FR4 circuit board or a BT substrate.

7. A high-density packaging structure, characterized in that: It comprises a substrate, a high-density packaging lead frame structure according to any one of claims 1 to 6, and a chip which are arranged in sequence; the chip is connected to the substrate through the high-density packaging lead frame structure, and is electrically connected through the pads or bumps.

8. The high-density packaging structure according to claim 7, characterized in that: The substrate is ceramic epoxy resin or silicon dioxide resin, or silicon dioxide PI.

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