Method, system and storage medium for generating integrated circuit layout diagram

Abstract

A method for generating an integrated circuit layout diagram includes arranging first cells having a first cell height in a first row and arranging second cells having a second cell height less than the first cell height in a second row adjacent to the first row. The first row and the second row extend along a first direction and are arranged relative to a wiring grid, the wiring grid including a first wiring trace along the first direction and a second wiring trace along a second direction perpendicular to the first direction. A first cell pin is placed in each first cell extending along the second wiring trace. A second cell pin is placed above a selected through-hole layout point in each second cell. At least one second cell pin extends along the corresponding second wiring trace across the boundary of the corresponding second cell and extends into the corresponding first cell adjacent to the corresponding second cell. In addition, a system and a non-transitory computer-readable storage medium for generating a layout diagram of an integrated circuit are also disclosed herein.

Description

Technical Field

[0001] The present invention relates to a method for generating an integrated circuit layout diagram, and more particularly to a method, system and storage medium for generating an integrated circuit layout diagram with pins of different unit heights. Background Art

[0002] Over the past few decades, semiconductor device scaling has followed Moore's Law. Due to lithography and integration limitations, advances in manufacturing processes cannot independently keep up with the constant device scaling trend, so layout design technology also helps further scaling of semiconductor devices. Summary of the invention

[0003] According to one embodiment of the present case, it is a method for generating an integrated circuit layout diagram, characterized in that the method includes arranging a plurality of first cells having a first cell height in a first column; arranging a plurality of second cells having a second cell height in a second column adjacent to the first column, the second cell height being less than the first cell height, and the first column and the second column extending along a first direction and arranged relative to a wiring grid, the wiring grid comprising a plurality of first wiring traces extending along the first direction and a plurality of second wiring traces extending along a second direction, the second direction being perpendicular to the first direction; placing a plurality of first cell pins in each of the plurality of first cells, each of the plurality of first cell pins extending along a corresponding second wiring trace of the plurality of second wiring traces; and placing a plurality of second cell pins above a plurality of selected through-hole layout points in each of the plurality of second cells, at least one second cell pin of the plurality of second cell pins extending along a corresponding second wiring trace of the plurality of second wiring traces across a boundary of the corresponding second cell of the plurality of second cells and extending into a corresponding first cell of the plurality of first cells adjacent to the corresponding second cell.

[0004] According to an embodiment of the present case, a method for generating a layout diagram of an integrated circuit includes: arranging a plurality of first cells having a first cell height in a plurality of first rows; arranging a plurality of second cells having a second cell height in a plurality of second rows, the second cell height being less than the first cell height, wherein the plurality of first rows and the plurality of second rows are arranged according to a wiring grid, the wiring grid comprising a plurality of first wiring traces extending in a first direction and a plurality of second wiring traces extending in a second direction, the second direction being perpendicular to the first direction; placing a plurality of first cell pins over a plurality of selected first through-hole layout points in each of the plurality of first cells, wherein each first cell pin of the plurality of first cell pins extends along a corresponding second wiring trace of the plurality of second wiring traces and has both ends terminated within top and bottom boundaries of a corresponding first cell of the plurality of first cells; and placing a plurality of second cell pins over a plurality of selected through-hole layout points in each of the plurality of second cells, wherein at least one second cell pin of the plurality of second cell pins extends along a corresponding second wiring trace of the plurality of second wiring traces across a boundary of a corresponding second cell of the plurality of second cells and extends into a corresponding first cell of the plurality of first cells adjacent to the corresponding second cell.

[0005] According to one embodiment of the present case, a system for processing a layout diagram of an integrated circuit includes: at least one processor; and a computer-readable storage medium connected to the at least one processor, wherein the at least one processor is used to execute instructions stored on the computer-readable storage medium to: arrange a plurality of first cells having a first cell height in a plurality of first columns; arrange a plurality of second cells having a second cell height in a plurality of second columns, wherein the second cell height is less than the first cell height, arrange the plurality of first columns and the plurality of second columns according to a wiring grid, the wiring grid including a plurality of first wiring traces extending in a first direction and a plurality of second wiring traces extending in a second direction, the second direction being perpendicular to the first direction; place a plurality of first cell pins in each of the plurality of first cells, each of the plurality of first cell pins extending along a plurality of second A corresponding second wiring track of the wiring track extends; a plurality of through-hole layout points in each of the plurality of second cells are identified at corresponding intersections of the plurality of intersections between the plurality of first wiring tracks and the plurality of second wiring tracks; a subset of through-hole layout points is selected from the plurality of through-hole layout points, wherein the subset of through-hole layout points corresponds to a group of second wiring tracks in the plurality of second wiring tracks, and a plurality of second cell pins for each of the plurality of second cells are placed along the group of second wiring tracks, wherein if none or only one of a pair of first cells of the plurality of first cells adjacent to the relative boundaries of a corresponding second cell of the plurality of second cells includes a first cell pin, then a second cell pin of the plurality of second cell pins can be placed on the same second wiring track as an adjacent first cell pin of the plurality of first cell pins; and a plurality of second cell pins are placed above the subset of through-hole layout points.

[0006] According to one embodiment of the present case, a method for generating an integrated circuit layout diagram includes: arranging a first unit having a first unit height in a first row; arranging a second unit having a second unit height in a second row adjacent to the first row, wherein the second unit height is different from the first unit height; placing a plurality of first unit pins in the first unit, wherein each of the plurality of first unit pins extends along a corresponding wiring trace; and placing a plurality of second unit pins above a plurality of selected through-hole layout points in the second unit, wherein at least one second unit pin among the plurality of second unit pins extends along a second wiring trace across a boundary of the second unit and extends into the first unit.

[0007] According to one embodiment of the present case, a method for generating an integrated circuit layout diagram is provided, the method comprising: arranging a plurality of cells in the layout diagram; and placing a plurality of cell pins on a plurality of selected through-hole layout points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a wiring trace of a plurality of wiring traces across a boundary of the first cell and extends into a second cell of the plurality of cells adjacent to the first cell.

[0008] According to one embodiment of the present case, it is related to a non-temporary computer-readable storage medium storing multiple instructions. When the multiple instructions are executed by a processor, the processor is used to: arrange multiple units in a layout diagram; and place multiple unit pins on multiple selected through-hole layout points in a first unit of the multiple units, wherein at least one unit pin of the multiple unit pins extends along a wiring track of the multiple wiring tracks across a boundary of the first unit and extends to a second unit of the multiple units adjacent to the first unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The aspects of one embodiment of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0010] Figure 1 is a flow chart of a method for generating a layout diagram of an integrated circuit (IC) according to an embodiment;

[0011] FIG. 2A to FIG. 2F is a depiction of a layout diagram at various stages of generating an IC layout diagram according to one embodiment;

[0012] Figure 3 is a flow chart of a method for generating a layout diagram of an IC according to an embodiment;

[0013] FIG. 4A to FIG. 4C is a depiction of a layout diagram at various stages of generating an IC layout diagram according to one embodiment;

[0014] Figure 5 is a block diagram of an electronic design automation (EDA) system according to one embodiment; and

[0015] Figure 6 is a block diagram of an IC manufacturing system and an IC manufacturing process associated therewith according to an embodiment.

[0016]

Explanation of symbols

[0017] 100, 300 Method for generating integrated circuit layout diagram

[0018] Steps 102, 104, 106, 108, 110, 112, 302, 304, 306, 308, 310

[0019] Layout of 200A, 200B, 200C, 200D, 200E, 200F, 400A, 400B, 400C

[0020] 202 Unit 1

[0021] 204 Unit 2

[0022] 206a~206e power rail

[0023] 212A, 214A top border

[0024] 212B, 214B bottom border

[0025] 212C, 214C side border

[0026] 220 first conductive line

[0027] 222, 224, 226, 228 first conductive line

[0028] 232, 234, 236 second conductive line

[0029] 240, 240(1) to 240(5) first unit pin

[0030] 242 first through hole

[0031] 250, 250(1) to 250(6) through hole layout points

[0032] 260 Second unit pin

[0033] 260' unit pin

[0034] 260(1), 260(2) Second unit pin

[0035] 262 Second through hole

[0036] 270 First through hole layout point

[0037] 500 Electronic Design Automation (EDA) System

[0038] 502 processor

[0039] 504 Non-transitory computer-readable storage media

[0040] 506 Computer program code (instructions)

[0041] 507 Standard Cell Library

[0042] 508 Bus

[0043] 510I / O interface

[0044] 512 Network interfaces

[0045] 514 Network

[0046] 542 User Interface

[0047] 600 IC manufacturing system

[0048] 620 Design Studio

[0049] 622 IC Design Layout

[0050] 630 Masking Room

[0051] 632 Data Preparation

[0052] 644 Mask Manufacturing

[0053] 645 Mask

[0054] 650IC Manufacturer / Fab

[0055] 652 Wafer Manufacturing

[0056] 653 Wafer

[0057] 660 Devices DETAILED DESCRIPTION

[0058] The following disclosure provides many different embodiments or examples to implement the different features of the provided subject matter. Specific examples of parts, materials, values, steps, operations, materials, arrangements or the like are described below to simplify an embodiment of this case. Of course, these are only examples and are not intended to be restrictive. Other parts, values, operations, materials, arrangements or the like are included. For example, in the following description, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, an embodiment of this case may repeat component symbols and / or letters in each example. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0059] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly accordingly.

[0060] Some integrated circuit (IC) designs are based on a collection of cells selected from a library. The layout includes at least one logic block customized for a specific purpose. The logic block is an arrangement of cells placed in a wiring grid of vertical and horizontal wiring tracks. Conductive structures such as metal wires are placed on the wiring tracks to provide connections between cells. The design of the IC layout is performed by an automatic placement and routing (APR) tool, which includes a placer and a router, by selecting standard cells from a standard cell library and placing and routing the cells according to a number of design rules. The placer determines the best location for each standard cell of the integrated circuit, and the router optimizes the routing of the input / output lines and the connections between the standard cells so that the IC layout does not become overcrowded due to input / output and other wiring.

[0061] Placers and routers use many design rules to decide where to place cells and how to create wires to connect all cells. Design rules include, for example, minimum length of wires, minimum spacing between wires, and the like. In some cases, failure to meet design rules sometimes leads to process-related problems, such as shorts between metal wires due to optical proximity.

[0062] The height of a cell is determined by the number of horizontal tracks extending between the top and bottom edges of the cell. Cells with smaller cell heights are used to achieve high integration and low power consumption, while cells with higher cell heights are used for high-speed operation. In some logic blocks, standard cells have the same cell height to facilitate cell placement and routing.

[0063] As the demand for high-speed and low-power integrated circuits suitable for portable electronic applications increases, logic blocks are modified to include standard cells of different cell heights. In such mixed cell designs, standard cells are arranged in multiple columns, and only standard cells of the same height are placed in one column.

[0064] A hybrid cell design using standard cells of different cell heights in one logic block helps achieve both high speed and low power in integrated circuit layout design. However, in a hybrid cell design, cell pins, such as input and output pins, used to transmit signals between cells, suffer from substantial reductions in end-to-end spacing and pin access areas. Therefore, additional cutting masks are used to perform cell routing. Using additional cutting masks typically results in increased manufacturing costs.

[0065] In some embodiments, a layout design method for implementing cell pin layout and routing for cells of different cell heights is provided. The layout design method allows the pins of high-speed cells and low-power cells to be placed and routed in the same logic block without the need to use additional cutting masks to comply with existing design rules. Therefore, the layout design method of one embodiment of the present case helps maintain the same process cost when a traditional uniform cell height design is changed to a mixed cell height design.

[0066] Figure 1 FIG. 1 is a flow chart of a method 100 for generating a layout diagram 200F of an integrated circuit (IC) according to an embodiment. Figure 1 The order of drawing or dividing Figure 1 The operations of method 100 may be performed in one or more orders other than the order depicted. In some embodiments, one or more additional operations are performed before, between, during, and / or after performing one or more operations of method 100. FIG. 2A to FIG. 2F Describing method 100, these figures include views of various stages in generating layout diagram 200F.

[0067] Some or all of the operations of method 100 can be performed as part of an automatic placement and routing (APR) tool. In some embodiments, some or all of method 100 is performed by a processor of a computer. In some embodiments, by referring to Figure 5 The processor 502 of the electronic design automation (EDA) system 500 discussed above performs some or all of the method 100. In some embodiments, some or all of the operations of the method 100 can be performed as part of a design program executed in a design studio, for example, as described below with respect to Figure 6 Design studio 620 discussed.

[0068] Please refer to Figure 1 and Figure 2AThe method 100 includes step 102, wherein a plurality of first conductive lines 220-228 for a plurality of first cells 202 and a plurality of conductive lines 232-236 for a plurality of second cells 204 are placed along corresponding horizontal wiring traces of a plurality of horizontal wiring traces HT1-HT21, the first cells 202 having a first cell height CH1 and the second cells 204 having a second cell height CH2, the second cell height CH2 being less than the first cell height CH1; and the first cells 202 and the second cells 204 are arranged into a plurality of rows. Figure 2A 2 is a layout diagram 200A of an IC after placing a plurality of first conductive lines 220 ˜ 228 and a plurality of second conductive lines 232 ˜ 236 along corresponding horizontal wiring traces of a plurality of horizontal wiring traces HT1 ˜ HT21 according to an embodiment.

[0069] Please refer to Figure 2A , the layout diagram 200A includes a plurality of cells of different cell heights arranged in rows, for example, a first cell 202 of a first cell height CH1 and a second cell 204 of a second cell height CH2. To simplify the description, the layout diagram 200A includes four rows, namely, a first row (row 1), a second row (row 2), a third row (row 3), and a fourth row (row 4). In some embodiments, the layout diagram 200A includes many rows other than four. Each row in the plurality of rows 1 to 4 extends along the X direction. In some embodiments, the X direction is the horizontal direction of the layout diagram 200A. In some embodiments, the X direction is a direction other than the horizontal. The rows in the plurality of rows 1 to 4 are adjacent to each other in the Y direction, and the Y direction is perpendicular to the X direction. In some embodiments, the Y direction is the vertical direction of the layout diagram 200A. In some embodiments, the Y direction is a direction other than the vertical.

[0070] A plurality of columns, such as columns 1 to 4, are arranged relative to a wiring grid defined by a plurality of horizontal wiring traces HT1-HT21 and a plurality of vertical wiring traces VT1-VT20. The horizontal wiring traces HT1-HT21 are arranged in parallel along the X direction. Each horizontal wiring trace HT1-HT21 represents a potential wiring path of the IC along the X direction. In some embodiments, each of the horizontal wiring traces HT1-HT21 is spaced an equal distance from the adjacent horizontal wiring traces HT1-HT21. The vertical wiring traces VT1-VT20 are arranged in parallel along the Y direction. Each vertical wiring trace VT1-VT20 represents a potential wiring path of the IC along the Y direction. In some embodiments, each of the vertical wiring traces VT1-VT20 is spaced an equal distance from the adjacent vertical wiring traces VT1-VT20. In some embodiments, two adjacent vertical wiring traces of the plurality of vertical wiring traces VT1-VT20 are separated by a nominal minimum distance to form a clear pattern using a single exposure of a single photomask at a given technology node (without using a double patterning technique). Therefore, two vertical second wiring traces among the plurality of vertical wiring traces VT1 to VT20 are designated to have the same color (not shown). In some embodiments, the odd vertical wiring traces VT1, VT3, ..., VT19 are spaced apart from each other at a minimum distance to form a clear pattern using a single exposure of a single photomask at a given technology node (without using double patterning technology), and the even vertical wiring traces VT2, VT4, ..., VT20 are spaced apart from each other at a minimum distance to form a clear pattern using a single exposure of a single photomask at a given technology node (without using double patterning technology). Therefore, the distance between two adjacent vertical wiring traces of the plurality of second wiring traces VT1 to VT20 (i.e., the pitch P) is less than the minimum distance allowed by single patterning lithography. Figure 2A In , each of the vertical wiring tracks VT1 to VT20 is assigned a first color, such as color A, or a second color, such as color B. Starting from the vertical wiring track VT1, each vertical wiring track VT1 to VT20 is designated as either color A or color B, so that two adjacent vertical wiring tracks do not have the same color. Figure 2A , every other vertical wiring track VT1-VT20 is assigned the same color. For example, odd-numbered vertical wiring tracks VT1, VT3, ..., VT19 are assigned color A, and even-numbered second wiring tracks VT2, VT4, ..., VT20 are assigned color B. The colors (e.g., color A, color B) indicate that features with the same color will be formed on the same mask of multiple mask sets, and features with different colors will be formed on different masks of multiple mask sets.

[0071] During the layout stage, cells 202 and 204 are placed by the APR tool to abut each other. In some embodiments, cells 202 and 204 are arranged so that cells placed in the same column have the same cell height, but the width of cells 202 or 204 in the same column varies. In some embodiments, first cells 202 and second cells 204 are placed alternately in multiple columns 1 to 4. Figure 2A , a first cell 202 having a first cell height CH1 is placed in odd columns, such as column 1 and column 3, and a second cell 204 having a second cell height CH2 is placed in even columns, such as column 2 and column 4. In some embodiments, the first cell height CH1 is set to be greater than the second cell height CH2. The cell height CH of a cell (e.g., cell 202 or 204) is determined by the number of horizontal wiring tracks HT1 to HT21 surrounding the topmost edge and the bottommost edge of the cell 202 or 204. In some embodiments, each first cell 202 has a track height of seven (7) and each second cell 204 has a track height of five (5). The first cell 202 having a relatively larger cell height CH1 operates at a higher speed and is therefore suitable for high-speed applications. The second cell 204 having a relatively smaller cell height CH2 operates at a lower power and is therefore useful in low-power applications. Although Figure 2A The cells in adjacent rows in the embodiment have different cell heights, but in one embodiment of the present invention, cells in adjacent rows have the same height. Figure 2A , the number of rows in the plurality of rows for placing the first unit 202 is equal to the number of rows (e.g., row 1 and row 3) in the plurality of rows (e.g., row 2 and row 4) for placing the second unit 204. Those skilled in the art will appreciate that in some embodiments, the number of rows in the plurality of rows for placing the first unit 202 is different from the number of rows in the plurality of rows for placing the second unit 204 (not shown).

[0072] In some embodiments, cells 202 and 204 are standard cells. Standard cells include, but are not limited to, INV, AND, OR, NOR, XOR, AOI, OAI, multiplexers, buffers, adders, fillers, flip-flops, latches, delays, clock cells, or the like. Alternatively, cells 202 and 204 are custom cells. In the layout stage, cells 202 and 204 are placed by an APR tool.

[0073] Each of the first cells 202 has a substantially rectangular shape, including a top boundary 212A, a bottom boundary 212B, and an opposite side boundary 212C. The top boundary 212A and the bottom boundary 212B are parallel to the X direction. The side boundary 212C is parallel to the Y direction. The height of each first cell 202, i.e., the cell height CH1, is defined between the top boundary 212A and the bottom boundary 212B. Similarly, each of the second cells 204 has a substantially rectangular shape, including a top boundary 214A, a bottom boundary 214B, and an opposite side boundary 214C. The top boundary 214A and the bottom boundary 214B are parallel to the X direction. The side boundary 214C is parallel to the Y direction. The height of each second cell 204, i.e., the cell height CH2, is defined between the top boundary 214A and the bottom boundary 214B. When a first cell 202 in one column (e.g., column 1 or column 3) abuts a second cell 204 in an adjacent column (e.g., column 2 or column 4), the top and bottom boundaries 214A, 214B of the second cell 204 merge with the corresponding top and bottom boundaries 212A, 212B of the first cell 202 in the adjacent columns Columns 1 to 4. Figure 2A , the top boundary 214A of the second cell 204 in column 2 merges with the bottom boundary 212B of the first cell 202 in column 1, the bottom boundary 214B of the second cell 204 in column 2 merges with the top boundary 212A of the first cell 202 in column 3, and the top boundary 214A of the second cell 204 in column 4 merges with the bottom boundary of the first cell 202 in column 3.

[0074] Layout 200A further includes a plurality of power rails, such as 206a-206e, extending along the boundaries of a plurality of columns 1 to 4. Figure 2A , power rail 206b exists at the common boundary of column 1 and column 2, power rail 206c exists at the common boundary of column 2 and column 3, and power rail 206d exists at the common boundary of column 3 and column 4. Each of the power rails 206a-206e is used to provide one of the power supply voltage potential Vdd and the ground voltage potential Vss to the cells 202 or 204 in the corresponding column 1 to column 4. The power rails 206a-206e are rectangular with a long axis substantially aligned with the corresponding horizontal wiring traces (e.g., HT1, HT7, HT11, HT17, and HT21). In some embodiments, the top boundary 212A of each first cell 202 is defined in the middle of the corresponding power rail 206a or 206c, and the bottom boundary 212B of each first cell 202 is defined in the middle of the corresponding power rail 206b or 206b. Additionally, a top boundary 214A of each second cell 204 is defined in the middle of the corresponding power rail 206b or 206d, and a bottom boundary 214B of each second cell 204 is defined in the middle of the corresponding power rail 206c or 206e.

[0075] Each of the first cells 202 includes a plurality of first conductive lines 220, 222, 224, 226, and 228 within the top and bottom boundaries 212A, 212B. The first conductive lines 220, 222, 224, 226, and 228 in each of the first cells 202 are arranged substantially parallel to each other along the X direction and aligned to respective horizontal wiring traces (e.g., HT2-HT6 and HT12-HT16). Each of the second cells 204 includes a plurality of second conductive lines 232, 234, and 236 within the top and bottom boundaries 214A, 214B. The second conductive lines 232, 234, and 236 in each of the second cells 204 are arranged substantially parallel to each other along the X direction and aligned to respective horizontal wiring traces (e.g., HT8-HT10 and HT18-HT20).

[0076] In some embodiments, power rails 206a-206e and conductive lines 220-228 and 232-236 are formed in a first metal layer (i.e., M1 layer) that is close to a substrate in which active components, such as transistors or the like, of cells 202 and 204 are formed. During the routing phase, power rails 206a-e and conductive lines 220-228 and 232-236 are arranged relative to corresponding horizontal routing traces HT1-HT21 by an APR tool.

[0077] Please refer to Figure 1 and Figure 2B , the method 100 proceeds to step 104 , where a plurality of first cell pins 240 for each first cell 202 are placed along corresponding vertical wiring traces of the plurality of vertical wiring traces VT1 ˜ VT20 . Figure 2B The layout diagram 200B is a layout diagram 200A according to an embodiment after placing a plurality of first cell pins 240 along a corresponding vertical wiring trace of the plurality of vertical wiring traces VT1 ˜ VT20 for each first cell 202 .

[0078] A cell pin as described herein refers to a conductive line that carries an input or output signal for a cell. Figure 2BIn the embodiment, the plurality of first unit pins 240 in each first unit 202 include at least one input pin or at least one output pin, wherein the at least one input pin is adapted to receive an input signal into the unit, and the at least one output pin is adapted to transmit an output signal from the unit. The number of input pins and output pins in each first unit 202 is adjusted according to actual circuit requirements. For example, the leftmost first unit 202 in row 1 includes three first unit pins 240(1) to 240(3), wherein the first unit pins 240(1) and 240(2) are used as input pins and the first unit pin 240(3) is used as an output pin; and the leftmost first unit 202 in row 3 includes two first unit pins 240(4) to 240(5), wherein the first unit pin 240(4) is used as an input pin and the first unit pin 240(5) is used as an output pin.

[0079] Each first unit pin 240 extends in the Y direction and is aligned with a corresponding vertical wiring track of a plurality of vertical wiring tracks VT1 to VT20. Each first unit pin 240 is rectangular and has a length along the Y direction and a width along the X direction. The length of the first unit pin 240 is equal to or greater than the minimum length, which is specified by the first design rule of the specific manufacturing process and thus meets the design rule line length requirement. As used herein, the minimum length of the manufacturing process is the minimum length at which the conductive line can be manufactured while still meeting the corresponding design rules to avoid erroneous circuit functions. In some embodiments, the second design rule imposes a minimum boundary offset between the end of the first unit pin 240 and the top and bottom boundaries 212A, 212B of the first unit 202. Therefore, the first unit pin 240 is located at the top and bottom boundaries 212A, 212B, so that no first unit pin 240 terminates at the top or bottom edge 212A or 212B of the first unit 202 to meet the minimum boundary offset criterion. In some embodiments, the first cell pin 240 extends across the entire set of first conductive lines 220 - 228 enclosed in the first cell 202 .

[0080] Each first unit pin 240 is assigned a color, which is the same as the color of the corresponding vertical wiring track VT1-VT20, along which the first unit pin 240 extends. In some embodiments, a first set of first unit pins 240 extending along odd vertical wiring tracks VT1, VT3, ..., VT19 is assigned a first color, such as color A, and a second set of first unit pins 240 extending along even vertical wiring tracks VT2, VT4, ..., VT20 is assigned a second color, such as color B, indicating that the first set of first unit pins 240 is formed using a first mask and the second set of first unit pins 240 is formed using a second mask, and the second mask is different from the first mask.

[0081] In some embodiments, the first unit pin 240 is located in the second metal layer (i.e., M2 layer) covering the M1 layer. The first unit pin 240 is electrically coupled to the corresponding first conductive lines 220-228 via a plurality of first through holes 242 arranged below the first unit pin 240. Each first through hole 242 is located at the intersection between the first unit pin 240 and the corresponding first conductive line 220-228.

[0082] Please refer to Figure 1 and Figure 2C , the method 100 proceeds to step 106 , where a plurality of via placement points 250 are identified for each of the second cells 204 . Figure 2C Layout diagram 200C is layout diagram 200B after a plurality of via placement points 250 are identified for each of second cells 204 according to an embodiment.

[0083] Via placement points 250 correspond to possible locations for placing vias 262 ( Figure 2E ), the second conductive lines 232-236 in the M1 layer are electrically connected to the second unit pin 260 ( Figure 2D ) is formed in the overlying M2 layer, thereby enabling element signal transmission. The via layout point 250 is located at the intersection of the second conductive lines 232-236 and the corresponding vertical wiring tracks in the vertical wiring tracks VT1-VH20. For example, for the leftmost second unit 204 in column 2, two exemplary via layout points 250(1) and 250(2) are identified as possible locations for placing vias above the second conductive line 232 placed on the horizontal wiring track HT8, two exemplary via layout points 250(3) and 250(4) are identified as possible locations for placing vias above the second conductive line 234 placed on the horizontal wiring track HT9, and two exemplary via layout points 250(5) and 250(6) are identified as possible locations for placing vias above the second conductive line 236 placed on the horizontal wiring track HT9.

[0084] Please refer to Figure 1 and Figure 2D , the method 100 proceeds to step 108 , where a plurality of second cell pins 260 for each second cell 204 are placed over the plurality of selected via placement points 250 . Figure 2D 2 is a layout diagram 200D after placing a plurality of second cell pins 260 over a plurality of selected via layout points 250 for each second cell 204 according to an embodiment.

[0085] In some embodiments, the third design rule imposes a minimum end-to-end spacing requirement that specifies that facing ends of adjacent cell pins on the same vertical wiring trace must be separated by a minimum distance. The minimum end-to-end spacing is a parameter of a specific process technology node. In step 108, the through-hole layout point 250 identified in step 106 is checked to determine whether there is enough space available to place the second cell pin 260 above the through-hole layout point 250, so that the second cell pin 260 is separated from the adjacent first cell pin 240 by the minimum end-to-end spacing, and the adjacent first cell pin 240 is located on the same vertical wiring trace VT1-VT20 as the second cell pin 260. After checking, a subset of through-hole layout points 250 suitable for placing the second cell pin 260 for the second cell 204 is selected. The following uses exemplary second cell pins 260(1)-260(3) and exemplary via placement points 250(1)-250(6) identified for the leftmost second cell 204 in column 2 to illustrate and describe the criteria for selecting via placement points 250 to place second cell pins 260 to meet the minimum end-to-end spacing requirement. The second cell pin 260(1) can be placed above via placement point 250(3) or above via placement point 250(6) along vertical routing trace VT2 without incurring a minimum end-to-end spacing violation. This is because in the columns, i.e., columns 1 and 3 that are immediately adjacent to column 2, only the leftmost first cell 202 in column 3 includes a first cell pin 240(4) along the same vertical routing trace VT2, while a portion of the vertical routing trace VT2 in column 1 is unoccupied. Thus, the second cell pin 260(1) may extend across the top boundary 214A of the second cell 204 and onto an unoccupied portion of the vertical routing trace VT2 in the leftmost first cell 202 in row 1 to ensure that one end of the second cell pin 260(1) is spaced apart from the adjacent end of the first cell pin 240(4) by a distance that is equal to or greater than the minimum end-to-end spacing. Similarly, along the vertical routing trace VT5, the second cell pin 260(2) may be placed above the via placement point 250(2) without incurring a minimum end-to-end spacing violation. This is because the leftmost first cells 202 in rows 1 and 3 do not include a first cell pin 240 along the same vertical routing trace VT5 to trigger a minimum end-to-end spacing violation, thereby preventing the second cell pin 260(2) from being placed above the via placement point 250(2). In some embodiments, the second cell pin 260(2) may be formed to have both ends terminated at the opposite top and bottom boundaries 214A and 214B of the leftmost second cell 204 in row 2.In other embodiments, the second cell pin 260(2) may be formed to have one end terminating within the leftmost second cell 204 in column 2 and an opposite end extending across the respective boundary 214A or 214B and extending onto a portion of the vertical wiring trace VT5 in column 1 or onto a portion of the vertical wiring trace VT5 in column 3 because both portions of the vertical wiring trace VT5 in columns 1 and 3 are unoccupied. In contrast, as indicated by the cross symbol, the placement of the cell pin 260' above the via placement point 250(1) along the vertical wiring trace VT4 is prohibited by the minimum end-to-end spacing requirement because each of the leftmost first cells 202 in columns 1 and 3 includes a first cell pin 240(2) or 240(5) along the same vertical wiring trace VT4 and insufficient space is available to accommodate the cell pins therebetween without incurring a minimum end-to-end spacing violation. Placing the cell pin 260' between the two first cell pins 240(2) and 240(5) in columns 1 and 3 along the same vertical wiring trace VT4 will trigger a minimum end-to-end spacing violation because the distance D1 between the cell pin 260' in column 1 and the facing ends of the first cell pin 240(2) or the distance D2 between the cell pin 260' in column 3 and the facing ends of the first cell pin 240(5) is less than the minimum end-to-end spacing. If the cell pin 260' is placed above the through-hole layout point 250(1) along the vertical wiring trace VT4, the self-layout diagram 200F( is added. Figure 2F ) Risk of manufacturing ICs resulting in faulty circuits.

[0086] Next, a second cell pin 260 for inputting and outputting signals to the second cell 204 is placed above the selected via layout point 250, thereby extending along the corresponding vertical wiring trace VT1-VT21 where the selected via layout point 250 is located. Therefore, according to the minimum end-to-end spacing requirement, in some embodiments, the second cell pin 260 for the second cell 204 can be formed to have an end that terminates within the corresponding top or bottom boundary 214A or 214B and extends across the corresponding top or bottom boundary 214A or 214B to the opposite end in the adjacent first cell 202, which does not include the first cell pin 240 on the same vertical wiring trace VT1-VT20. In this case, the second cell pin 260 can be formed of any length, so that in some embodiments, the second cell pin 260 has a length equal to or greater than the minimum line length. In this case, the second cell pin 260 has a length less than the minimum line length. In the case where the adjacent vertical traces VT1 ˜ VT20 are assigned different colors, the second unit pins 260 on the adjacent vertical wiring traces VT1 ˜ VT20 are also assigned different colors, color A or color B, which indicates that the adjacent second unit pins 260 are manufactured by different masks.

[0087] Please refer to Figure 1 and Figure 2E , the method 100 proceeds to step 110 , where a plurality of second vias 262 are placed to couple the plurality of second unit pins 260 to the plurality of second conductive lines 232 ˜ 236 . Figure 2E It is a layout diagram 200E after placing a plurality of second vias 262 to couple the plurality of second unit pins 260 to the plurality of second conductive lines 232 ˜ 236 according to the layout diagram 200D according to an embodiment.

[0088] The second unit pins 260 are electrically coupled to the corresponding lower second conductive lines 232-236 via the second vias 262. The second vias 262 are placed at the locations of the via layout points 250 selected in step 108.

[0089] Please refer to Figure 1 and Figure 2F , the method 100 proceeds to step 112 , where at least one second unit pin 260 and / or at least one first unit pin 240 is lengthened. Figure 2F FIG. 2 is a layout diagram 200F after the first unit pin 240 and the second unit pin 260 are lengthened according to an embodiment of the layout diagram 200F.

[0090] In step 112, at least one of the second unit pins 260 is elongated in the Y direction so that all of the second unit pins 260 have a length equal to or greater than the minimum line length. The elongation of the second unit pins 260 helps improve pin accessibility, thereby helping to provide better wiring efficiency and wiring density for the second unit 204. Similarly, in some embodiments, at least one of the first unit pins 240 is elongated in the Y direction so as to cross the corresponding boundary 212A or 212B of the first unit 202 where the at least one first unit pin 240 is located. The elongation of the first unit pin 240 helps improve pin accessibility, thereby helping to provide better wiring efficiency and wiring density for the first unit 202. Each of the first unit pins 240 and the second unit pins 260 can be elongated to any length as long as the minimum end-to-end spacing requirement is met between the facing ends of adjacent first unit pins 240 and second unit pins 260 on the same vertical wiring track VT1-VT30 after the pins are elongated.

[0091] Figure 3 FIG. 2 is a flow chart of a method 300 for generating a layout diagram 200F according to an embodiment. Figure 3 The order of drawing or dividing Figure 3 The steps of method 300 may be performed in one or more orders other than the order depicted. In some embodiments, one or more additional operations are performed before, between, during, and / or after performing one or more steps of method 300. FIG. 4A to FIG. 4CA method 300 is described, wherein various stages of generating a layout diagram 200F are illustrated. Unless otherwise specified, FIG. 4A to FIG. 4C The components in FIG. 2A to FIG. 2F The same component symbols as shown in FIG. 4A to FIG. 4C The parts in FIG. 2A to FIG. 2F The same parts in are basically the same.

[0092] Similar to method 100, some or all of the operations of method 300 can be performed as part of an APR tool. In some embodiments, some or all of method 300 is performed by a processor of a computer. In some embodiments, by referring to Figure 5 The processor 502 of the discussed EDA system 500 performs some or all of the method 300. In some embodiments, some or all of the operations of the method 300 can be performed as part of a design program executed in a design studio, for example, as described below with respect to Figure 6 Design studio 620 discussed.

[0093] Please refer to Figure 3 , the method 300 includes an operation 302, wherein a plurality of first conductive lines 220-228 for a plurality of first cells 202 of a first cell height and a plurality of conductive lines 232-236 for a plurality of second cells 204 of a second cell height CH2 are placed along corresponding horizontal wiring traces HT1-HT21 of a wiring grid, wherein the second cell height CH2 is less than the first cell height CH1; and the first cells 202 and the second cells 204 are arranged into a plurality of columns. Step 302 is substantially the same as step 102, and a layout diagram 200A is generated after step 302.

[0094] Please refer to Figure 3 and Figure 4A , the method 300 proceeds to operation 304 , where a plurality of first via placement points 270 are identified for each of the first cells 202 and a plurality of second via placement points 250 are identified for each of the second cells 204 . Figure 4A Layout diagram 400A is layout diagram 200A after identifying a plurality of first via layout points 270 for each of first cells 202 and a plurality of second via layout points 250 for each of second cells 204 according to an embodiment.

[0095] The first via placement point 270 corresponds to a possible location for placing the first via 242 ( Figure 4C ), the first through hole 242 is used to electrically connect the first conductive lines 220-228 in the M1 layer to the first unit pin 240 ( Figure 4B) is formed in the overlying M2 layer to enable signal transmission of the first unit 202. The first via layout point 270 is located at the intersection of the first conductive lines 220-228 and the corresponding vertical wiring traces of the vertical wiring traces VT1-VT20.

[0096] Likewise, the second via layout point 250 corresponds to a possible location for placing the second via 262 ( Figure 4C ), the second through hole 262 is used to electrically connect the second conductive lines 232-236 in the M1 layer to the second unit pin 260 ( Figure 4B ) is formed in the overlying M2 layer to enable signal transmission of the second unit 204. The second via layout point 250 is located at the intersection of the second conductive lines 232-236 and the corresponding vertical wiring traces of the vertical wiring traces VT1-VT20.

[0097] Please refer to Figure 3 and Figure 4B , the method 300 proceeds to step 306, wherein a plurality of first unit pins 240 are placed above the selected first through-hole layout point 270 along the corresponding vertical wiring traces VT1-VT20 and a plurality of second unit pins 260 are placed above the selected second through-hole layout point 250 along the corresponding vertical wiring traces VT1-VT20. Figure 4B It is the layout diagram 400B after the layout diagram 400A places a plurality of first unit pins 240 above the selected first through-hole layout points 270 along the corresponding vertical wiring traces VT1-VT20 and places a plurality of second unit pins 260 above the selected second through-hole layout points 250 along the corresponding vertical wiring traces VT1-VT20.

[0098] An algorithm is iteratively executed for all via layout points 270 and 250 to evaluate the free space available around the first via layout points 270 and the second via layout points 250. Based on the free space available, some of the first via layout points 270 and the second via layout points 250 are selected so that placing the first cell pins 240 and the second cell pins 270 on the respective selected via layout points 270 and 250 does not cause any violation of the minimum end-to-end spacing requirement because the first cell pins 240 and the second cell pins 260 for the adjacent first cells 202 and the second cells 204 are placed on the same vertical routing traces VT1-VT20.

[0099] The first through-hole layout points 270 suitable for placing the first unit pins 240 and the second through-hole layout points 250 suitable for placing the second unit pins 260 are selected based on different design constraints applied to the first unit pins 240 and the second unit pins 260. For example, since the first unit 202 has a relatively large unit height CH1, this unit height CH1 allows the first unit 202 to accommodate unit pins having a length that is equal to or greater than the minimum length, the first unit pins 240 can be formed to meet both the minimum length requirement and the minimum boundary offset requirement. Therefore, each first unit pin 240 is formed to have both ends terminated within the top and bottom boundaries 212A and 212B of the first unit 202. In contrast, since the second unit 204 has a relatively small unit height CH2, this unit height CH2 only allows the second unit 204 to accommodate unit pins having a length that is less than the minimum length, and the second unit pins 260 cannot be formed to meet the minimum length requirement and the minimum boundary offset requirement. Therefore, each second unit pin 260 is used to have both ends terminated at the top and bottom boundaries 214A and 214B of the second unit 204 when there is no first unit pin 240 on the same vertical wiring trace VT1-VT20 in the adjacent columns Column 1 and Column 3, or is used to have one end terminated within the top and bottom boundaries 214A and 214B and the other end extending across the corresponding top or bottom boundary 214A or 214B of the second unit 204 to the adjacent column Column 1 or Column 3 when there is only one first unit pin 240 on the same vertical wiring trace VT1-VT20 in Column 1 or Column 3. By applying different design constraints to the first unit pins 240 and the second unit pins 260, the first unit pins 240 and the second unit pins 260 can be placed so that the facing ends of two adjacent first unit pins 240 and second unit pins 260 on the same vertical wiring trace VT1-VT20 meet the minimum end-to-end spacing requirement.

[0100] Next, the first unit pin 240 for inputting and outputting signals to the first unit 202 is placed above the selected first via layout point 270 to extend along the corresponding vertical wiring traces VT1-VT21 where the selected first via layout point 270 is located. Also, the second unit pin 260 for inputting and outputting signals to the second unit 204 is placed above the selected second via layout point 250 to extend along the corresponding vertical wiring traces VT1-VT21 where the selected second via layout point 250 is located.

[0101] Please refer to Figure 3 and Figure 4C, the method 300 proceeds to step 308, wherein a plurality of first through-holes 242 are positioned to couple a plurality of first unit pins 240 to a plurality of first conductive lines 220-228 and a plurality of second through-holes 262 are positioned to couple a plurality of second unit pins 260 to a plurality of second conductive lines 232-236. Figure 4C The layout diagram 400C is a layout diagram 400B according to an embodiment after placing a plurality of first vias 242 to couple a plurality of first unit pins 240 to a plurality of first conductive lines and placing a plurality of second vias 262 to couple a plurality of second unit pins 260 to a plurality of second conductive lines 232 ˜ 236 .

[0102] The first unit pin 240 is electrically coupled to the corresponding lower first conductive lines 220-228 via the first via 242. The first via 242 is placed at the location of the via layout points 270 selected in step 306. Similarly, the second unit pin 260 is electrically coupled to the corresponding lower second conductive lines 232-236 via the second via 262. The second via 262 is placed at the location of the via layout points 250 selected in step 308.

[0103] Please refer to Figure 3 and Figure 2F The method 300 proceeds to step 310, wherein at least one second unit pin 260 and / or at least one first unit pin 240 is lengthened. Step 310 is substantially the same as step 112, and after step 310, a layout diagram 200F is generated.

[0104] In one embodiment of the present invention, by using different design constraints in placing cell pins for cells of different cell heights, the routing of cells of different heights in a mixed cell design can be performed under the same design block without pushing the existing design rules. As a result, the pin routing utilization rate is increased by 10%.

[0105] Figure 5 is a block diagram of an electronic design automation (EDA) system 500 according to one embodiment.

[0106] In some embodiments, EDA system 500 includes an APR tool. According to some embodiments, the method described herein for designing a layout diagram representing a wire routing arrangement according to one or more embodiments may be implemented, for example, using EDA system 500 .

[0107] In some embodiments, the EDA system 500 is a general purpose computing device including a hardware processor 502 and a non-transitory computer readable storage medium 504. The storage medium 504 is encoded with a computer program code 506, i.e., the storage medium stores computer program code, wherein the computer program code 506 is a set of computer executable instructions. The computer program code 506 is executed (at least in part) by the processor 502 to represent an APR tool that implements, for example, a portion or all of the methods described herein according to one or more (hereinafter, the process and / or method).

[0108] The processor 502 is electrically coupled to the computer readable storage medium 504 via the bus 508. The processor 502 is also electrically coupled to the I / O interface 510 via the bus 508. A network interface 512 is also electrically coupled to the processor 502 via the bus 508. The network interface 512 is connected to a network 514 so that the processor 502 and the computer readable storage medium 504 can be connected to external components via the network 514. The processor 502 is used to execute the computer program code 506 encoded in the computer readable storage medium 504 to cause the EDA system 500 to be used to perform part or all of the processes and / or methods. In one or more embodiments, the processor 502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0109] In one or more embodiments, the computer-readable storage medium 504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 504 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 504 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0110] In one or more embodiments, the storage medium 504 stores computer program code 506 that causes the EDA system 500 (where such execution (at least in part) represents an APR tool) to be used to perform some or all of the processes and / or methods. In one or more embodiments, the storage medium 504 also stores information that facilitates the execution of some or all of the processes and / or methods. In one or more embodiments, the storage medium 504 stores a standard cell library 507 that includes such standard cells that correspond to the cells disclosed herein.

[0111] The EDA system 500 includes an I / O interface 510. The I / O interface 510 is coupled to an external circuit system. In one or more embodiments, the I / O interface 510 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a screen and / or cursor arrow keys to transmit information and commands to the processor 502.

[0112] The EDA system 500 also includes a network interface 512 coupled to the processor 502. The network interface 512 allows the EDA system 500 to communicate with a network 514 to which one or more other computer systems are connected. The network interface 512 includes a wireless network interface such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the processes and / or methods are implemented in two or more systems 500.

[0113] The EDA system 500 is configured to receive information via an I / O interface 510. The information received via the I / O interface 510 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by the processor 502. The information is transmitted to the processor 502 via a bus 508. The EDA system 500 is configured to receive information related to a UI via the I / O interface 510. The information is stored in a computer readable medium 504 as a user interface (UI) 542.

[0114] In some embodiments, some or all of the processes and / or methods are implemented as a standalone software application executed by a processor. In some embodiments, some or all of the processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the processes and / or methods are implemented as a plug-in in a software application. In some embodiments, at least one of the processes and / or methods is implemented as a software application that is part of an APR tool. In some embodiments, some or all of the processes and / or methods are implemented as a software application used by the EDA system 500. In some embodiments, the system is implemented using a software application such as that available from CADENCE DESIGN SYSTEMS, Inc. or another suitable layout generation tool to generate a layout diagram including standard cells.

[0115] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more of the following: optical disks, such as DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROM, RAM, memory cards, and the like.

[0116] Figure 6 is a block diagram of an IC manufacturing system 600 and an IC manufacturing process associated therewith according to an embodiment.

[0117] In some embodiments, based on the layout diagram, at least one of the following is manufactured using the IC manufacturing system 600: (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit.

[0118] exist Figure 6In the present invention, the IC manufacturing system 600 includes entities that interact with each other in the design, development and manufacturing cycle and / or services related to manufacturing IC devices 660, such as design studio 620, mask room 630 and IC manufacturer / fabricator ("fab") 650. The entities in the system 600 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an internal network and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities. In some embodiments, two or more of the design studio 620, mask room 630 and IC wafer fab 650 are owned by a single larger company. In some embodiments, two or more of the design studio 620, mask room 630 and IC wafer fab 650 coexist in a common facility and use common resources.

[0119] The design office (or design team) 620 generates an IC design layout 622. The IC design layout 622 includes various geometric patterns designed for the IC device 660. The geometric patterns correspond to patterns of metal, oxide or semiconductor layers, which constitute various components of the IC device 660 to be manufactured. The various layers are combined to form various IC features. For example, a portion of the IC design layout 622 includes various IC features to be formed in a semiconductor substrate (such as a silicon wafer), such as active regions, gate electrodes, source and drain electrodes, conductive lines or through holes for interlayer interconnections, and openings for bonding pads, as well as various material layers disposed on the semiconductor substrate. The design office 620 implements a suitable design program to form the IC design layout 622. The design program includes one or more of a logical design, a physical design, or a layout and routing. The IC design layout 622 is presented in one or more data files having information of the geometric patterns. For example, the IC design layout 622 can be represented in a GDSII file format or a DFII file format.

[0120] The mask chamber 630 includes data preparation 632 and mask manufacturing 644. The mask chamber 630 uses the IC design layout drawing 622 to manufacture one or more masks 645 for manufacturing various layers of the IC device 660 according to the IC design layout drawing 622. The mask chamber 630 performs mask data preparation 632, in which the IC design layout drawing 622 is converted into a representative data file (RDF). The mask data preparation 632 provides the RDF to the mask manufacturing 644. The mask manufacturing 644 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (master mask) 645 or a semiconductor wafer 653. The design layout drawing 622 is manipulated by the mask data preparation 632 to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer factory 650. In Figure 6 , mask data preparation 632 and mask manufacturing 644 are illustrated as separate elements. In some embodiments, mask data preparation 632 and mask manufacturing 644 may be collectively referred to as mask data preparation.

[0121] In some embodiments, mask data preparation 632 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, crosstalk, other process effects, and the like. OPC adjusts IC design layout 862. In some embodiments, mask data preparation 632 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shifting masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0122] In some embodiments, mask data preparation 632 includes a mask rule checker (MRC) that checks the IC design layout 622 that is processed in the OPC using a set of mask generation rules that include certain geometric and / or connection constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes and the like. In some embodiments, the MRC modifies the IC design layout 622 to compensate for the constraints during mask generation 644, which may override a portion of the modifications performed by the OPC to satisfy the mask generation rules.

[0123] In some embodiments, mask data preparation 632 includes lithography process checking (LPC), which simulates the process to be performed by IC fab 650 to manufacture IC device 660. LPC simulates this process based on IC design layout 622 to generate simulated manufacturing components, such as IC device 660. Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof. In some embodiments, after LPC has generated simulated manufacturing components, if the simulated components are not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine IC design layout 622.

[0124] It should be understood that the above description of mask data preparation 632 has been simplified for clarity purposes. In some embodiments, data preparation 632 includes additional features, such as logic operations (LOPs) to improve IC design layout 622 according to manufacturing rules. In addition, the processes applied to IC design layout 622 during data preparation 632 can be performed in a variety of different orders.

[0125] After the mask data preparation 632 and during the mask manufacturing 644, a mask 645 or a set of masks 645 are manufactured based on the modified IC design layout 622. In some embodiments, the mask manufacturing 644 includes performing one or more lithography exposures based on the IC design layout 622. In some embodiments, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on a mask (mask or master mask) 645 based on the modified IC design layout 622. The mask 645 can be formed by various techniques. In some embodiments, the mask 645 is formed using a binary technique. In some embodiments, the mask pattern includes an opaque area and a transparent area. A radiation beam (such as an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of the mask 645 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque area of ​​the binary mask. In another example, the mask 645 is formed using a phase shift technique. In a phase shift mask (PSM) version of the mask 645, each feature in the pattern formed on the phase shift mask is used to have a suitable phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask produced by the mask manufacturing 644 is used in various processes. For example, such a mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 653, used in an etching process to form various etched regions in the semiconductor wafer 653, and / or used in other suitable processes.

[0126] IC fab 650 includes wafer fabrication 652. IC fab 650 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 650 is a semiconductor factory. For example, there may be a manufacturing facility for front-end manufacturing of multiple IC products (front-end-of-line, FEOL manufacturing), while a second manufacturing facility may provide back-end manufacturing for interconnection and packaging of IC products (back-end-of-line, BEOL manufacturing), and a third manufacturing facility may provide other services for the factory business.

[0127] IC fab 650 uses mask 645 manufactured by mask chamber 630 to manufacture IC device 660. Therefore, IC fab 650 at least indirectly uses IC design layout 622 to manufacture IC device 660. In some embodiments, semiconductor wafer 653 is manufactured by IC fab 650 using mask 645 to form IC device 660. In some embodiments, IC manufacturing includes performing one or more lithography exposures based at least indirectly on IC design layout 622. Semiconductor wafer 653 includes a silicon substrate or other suitable substrate with material layers formed thereon. Semiconductor wafer 653 further includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed in subsequent manufacturing steps).

[0128] With respect to integrated circuit (IC) manufacturing systems (e.g., Figure 6 Details of the system 600 and the IC manufacturing process associated therewith can be found, for example, in U.S. Patent No. 9,256,709 issued on February 9, 2016, U.S. Pre-Grant Publication No. 20150278429 published on October 1, 2015, U.S. Pre-Grant Publication No. 20140040838 published on February 6, 2014, and U.S. Patent No. 7,260,442 issued on August 21, 2007, each of which is incorporated herein by reference in its entirety.

[0129] According to one embodiment of the present invention, a method for generating an integrated circuit layout diagram is provided, the method comprising arranging a plurality of first cells having a first cell height in a first row; arranging a plurality of second cells having a second cell height in a second row adjacent to the first row, the second cell height being less than the first cell height, and the first row and the second row extending along a first direction and arranged relative to a wiring grid, the wiring grid comprising a plurality of first wiring traces extending along the first direction and a plurality of second wiring traces extending along a second direction, the second direction being perpendicular to the first direction; placing a plurality of first cell pins in each of the plurality of first cells, each of the plurality of first cell pins extending along a corresponding second wiring trace of the plurality of second wiring traces; and placing a plurality of second cell pins above a plurality of selected through-hole layout points in each of the plurality of second cells, at least one second cell pin of the plurality of second cell pins extending along a corresponding second wiring trace of the plurality of second wiring traces across a boundary of the corresponding second cell of the plurality of second cells and extending into a corresponding first cell of the plurality of first cells adjacent to the corresponding second cell. In some embodiments, the method further comprises identifying a plurality of through-hole layout points in each of the plurality of second cells at corresponding intersections between the plurality of first wiring traces and the plurality of second wiring traces. The plurality of through-hole layout points are possible locations for placing the plurality of second unit pins. In some embodiments, the method further includes identifying a plurality of selected through-hole layout points from the plurality of through-hole layout points for each second unit of the plurality of second units, such that after placing the plurality of second unit pins over the plurality of selected through-hole layout points, the facing ends of adjacent first unit pins and second unit pins on the same routing trace are separated by a distance that is equal to or greater than the minimum end-to-end spacing according to a set of design rules. In some embodiments, each of the plurality of first unit pins is placed such that the opposite end of each of the plurality of first unit pins terminates within the top and bottom boundaries of the corresponding first unit of the plurality of first units. In some embodiments, at least one second unit pin of the plurality of second unit pins is placed such that one end of at least one second unit pin of the plurality of second unit pins terminates within the top and bottom boundaries of the corresponding second unit of the plurality of second units, and the opposite end of at least one second unit pin of the plurality of second unit pins terminates within the corresponding first unit of the plurality of first units, and the corresponding first unit of the plurality of first units is adjacent to the corresponding second unit of the plurality of second units. In some embodiments, at least one other second unit pin of the plurality of second unit pins is placed so that the opposite ends of the at least one other second unit pin of the plurality of second unit pins terminate at the top and bottom boundaries of the corresponding second unit of the plurality of second units. In some embodiments, the method further includes stretching at least one first unit pin of the plurality of first unit pins along the corresponding second wiring trace of the plurality of second wiring traces to cross the boundary of the corresponding first unit where the at least one first unit pin is located.In some embodiments, the method further includes stretching at least one second unit pin of the plurality of second unit pins along a corresponding second wiring trace of the plurality of second wiring traces. The distance between the facing ends of at least one stretched second unit pin of the plurality of second unit pins and the adjacent first unit pin on the same second wiring trace as the at least one stretched second unit pin is equal to or greater than the minimum end-to-end spacing according to a set of design rules. In some embodiments, the method further includes placing a plurality of first conductive wires along a first set of first wiring traces of the plurality of first wiring traces for the plurality of first units, and placing a plurality of second conductive wires along a second set of first wiring traces of the plurality of first wiring traces for the plurality of second units. In some embodiments, the method further includes placing a plurality of first through holes to couple the plurality of first conductive wires to the plurality of first unit pins. In some embodiments, the method further includes placing a plurality of second through holes to couple the plurality of second conductive wires to the plurality of second unit pins.

[0130] Another embodiment of the present invention is a method for generating an integrated circuit layout diagram, comprising arranging a plurality of first cells having a first cell height in a plurality of first columns; arranging a plurality of second cells having a second cell height in a plurality of second columns, the second cell height being less than the first cell height; arranging the plurality of first columns and the plurality of second columns according to a wiring grid, the wiring grid comprising a plurality of first wiring traces extending in a first direction and a plurality of second wiring traces extending in a second direction, the second direction being perpendicular to the first direction; placing a plurality of first cell pins over a plurality of selected first through-hole layout points in each of the plurality of first cells, each first cell pin of the plurality of first cell pins extending along a corresponding second wiring trace of the plurality of second wiring traces and having both ends terminating within the top and bottom boundaries of the corresponding first cell of the plurality of first cells; and placing a plurality of second cell pins over a plurality of selected through-hole layout points in each of the plurality of second cells, at least one second cell pin of the plurality of second cell pins extending along a corresponding second wiring trace of the plurality of second wiring traces across the boundary of the corresponding second cell of the plurality of second cells and extending into the corresponding first cell of the plurality of first cells adjacent to the corresponding second cell. In some embodiments, the method further includes identifying a plurality of first through-hole layout points within each of the plurality of first cells and a plurality of second through-hole layout points within each of the plurality of second cells, each of the plurality of first through-hole layout points and the plurality of second through-hole layout points being at an intersection of a corresponding first wiring track of the plurality of first wiring tracks and a corresponding second wiring track of the plurality of second wiring tracks. In some embodiments, the method further includes identifying a plurality of selected first through-hole layout points from the plurality of first through-hole layout points and identifying a plurality of selected second through-hole layout points from the plurality of second through-hole layout points, such that after placing a plurality of first cell pins on the plurality of selected first through-hole layout points and placing a plurality of second cell pins on the plurality of selected second through-hole layout points, facing ends of adjacent first cell pins and second cell pins placed along the same second wiring track are separated by a distance that is equal to or greater than a minimum end-to-end spacing according to a set of design rules. In some embodiments, placing a plurality of first cell pins includes placing a plurality of first cell pins having a length that is equal to or greater than a minimum length according to a set of design rules. In some embodiments, placing a plurality of second cell pins includes placing a plurality of second cell pins having a length that is less than a minimum length according to a set of design rules. In some embodiments, the method further includes manufacturing the integrated circuit based on the layout diagram.

[0131] Another embodiment of the present invention is a system for processing an integrated circuit layout diagram. The system includes at least one processor and a computer-readable storage medium connected to the at least one processor. The at least one processor is used to execute instructions stored on the computer-readable storage medium to arrange a plurality of first cells having a first cell height in a plurality of first columns; the at least one processor is used to execute instructions stored on the computer-readable storage medium to further arrange a plurality of second cells having a second cell height in a plurality of second columns, wherein the second cell height is less than the first cell height, and the plurality of first columns and the plurality of second columns are arranged according to a wiring grid, wherein the wiring grid includes a plurality of first wiring traces extending in a first direction and a plurality of second wiring traces extending in a second direction, wherein the second direction is perpendicular to the first direction; the at least one processor is used to execute instructions stored on the computer-readable storage medium to place a plurality of first cell pins in each of the plurality of first cells, wherein each of the plurality of first cell pins extends along a corresponding second wiring trace of the plurality of second wiring traces; the at least one processor is used to execute instructions stored on the computer-readable storage medium to arrange a plurality of first wiring traces in the plurality of first cells; A plurality of through-hole layout points in each of the plurality of second cells are further identified at corresponding intersections of the plurality of intersections between the plurality of second wiring traces; at least one processor is configured to execute instructions stored on a computer-readable storage medium to further select a subset of through-hole layout points from the plurality of through-hole layout points, wherein the subset of through-hole layout points corresponds to a set of second wiring traces in the plurality of second wiring traces, and a plurality of second cell pins for each of the plurality of second cells are placed along the set of second wiring traces, and if none or only one of a pair of first cells of the plurality of first cells includes a first cell pin, and the first cells are adjacent to opposite boundaries of the respective second cells of the plurality of second cells, the second cell pins of the plurality of second cell pins may be placed on the same second wiring trace as the adjacent first cell pins of the plurality of first cell pins; at least one processor is configured to execute instructions stored on a computer-readable storage medium to place the plurality of second cell pins over the subset of through-hole layout points. In some embodiments, each of the plurality of first cell pins has opposite ends that terminate within the boundaries of the respective first cells of the plurality of first cells. In some embodiments, at least one second cell pin of the plurality of second cell pins has an end extending across a corresponding common boundary between a corresponding first cell and a second cell.

[0132] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of an embodiment of the present invention. Those skilled in the art should understand that an embodiment of the present invention can be easily used as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of an embodiment of the present invention, and various changes, substitutions and modifications can be implemented herein without departing from the spirit and scope of an embodiment of the present invention.

Claims

1. A method for generating an integrated circuit layout diagram, characterized in that: The method comprises the following steps: Arranging a plurality of first cells having a first cell height in a first column; Arranging a plurality of second cells having a second cell height in a second row adjacent to the first row, wherein the second cell height is less than the first cell height, and the first row and the second row extend along a first direction and are arranged relative to a wiring grid, the wiring grid comprising a plurality of first wiring traces extending along the first direction and a plurality of second wiring traces extending along a second direction, the second direction being perpendicular to the first direction; placing a plurality of first cell pins within each of the plurality of first cells, wherein each of the plurality of first cell pins extends along a corresponding one of the plurality of second routing traces; as well as A plurality of second unit pins are placed above a plurality of selected through-hole layout points in each of the plurality of second units, wherein at least one second unit pin among the plurality of second unit pins extends along a corresponding second wiring trace of the plurality of second wiring traces across a boundary of a corresponding second unit of the plurality of second units and extends into a corresponding first unit of the plurality of first units adjacent to the corresponding second unit.

2. The method according to claim 1, characterized in that Further including: A plurality of via placement points in each of a plurality of second cells are identified at a corresponding plurality of intersections between the plurality of first routing traces and the plurality of second routing traces, wherein the plurality of via placement points are a plurality of possible locations for placing the plurality of second cell pins.

3. The method according to claim 2, characterized in that Further including: The plurality of selected through-hole layout points are identified from the plurality of through-hole layout points for each of the plurality of second cells, so that after the plurality of second cell pins are placed over the plurality of selected through-hole layout points, facing ends of adjacent first cell pins and second cell pins on a same routing trace are separated by a distance that is equal to or greater than a minimum end-to-end spacing according to a set of design rules.

4. The method according to claim 1, characterized in that: Each of the plurality of first cell pins is positioned such that opposite ends of each of the plurality of first cell pins terminate within top and bottom boundaries of a respective first cell of the plurality of first cells.

5. The method according to claim 1, characterized in that At least one of the multiple second unit pins is placed so that one end of the at least one of the multiple second unit pins terminates within the top and bottom boundaries of the corresponding second unit of the multiple second units, and an opposite end of the at least one of the multiple second unit pins terminates within the corresponding first unit of the multiple first units, and the corresponding first unit of the multiple first units is adjacent to the corresponding second unit of the multiple second units.

6. The method according to claim 1, characterized in that At least one other second cell pin of the plurality of second cell pins is positioned such that opposite ends of the at least one other second cell pin of the plurality of second cell pins terminate at top and bottom boundaries of the corresponding second cell of the plurality of second cells.

7. The method according to claim 1, characterized in that Further including: At least one first cell pin among the plurality of first cell pins is elongated along a corresponding second wiring trace of the plurality of second wiring traces to cross over a boundary of a corresponding first cell where the at least one first cell pin is located.

8. The method according to claim 1, characterized in that Further including: At least one of the plurality of second unit pins is elongated along a corresponding second wiring trace of the plurality of second wiring traces, wherein a distance between facing ends of the at least one elongated second unit pin among the plurality of second unit pins and an adjacent first unit pin on the same second wiring trace as the at least one elongated second unit pin is equal to or greater than a minimum end-to-end spacing according to a set of design rules.

9. The method according to claim 1, characterized in that: Further including: A plurality of first conductive lines are placed along a first set of first wiring traces for the first cells, and a plurality of second conductive lines are placed along a second set of first wiring traces for the second cells.

10. The method according to claim 9, characterized in that Further including: A plurality of first vias are positioned to couple the plurality of first conductive lines with the plurality of first cell pins.

11. The method according to claim 9, characterized in that Further including: A plurality of second vias are positioned to couple the plurality of second conductive lines with the plurality of second cell pins.

12. A method for generating a layout diagram of an integrated circuit, characterized in that: include: Arranging a plurality of first cells having a first cell height in a plurality of first columns; Arranging a plurality of second cells having a second cell height in a plurality of second columns, the second cell height being less than the first cell height, wherein the plurality of first columns and the plurality of second columns are arranged according to a wiring grid, the wiring grid comprising a plurality of first wiring traces extending in a first direction and a plurality of second wiring traces extending in a second direction, the second direction being perpendicular to the first direction; placing a plurality of first cell pins over a plurality of selected first via layout sites in each of the plurality of first cells, wherein each of the plurality of first cell pins extends along a respective one of the plurality of second routing traces and has both ends terminating within top and bottom boundaries of a respective one of the plurality of first cells; and A plurality of second unit pins are placed above a plurality of selected second through-hole layout points in each of the plurality of second units, wherein at least one second unit pin among the plurality of second unit pins extends along a corresponding second wiring trace of the plurality of second wiring traces across a boundary of a corresponding second unit of the plurality of second units and extends into a corresponding first unit of the plurality of first units adjacent to the corresponding second unit.

13. The method according to claim 12, characterized in that Further including: Identify a plurality of first through-hole layout points within each of the plurality of first cells and a plurality of second through-hole layout points within each of the plurality of second cells, each of the plurality of first through-hole layout points and the plurality of second through-hole layout points being located at an intersection of a corresponding first wiring trace of the plurality of first wiring traces and a corresponding second wiring trace of the plurality of second wiring traces.

14. The method according to claim 12, characterized in that Further including: The multiple selected first through-hole layout points are identified from the multiple first through-hole layout points and the multiple selected second through-hole layout points are identified from the multiple second through-hole layout points, so that after the multiple first unit pins are placed on the multiple selected first through-hole layout points and the multiple second unit pins are placed on the multiple selected second through-hole layout points, the facing ends of adjacent first unit pins and second unit pins placed along a same second wiring trace are separated by a distance that is equal to or greater than a minimum end-to-end spacing according to a set of design rules.

15. The method according to claim 12, characterized in that Placing the plurality of first unit pins includes placing the plurality of first unit pins having a length that is equal to or greater than a minimum length according to a set of design rules.

16. The method according to claim 12, characterized in that Placing the plurality of second unit pins includes placing the plurality of second unit pins having a length that is less than a minimum length according to a set of design rules.

17. The method according to claim 12, characterized in that Further comprising manufacturing the integrated circuit based on the layout diagram.

18. A system for processing a layout diagram of an integrated circuit, characterized in that: include: at least one processor; and a computer-readable storage medium connected to the at least one processor, wherein the at least one processor is configured to execute instructions stored on the computer-readable storage medium to: Arranging a plurality of first cells having a first cell height in a plurality of first columns; Arranging a plurality of second cells having a second cell height in a plurality of second columns, wherein the second cell height is less than the first cell height, arranging the plurality of first columns and the plurality of second columns according to a wiring grid, the wiring grid comprising a plurality of first wiring traces extending in a first direction and a plurality of second wiring traces extending in a second direction, the second direction being perpendicular to the first direction; placing a plurality of first cell pins within each of the plurality of first cells, each of the plurality of first cell pins extending along a corresponding one of the plurality of second routing traces; identifying a plurality of via placement points in each of the plurality of second cells at respective intersections of a plurality of intersections between the plurality of first routing traces and the plurality of second routing traces; Selecting a subset of through-hole layout points from the plurality of through-hole layout points, wherein the subset of through-hole layout points corresponds to a group of second wiring traces among the plurality of second wiring traces, placing a plurality of second-cell pins for each second cell of the plurality of second cells along the group of second wiring traces, wherein if none or only one of a pair of first cells of the plurality of first cells adjacent to an opposite boundary of a corresponding second cell of the plurality of second cells includes a first-cell pin, a second-cell pin of the plurality of second-cell pins may be placed on a same second wiring trace as an adjacent first-cell pin of the plurality of first-cell pins; and The plurality of second unit pins are placed over the subset of through-hole placement points.

19. The system according to claim 18, characterized in that Each first cell pin of the plurality of first cell pins has opposite ends that terminate within boundaries of a corresponding first cell of the plurality of first cells.

20. The system according to claim 18, characterized in that At least one second cell pin of the plurality of second cell pins has an end extending across a corresponding common boundary between the corresponding first cell and the second cell.

21. A method for generating an integrated circuit layout diagram, characterized in that: Include: Arranging a first unit having a first unit height in a first column; Arranging a second cell having a second cell height in a second row adjacent to the first row, wherein the second cell height is different from the first cell height; placing a plurality of first unit pins within the first unit, wherein each of the plurality of first unit pins extends along a respective routing trace; as well as A plurality of second cell pins are placed over a plurality of selected through-hole layout points in the second cell, wherein at least one second cell pin of the plurality of second cell pins extends along a second routing trace across a boundary of the second cell and into the first cell.

22. The method according to claim 21, characterized in that Placing the plurality of second unit pins over the plurality of selected via layout sites includes determining whether a second unit pin of the plurality of second unit pins violates an end-to-end spacing requirement.

23. The method according to claim 22, characterized in that Also included is setting a position of the second unit pin in response to a determination that the end-to-end spacing requirement is met.

24. The method according to claim 22, characterized in that Also included is removing the second unit pin in response to a determination that the end-to-end spacing requirement is not met.

25. The method according to claim 21, characterized in that Also included is extending at least one of the plurality of second unit pins after the placing of the plurality of second unit pins.

26. The method according to claim 25, characterized in that Elongating the at least one of the plurality of second unit pins includes extending the at least one of the plurality of second unit pins across the boundary.

27. The method according to claim 21, characterized in that Also included is extending at least one of the plurality of first unit pins after the placing of the plurality of first unit pins.

28. The method according to claim 27, characterized in that Elongating the at least one of the plurality of first unit pins includes extending the at least one of the plurality of first unit pins across the boundary.

29. The method according to claim 21, characterized in that The method also includes manufacturing at least one mask for forming the first unit or the second unit.

30. A method for generating an integrated circuit layout diagram, characterized in that: The method includes: Arranging a plurality of cells in the layout diagram; and A plurality of cell pins are placed at a plurality of selected through-hole layout points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a wiring trace of a plurality of wiring traces over a boundary of the first cell and into a second cell of the plurality of cells adjacent to the first cell.

31. The method according to claim 30, characterized in that Placing the plurality of cell pins includes placing the plurality of cell pins based on a design rule.

32. The method according to claim 31, characterized in that The design rules include a minimum end-to-end spacing design rule.

33. The method according to claim 30, characterized in that Also includes: A plurality of through-hole layout locations within the first cell are identified, wherein placing the plurality of cell pins includes placing the plurality of cell pins based on the identified plurality of through-hole layout locations.

34. The method according to claim 30, characterized in that Placing the plurality of cell pins includes placing the plurality of cell pins using an automatic placement and routing tool.

35. The method according to claim 30, characterized in that Placing the plurality of unit pins includes placing the plurality of unit pins in a metal layer 2 of the layout diagram.

36. The method according to claim 30, characterized in that Also includes: At least one mask is manufactured based on the layout pattern for forming the integrated circuit.

37. A non-transitory computer-readable storage medium storing a plurality of instructions, characterized in that: When the plurality of instructions are executed by a processor, the processor is used to: Arranging a plurality of cells in a layout; and A plurality of cell pins are placed at a plurality of selected through-hole layout points in a first cell of the plurality of cells, wherein at least one cell pin of the plurality of cell pins extends along a wiring trace of a plurality of wiring traces over a boundary of the first cell and into a second cell of the plurality of cells adjacent to the first cell.

38. The non-transitory computer readable storage medium of claim 37, wherein: When the instructions are executed by the processor, the processor is caused to instruct a manufacturing device to manufacture a mask based on the placement of the plurality of cell pins.

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