Semiconductor substrate

Abstract

The present invention discloses a semiconductor substrate (10), comprising a dielectric insulating layer (110) and a first metallization layer (111) attached to the dielectric insulating layer (110). The dielectric insulating layer (110) comprises a first material (40) having a thermal conductivity between 25 and 180 W / mK and a dielectric strength between 15 and 50 kV / mm, and a second conductive or semiconductive material (41), wherein the second material (41) is uniformly distributed in the first material (40).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor substrate, and in particular to a semiconductor substrate for a power semiconductor module. Background Art

[0002] The power semiconductor module device generally includes a substrate in a housing. At least one substrate is arranged on the substrate. A semiconductor device including a plurality of controllable semiconductor components (e.g., two IGBTs in a half-bridge configuration) is generally arranged on at least one substrate. Each substrate generally includes a substrate layer (e.g., a ceramic layer), a first metallization layer deposited on a first side of the substrate layer, and a second metallization layer deposited on a second side of the substrate layer. The controllable semiconductor components are, for example, mounted on the first metallization layer. The first metallization layer may be a structured layer, while the second metallization layer is generally a continuous layer. The second metallization layer is generally attached to the substrate.

[0003] The heat generated by the controllable semiconductor components is dissipated through the substrate to the base plate or the heat sink. Since the first metallization layer is usually a structured layer, the electric field distribution that occurs in the substrate during use of the semiconductor device is not uniform and may cause local spikes. In areas of high electric field strength, local discharge effects may occur. These local discharge effects may lead to degradation of the substrate layer, which may shorten the life of the power semiconductor module device.

[0004] There is a need for an improved semiconductor substrate having good thermal conductivity and having increased resistance to partial discharge effects. Summary of the invention

[0005] The semiconductor substrate comprises: a dielectric insulating layer and a first metallization layer attached to the dielectric insulating layer. The dielectric insulating layer comprises a first material having a thermal conductivity between 25 and 180 W / mK and a dielectric strength between 15 and 50 kV / mm, and a second conductive or semiconductive material, wherein the second material is uniformly distributed within the first material.

[0006] The present invention can be better understood with reference to the following drawings and descriptions. The components in the drawings are not necessarily drawn to scale, but emphasis is placed on illustrating the principles of the present invention. In addition, in the drawings, similar reference numerals represent corresponding parts throughout the different views. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A cross-sectional view of a semiconductor substrate arrangement is shown.

[0008] Figure 2 Schematically shows Figure 1 A cross-sectional view of a portion of a semiconductor substrate device.

[0009] Figure 3 The crystal structure of aluminum nitride is schematically shown.

[0010] Figure 4 The structure of a semiconductor substrate according to an example is schematically shown.

[0011] Figure 5 The crystal structure of zirconium nitride is schematically shown.

[0012] Figure 6 A cross-sectional view of a semiconductor substrate arrangement having a semiconductor substrate according to an example is schematically shown.

[0013] Figure 7 The dielectric insulation layer is schematically shown.

[0014] Figure 8 A cross-sectional view of a multi-layer semiconductor substrate is schematically shown. DETAILED DESCRIPTION

[0015] In the following detailed description, reference is made to the accompanying drawings. The accompanying drawings show specific examples in which the present invention can be practiced. It should be understood that, unless otherwise specifically noted, the features and principles described with respect to the various examples can be combined with each other. In the specification and in the claims, certain elements are designated as "first element", "second element", "third element", etc., which should not be understood as enumeration. On the contrary, this designation is only used to address different "elements". That is, for example, the presence of a "third element" does not require the presence of a "first element" and a "second element". The semiconductor body described herein can be made of (doped) semiconductor material and can be a semiconductor chip or be included in a semiconductor chip. The semiconductor body has an electrically connected pad and includes at least one semiconductor element having an electrode.

[0016] Figure 1 A power semiconductor module device including a semiconductor substrate 10 is exemplarily shown. The semiconductor substrate 10 includes a dielectric insulating layer 110, a structured first metallization layer 111 attached to the dielectric insulating layer 110, and a second metallization layer 112 attached to the dielectric insulating layer 110. The dielectric insulating layer 110 is arranged between the first and second metallization layers 111, 112. The power semiconductor module device may further include a housing 50, wherein the housing 50 may include side walls and a cover.

[0017] Each of the first and second metallization layers 111, 112 may consist of or include one of the following materials: copper; copper alloy; aluminum; aluminum alloy; any other metal or alloy that remains solid during operation of the power semiconductor module device. The semiconductor substrate 10 is a ceramic substrate, i.e., a substrate in which the dielectric insulating layer 110 is a ceramic (e.g., a thin ceramic layer). The ceramic may consist of or include one of the following materials: aluminum oxide; aluminum nitride; zirconium oxide; silicon nitride; boron nitride; or any other dielectric ceramic. For example, the dielectric insulating layer 110 may consist of or include one of the following materials: Al 2 O 3 , AlN or Si 3 N 4 For example, the substrate may be, for example, a direct copper bonding (DCB) substrate, a direct aluminum bonding (DAB) substrate, or an active metal brazing (AMB) substrate. The dielectric insulating layer 110 generally includes a high insulation resistance while having a low thermal conductivity.

[0018] Typically, one or more semiconductor bodies 20 are arranged on the semiconductor substrate 10. Each of the semiconductor bodies 20 arranged on the semiconductor substrate 10 may include a diode, an IGBT (insulated gate bipolar transistor), a MOSFET (metal oxide semiconductor field effect transistor), a JFET (junction field effect transistor), a HEMT (high electron mobility transistor), or any other suitable controllable semiconductor element. The one or more semiconductor bodies 20 may form a semiconductor device on the semiconductor substrate. Figure 1 In FIG. 2 , two semiconductor bodies 20 are shown by way of example. However, any other number of semiconductor bodies 20 is also possible.

[0019] The semiconductor substrate 10 may be attached to a base plate or heat sink 30, and the second metallization layer 112 may be arranged between the dielectric insulating layer 110 and the base plate / heat sink 30. However, this is merely an example. Other semiconductor module devices are known in which the semiconductor substrate 10 includes only the first metallization layer 111, and in which the second metallization layer 112 is omitted. In such a power semiconductor module device, the dielectric insulating layer 110 may form a base plate and may be attached to the heat sink 30, without the second metallization layer 112 being arranged between the dielectric insulating layer 110 and the heat sink 30. The heat generated by the semiconductor body 20 may be dissipated to the base plate or heat sink 30 through the semiconductor substrate 10. This is Figure 1 This is exemplarily shown by thick arrows. Figure 1 The second metallization layer 112 of the semiconductor substrate 10 in FIG. 1 is a continuous layer. Figure 1 The first metallization layer 111 of the semiconductor substrate 10 is Figure 1Structured layer in the device shown. "Structured layer" means that the first metallization layer 111 is not a continuous layer, but includes recesses between different parts of the layer. Figure 1 Such a recess is schematically shown in . In this device, the first metallization layer 111 exemplarily includes four different parts. Different semiconductor bodies 20 can be mounted to the same or different parts of the first metallization layer 111. Different parts of the first metallization layer 111 may not have electrical connections, or may be electrically connected to one or more other parts using electrical connections such as bonding wires. The electrical connections may also include, for example, connecting plates or conductor tracks, which are just a few examples. However, it is only an example that the first metallization layer 111 is a structured layer. The first metallization layer 111 may also be a continuous layer.

[0020] During use of the power semiconductor module device, an electric field is generated within the device. Such an electric field may be unevenly distributed within the dielectric insulating layer 110. Typical voltages during use of the semiconductor device range up to 6500V ACRMS (root mean square), which, for example, generates electric field strengths of up to 60 kV / mm or even higher within the dielectric insulating layer 110, in particular in the area adjacent to the (structured) first metallization layer 111 (adjacent to the junction between the first metallization layer 111 and the dielectric insulating layer 110). Due to the high electric field strength, the insulation strength of the dielectric insulating layer 110 may be exceeded, resulting in local discharge effects in some parts of the dielectric insulating layer 110. The local discharge effect is typically a slow growth degradation of the ceramic material, typically close to the surface in the area where the junction is formed between the first metallization layer 111 and the dielectric insulating layer 110. This is particularly evident in the embodiment of the invention. Figure 2 It is schematically shown in FIG. Figure 1 A is a cross section of a semiconductor substrate 10. Figure 2 As can be seen in FIG. 1 , the degradation generally extends into the dielectric insulation layer 110 in a tree-like manner, thereby weakening the dielectric insulation layer 110 .

[0021] The degradation caused by partial discharge effects is related to several physical principles. On the one hand, as mentioned above, they depend on the electric field strength. On the other hand, they depend on the mean free length of the path within the dielectric insulating layer 110, which is the distance that a charged particle can be accelerated in the electric field. Cavities within the dielectric insulating material can serve as regeneration centers for partial discharges, because they can make the mean free length large enough to allow other free charge carriers to move to higher energy levels, which in turn may cause other free charge carriers to move to higher energy levels. In this way, an avalanche effect may occur.

[0022] As previously mentioned, the dielectric insulating layer 110 may include, for example, aluminum nitride (AlN). Figure 3 The crystal structure of AlN is shown in FIG.3+ and nitride N 3- The atoms are evenly distributed in the lattice. Ceramic crystals usually have a triangular or needle-shaped structure, such as Figure 3 . The crystals of other ceramic materials may also have similar structures. Such a crystal structure may promote the formation of cavities within the dielectric insulating layer 110, which may lead to the disadvantages outlined above.

[0023] like Figure 4 As schematically shown in FIG. 1 , according to an example, the dielectric insulating layer 110 includes a first material 40 and a second material 41. The first material 40 has a thermal conductivity between 25-180 W / mK and a dielectric strength between 15 and 50 kV / mm. As described above, the first material 40 may be, for example, a ceramic material. For example, the first material 40 may include Al 2 O 3 , AlN and Si 3 N 4 However, any other suitable material having a thermal conductivity between 25-180 W / mK and a dielectric strength between 15 and 50 kV / mm is also possible. The second material 41 may be added to the first material 40 and may be evenly distributed within the first material 40. Now referring to Figure 7 , the dielectric insulating layer 110 includes a first length l, a first width w and a first height h. The first height h corresponds to the first metallization layer 111 and the second metallization layer 112 ( Figure 7 The distance between the metallization layers 111, 112 is not shown in FIG. 1 . Therefore, the dielectric insulating layer 110 forms a first volume V=l*w*h. The second material 41 may be uniformly distributed in the entire volume V.

[0024] The second material 41 is a conductive or semiconductive material. Generally speaking, the first material 40 has a first specific resistance, and the second material 41 has a second specific resistance, wherein the second specific resistance is less than the first specific resistance. Therefore, compared to the dielectric insulation layer 110 formed only by the first material 40, adding a specific amount of the second material 41 to the first material 40 reduces the resistance of the dielectric insulation layer 110 to a certain extent and increases the conductivity of the dielectric insulation layer 110. Therefore, the amount of the second material 41 should be selected so that the sufficient insulation capability of the dielectric insulation layer 110 is still maintained. Adding a small amount of the second material 41 generally does not result in a significant reduction in the insulation properties of the dielectric insulation layer 110.

[0025] The amount of the second material 41 added to the first material 40 may depend on the type of the first material 40. For example, the amount of the second material 41 that may be added to AlN may be significantly lower than that that may be added to Si. 3 N 4In any case, the amount of the first material 40 can be greater than the amount of the second material 41. For example, the ratio between the amount of the first material 40 and the amount of the second material 41 can be less than 9:1. A dielectric insulating layer 110 including more than 10% of the second material 41 may not provide sufficient insulation strength. The amount of the second material 41 can depend on the type of first material 40 used for the dielectric insulating layer 110. For some types of first materials 40, the maximum amount of the second material 41 can be only about 5%. For most applications, the amount of the second material 41 within the dielectric insulating layer 110 can be between 5% and 10%. The second material 41 can include particles uniformly distributed within the lattice of the first material 40. The amount of the second material 41 within the first material 40 can be low enough so that multiple adjacent particles of the second material 41 do not form a conductive path.

[0026] exist Figure 4 , for convenience only, particles of the first material 40 and the second material 41 are schematically shown in circles. Figure 4 It is only used to illustrate the distribution of the second material 41 within the first material 40 in a very simple manner. Some particles of the second material 41 may be arranged adjacent to one of the surfaces of the dielectric insulating layer 110. Other particles may be surrounded by particles of the first material 40. The second material 41 may include particles having a particle size of, for example, less than 100 μm or less than 1 μm. The particle size may depend on the effect of the second material 41 on the mechanical properties of the dielectric insulating layer 110. For example, if the particle size of the second material 41 is too large, the fracture strength of the dielectric insulating layer 110 may be reduced. However, this depends on the first material 40 used to form the dielectric insulating layer 110.

[0027] The second material 41 may include, for example, ZrN, ZrO 2 and graphite. However, these materials are only examples. Any other suitable conductive or semiconductive material that is compatible with the first material 40 may be used. Compatible in this context means that particles of the second material 41 can be inserted into the crystal structure of the first material 40. Figure 5 The structure of ZrN is shown in FIG. Figure 5 As shown by the dotted line in , the ZrN structure has an octahedral shape. By adding this material of different shapes to the triangle of the ceramic material, the formation of cavities can be reduced. In addition, if a high electric field strength occurs near the particles of the second material 41, the selective field strain can be spread by the particles to a larger area with lower resistance, which can reduce the degradation of the ceramic material of the dielectric insulating layer 110 due to permanent selective electric field strain.

[0028] As can be seen from the above description, the second material 41 forms trapping centers within the first material 40, which reduces the average free length of the path for free charge carriers within the dielectric insulating layer 110. Therefore, the avalanche effect can be reduced or even prevented. The electric field is more uniformly distributed within the dielectric insulating layer 110.

[0029] According to one example, the first material 40 is silicon nitride Si 3 N 4 , and the second material is zirconium nitride ZrN. Silicon nitride generally has a very high fracture strength. However, silicon nitride is generally not suitable for high voltage applications requiring voltages exceeding 3300V AC RMS because it is susceptible to local discharge effects. Under high electric field strengths, silicon nitride tends to completely lose its insulating properties. For example, a dielectric insulating layer 110 formed of silicon nitride with a height h of 1 mm may lose its insulating properties at a voltage of about 8 to 10 kV AC RMS. Adding zirconium nitride, for example, to silicon nitride increases the electrical stability of the dielectric insulating layer 110. Compared to a dielectric insulating layer 110 comprising only silicon nitride, a dielectric insulating layer 110 comprising silicon nitride and a specific amount of zirconium nitride can be used for higher voltages. For example, for a layer comprising silicon nitride and a specific amount of zirconium nitride, there may be a voltage of 3300V ACRMS or higher. A pure silicon nitride substrate is typically used at a voltage of 1700V AC RMS or lower.

[0030] According to another example, the first material 40 is Al 2 O 3 , and the second material 41 is ZrO 2 According to another example, the first material 40 is AlN and the second material 41 is ZrN.

[0031] Figure 6 A power semiconductor module arrangement including a semiconductor substrate 10 is shown as an example, as described above with respect to Figures 3 to 5 The device is generally similar to Figure 1 However, as mentioned above, Figure 6 The semiconductor substrate 10 in the example includes a first material 40 and a second material 41. The dielectric insulating layer 110 including the first material 40 and the second material 41 can also be used in a multi-layer substrate, such as Figure 8 As shown schematically in Figure 8The multilayer substrate exemplarily shown in FIG. 1 further includes a second dielectric insulating layer 113. The first metallization layer 111 is arranged between the first dielectric insulating layer 110 and the second dielectric insulating layer 113, and the third metallization layer 114 is formed on the top surface of the second dielectric insulating layer 113. The first metallization layer 111 and the third metallization layer 114 are connected by a via 120 extending through the second dielectric insulating layer 113. The semiconductor body 20 is arranged on the third metallization layer 114. The first and second dielectric insulating layers 110, 113 may both include a first material 40 and a second material 41 uniformly distributed within the first material 40, as described above with reference to FIG. Figures 4 to 7 as described.

Claims

1. A power semiconductor module device, comprising a semiconductor substrate (10), wherein the semiconductor substrate (10) comprises: a dielectric insulating layer (110); as well as a first metallization layer (111) attached to the dielectric insulating layer (110); in The dielectric insulating layer (110) comprises a first material (40) having a thermal conductivity between 25 and 180 W / mK and a dielectric strength between 15 and 50 kV / mm, and a second conductive or semiconductive material (41), wherein the second conductive or semiconductive material (41) is distributed in the first material (40) so that the second conductive or semiconductive material (41) forms a trapping center in the first material (40), The amount of the second conductive or semiconductive material (41) in the dielectric insulating layer (110) is less than 10%, The first material (40) comprises one of AlN and Si3N4, and The second conductive or semiconductive material (41) comprises ZrN.

2. The power semiconductor module device according to claim 1, wherein: The dielectric insulating layer (110) comprises a first amount of the first material (40) and a second amount of the second conductive or semiconductive material (41), and wherein the first amount is greater than the second amount.

3. The power semiconductor module device according to claim 1, wherein: The amount of the second conductive or semiconductive material (41) in the dielectric insulating layer (110) is between 5% and 10%.

4. The power semiconductor module device according to claim 1, wherein: The second conductive or semiconductive material (41) comprises particles having a particle size of less than 100 μm.

5. The power semiconductor module device according to claim 4, wherein: The second conductive or semiconductive material (41) comprises particles having a particle size of less than 1 μm.

6. The power semiconductor module device according to any one of claims 1 to 5, wherein: The dielectric insulating layer (110) comprises a first length (l), a first width (w) and a first height (h), thereby forming a first volume (V), wherein the first height (h) corresponds to the distance between the first metallization layer (111) and a second metallization layer (112) attached to the dielectric insulating layer (110), and The second conductive or semiconductive material (41) is uniformly distributed throughout the first volume (V).

7. The power semiconductor module device according to any one of claims 1 to 5, wherein: The first material (40) has a first specific resistance, and the second conductive or semiconductive material (41) has a second specific resistance, and wherein the second specific resistance is smaller than the first specific resistance.

8. The power semiconductor module device according to any one of claims 1 to 5, wherein: The first metallization layer (111) is a structured metallization layer that only partially covers the first surface of the dielectric insulating layer (110).

9. The power semiconductor module device according to any one of claims 1 to 5, wherein: The semiconductor substrate (10) further comprises a second metallization layer (112) attached to the dielectric insulating layer (110), wherein the dielectric insulating layer (110) is disposed between the first metallization layer and the second metallization layer (111, 112).

10. The power semiconductor module device according to claim 9, wherein: The second metallization layer (112) is configured to be attached to a substrate or a heat sink (30).

11. The power semiconductor module arrangement according to any one of claims 1-5 and 10, further comprising at least one semiconductor body (20) mounted to the first metallization layer (111).

12. The power semiconductor module device according to any one of claims 1 to 5, further comprising a second dielectric insulation layer (113) and a third metallization layer (114), wherein The first metallization layer (111) is arranged between the dielectric insulating layer (110) and the second dielectric insulating layer (113); The second dielectric insulating layer (113) is arranged between the first metallization layer (111) and the third metallization layer (114); at least one semiconductor body (20) is mounted to the third metallization layer (114); and The second dielectric insulating layer (113) comprises the first material (40) and the second conductive or semiconductive material (41), wherein: The second conductive or semiconductive material (41) in the second dielectric insulating layer (113) is uniformly distributed within the first material (40) in the second dielectric insulating layer (113).

13. The power semiconductor module device according to any one of claims 1 to 5 and 10, further comprising at least one of the following: Housing (50); substrate; and Radiator (30).

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