Pixel

Abstract

A pixel is provided. The pixel includes: a substrate; a first electrode disposed on the substrate; a partition wall insulating layer disposed on the substrate to cover a first portion of the first electrode; a second electrode disposed on the partition wall insulating layer and including a second portion overlapping the first portion; and a light emitting element disposed on a first side surface between the first portion and the second portion of the partition wall insulating layer and connected to the first electrode and the second electrode.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2018-0134120, filed on November 5, 2018, which is hereby incorporated by reference in its entirety. Technical Field

[0002] The present disclosure herein relates to a pixel, a display device including the pixel, and a method for manufacturing the pixel. Background Art

[0003] Typically, a display device includes a plurality of pixels for displaying an image. Different types of pixels such as a pixel including a liquid crystal layer, a pixel including an electrowetting layer, a pixel including an electrophoretic layer, and a pixel including a light-emitting element are used to display an image. Among the different types of pixels, the light-emitting element can emit light by itself, and the display device including the light-emitting element does not require a separate light source.

[0004] Recently, ultra-small LED elements are being developed as light-emitting elements. Ultra-small LED elements are manufactured in nanometer or micrometer units and have a rod-like shape or a strip-like shape. Ultra-small LED elements are arranged horizontally and electrically connected to two electrodes with opposite polarities.

[0005] As technology develops, high-resolution display devices are required. However, since ultra-small LED elements are arranged horizontally, a space for arranging the ultra-small LED elements should be ensured. Therefore, there is a limitation in achieving high resolution of the display device. Summary of the invention

[0006] The present disclosure will provide a pixel capable of achieving high resolution, a display device including the pixel, and a method for manufacturing the pixel.

[0007] An embodiment of the inventive concept provides a pixel, which includes: a substrate; a first electrode disposed on the substrate; a partition wall insulating layer disposed on the substrate to cover a first portion of the first electrode; a second electrode disposed on the partition wall insulating layer and including a second portion overlapping the first portion; and a light emitting element disposed on a first side surface between the first portion and the second portion of the partition wall insulating layer and connected to the first electrode and the second electrode.

[0008] The pixel may further include a partition wall layer disposed between the substrate and the first electrode, wherein the first electrode is disposed on the substrate to cover the partition wall layer.

[0009] The partition wall insulating layer has a rectangular shape in cross section.

[0010] The light emitting element has a cylindrical shape and is vertically arranged in a direction crossing an upper surface of the substrate.

[0011] The first electrode includes: a first extension portion extending in a first direction; and a plurality of first branch portions branching from the first extension portion in a second direction intersecting the first direction, wherein the second electrode includes: a second extension portion extending in the first direction; and at least one second branch portion branching from the second extension portion in the second direction, wherein the second branch portions are arranged between the first branch portions.

[0012] The first part includes: each side of the first branch part, adjacent to one of the two sides of the second branch part, and the two sides of the second branch part are opposite to each other in the first direction; and a predetermined part of the first branch part, adjacent to each side of the first branch part, wherein the second part includes: both sides of the second branch part; and a predetermined part of the second branch part, adjacent to both sides of the second branch part.

[0013] The partition wall insulating layer includes an inorganic material.

[0014] The first electrode includes a reflective electrode.

[0015] The first electrode further includes a transparent electrode disposed on the reflective electrode.

[0016] The lower end of the light emitting element contacts the first electrode, wherein the side surface of the upper portion of the light emitting element contacts

[0017] The second portion, the upper portion of the light emitting element is defined as a predetermined portion of the light emitting element adjacent to the upper end of the light emitting element.

[0018] The pixel may further include an insulating layer disposed on the first electrode, the second electrode, and the light emitting element and having a defined opening exposing an upper portion and a second portion of the light emitting element.

[0019] The pixel may further include a contact electrode disposed in the opening and contacting the second electrode and an upper portion of the light emitting element.

[0020] The pixel may also include: a sub-insulating layer arranged between the light-emitting element and the partition wall insulating layer, between the light-emitting element and the second part, between the insulating layer and the second electrode, and between the insulating layer and the second side surface of the partition wall insulating layer, and the second side surface is defined as a side surface of the partition wall insulating layer other than the first side surface.

[0021] The first side surface is an inclined surface forming a predetermined inclined angle with respect to an upper surface of the substrate.

[0022] In an embodiment of the inventive concept, a display device includes a plurality of pixels, wherein each of the plurality of pixels includes: a substrate; a first electrode disposed on the substrate; a partition wall insulating layer disposed on the substrate to cover a first portion of the first electrode; a second electrode disposed on the partition wall insulating layer and including a second portion overlapping the first portion; and a light emitting element disposed on a first side surface between the first portion and the second portion of the partition wall insulating layer and connected to the first electrode and the second electrode.

[0023] In an embodiment of the inventive concept, a method for manufacturing a pixel includes: providing a partition wall layer on a substrate; providing a first electrode on the substrate to cover the partition wall layer; providing a partition wall insulating layer to cover a first portion of the first electrode, the partition wall insulating layer being provided on the substrate and spaced apart from the partition wall layer; providing a second electrode, the second electrode being provided on the partition wall insulating layer and including a second portion overlapping the first portion; providing a light-emitting element between the partition wall layer and the partition wall insulating layer; applying voltages of opposite polarities to the first electrode and the second electrode to provide a light-emitting element on a first side surface between the first portion and the second portion of the partition wall insulating layer, wherein the light-emitting element is connected to the first electrode and the second electrode.

[0024] In the method, a lower end of the light emitting element contacts the first electrode, wherein a side surface of an upper portion of the light emitting element contacts the second portion, the upper portion of the light emitting element being defined as a predetermined portion of the light emitting element adjacent to the upper end of the light emitting element.

[0025] The method may further include: providing an insulating layer on the substrate to cover the first electrode, the light emitting element, and the second electrode; removing a portion of the insulating layer overlapping an upper portion and a second portion of the light emitting element; providing an opening defined as the removed portion of the insulating layer, and providing a contact electrode on the insulating layer adjacent to the opening, wherein the contact electrode contacts the upper portion and the second electrode of the light emitting element.

[0026] In the method, the first electrode includes: a first extension portion extending in a first direction; and a plurality of first branch portions branching from the first extension portion in a second direction intersecting the first direction, wherein the second electrode includes: a second extension portion extending in the first direction; and at least one second branch portion branching from the second extension portion in the second direction, wherein the second branch portions are arranged between the first branch portions, wherein the first portion includes: each side of the first branch portion adjacent to one of the two sides of the second branch portion, the two sides of the second branch portion being opposite to each other in the first direction; and a predetermined portion of the first branch portion adjacent to each side of the first branch portion, wherein the second portion includes: both sides of the second branch portion; and a predetermined portion of the second branch portion adjacent to both sides of the second branch portion.

[0027] In the method, a cross section of the partition wall insulating layer has a rectangular shape, and the light emitting element has a cylindrical shape and is vertically arranged in a direction crossing an upper surface of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0029] Figure 1 is a plan view of a display device including a pixel according to an embodiment of the inventive concept;

[0030] Figure 2 yes Figure 1 An equivalent circuit diagram of a pixel shown in FIG.

[0031] Figure 3 yes Figure 2 A plan view of a first electrode and a second electrode connected to a light emitting element shown in FIG.

[0032] Figure 4 yes Figure 3 A perspective view of a light emitting element shown in FIG.

[0033] Figure 5 It is shown Figure 2 A view of an exemplary cross section of a pixel shown in FIG.

[0034] Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 , Fig.15 , Fig.16 , Fig.17 and Fig.18 is a view for explaining a method of manufacturing a pixel according to an embodiment of the inventive concept;

[0035] Fig.19 is a cross-sectional view of a pixel according to another embodiment of the inventive concept; and

[0036] Fig. 20 is a cross-sectional view of a pixel according to another embodiment of the inventive concept. DETAILED DESCRIPTION

[0037] In the specification, when a component (or region, layer, part, etc.) is referred to as being "on", "connected to" or "combined to" another component, this means that the component may be directly on, connected to or combined to the other component, or there may be a third component located between them.

[0038] The same reference numerals denote the same elements. In addition, in the drawings, the thickness, proportion, and size of components are exaggerated for efficient description.

[0039] “And / or” includes all combinations of one or more combinations defined by the relevant components.

[0040] It will be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The above terms are only used to distinguish one component from another component. For example, without departing from the scope of the inventive concept, a first component may be referred to as a second component, and vice versa. Unless the context clearly dictates otherwise, a singular expression includes a plural expression.

[0041] In addition, terms such as "below", "lower side", "on", and "upper side" are used to describe the relationship of the configurations shown in the drawings. These terms are described as relative concepts based on the directions shown in the drawings.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as the terms commonly understood by those skilled in the art to which the present invention belongs. In addition, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and unless the terms are interpreted in an ideal or overly formalized meaning, the terms are clearly defined here.

[0043] In various embodiments of the inventive concept, the terms "comprises", "includes" and their variations specify attributes, regions, fixed numbers, steps, processes, elements and / or components, but do not exclude other attributes, regions, fixed numbers, steps, processes, elements and / or components.

[0044] Hereinafter, embodiments of the inventive concept are described in more detail with reference to the accompanying drawings.

[0045] Figure 1 is a plan view of a display device including a pixel according to an embodiment of the inventive concept.

[0046] Reference Figure 1 , a display device DD according to an embodiment of the inventive concept may include a display panel DP, a scan driver SDV, and a data driver DDV. The scan driver SDV and the data driver DDV may be disposed on the display panel DP.

[0047] The display panel DP may have a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 crossing the first direction DR1. However, the inventive concept is not limited thereto, and the shape of the display panel DP may have various shapes such as a circular shape and a polygonal shape.

[0048] The plane area of ​​the display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may be an area for displaying an image, and the non-display area NDA may be an area not for displaying an image.

[0049] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, and a plurality of data lines DL1 to DLn. m and n are natural numbers. Illustratively, the pixels PX may be arranged in a matrix form, but the arrangement form of the pixels PX is not limited thereto.

[0050] The pixels PX may be disposed in the display area DA and connected to the scan lines SL1 to SLm and the data lines DL1 to DLn. Each pixel PX may include a light emitting element for displaying an image.

[0051] The scan driver SDV and the data driver DDV may be disposed in the non-display area NDA. The scan driver SDV may be disposed in the non-display area NDA adjacent to one of the long sides of the display panel DP. The data driver DDV may be disposed in the non-display area NDA adjacent to one of the short sides of the display panel DP. The data driver DDV may be manufactured in the form of an integrated circuit chip and mounted on the display panel DP.

[0052] The scan lines SL1 to SLm may each extend in the first direction DR1 and may be connected to the scan driver SDV. The data lines DL1 to DLn may each extend in the second direction DR2 and may be connected to the data driver DDV.

[0053] The scan driver SDV generates a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The scan signals may be sequentially applied to the pixels PX. The data driver DDV generates a plurality of data voltages, and the data voltages may be applied to the pixels PX through the data lines DL1 to DLn.

[0054] Although not shown in the drawings, the display device DD may include a timing controller for controlling the operation of the scan driver SDV and the data driver DDV. The timing controller may generate a scan control signal and a data control signal in response to a control signal received from the outside. The timing controller receives an image signal from the outside, converts the data format of the image signal so that the interface specification matches the data driver DDV, and provides the converted image data to the data driver DDV.

[0055] The scan driver SDV may generate a scan signal in response to the scan control signal. The data driver DDV is supplied with the image signal whose data format is converted, and may generate a data voltage corresponding to the image signal in response to the data control signal.

[0056] The data voltage may be supplied to the pixel PX in response to the scan signal, and the pixel PX may display an image by emitting light having a brightness corresponding to the data voltage.

[0057] Figure 2 yes Figure 1 Equivalent circuit diagram of the pixel shown in .

[0058] although Figure 2 It is shown in Figure 1 , but Figure 1 The other pixels PX shown in FIG. 1 may each have Figure 2 The same circuit diagram of the pixel PX shown in FIG. illustratively, Figure 2 Pixels PX connected to scan lines SLi and data lines DLj are shown in FIG. i and j are natural numbers.

[0059] Reference Figure 2 , the pixel PX may include a light emitting element ED, a driving element DT, a capacitive element C, and a switching element ST. A plurality of light emitting elements ED may be provided. Figure 3 A plurality of light emitting elements ED are shown in FIG.

[0060] The driving element DT and the switching element ST may be P-type transistors. However, the inventive concept is not limited thereto, and the driving element DT and the switching element ST may be N-type transistors. The capacitive element C may be a capacitor.

[0061] The driving element DT includes an input terminal connected to a first capacitor electrode of the capacitor element C and a first power line PL1, an output terminal connected to the light emitting element ED, and a control terminal connected to an output terminal of the switching element ST. The driving element DT may receive a first power supply voltage ELVDD through the first power line PL1. A second capacitor electrode of the capacitor element C may be connected to the control terminal of the driving element DT.

[0062] The switching element ST may include an input terminal connected to the data line DLj, an output terminal connected to the control terminal of the driving element DT, and a control terminal connected to the scan line SLi.

[0063] The light emitting element ED may be connected to the driving element DT and the second power line PL2. For example, the light emitting element ED may be connected to a first electrode E1 and a second electrode E2, the first electrode E1 being electrically connected to the driving element DT and the second electrode E2 being connected to the second power line PL2. The light emitting element ED may receive a second power voltage ELVSS through the second power line PL2. The second power voltage ELVSS may be a voltage having a level lower than the first power voltage ELVDD.

[0064] The scan signal is applied to the control terminal of the switching element ST through the scan line SLi, and the switching element ST may be turned on in response to the scan signal. The turned-on switching element ST may provide the data voltage received through the data line DLj to the first node N1.

[0065] The capacitance element C may be charged with an amount of charges corresponding to a difference between the data voltage supplied to the first node N1 and the first power source voltage ELVDD, and maintain the amount of charges even after the switching element ST is turned off.

[0066] The driving element DT may be turned on according to the amount of charge charged in the capacitive element C. The on time of the driving element DT may be determined according to the amount of charge charged in the capacitive element C. A current may be supplied to the light emitting element ED through the turned-on driving element DT, so that the light emitting element ED emits light. The light emitting element ED may emit light to generate an image.

[0067] The light emitting element ED may be an ultra-small LED element. The ultra-small LED element may be an LED device having a length of several nanometers to several hundred micrometers. The length of the ultra-small LED element is only an example, and the length of the ultra-small LED element is not limited to the above numerical range.

[0068] Figure 3 yes Figure 2 A plan view of a first electrode and a second electrode connected to a light emitting element shown in FIG.

[0069] Reference Figure 3 The first electrode E1 includes a first extension portion E1_1 extending in a first direction DR1 and a plurality of first branch portions E1_2 branching from the first extension portion E1_1 in a second direction DR2. Although two first branch portions E1_2 are illustratively shown, the number of the first branch portions E1_2 is not limited thereto. For example, one pixel PX may include more than two first branch portions E1_2.

[0070] The second electrode E2 may include a second extension portion E2_1 extending in the first direction DR1 and a second branch portion E2_2 branching from the second extension portion E2_1 in the second direction DR2. Illustratively, one second branch portion E2_2 is shown, but the inventive concept is not limited thereto, and one pixel PX may include two or more second branch portions E2_2.

[0071] The second branch portions E2_2 may be disposed between the first branch portions E1_2. When the plurality of second branch portions E2_2 are disposed to the second extension portion E2_1, the first branch portions E1_2 and the plurality of second branch portions E2_2 may be alternately arranged at 1:1 along the first direction DR1.

[0072] The first electrode E1 and the second electrode E2 may partially overlap each other. The first electrode E1 may include a first portion PT1 overlapping a predetermined portion of the second electrode E2. The second electrode E2 may include a second portion PT2 overlapping a predetermined portion of the first electrode E1.

[0073] The first portion PT1 may include each side of the two first branch portions E1_2 adjacent to one of both sides of the second branch portion E2_2 opposite to each other in the first direction DR1 and a predetermined portion of the first branch portion E1_2 adjacent to the each side of the first branch portion E1_2. The first portion PT1 may overlap the predetermined portion of the second branch portion E2_2.

[0074] The second portion PT2 may include both sides of the second branch portion E2_2 and predetermined portions of the second branch portion E2_2 adjacent to the both sides of the second branch portion E2_2. The second portion PT2 may overlap a predetermined portion of the first branch portion E1_2.

[0075] The pixel PX may include a plurality of light emitting elements ED. A direction perpendicular to a plane defined by the first direction DR1 and the second direction DR2 may be defined as a third direction DR3. When viewed in the third direction DR3, the light emitting elements ED may be disposed on both sides of the second branch portion E2_2.

[0076] A planar area of ​​the pixel PX may include a pixel area PA and a non-pixel area NPA around the pixel area PA. A light emitting element ED may be disposed in the pixel area PA.

[0077] Figure 4 yes Figure 3 A perspective view of a light emitting element is shown in FIG.

[0078] although Figure 4 One light emitting element ED is illustratively shown in FIG. 1 , but other light emitting elements ED will have the same Figure 4The structure of the light emitting element ED shown in FIG.

[0079] Reference Figure 4 , the light emitting element ED may have a cylindrical shape. However, the inventive concept is not limited thereto, and the light emitting element ED may have a polygonal columnar shape. The light emitting element ED may be vertically aligned and disposed on both sides of the second branch portion E2_2. Figure 3 As shown in FIG. 4 , the light emitting element ED may have a circular shape when viewed in the third direction DR3 .

[0080] The light emitting element ED may include an n-type semiconductor layer NS, a p-type semiconductor layer PS, and an active layer AL disposed between the n-type semiconductor layer NS and the p-type semiconductor layer PS. The n-type semiconductor layer NS may be formed by doping an n-type dopant into the semiconductor layer. The p-type semiconductor layer PS may be formed by doping a p-type dopant into the semiconductor layer. The semiconductor layer may include a semiconductor material. For example, the semiconductor layer may include GaN, AlN, AlGaN, InGaN, InN, InAlGaN, or AlInN, but is not limited thereto.

[0081] The n-type dopant may be silicon (Si), germanium (Ge), tin (Sn), selenium (Se), tellurium (Te) or a combination thereof, but is not limited thereto. The p-type dopant may be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba) or a combination thereof, but is not limited thereto.

[0082] The active layer AL may be formed of at least one of a single quantum well structure, a multi-quantum well structure, a quantum wire structure, and a quantum dot structure. The active layer AL may be a region where electrons injected through the n-type semiconductor layer NS and holes injected through the p-type semiconductor layer PS recombine. The active layer AL may be defined as a layer that emits light having energy determined by a material-specific energy band. The position of the active layer AL may vary depending on the type of diode.

[0083] The n-type semiconductor layer NS may be connected to one of the first electrode E1 and the second electrode E2. The p-type semiconductor layer PS may be connected to the other of the first electrode E1 and the second electrode E2.

[0084] The length LT of the light emitting element ED may be between a few nanometers and a few hundred micrometers. For example, the length LT of the light emitting element ED may be between 1 micrometer and 100 micrometers.

[0085] Figure 5 It is shown Figure 2 0047] Figure 2 is a diagram of an exemplary cross-section of a pixel shown in FIG.

[0086] Reference Figure 5The pixel PX may include a driving element DT, a switching element ST, a first electrode E1, a second electrode E2, and a light emitting element ED. The driving element DT, the switching element ST, the first and second electrodes E1 and E2, and the light emitting element ED may be disposed on the first base substrate BS1.

[0087] The second base substrate BS2 may face the first base substrate BS1. The driving element DT, the switching element ST, the first and second electrodes E1 and E2, and the light emitting element ED may be disposed between the first and second base substrates BS1 and BS2. The first and second base substrates BS1 and BS2 may each be a silicon substrate, a plastic substrate, a glass substrate, an insulating film, or a stacked structure including a plurality of insulating layers.

[0088] Since the configuration of the driving element DT and the configuration of the switching element ST are substantially the same, the configuration of the driving element DT will be mainly described below, and the configuration of the switching element ST will be briefly described or omitted.

[0089] The buffer layer BFL may be disposed on the first base substrate BS1. The buffer layer BFL may include an inorganic material. The driving element DT and the switching element ST may be disposed on the buffer layer BFL.

[0090] The driving element DT may include a first gate electrode GE1, a first source electrode SE1, a first drain electrode DE1, and a first semiconductor layer SM1. The switching element ST may include a second gate electrode GE2, a second source electrode SE2, a second drain electrode DE2, and a second semiconductor layer SM2.

[0091] The second gate electrode GE2 , the second source electrode SE2 , the second drain electrode DE2 , and the second semiconductor layer SM2 may have the same structures as the first gate electrode GE1 , the first source electrode SE1 , the first drain electrode DE1 , and the first semiconductor layer SM1 , respectively, and may be disposed on the same layer.

[0092] The first semiconductor layer SM1 may be disposed on the buffer layer BFL. The first semiconductor layer SM1 may include an organic semiconductor or a semiconductor of an inorganic material such as amorphous silicon or polycrystalline silicon. In addition, the first semiconductor layer SM1 may include an oxide semiconductor. Figure 5 , but the first semiconductor layer SM1 may include a source region, a drain region, and a channel region between the source region and the drain region.

[0093] The buffer layer BFL may provide a modified surface to the first semiconductor layer SM1. In this case, the first semiconductor layer SM1 may have a higher adhesion to the buffer layer BFL than when directly placed on the first base substrate BS1. The buffer layer BFL may be a barrier layer for protecting the lower surface of the first semiconductor layer SM1. In this case, the buffer layer BFL may prevent contaminants or moisture entering from the first base substrate BS1 itself or through the first base substrate BS1 from penetrating into the first semiconductor layer SM1.

[0094] The first insulating layer INS1 may be disposed on the buffer layer BFL to cover the first semiconductor layer SM1. The first insulating layer INS1 may include an inorganic material. For example, the first insulating layer INS1 may include silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, or aluminum oxide, but is not limited thereto.

[0095] The first gate electrode GE1 overlapping the first semiconductor layer SM1 may be disposed on the first insulating layer INS1. The first gate electrode GE1 may be disposed overlapping the channel region of the first semiconductor layer SM1. The second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the first gate electrode GE1. The second insulating layer INS2 may include an inorganic material.

[0096] Capacitor element C (in Figure 2 The first capacitor electrode may be branched from the second gate electrode GE2, and the second capacitor electrode CPa may be disposed on the second insulating layer INS2.

[0097] The third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the second capacitor electrode CPa. The third insulating layer INS3 may be defined as an interlayer insulating layer. The third insulating layer INS3 may include an organic material and / or an inorganic material.

[0098] The first source electrode SE1 and the first drain electrode DE1 may be spaced apart from each other and disposed on the third insulating layer INS3. The first source electrode SE1 is connected to the source region of the first semiconductor layer SM1 through a first contact hole CH1 defined by the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3. The first drain electrode DE1 is connected to the drain region of the first semiconductor layer SM1 through a second contact hole CH2 defined by the first insulating layer INS1, the second insulating layer INS2, and the third insulating layer INS3.

[0099] The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the first source electrode SE1 and the first drain electrode DE1. The fourth insulating layer INS4 may be defined as a planarization film providing a planar upper surface, and may include an organic material.

[0100] A layer in which the first base substrate BS1 , the buffer layer BFL, and the first to fourth insulating layers INS1 to INS4 are disposed may be defined as a first substrate SUB1 .

[0101] The partition wall layer BR and the partition wall insulating layer BRI may be disposed spaced apart from each other and disposed on the first substrate SUB1. The partition wall layer BR may include an organic material, and the partition wall insulating layer BRI may include an inorganic material, but are not limited thereto.

[0102] The first electrode E1 may be disposed on the first substrate SUB1 to cover the partition wall layer BR. For example, the first electrode E1 may be disposed on the partition wall layer BR and disposed on a portion of the first substrate SUB1 adjacent to the partition wall layer BR. Therefore, the partition wall layer BR may be disposed between the first substrate SUB1 and the first electrode E1.

[0103] The first electrode E1 may be connected to the first drain electrode DE1 through a third contact hole CH3 defined by the fourth insulating layer INS4 of the first substrate SUB1. Thus, the first electrode E1 may be electrically connected to the driving element DT.

[0104] The first electrode E1 may have a single-layer structure or a multi-layer structure. For example, the first electrode E1 may include a reflective electrode, or may include a reflective electrode and a transparent electrode disposed on the reflective electrode.

[0105] The reflective electrode may include copper (Cu), aluminum (Al) and silver (Ag) that can reflect light. The transparent electrode may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO) and mixtures / composites thereof that can transmit light.

[0106] The partition wall insulating layer BRI may have a rectangular cross-section. Therefore, the side surfaces SS1 and SS2 of the partition wall insulating layer BRI may extend in a direction perpendicular to the upper surface of the first substrate SUB1. The upper surface of the first substrate SUB1 may be a plane defined by the first direction DR1 and the second direction DR2, and the direction perpendicular to the upper surface of the first substrate SUB1 may be a third direction DR3.

[0107] The partition wall insulating layer BRI may be disposed on the first substrate SUB1 to cover the first portion PT1 of the first electrode E1. As described above, the first portion PT1 may be a portion of the first electrode E1 overlapping the second electrode E2.

[0108] Hereinafter, a side surface of the partition wall insulating layer BRI adjacent to the first portion PT1 and disposed between the first portion PT1 and the second portion PT2 is defined as a first side surface SS1. A side surface of the partition wall insulating layer BRI other than the first side surface SS1 is defined as a second side surface SS2. The second electrode E2 may be disposed on the upper surface US of the partition wall insulating layer BRI, and may not be disposed on the first side surface SS1 and the second side surface SS2.

[0109] The light emitting element ED may extend in the third direction DR3 and be disposed on the first side surface SS1. The light emitting element ED may contact the first side surface SS1. The light emitting element ED may be electrically connected to the first electrode E1 and the second electrode E2.

[0110] The lower end of the light emitting element ED may contact the first electrode E1 to be electrically connected to the first electrode E1. The upper portion of the light emitting element ED (defined as a predetermined portion of the light emitting element ED adjacent to the upper end of the light emitting element ED) contacts the second electrode E2 to be electrically connected to the second electrode E2. The second portion PT2 of the second electrode E2 may contact the upper side surface of the light emitting element ED.

[0111] The fifth insulating layer INS5 may be disposed on the first substrate SUB1. The fifth insulating layer INS5 may be disposed on the first electrode E1, the second electrode E2, and the light emitting element ED. An opening OP for exposing the upper portion and the second portion PT2 of the light emitting element ED may be defined in the fifth insulating layer INS5. The fifth insulating layer INS5 may include an inorganic material.

[0112] The contact electrode CE may be disposed in the opening OP and disposed on the fifth insulating layer INS5 adjacent to the opening OP. However, the inventive concept is not limited thereto, and the contact electrode CE may not be disposed on the fifth insulating layer INS5 but may be disposed only in the opening OP. The contact electrode CE may contact the upper portion of the light emitting element ED and the second electrode E2 through the opening OP.

[0113] The contact electrode CE may include a transparent material. For example, the contact electrode CE may include at least one of indium zinc oxide (IZO), indium tin oxide (ITO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), and mixtures / composites thereof, and is not limited thereto.

[0114] Since the lower end of the light emitting element ED has a circular plane, it can be in surface contact with the upper surface of the first electrode E1. However, since the light emitting element ED has a cylindrical shape, the upper side surface of the light emitting element ED, which is a cylindrical side surface, can be in line contact with the second portion PT2. Line contact has a smaller contact area than surface contact, and as the contact area is smaller, the contact resistance can be larger. The resistance may interfere with the flow of current.

[0115] The upper end of the light emitting element ED having a rounded plane may be electrically connected to the second portion PT2 through the contact electrode CE. That is, basically, the contact area may be increased through the contact electrode CE, so that the contact resistance between the light emitting element ED and the second electrode E2 may be reduced.

[0116] The sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the contact electrode CE. The sixth insulating layer INS6 may be a sealing layer.

[0117] The light conversion layer LCL and the black matrix BM may be disposed on one surface of the second base substrate BS2 facing the first base substrate BS1. The light conversion layer LCL may be disposed in the pixel area PA, and the black matrix BM may be disposed in the non-pixel area NPA. Some pixels PX may not include the light conversion layer LCL.

[0118] The light conversion layer LCL may include an emitter. For example, the emitter may convert the wavelength of the first color light provided from the light emitting element ED to emit a second color light having a different color from the first color light. The emitter may be a quantum dot. The first color light may be blue light, and the second color light may be red light or green light.

[0119] Pixels PX including a light conversion layer LCL for converting blue light into red light, pixels PX including a light conversion layer LCL for converting blue light into green light, and pixels PX not including a light conversion layer LCL may be disposed on the display panel DP. Therefore, red light, blue light, and green light may be generated by the pixels PX.

[0120] However, the embodiments of the inventive concept are not limited thereto. For example, the light conversion layer LCL may be replaced with a color filter. In addition, the light conversion layer LCL may be omitted from the pixel PX. In this case, the light emitting element ED may emit blue light, green light, or red light. The black matrix BM may prevent light leakage between pixels.

[0121] A layer in which the second base substrate BS2 , the light conversion layer LCL, and the black matrix BM are disposed may be defined as a second substrate SUB2 .

[0122] The seventh insulating layer INS7 may be disposed between the first substrate SUB1 and the second substrate SUB2. The seventh insulating layer INS7 may be an optically transparent adhesive film, an optically transparent adhesive resin, or a pressure-sensitive adhesive film. However, this is only an example, and in another embodiment of the inventive concept, the seventh insulating layer INS7 may be omitted.

[0123] In an embodiment of the inventive concept, the light emitting element ED may be arranged vertically and connected to the first electrode E1 and the second electrode E2. Therefore, the arrangement area of ​​the light emitting element ED may be reduced compared to when the light emitting element ED is arranged horizontally. Since the arrangement area of ​​the light emitting element ED may be reduced, a greater number of light emitting elements ED may be provided to the display device DD. As a result, a high resolution of the display device DD may be achieved.

[0124] Figures 6 to 18 is a view for explaining a method of manufacturing a pixel according to an embodiment of the inventive concept.

[0125] For ease of explanation, Figures 6 to 18 A portion of the partition wall layer BR and a portion of the partition wall insulating layer BRI are shown. In addition, the first substrate SUB1 is not divided into the first base substrate BS1, the buffer layer BFL, and the first to fourth insulating layers INS1 to INS4, but is shown as a single layer. The second substrate SUB2 and the seventh insulating layer INS7 are omitted.

[0126] Reference Figure 6 A partition wall layer BR is disposed on the first substrate SUB1, and a first electrode E1 is disposed on the first substrate SUB1 to cover the partition wall layer BR. An insulating layer IL may be disposed on the first substrate SUB1 to cover the first electrode E1. A conductive layer CL may be disposed on the insulating layer IL.

[0127] The insulating layer IL may include the same material as that of the partition wall insulating layer BRI, and the conductive layer CL may include the same material as that of the second electrode E2. The insulating layer IL may be disposed on the first substrate SUB1 to form the partition wall insulating layer BRI, and the conductive layer CL may be disposed on the insulating layer IL to form the second electrode E2.

[0128] A first photoresist pattern PR1 may be disposed on the conductive layer CL. The first photoresist pattern PR1 may be disposed in a region for forming the partition wall insulating layer BRI and the second electrode E2. For example, a photoresist (or photosensitive resin) may be disposed on the conductive layer CL. Hereinafter, the photoresist around the region for forming the partition wall insulating layer BRI and the second electrode E2 is exposed and developed and removed, so that the first photoresist pattern PR1 is disposed on the conductive layer CL.

[0129] Reference Figure 7 and Figure 8, the conductive layer CL and the insulating layer IL around the area for forming the partition wall insulating layer BRI and the second electrode E2 may be removed using the first photoresist pattern PR1 as a mask. Therefore, the partition wall insulating layer BRI and the second electrode E2 may be disposed on the first substrate SUB1. The partition wall insulating layer BRI may be disposed on the first substrate SUB1 to cover the first portion PT1, and the second electrode E2 may be disposed on the upper surface US of the partition wall insulating layer BRI. After forming the partition wall insulating layer BRI and the second electrode E2, the first photoresist pattern PR1 may be removed.

[0130] Reference Fig. 9 and Fig.10 , a light emitting element ED may be disposed on the first substrate SUB1. For example, a solution LQ containing the light emitting element ED may be provided between the partition wall layer BR and the partition wall insulating layer BRI. The solution LQ may be ink or paste. The solution LQ may be a substance that can be evaporated at room temperature or by heating.

[0131] Since voltages of opposite polarities can be applied to the first electrode E1 and the second electrode E2, an electric field can be formed between the first electrode E1 and the second electrode E2. A DC voltage or an AC voltage can be applied to the first electrode E1 and the second electrode E2. Bipolarity is induced in the light emitting element ED by the electric field, and the light emitting element ED can be self-aligned between the first electrode E1 and the second electrode E2 by an electrophoretic force.

[0132] The second electrode E2 is spaced apart from and disposed above the first electrode E1, and the partition wall insulating layer BRI is disposed between the first portion PT1 and the second portion PT2 so that the light emitting element ED can be vertically aligned. The vertically aligned light emitting element ED can be disposed on the first side surface SS1 of the partition wall insulating layer BRI.

[0133] As described above, the lower end of the light emitting element ED contacts the first electrode E1 to be electrically connected to the first electrode E1 , and the upper portion of the light emitting element ED contacts the second electrode E2 to be electrically connected to the second electrode E2 .

[0134] Reference Fig.11 An insulating layer IL' may be disposed on the first substrate SUB1 to cover the first electrode E1, the second electrode E2, and the light emitting element ED. The insulating layer IL' includes the same material as that of the fifth insulating layer INS5 and may be disposed on the first substrate SUB1 to form the fifth insulating layer INS5.

[0135] Reference Fig.12, a second photoresist pattern PR2 may be provided on the insulating layer IL'. The second photoresist pattern PR2 may be provided around the region for forming the opening OP. For example, a photoresist is provided on the insulating layer IL', and the photoresist in the region for forming the opening OP is exposed, developed, and removed, so that the second photoresist pattern PR2 may be provided on the insulating layer IL'.

[0136] Reference Fig.13 and Fig.14 , the insulating layer IL' of the region for forming the opening OP is removed using the second photoresist pattern PR2 as a mask, so that a fifth insulating layer INS5 defining the opening OP may be disposed on the first substrate SUB1. The upper portion and the second portion PT2 of the light emitting element ED may be exposed through the opening OP. After forming the fifth insulating layer INS5, the second photoresist pattern PR2 may be removed.

[0137] Reference Fig.15 , a conductive layer CL' may be disposed in the opening OP and on the fifth insulating layer INS5. The conductive layer CL' includes the same material as that of the contact electrode CE and may be disposed on the first substrate SUB1 to form the contact electrode CE.

[0138] Reference Fig.16 , a third photoresist pattern PR3 may be disposed on the conductive layer CL'. The third photoresist pattern PR3 may be disposed to overlap the opening OP and a region adjacent to the opening OP. For example, a photoresist is disposed on the conductive layer CL', and the photoresist around the region for forming the contact electrode CE is exposed, developed, and removed, so that the third photoresist pattern PR3 may be disposed on the conductive layer CL'.

[0139] Reference Fig.17 and Fig.18 The conductive layer CL' around the area for forming the contact electrode CE is removed using the third photoresist pattern PR3 as a mask so that the contact electrode CE can be disposed on the first substrate SUB1. The contact electrode CE can be disposed at the opening OP to contact the upper portion and the second portion PT2 of the light emitting element ED.

[0140] After forming the contact electrode CE, the third photoresist pattern PR3 may be removed, and a sixth insulating layer INS6 may be disposed on the fifth insulating layer INS5 to cover the contact electrode CE.

[0141] Although not shown in the drawings, thereafter, a second substrate SUB2 may be disposed on the first substrate SUB1, and a seventh insulating layer INS7 may be disposed between the first substrate SUB1 and the second substrate SUB2.

[0142] According to the method of manufacturing a pixel according to an embodiment of the inventive concept, the light emitting element ED can be vertically arranged and connected to the first electrode E1 and the second electrode E2. As a result, the arrangement area of ​​the light emitting element ED can be reduced, and a larger number of light emitting elements ED can be provided to the display device DD, so that a high resolution of the display device DD can be achieved.

[0143] Fig.19 is a cross-sectional view of a pixel according to another embodiment of the inventive concept.

[0144] For ease of explanation, Fig.19 The pixel PX_1 shown in FIG. 1 is shown in FIG. Fig.18 Therefore, a cross section of a part of the configuration of the pixel PX_1 is shown, and other configurations are omitted.

[0145] Basically, the pixel PX_1 may have the same Figure 5 Therefore, the sub-insulating layer SINS will be described below, and the same elements are denoted by the same reference numerals.

[0146] Reference Fig.19 , the sub-insulating layer SINS may be disposed between the light emitting element ED and the partition wall insulating layer BRI and between the light emitting element ED and the second portion PT2. In addition, the sub-insulating layer SINS is disposed between the fifth insulating layer INS5 and the second electrode E2, between the fifth insulating layer INS5 and the second side surface SS2, and between the fifth insulating layer INS5 and the first substrate SUB1.

[0147] The sub-insulating layer SINS may include an inorganic material. The fifth insulating layer INS5 may protect the second electrode E2, and further, the sub-insulating layer SINS is disposed on the side surface of the second portion PT2 and on the second electrode E2, so that the second electrode E2 may be further protected.

[0148] An upper portion of the light emitting element ED is insulated from the second portion PT2 by the sub-insulating layer SINS, and the light emitting element ED may be electrically connected to the second portion PT2 through the contact electrode CE.

[0149] Fig. 20 is a cross-sectional view of a pixel according to another embodiment of the inventive concept.

[0150] For ease of explanation, Fig. 20 The pixel PX_2 shown in FIG. Fig.18 Therefore, a cross section of a part of the structure of the pixel PX_2 is shown, and other structures are omitted.

[0151] Basically, the pixel PX_2 may have the same Figure 5 Therefore, the first side surface SS1' and the second side surface SS2' of the partition wall insulating layer BRI' will be described, and the same elements are denoted by the same reference numerals.

[0152] Reference Fig. 20 , the cross section of the partition wall insulating layer BRI' may have a trapezoidal shape. Figure 5 Unlike the first side surface SS1 and the second side surface SS2 shown in the figure, the first side surface SS1' and the second side surface SS2' of the partition wall insulating layer BRI' may be inclined surfaces having a predetermined inclination angle relative to the upper surface of the first substrate SUB1. Illustratively, the inclination angle may be less than 90 degrees and greater than 0 degrees, and may preferably be less than 90 degrees and greater than or equal to 45 degrees.

[0153] The light emitting element ED may be disposed on the first side surface SS1 ′ having the inclined surface to be electrically connected to the first electrode E1 and the second electrode E2 .

[0154] According to an embodiment of the inventive concept, since the light emitting element of the pixel is vertically arranged and connected to the first electrode and the second electrode, the arrangement area of ​​the light emitting element can be reduced. Therefore, a display device including a pixel according to an embodiment of the inventive concept can achieve high resolution.

[0155] Although exemplary embodiments of the inventive concept have been described, it should be understood that the inventive concept should not be limited to these exemplary embodiments, and various changes and modifications may be made by those skilled in the art within the spirit and scope of the inventive concept as claimed.

Claims

1. A pixel, comprising: substrate; A first electrode is disposed on the substrate; a partition wall insulating layer, disposed on the substrate to cover a first portion of the first electrode; a second electrode disposed on the partition wall insulating layer and including a second portion overlapping the first portion; as well as A light-emitting element is arranged on a first side surface of the partition wall insulating layer between the first portion and the second portion and is connected to the first electrode and the second electrode, wherein a portion of the first electrode overlapping with the light-emitting element does not overlap with the second electrode in a thickness direction.

2. The pixel according to claim 1, further comprising a partition wall layer disposed between the substrate and the first electrode, in, The first electrode is disposed on the substrate to cover the partition wall layer.

3. The pixel according to claim 1, wherein: The partition wall insulating layer has a rectangular shape in cross section.

4. The pixel according to claim 1, wherein: The light emitting element has a cylindrical shape and is vertically arranged in a direction intersecting an upper surface of the substrate.

5. The pixel according to claim 1, wherein: The first electrode includes: a first extending portion extending in a first direction; and a plurality of first branch portions branching from the first extending portion in a second direction intersecting the first direction. The second electrode includes: a second extending portion extending in the first direction; and at least one second branch portion branching from the second extending portion in the second direction. Wherein, the second branch portion is arranged between the plurality of first branch portions.

6. The pixel according to claim 5, wherein: The first portion includes: each side of the plurality of first branch portions, adjacent to one of the two sides of the second branch portion, the two sides of the second branch portion being opposite to each other in the first direction; and a predetermined portion of the plurality of first branch portions, adjacent to each side of the plurality of first branch portions, The second portion includes: the two sides of the second branch portion; and a predetermined portion of the second branch portion, adjacent to the two sides of the second branch portion.

7. The pixel according to claim 1, wherein: The partition wall insulating layer includes an inorganic material.

8. The pixel according to claim 1, wherein: The first electrode includes a reflective electrode.

9. The pixel according to claim 8, wherein: The first electrode further includes a transparent electrode disposed on the reflective electrode.

10. The pixel according to claim 1, wherein: The lower end of the light emitting element contacts the first electrode, The side surface of the upper portion of the light emitting element contacts the second portion, and the upper portion of the light emitting element is defined as a predetermined portion of the light emitting element adjacent to an upper end of the light emitting element. 11 . The pixel according to claim 10 , further comprising an insulating layer disposed on the first electrode, the second electrode, and the light emitting element, and having a defined opening exposing the upper portion and the second portion of the light emitting element. 12 . The pixel according to claim 11 , further comprising a contact electrode disposed in the opening and contacting the second electrode and the upper portion of the light emitting element.

13. The pixel according to claim 12, further comprising: A sub-insulating layer is arranged between the light-emitting element and the partition wall insulating layer, between the light-emitting element and the second part, between the insulating layer and the second electrode, and between the insulating layer and the second side surface of the partition wall insulating layer, and the second side surface is defined as the side surface of the partition wall insulating layer other than the first side surface.

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