Flash memory device and related method

Abstract

Flash memory technology is disclosed. In one example, a flash memory cell may include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Related systems and methods are also disclosed.

Description

Technical Field

[0001]

[0014] Embodiments described herein relate generally to computer memory and, more particularly, to flash memory devices. Background Art

[0002] Flash memory is a type of computer memory that uses floating-gate transistors (such as metal-oxide-semiconductor field-effect transistors) as memory cells to store information. Commercial flash memory is based on the NAND and NOR memory types. In NAND memory, cells are arranged in an array such that the control gates of each memory cell in a row are connected to form an access line, such as a word line. A column of the array includes a string of memory cells (often referred to as a NAND string) connected in series, source to drain, between a pair of select lines (source select line and drain select line). The source select line includes a source select gate at each intersection between a NAND string and a source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and a drain select line. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as a column bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Technical features and advantages will be apparent from the following detailed description taken in conjunction with the accompanying drawings, which together illustrate various technical embodiments by way of example; and wherein:

[0004] Figure 1 illustrates a portion of a NAND memory device according to an example embodiment;

[0005] Figure 2 Pictured Figure 1 A detailed view of a portion of a conductive channel and memory cell of a NAND memory device;

[0006] Figures 3A to 3D A method for manufacturing a flash memory cell according to an example embodiment is illustrated;

[0007] Figures 4A to 4D A method for manufacturing a flash memory cell according to another example embodiment is illustrated; and

[0008] Figure 5 is a schematic diagram of an exemplary computing system.

[0009] Reference will now be made to the exemplary embodiments illustrated, and specific language will be used herein to describe the same. However, it will be understood that no limitation is intended to the scope of the disclosure or the specific inventive embodiments.

[0010] Description of Embodiments

[0011] Before disclosing and describing technical embodiments, it should be understood that there is no intention to limit the specific structures, processing steps or materials disclosed herein, but rather to include their equivalents as will be recognized by those skilled in the relevant art. It should also be understood that the terms used herein are only for the purpose of describing specific examples and are not intended to be limiting. The same reference numerals in different figures represent the same elements. The numbers provided in the flow charts and processes are provided to clearly illustrate the steps and operations and do not necessarily indicate a specific order or sequence. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this disclosure belongs.

[0012] As used in this written description, the singular forms "a," "an," and "the" include explicit support for plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes explicit support for a plurality of such layers.

[0013] In this application, the words "comprising," "including," "containing," and "having" may have the meanings ascribed to them in U.S. patent law and may mean "include" and "comprising," and are generally to be interpreted as open-ended terms. The terms "consisting of" or "consisting of" are closed terms and include only the components, structures, steps, etc. specifically listed in conjunction with such terms, as well as the components, structures, steps, etc. according to U.S. patent law. "Consisting essentially of" or "consisting essentially of" have the meanings generally ascribed to them in U.S. patent law. In particular, such terms are generally closed terms except where permitted to include additional items, materials, components, steps, or elements that do not materially affect the basic and novel characteristic or function of the item(s) with which they are used. For example, the presence of a trace element in a composition that does not affect the properties or characteristics of the composition would be permissible under "consisting essentially of" language, even if not explicitly recited in the list of items following such terminology. When open-ended terms like "comprising" or "including" are used in a written description, it is understood that direct support is also given to "consisting essentially of" language and "consisting of" language, and vice versa, as expressly stated.

[0014] The terms "first," "second," "third," and "fourth," etc., as used in the description and in the claims, if any, are used to distinguish between similar elements and not necessarily to describe a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable where appropriate, such that the embodiments described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Similarly, if a method is described herein as comprising a series of steps, the order of such steps presented herein is not necessarily the only order in which such steps may be performed, and some of the stated steps may be omitted, and / or some other steps not described herein may be added to the method.

[0015] The terms "left," "right," "front," "back," "top," "bottom," "upper," and "lower," etc., as used in the specification and claims, if any, are used for descriptive purposes and are not necessarily intended to describe permanent relative positioning. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that, for example, the embodiments described herein are capable of operation in orientations other than those illustrated or otherwise described herein.

[0016] As used herein, the term "coupled" is defined as connected directly or indirectly by electrical or non-electrical means. Structures or elements that are "directly coupled" are in physical contact with each other. Objects described herein as being "adjacent" to each other can be in physical contact with each other, in close proximity to each other, or in the same general area or region as applicable to the context in which the phrase is used.

[0017] As used herein, comparative terms such as "increase," "decrease," "better," "worse," "higher," "lower," "enhance," "maximize," and "minimize" refer to a property of a device, component, or activity that is measurably different from a property of other comparable devices, components, or activities, or from a property in a different iteration or embodiment of the same device or the prior art.

[0018] As used herein, the term "substantially" refers to the degree or degree of completeness or near-completeness of an action, characteristic, property, state, structure, item, or result. For example, "substantially" containing an object will mean that it is completely contained or almost completely contained. In some cases, the precise degree of permissible deviation from absolute completeness may depend on the specific context. However, generally speaking, a degree of near-completeness will have the same overall result as if absolute completeness and overall completeness were achieved. The use of "substantially" can also be applied in a negative sense to refer to the complete or near-complete lack of an action, characteristic, property, state, structure, item, or result. For example, a composition that is "substantially free" of particles will completely lack particles, or almost completely lack particles, and its effect will be the same as if it completely lacked particles. In other words, a composition that is "substantially free" of a certain component or element may still actually contain such an item (component or element) as long as there is no measurable effect of such an item.

[0019] As used herein, the term "about" is used to provide flexibility to a numerical range endpoint by providing that a given value may be "a little above" or "a little below" the endpoint.

[0020] As used herein, for convenience, multiple items, structural elements, component elements, and / or materials may be presented in common lists. However, these lists should be interpreted as if each member of the list were individually identified as a separate and unique member. Therefore, in the absence of contrary indications, any individual member of such a list should not be interpreted as being in fact equivalent to any other member of the same list solely based on their appearance in a common group.

[0021] Concentration, amount, size and other numerical data can be expressed or presented in range format in this article.It is to be understood that such range format is only used for convenience and simplicity, and therefore should be flexibly interpreted as not only including the numerical value clearly enumerated as the limitation of scope, but also including all individual numerical values ​​or subranges contained in this scope, as each numerical value and subrange are all clearly enumerated.As an illustration, the numerical range of "about 1 to about 5" should be interpreted as not only including the value of about 1 to about 5 clearly enumerated, but also including the individual value and subrange in the indicated range.Therefore, included in this numerical range are individual values ​​such as 2,3 and 4, and subranges such as from 1 to 3, from 2 to 4 and from 3 to 5, and individual 1, 2, 3, 4 and 5.

[0022] This same principle applies to ranges that recite only one numerical value as a minimum or maximum. Furthermore, such an interpretation should apply regardless of the breadth of the range or characteristic being described.

[0023] Throughout this specification, reference to "one example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one embodiment. Thus, the appearances of the phrase "in an example" in various places throughout this specification do not necessarily all refer to the same embodiment. In this document, the appearances of the phrase "in one embodiment" or "in one aspect" do not necessarily all refer to the same embodiment or aspect.

[0024] Furthermore, in one or more embodiments, the described features, structures, or characteristics may be combined in any suitable manner. In this specification, many specific details are provided, such as layout examples, distances, network examples, etc. However, those skilled in the relevant art will recognize that many variations are possible without one or more of the specific details or with other methods, components, layouts, measurements, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail, but are considered to be well within the scope of this disclosure. DETAILED DESCRIPTION

[0025] The following provides an initial overview of the technical embodiments, and then further describes specific technical embodiments in detail. This initial summary is intended to help readers understand the technology more quickly, but is not intended to identify the key or essential features of the technology, nor is it intended to limit the scope of the claimed subject matter.

[0026] The data density of flash memory devices can be increased by increasing the number of bits of information stored per memory cell. For example, single-level cells (SLC) store only one bit per cell, so-called multi-level cells (MLC) store two bits per cell, triple-level cells (TLC) store three bits per cell, quad-level cells (QLC) store four bits per cell, and so on. However, one drawback of increasing data density is the increase in the number of voltage states required to store information. For example, SLC requires only two voltage states, while MLC requires four, TLC requires eight, and QLC requires 16 to store the required number of bits of information per cell. Therefore, increasing data density in this way reduces the margin for separating voltage states and increases the likelihood of errors.

[0027] As data density increases, it is desirable to increase the program erase window (PEW) to reduce or otherwise minimize the likelihood of errors. The PEW is limited by the programming saturation voltage threshold. The interlayer dielectric (IPD) material between the charge storage structure and the control gate can be designed to control electron "leakage", which is a significant factor limiting the programming saturation voltage threshold. A typical IPD configuration utilizes no more than three dielectric layers in an oxide-nitride-oxide (ONO) configuration. While this IPD configuration has been sufficient for lower data densities, it has not produced the desired results for increased data densities (such as for QLC and higher data densities).

[0028] Thus, disclosed are flash memory cells and structures that provide increased data density capacity by modifying the IPD layer structure, which can be designed to provide an energy band that reduces IPD electron leakage and thus increases the programmed saturation voltage threshold and PEW. One exemplary mechanism by which cell performance can be improved is by increasing the number of IPD layers, such as including four or more IPD layers. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated devices, systems, and methods are also disclosed.

[0029] refer to Figure 1, illustrates a portion of a flash memory device 100. The figure shows a cross-section of the flash memory device with a vertically oriented cross-section to illustrate various features and geometries of the flash memory device 100 in the vertical cross-section. Generally, this portion of the flash memory device includes a memory pillar or conductive channel 110, and memory cells 120a-120n (i.e., a string 126 of memory cells, such as a NAND string) located adjacent to the conductive channel 110. Any suitable number of memory cells may be included. The conductive channel 110 may be made of any suitable material (e.g., polysilicon, germanium (e.g., Ge or SiGe), SiC, a high bandgap and high mobility material (e.g., ZnO, indium gallium zinc oxide (IGZO), GaP), etc.), such that the conductive channel can serve as a channel region for the memory cells 120a-120n that can be coupled in series. For example, during operation of one or more of the memory cells 120a-120n of the string, an electrical channel may form in the conductive channel 110. In some embodiments, the conductive channel 110 may have a hollow interior filled with an insulating material 115, such as an oxide material. The conductive channel 110 and the string of memory cells 120a-120n may be vertically oriented, such as in a three-dimensional memory array. For example, the memory cell 120a is located at a vertical level (e.g., near the bottom of the memory array) that is higher than the vertical level (e.g., near the top of the memory array) where the memory cell 120n is located. Typically, the conductive channel 110 will have a generally cylindrical configuration, and the structure of each memory cell 120a-120n will be arranged in a concentric ring structure radially outward from the conductive channel.

[0030] Each memory cell 120a-120n in this example can be a non-volatile memory cell and can have a charge storage structure, such as a floating gate, which can be a conductor (e.g., polysilicon), a charge trap, which can be a dielectric, etc. Non-limiting examples of conductive or semiconductive materials suitable for the floating gate include polysilicon, silicided or non-silicided metals (such as Ru, Pt, Ge), where the metal can be continuous or discontinuous. Non-limiting examples of dielectrics suitable for the charge trap include nitrides, silicon-rich dielectrics, or SiON / Si3N4. The tunnel dielectric for charge trap-based devices can have multiple layers (e.g., oxide / nitride / oxide (O / N / O)) rather than a single dielectric layer, which is the typical structure of a floating gate tunnel dielectric.

[0031] like Figure 2 As shown in Figure 2 A portion of a conductive channel 110 and a portion of a representative memory cell 120 are shown (in FIG. Figure 1As shown in a detailed view of the memory cell 120 (indicated by the region indicated at 115 in FIG), the memory cell 120 may have a charge storage structure 121. Each memory cell 120a-120n may be a non-volatile memory cell (e.g., a floating gate MOSFET, a charge trap, etc.). The charge storage structure 121 may be a floating gate made of any suitable material (e.g., polysilicon, SiN, metal silicide, etc.) with any suitable properties (e.g., conductivity and charge trapping / storage / isolation). Each memory cell 120a-120n may also have a tunnel dielectric layer interposed between its charge storage structure and the conductive channel 110. For example, the memory cell 120 may have a tunnel dielectric layer 113 interposed between the charge storage structure 121 and the conductive channel 110. The tunnel dielectric layer between the charge storage structure and the conductive channel may include any suitable dielectric material. For example, the tunnel dielectric layer 113 may include an oxide material (e.g., silicon oxide), ONO (oxide / nitride / oxide), etc. Furthermore, each memory cell 120a-120n can have a control gate that is laterally separated from the charge storage structure (e.g., as part of or coupled to an access line (such as a word line)). For example, memory cell 120 can include a control gate 130 that is laterally separated from charge storage structure 121, such that charge storage structure 121 is positioned between control gate 130 and conductive channel 110. Control gate 130a can comprise any suitable conductive or semiconductive material. For example, control gate 130 can comprise polysilicon (e.g., doped or undoped polysilicon), tungsten, or other metals.

[0032] Each memory cell 120a-120n may have at least four dielectric materials or dielectric layers (i.e., interlayer dielectric layers) interposed between its charge storage structure and control gate, which may serve as blocking dielectrics. For example, memory cell 120 may include dielectric layers 122-125 interposed between charge storage structure 121 and control gate 130. The dielectric layers between the charge storage structure and the control gate may include any suitable dielectric material, and two or more of the dielectric layers may have the same or different material compositions. For example, dielectric layer 122 adjacent to charge storage structure 121 may include a nitride material (e.g., silicon nitride), an oxide material (e.g., aluminum oxide), or a high-k dielectric constant material (e.g., HfOx, HfAlOx, AlOx, and ZrOx). Dielectric layer 123 may include an oxide material (e.g., silicon oxide), an oxynitride material (e.g., silicon oxynitride), a high-k dielectric constant material (e.g., HfSiOx, HfOx, AlOx, and ZrOx), etc. Dielectric layer 124 may include a nitride material (e.g., silicon nitride), an oxide material (e.g., silicon oxide), or the like. Dielectric layer 125 may include an oxide material (e.g., silicon oxide), an oxynitride material (e.g., silicon oxynitride), a high-k dielectric material (e.g., HfSiOx, HfOx, AlOx, and ZrOx), or the like. In some embodiments, dielectric layers 123-125 may include alternating layers of oxide material (e.g., silicon oxide) and nitride material (e.g., silicon nitride), thereby forming an ONO (oxide / nitride / oxide) configuration in successive layers 123-125. In the case of dielectric layer 122, dielectric layers 122-125 may be formed as a NONO (nitride / oxide / nitride / oxide) or an AONO (AlOx / oxide / nitride / oxide) configuration in successive layers 122-125.

[0033] Further references Figure 1 and Figure 2 , an insulating layer or spacer 140 (e.g., a dielectric such as an oxide material (e.g., silicon oxide); an oxynitride material (e.g., silicon oxynitride); a nitride material (e.g., silicon nitride), etc.) can be vertically spaced apart from another insulating layer or spacer 140 interposed between the memory cells 120a-120n in the string 126. The conductive channel 110 can extend vertically along (e.g., through) the insulating layer 140, and the charge storage structures of the memory cells 120a-120n can be at least partially disposed between adjacent insulating layers 140.

[0034] like Figure 1As shown in FIG, dielectric 141 may be interposed between one end of string 126 (e.g., memory cell 120a) and select gate 111, and dielectric 142 may be interposed between the opposite end of string 126 (e.g., memory cell 120n) and select gate 112. Each memory cell 120a-120n of string 126 may be coupled in series with a select gate (e.g., drain select gate) 111 adjacent to (e.g., in contact with) conductive channel 110 and a select gate (e.g., source select gate) 112 adjacent to (e.g., in contact with) conductive channel 110, and may be located therebetween. Conductive channel 110 is electrically coupled to a data line (e.g., bit line 116) indicated at 117. Thus, select gate 111 can selectively couple string 126 to a data line (e.g., bit line 116). Furthermore, conductive channel 110 is electrically coupled to source line 118 indicated at 119. Thus, select gate 112 can selectively couple string 126 to source line 118. For example, select gate 111 can be coupled in series with memory cell 120a, and select gate 112 can be coupled in series with memory cell 120n. Select gates 111 and 112 can each include a gate dielectric 113 adjacent to (e.g., in contact with) conductive channel 110 and a control gate 114 adjacent to (e.g., in contact with) the corresponding gate dielectric 113.

[0035] Certain features of the memory cells 120a-120n may be configured to provide performance benefits. Figure 2 Describe the sizes, geometries, and relationships of the various memory cell components. As a schematic representation, Figure 2 Certain features are not necessarily depicted as they would be found in an actual memory cell. For example, straight lines shown in the figures may not be exactly straight, and sharp angles may be rounded. Therefore, some leeway exists when characterizing the shape of the cell geometry.

[0036] In one aspect, including four or more dielectric layers 122-125 can be configured to improve the performance of memory cell 120. For example, the energy bands of dielectric layers 122-125 can be designed such that charge leakage through dielectric layers 122-125 is significantly (e.g., orders of magnitude) reduced compared to typical dielectric layer configurations including three or fewer layers, which can result in a higher programmed saturation voltage than currently achievable and, therefore, increase PEW. Furthermore, dielectric layer 122 can eliminate charge gain from dielectric layer 124 in the cell's erased state.

[0037] In one aspect, the thickness 101 of dielectric layer 122 adjacent to charge storage structure 121 can be configured to provide performance benefits. Dielectric layer 122 can have any suitable thickness 101. In some embodiments, thickness 101 of dielectric layer 122 can be from approximately 1 nm to approximately 5 nm, and thickness 101 can be "tuned" to tailor the energy bands of dielectric layers 122-125. In one aspect, dielectric layer 122 can be relatively thin compared to the other dielectric layers 123-125. For example, the ratio of thickness 101 of dielectric layer 122 to the thickness of any of dielectric layers 123-125 (e.g., thickness 102 of dielectric layer 123, in one embodiment) can be from approximately 1:2 to approximately 1:5. The relative thicknesses of dielectric layers 122-125 can be configured to tailor the energy bands of the dielectric layers.

[0038] In one aspect, one or more of dielectric layers 122-125 and / or charge storage structure 121 can be configured to have a specific shape or geometry. For example, in some embodiments, dielectric layer 122 and charge storage structure 121 can be configured such that dielectric layer 122 is adjacent to at least a portion of three sides 127-129 of charge storage structure 121. In this case, at least a portion of dielectric layer 122 adjacent to sides 127 and 129 of charge storage structure 121 can be disposed between charge storage structure 121 and spaced-apart insulating layer 140. This configuration of dielectric layer 122 and charge storage structure 121 can reduce charge leakage and, therefore, provide an increased programmed saturation voltage.

[0039] Thus, as compared to conventional memory cells currently known or having no more than three IPD layers, the inclusion of four or more dielectric layers 122-125, the thickness 101 of dielectric layer 122 adjacent to charge storage structure 121, and / or the relationship between dielectric layer 122 and charge storage structure 121 can be configured to improve the performance of memory cell 120. For example, by designing the energy bands of dielectric layers 122-125 to minimize or control charge leakage, a suitable programmed saturation voltage can be provided for a given memory cell design. For example, dielectric layers 122-125 can be configured to provide a band gap sufficient for QLC operation. In other words, dielectric layers 122-125 can be configured to provide a PEW sufficient for QLC operation.

[0040] Figures 3A-3D Illustrated are aspects of an exemplary method or process for manufacturing a flash memory cell that is included in a flash memory assembly or device as disclosed herein. Figure 3AA schematic diagram illustrates a side cross-sectional view of a control gate 230 between vertically spaced insulating layers 240. Three dielectric layers 223-225 are formed adjacent to each other between the insulating layers 240, with dielectric layer 225 adjacent to the control gate 230. The structure can be formed using any suitable process or technique known in the art. For example, the control gate 230 geometry can be formed by removing conductive material between the insulating layers 240, such as by utilizing a wet and / or dry cutting (e.g., etching) process. The dielectric layers 223-225 can be formed on the control gate 230 in the recess or gap between the insulating layers 240 using deposition and oxidation processes. Any suitable oxidation and / or deposition process can be used. Wet and / or dry cutting (e.g., etching) processes can also be used to achieve the desired shape or geometry of the dielectric layers 223-225. For example, material can be deposited, oxidized (e.g., grown), and at least partially removed to form the dielectric layers 223-225. In one embodiment, a material may be deposited and oxidized to form an oxide layer 225 (e.g., silicon oxide), a material may be deposited to form a nitride layer 224 (e.g., silicon nitride), and a material may be deposited and oxidized to form an oxide layer 223 (e.g., silicon oxide). Thus, alternating layers of oxide material (e.g., silicon oxide) and nitride material (e.g., silicon nitride) may be formed.

[0041] like Figure 3B As shown in FIG, fourth dielectric layer 222 may be formed on or adjacent to dielectric layer 223. As described above, dielectric layer 222 may be formed by any suitable process or technique known in the art. In one embodiment, material may be deposited to form nitride layer 222 (e.g., silicon nitride). Dielectric layer 222 may have a thickness of from approximately 1 nm to approximately 5 nm. Dielectric layer 222 may be relatively thin compared to the other dielectric layers 223-225. For example, the ratio of the thickness of dielectric layer 222 to the thickness of any of the other dielectric layers 223-225 (e.g., dielectric layer 223) may be from approximately 1:2 to approximately 1:5. Although dielectric layer 222 is relatively thin, its presence reduces the space available for the other dielectric layers 223-225. Therefore, in one embodiment, the thickness of individual dielectric layers 223-225 or any combination of dielectric layers 223-225 may be reduced to accommodate the thickness of dielectric layer 222. For example, dielectric layer 223 and / or dielectric layer 224 may be reduced in thickness by an amount equal to the thickness of dielectric layer 222. Although four dielectric layers are shown, it should be appreciated that any number of four or more dielectric layers may be formed or included in a memory cell as disclosed herein.

[0042] Figure 3B-3DIt may refer to a process in which the fourth dielectric layer 222 (ie, the dielectric layer closest to or adjacent to the charge storage structure 221) is formed of a nitride material (eg, silicon nitride). Figure 3C As shown in FIG, a conductive layer 250 may then be formed on the dielectric layer 222. The conductive layer 250 may include any suitable conductive material (such as polysilicon), which may be conductively doped (e.g., to N+ type conductivity). The conductive layer 250 material will form the final charge storage structure 221 adjacent to the dielectric layer 222 (see FIG. Figure 3D ). Conductive layer 250 may be formed by any suitable process or technique, such as a deposition process. A portion of conductive layer 250 may be removed (e.g., by etching and / or oxidation cutting) to expose portions 251, 252 of dielectric layer 222. The presence of dielectric layer 222 may preserve underlying materials, such as insulating layer 240 and / or dielectric layer 223, during the removal of portions of conductive layer 250.

[0043] like Figure 3C As shown in FIG, the exposed portions 251, 252 of the dielectric layer 222 and a portion of the conductive layer 250 may be oxidized to form (eg, grow) a continuous vertical oxide layer 253, as shown in FIG. Figure 3D As shown in FIG. A portion of the conductive layer 250 material may be converted to form a tunnel dielectric layer (e.g., tunnel oxide) 213 and simultaneously form the final shape of the charge storage structure 221. Tunnel dielectric layer 213 may thus be formed on the charge storage structure 221. Any suitable oxidation process may be utilized. The composition of the oxide material will depend on the type of material being oxidized. In some embodiments, dielectric layer 222 and charge storage structure 221 may be configured such that dielectric layer 222 is adjacent to at least portions of three sides 227-229 of charge storage structure 221. After forming charge storage structure 221 and tunnel dielectric layer 213, a suitable semiconductor material (e.g., polysilicon, Ge, SiGe, SiC, etc.) may be disposed (e.g., deposited) on tunnel dielectric layer 213 to form conductive channel 210. In some embodiments, the conductive channel may have a hollow interior, which may be filled with an insulating material (e.g., oxide). In one aspect, when forming the oxide layer 253 , the conversion of the exposed dielectric layer 222 portions 251 , 252 to oxide can enable the formation of a straight conductive channel 210 , as well as enable scaling of the size of the conductive channel 210 .

[0044] Figures 4A-4D Aspects of other exemplary methods or processes for manufacturing a flash memory cell included in a flash memory assembly or device, such as flash memory assembly or device 100, are illustrated. The process may be similar to that described above with reference to Figure 3ABegin as described, with a control gate 330 formed between insulating layers 340, and three dielectric layers 323-325 formed between insulating layers 340 on the control gate 330. In one embodiment, a material may be deposited and oxidized to form an oxide layer 325 (e.g., silicon oxide), a material may be deposited to form a nitride layer 324 (e.g., silicon nitride), and a material may be deposited and oxidized to form an oxide layer 323 (e.g., silicon oxide). Thus, alternating layers of oxide material (e.g., silicon oxide) and nitride material (e.g., silicon nitride) may be formed. Figure 4B As shown in FIG, the fourth dielectric layer 322 may be formed on or adjacent to the dielectric layer 323. As described above, the dielectric layer 322 may be formed by any suitable process or technique known in the art. In the following discussion of an embodiment in which the fourth dielectric layer 322 (i.e., the dielectric layer closest to or adjacent to the charge storage structure 321) is formed of an oxide material (e.g., aluminum oxide), Figure 4B-4D .

[0045] like Figure 4C As shown in FIG, a conductive layer 350 may be formed on the dielectric layer 322. The conductive layer 350 may include any suitable conductive material (such as polysilicon), which may be conductively doped (e.g., to N+ type conductivity). The conductive layer 350 material will form the final charge storage structure 321 adjacent to the dielectric layer 322 (see FIG. Figure 4D ). Conductive layer 350 can be formed by any suitable process or technique, such as a deposition process. Portions of conductive layer 350 and dielectric layer 322 can be removed (e.g., by etching and / or oxidation cutting) to expose portions 354 and 355 of dielectric layer 323. The presence of dielectric layer 323 can preserve underlying materials, such as insulating layer 340 and / or dielectric layer 324, during the removal of portions of conductive layer 350 and dielectric layer 322.

[0046] like Figure 4DAs shown in FIG, a portion of the conductive layer 350 material may be oxidized to form (e.g., grow) a tunnel dielectric layer (e.g., tunnel oxide) 313. For example, a portion of the conductive layer 350 may be converted to form the tunnel dielectric layer 313 and simultaneously form the final shape of the charge storage structure 321. Tunnel dielectric layer 313 may thus be formed on the charge storage structure 321. Any suitable oxidation process may be utilized. The composition of the oxide material will depend on the type of material being oxidized. In some embodiments, dielectric layer 322 and charge storage structure 321 may be configured such that dielectric layer 322 is adjacent to at least portions of three sides 327-329 of the charge storage structure 321. After forming the charge storage structure 321 and tunnel dielectric layer 313, a suitable semiconductor material (e.g., polysilicon, Ge, SiGe, SiC, etc.) may be disposed (e.g., deposited) on tunnel dielectric layer 313 to form the conductive channel 310. In some embodiments, the conductive channel may have a hollow interior, which may be filled with an insulating material (e.g., an oxide).

[0047] Although the present disclosure is provided in the context of NAND flash memory devices (e.g., 3D NAND flash memory), it should be recognized that certain aspects of the present disclosure may also be applicable to NOR flash memory, charge trap flash memory (e.g., VNAND), or other memories that utilize floating gate metal oxide semiconductor field effect transistors (FGMOSFETs) as memory cells.

[0048] Figure 5 An example computing system 460 is illustrated. The computing system 460 may include a memory device (e.g., flash memory) 400 coupled to a motherboard 461 as disclosed herein. In one aspect, the computing system 460 may also include a processor 462, a memory device 463, a radio 464, a heat sink 465, a port 466, a slot, or any other suitable device or component that may be operably coupled to the motherboard 461. The computing system 460 may include any type of computing system, such as a desktop computer, a laptop computer, a tablet computer, a smartphone, a wearable device, a server, etc. Other embodiments need not include Figure 5 All features specified in and may include Figure 5 Alternative features not specified in .

[0049] The circuits used in the electronic components or devices (e.g., die) of a memory device may include hardware, firmware, program code, executable code, computer instructions, and / or software. Electronic components and devices may include non-transitory computer-readable storage media, which may be computer-readable storage media that does not include signals. In the case of executing program code on a programmable computer, the computing device described herein may include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and / or storage elements, including those described herein), at least one input device, and at least one output device. The volatile and non-volatile memory and / or storage elements may be RAM, EPROM, a flash drive, an optical drive, a magnetic hard drive, a solid-state drive, or other media for storing electronic data, including the memory disclosed herein. Nodes and wireless devices may also include a transceiver module, a counter module, a processing module, and / or a clock module or a timer module. One or more programs that can implement or utilize any of the techniques described herein may use application programming interfaces (APIs), reusable controls, and the like. Such programs may be implemented using high-level procedural or object-oriented programming languages ​​to communicate with the computer system. However, if desired, the program(s) can be implemented in assembly language or machine language. In any case, the language can be a compiled or interpreted language and combined with hardware implementation.

[0050] Example

[0051] The following examples relate to further embodiments.

[0052] In one example, a flash memory cell is provided that includes a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure.

[0053] In one example of a memory cell, one of the at least four dielectric layers is adjacent to the charge storage structure and includes a nitride material.

[0054] In one example of a memory cell, the nitride material includes silicon nitride.

[0055] In one example of a memory cell, one of the at least four dielectric layers is adjacent to the charge storage structure and includes an oxide material.

[0056] In one example of a memory cell, the oxide material includes aluminum oxide.

[0057] In one example of a memory cell, one of the at least four dielectric layers is adjacent to the charge storage structure and includes a high dielectric constant material.

[0058] In one example of a memory cell, the high dielectric constant material includes HfOx, HfAlOx, or a combination thereof.

[0059] In one example of the memory cell, one of the at least four dielectric layers is adjacent to at least a portion of three sides of the charge storage structure.

[0060] In one example of a memory cell, the at least four dielectric layers include alternating layers of oxide material and nitride material.

[0061] In one example of a memory cell, the oxide material includes silicon oxide.

[0062] In one example of a memory cell, the nitride material includes silicon nitride.

[0063] In one example of a memory cell, one of the at least four dielectric layers is adjacent to the charge storage structure and has a thickness of about 1 nm to about 5 nm.

[0064] In one example of a memory cell, a first layer of the at least four dielectric layers is adjacent to the charge storage structure, and a ratio of a thickness of the first layer to a thickness of the second layer of the at least four dielectric layers is about 1:2 to about 1:5.

[0065] In one example of a memory cell, the second layer is adjacent to the first layer.

[0066] In one example of a memory cell, the at least four dielectric layers are configured to provide a program erase window sufficient for operating a quad level cell (QLC).

[0067] In one example of a memory cell, the at least four dielectric layers are configured to provide a bandgap sufficient for operating a quad level cell (QLC).

[0068] In one example of a memory cell, the charge storing structure is a floating gate or a charge trap.

[0069] In one example, a flash memory device is provided, comprising: a plurality of insulating layers vertically spaced apart from one another; a vertically oriented conductive channel extending through the plurality of insulating layers; a charge storage structure disposed between adjacent insulating layers; a control gate laterally separated from the charge storage structure such that the charge storage structure is between the control gate and the conductive channel; and at least four dielectric layers disposed between the control gate and the charge storage structure.

[0070] In one example of a flash memory device, one of the at least four dielectric layers is adjacent to the charge storage structure and includes a nitride material.

[0071] In one example of a flash memory device, the nitride material includes silicon nitride.

[0072] In one example of a flash memory device, one of the at least four dielectric layers is adjacent to the charge storage structure and includes an oxide material.

[0073] In one example of a flash memory device, the oxide material includes aluminum oxide.

[0074] In one example of a flash memory device, one of the at least four dielectric layers is adjacent to the charge storage structure and includes a high dielectric constant material.

[0075] In one example of a flash memory device, the high dielectric constant material includes HfOx, HfAlOx, or a combination thereof.

[0076] In one example of a flash memory device, one of the at least four dielectric layers is adjacent to at least a portion of three sides of the charge storage structure.

[0077] In one example of the flash memory device, the at least four dielectric layers include alternating layers of oxide material and nitride material.

[0078] In one example of a flash memory device, the oxide material includes silicon oxide.

[0079] In one example of a flash memory device, the nitride material includes silicon nitride.

[0080] In one example of a flash memory device, one of the at least four dielectric layers is adjacent to the charge storage structure and has a thickness from about 1 nm to about 5 nm.

[0081] In one example of a flash memory device, a first layer of the at least four dielectric layers is adjacent to the charge storage structure, and a ratio of a thickness of the first layer to a thickness of the second layer of the at least four dielectric layers is about 1:2 to about 1:5.

[0082] In one example of a flash memory device, the second layer is adjacent to the first layer.

[0083] In one example of a flash memory device, the at least four dielectric layers are configured to provide a program erase window sufficient for operating a quad level cell (QLC).

[0084] In one example of a flash memory device, the at least four dielectric layers are configured to provide a bandgap sufficient for operating a quad level cell (QLC).

[0085] In one example of a flash memory device, the charge storage structure is a floating gate or a charge trap.

[0086] In one example, a flash memory device includes a tunnel dielectric layer disposed between a charge storage structure and a conductive channel.

[0087] In one example of the flash memory device, the plurality of insulating layers include oxide material, oxynitride material, nitride material, or a combination thereof.

[0088] In one example of a flash memory device, the conductive channel includes polysilicon material, Ge, SiGe, SiC, or a combination thereof.

[0089] In one example, a computing system is provided, comprising: a motherboard and a flash memory device operatively coupled to the motherboard. The flash memory device comprises: a plurality of insulating layers vertically spaced apart from one another; a vertically oriented conductive channel extending through the plurality of insulating layers; a charge storage structure disposed between adjacent insulating layers; a control gate laterally separated from the charge storage structure such that the charge storage structure is between the control gate and the conductive channel; and at least four dielectric layers disposed between the control gate and the charge storage structure.

[0090] In one example of a computing system, the computing system includes a desktop computer, a laptop computer, a tablet computer, a smartphone, a wearable device, a server, or a combination thereof.

[0091] In one example of the computing system, the computing system further includes a processor, a memory device, a heat sink, a radio device, a slot, a port, or a combination thereof operably coupled to the motherboard.

[0092] In one example, a method for manufacturing a flash memory device is provided, comprising: forming at least four dielectric layers between adjacent vertically spaced insulating layers, wherein a first layer of the at least four dielectric layers is adjacent to a control gate between the insulating layers; and forming a charge storage structure adjacent to a second layer of the at least four dielectric layers, such that the charge storage structure is laterally separated from the control gate, and the at least four dielectric layers are between the control gate and the charge storage structure.

[0093] In one example of the method for manufacturing a flash memory device, a second layer of the at least four dielectric layers includes a nitride material.

[0094] In one example of a method for manufacturing a flash memory device, the nitride material includes silicon nitride.

[0095] In one example of the method for manufacturing a flash memory device, the second layer is formed by depositing a nitride material.

[0096] In one example of the method for manufacturing a flash memory device, a second layer of the at least four dielectric layers includes an oxide material.

[0097] In one example of a method for manufacturing a flash memory device, the oxide material includes aluminum oxide.

[0098] In one example of the method for manufacturing a flash memory device, the second layer is formed by depositing an oxide material.

[0099] In one example of the method for manufacturing a flash memory device, a second layer of the at least four dielectric layers includes a high dielectric constant material.

[0100] In one example of a method for manufacturing a flash memory device, the high dielectric constant material includes HfOx, HfAlOx, or a combination thereof.

[0101] In one example of the method for manufacturing a flash memory device, the second layer is formed by depositing a high dielectric constant material.

[0102] In one example of a method for manufacturing a flash memory device, the second layer is adjacent to at least a portion of three sides of the charge storage structure.

[0103] In one example of a method for manufacturing a flash memory device, the at least four dielectric layers include alternating layers of oxide material and nitride material.

[0104] In one example of a method for manufacturing a flash memory device, the oxide material includes silicon oxide.

[0105] In one example of a method for manufacturing a flash memory device, the nitride material includes silicon nitride.

[0106] In one example of the method for manufacturing a flash memory device, a second layer of the at least four dielectric layers has a thickness from about 1 nm to about 5 nm.

[0107] In one example of the method for manufacturing a flash memory device, a ratio of a thickness of the second layer to a thickness of the third layer of the at least four dielectric layers is from about 1:2 to about 1:5.

[0108] In one example of the method for manufacturing a flash memory device, the third layer is adjacent to the second layer.

[0109] In one example of a method for manufacturing a flash memory device, the at least four dielectric layers are configured to provide a program erase window sufficient for operating a quad level cell (QLC).

[0110] In one example of a method for manufacturing a flash memory device, the at least four dielectric layers are configured to provide a band gap sufficient for operating a quad level cell (QLC).

[0111] In one example of a method for fabricating a flash memory device, the charge storage structure is a floating gate or a charge trap.

[0112] In one example of a method for manufacturing a flash memory device, the insulating layer includes an oxide material, an oxynitride material, a nitride material, or a combination thereof.

[0113] In one example, a method for fabricating a flash memory device includes forming a tunnel dielectric layer on a charge storage structure.

[0114] In one example, a method for fabricating a flash memory device includes forming a conductive channel on a tunnel dielectric layer.

[0115] In one example of a method for manufacturing a flash memory device, the conductive channel includes polysilicon material, Ge, SiGe, SiC, or a combination thereof.

[0116] Although the foregoing examples illustrate specific embodiments for one or more particular applications, it will be apparent to those skilled in the art that numerous modifications may be made to the form, use, and details of implementation without departing from the principles and concepts set forth herein.

Claims

1. A flash memory device, comprising: a plurality of insulating layers vertically spaced apart from one another; a vertically-oriented conductive channel extending through the plurality of insulating layers; a charge storage structure disposed between adjacent insulating layers; a control gate laterally separated from the charge storage structure such that the charge storage structure is between the control gate and the conductive channel; as well as at least four dielectric layers disposed between the control gate and the charge storage structure; wherein one of the at least four dielectric layers is adjacent to the charge storage structure and has a thickness from about 1 nm to about 5 nm, and wherein a first layer of the at least four dielectric layers is adjacent to the charge storage structure, and a ratio of a thickness of the first layer to a thickness of the second layer of the at least four dielectric layers is from about 1:2 to about 1:

5. 2 . The flash memory device of claim 1 , wherein one of the at least four dielectric layers is adjacent to the charge storage structure and comprises a nitride material. The flash memory device of claim 2 , wherein the nitride material comprises silicon nitride. 4 . The flash memory device of claim 1 , wherein one of the at least four dielectric layers is adjacent to the charge storage structure and comprises an oxide material. The flash memory device of claim 4 , wherein the oxide material comprises aluminum oxide. 6 . The flash memory device of claim 1 , wherein one of the at least four dielectric layers is adjacent to the charge storage structure and comprises a high dielectric constant material. 7 . The flash memory device of claim 6 , wherein the high dielectric constant material comprises HfO x , HfAlO x , or a combination thereof.

8. The flash memory device of claim 1, wherein the at least four dielectric layers comprise alternating layers of oxide material and nitride material.

9. The flash memory device of claim 8, wherein the oxide material comprises silicon oxide.

10. The flash memory device of claim 8, wherein the nitride material comprises silicon nitride.

11. The flash memory device of claim 1, wherein one of the at least four dielectric layers is adjacent to at least a portion of three sides of the charge storage structure.

12. The flash memory device of claim 1, wherein the second layer is adjacent to the first layer.

13. The flash memory device of claim 1, wherein the at least four dielectric layers are configured to provide a program erase window sufficient for operating a quad level cell (QLC).

14. The flash memory device of claim 1, wherein the at least four dielectric layers are configured to provide a band gap sufficient for operating a quad level cell (QLC).

15. The flash memory device of claim 1, wherein the charge storage structure is a floating gate or a charge trap.

16. The flash memory device of claim 1, further comprising a tunnel dielectric layer disposed between the charge storage structure and the conductive channel. 17 . The flash memory device of claim 1 , wherein the plurality of insulating layers comprise an oxide material, an oxynitride material, a nitride material, or a combination thereof.

18. The flash memory device of claim 16, wherein the conductive channel comprises polysilicon material, Ge, SiGe, SiC, or a combination thereof.

19. A method for manufacturing a flash memory device, comprising: forming at least four dielectric layers between adjacent vertically spaced-apart insulating layers, wherein a first layer of the at least four dielectric layers is adjacent to a control gate between the insulating layers; as well as forming a charge storage structure adjacent to a second of the at least four dielectric layers such that the charge storage structure is laterally separated from the control gate and the at least four dielectric layers are between the control gate and the charge storage structure; The second layer of the at least four dielectric layers has a thickness of from about 1 nm to about 5 nm, wherein a ratio of the thickness of the second layer to the thickness of the third layer of the at least four dielectric layers is from about 1:2 to about 1:

5.

20. The method of claim 19, wherein the at least four dielectric layers are configured to provide a program erase window sufficient for operating a quad level cell (QLC).

21. The method of claim 19, wherein the at least four dielectric layers are configured to provide a bandgap sufficient for operating a quad-level cell (QLC).

22. The method of claim 19, wherein the charge storage structure is a floating gate or a charge trap.

23. The method of claim 19, further comprising forming a tunnel dielectric layer on the charge storage structure.

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