Storage Devices

Abstract

A storage device is disclosed. The storage device includes: a nonvolatile memory device; and a controller that exchanges data signals with the nonvolatile memory device through data input and output lines and exchanges data strobe signals with the nonvolatile memory device through data strobe lines. In a training operation, at least one of the nonvolatile memory device and the controller performs a coarse training that adjusts the delay of the data signal with a first step and a fine training that adjusts the delay of the data signal with a second step that is smaller than the first step.

Description

[0001] This application claims the priority benefit of Korean Patent Application No. 10-2018-0135620 filed on November 7, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Exemplary embodiments of the inventive concepts described herein relate to a semiconductor device, and more particularly, to a memory device that aligns, verifies, and adjusts a timing of a data signal and a timing of a data strobe signal. Background Art

[0003] In a memory device including a nonvolatile memory device and a controller, as technology for manufacturing semiconductor devices develops, the speed at which the nonvolatile memory device and the controller exchange data signals is increasing.

[0004] As the speed of exchanging data signals increases, the time that data signals retain information becomes shorter, and the margin for accurately identifying data signals decreases. In order to accurately identify data signals sent at high speed, training operations can adjust the timing of nonvolatile memory devices or controllers sending data signals.

[0005] The time taken to perform the training operation may result in a reduction in the operating performance of the memory device. In addition, after the training operation is completed, the timing at which the nonvolatile memory device or controller sends a data signal may be changed due to changes in the environment. Summary of the invention

[0006] According to an exemplary embodiment of the inventive concept, a memory device includes: a nonvolatile memory device; and a controller that exchanges a data signal with the nonvolatile memory device through a data input and output line and exchanges a data strobe signal with the nonvolatile memory device through a data strobe line. In a training operation, at least one of the nonvolatile memory device and the controller performs a coarse training that adjusts a delay of the data signal with a first step and a fine training that adjusts a delay of the data signal with a second step smaller than the first step.

[0007] According to an exemplary embodiment of the inventive concept, a storage device includes: a nonvolatile memory device; and a controller, which exchanges a plurality of data signals with the nonvolatile memory device through a plurality of data input and output lines, and exchanges a data strobe signal with the nonvolatile memory device through a data strobe line. In a training operation, the controller and the nonvolatile memory device align a plurality of center positions of the plurality of data signals with a timing of a data strobe signal transition. The controller stores information of a plurality of boundaries of a signal having a minimum width among the plurality of data signals. After the training operation is completed, the controller verifies the alignment of the plurality of center positions of the plurality of data signals with a timing of a data strobe signal transition by using the information of the plurality of boundaries.

[0008] According to an exemplary embodiment of the inventive concept, a storage device includes: a nonvolatile memory device; and a controller: exchanging data signals with the nonvolatile memory device through data input and output lines, and exchanging data strobe signals with the nonvolatile memory device through data strobe lines. In a training operation, the controller and the nonvolatile memory device align the center position of the data signal with the timing of the transition of the data strobe signal by adjusting a first delay for sending the data signal. At least one of the controller and the nonvolatile memory device adjusts a second delay of the data strobe signal based on a change in the length of one cycle of the data strobe signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other objects and features of the inventive concept will become apparent by describing in detail exemplary embodiments of the inventive concept with reference to the attached drawings.

[0010] Figure 1 is a block diagram illustrating a storage device according to an exemplary embodiment of the inventive concept.

[0011] Figure 2 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A block diagram of a non-volatile memory device.

[0012] Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flowchart of a method for operating a storage device.

[0013] Figure 4 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flowchart of an example of a storage device performing a training operation with a first stride and a second stride.

[0014] Figure 5 An example of determining a delay corresponding to a first boundary of a specific data signal according to an exemplary embodiment of the inventive concept is illustrated.

[0015] Figure 6 An exemplary embodiment according to the inventive concept is shown Figure 2 Input and output circuits of a nonvolatile memory device.

[0016] Figure 7 An exemplary embodiment according to the inventive concept is shown Figure 6 Output delay circuit.

[0017] Figure 8 An exemplary embodiment according to the inventive concept is shown Figure 1 The memory interface of the controller.

[0018] Fig. 9 An example is shown in which delays of data signals of first to eighth data input and output lines are aligned with a data strobe signal according to an exemplary embodiment of the inventive concept.

[0019] Fig.10 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flow chart of a method for verifying a delay of a data signal in a storage device.

[0020] Fig.11 An example of changing the delay of a data signal based on a result of comparing a first verification value with a second verification value according to an exemplary embodiment of the inventive concept is illustrated.

[0021] Fig.12 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flow chart of an example in which a memory device adjusts a delay of a data strobe signal based on a change of the data strobe signal.

[0022] Fig.13 An exemplary embodiment according to the inventive concept is shown Figure 1 An example of a memory device measuring the length of one cycle of a data strobe signal.

[0023] Fig.14 An example in which a lock value of a data strobe signal is reduced according to an exemplary embodiment of the inventive concept is illustrated.

[0024] Fig.15 An example of adjusting the delay of a data signal based on a change of a data strobe signal according to an exemplary embodiment of the inventive concept is shown.

[0025] Fig.16 An example in which a lock value of a data strobe signal increases according to an exemplary embodiment of the inventive concept is illustrated.

[0026] Fig.17An example of adjusting the delay of a data signal based on a change of a data strobe signal according to an exemplary embodiment of the inventive concept is shown. DETAILED DESCRIPTION

[0027] Exemplary embodiments of the inventive concept provide a storage device that reduces the time of a training operation, verifies whether a data transmission timing is changed, and dynamically adjusts the data transmission timing to cope with a change in its environment.

[0028] Exemplary embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings.Throughout the application, the same reference numerals may denote the same elements.

[0029] Figure 1 is a block diagram illustrating a storage device according to an exemplary embodiment of the inventive concept. Figure 1 , the storage device 100 includes a nonvolatile memory device 110 and a controller 120. The nonvolatile memory device 110 may include various memories (such as flash memory, phase change random access memory (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.).

[0030] The nonvolatile memory device 110 may include a homogeneous memory or a heterogeneous memory. The nonvolatile memory device 110 may communicate with the controller 120 through data input and output lines DQ and control lines CT.

[0031] The controller 120 is configured to control the nonvolatile memory device 110. The controller 120 may transmit data to the nonvolatile memory device 110 through the data input and output lines DQ. The controller 120 may control the nonvolatile memory device 110 by sending and receiving control signals through the control lines CT. For example, the controller 120 may allow the nonvolatile memory device 110 to perform a write operation, a read operation, or an erase operation.

[0032] In addition, the controller 120 may perform a training operation with the nonvolatile memory device 110. The training operation may include adjusting (e.g., aligning) the timing of the controller 120 or the nonvolatile memory device 110 sending a data signal through the data input and output lines DQ. The accuracy and reliability of the received data signal may be improved by adjusting the timing of sending the data signal.

[0033] The training operation may be performed after power is supplied to the memory device 100 or after the memory device 100 is switched from a power saving mode to a normal mode. The training operation may be performed before the controller 120 normally controls the nonvolatile memory device 110 (e.g., before the controller 120 allows the nonvolatile memory device 110 to perform a program operation, a read operation, or an erase operation).

[0034] The controller 120 includes a memory interface 121, an input and output trainer 122, and a memory 123. The memory interface 121 may communicate with the nonvolatile memory device 110. For example, the memory interface 121 may exchange signals (e.g., data signals and control signals) having levels and timings determined by a given rule with the nonvolatile memory device 110.

[0035] The input and output trainer 122 may perform a training operation with the nonvolatile memory device 110 through the memory interface 121. The input and output trainer 122 may store a plurality of pieces of information used for the training operation or a plurality of pieces of information (e.g., delay) obtained through the training operation. The input and output trainer 122 may perform a training operation with the nonvolatile memory device 110 by using the memory 123.

[0036] Figure 2 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A block diagram of a nonvolatile memory device is shown. Figure 1 and Figure 2 , the nonvolatile memory device 110 includes a memory cell array 111 , a row decoder circuit 112 , a page buffer circuit 113 , an input and output circuit 114 , a success-failure check circuit 115 , and a control logic circuit 116 .

[0037] The memory cell array 111 includes a plurality of memory blocks BLK1 to BLKz. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. Each of the memory blocks BLK1 to BLKz may be connected to a row decoder circuit 112 through at least one ground selection line GSL, a plurality of word lines WL, and at least one string selection line SSL. Each of the memory blocks BLK1 to BLKz may be connected to a page buffer circuit 113 through a plurality of bit lines BL. The plurality of memory blocks BLK1 to BLKz may be commonly connected to a plurality of bit lines BL.

[0038] In an exemplary embodiment of the inventive concept, each of the memory blocks BLK1 to BLKz may correspond to a unit of an erase operation. The memory cells of the memory cell array 111 may be erased for each memory block. The memory cells belonging to one memory block may be erased substantially at the same time. As another example, each memory block may be divided into a plurality of sub-blocks. Each of the plurality of sub-blocks may be a unit of an erase operation.

[0039] The row decoder circuit 112 is connected to the memory cell array 111 through a plurality of ground selection lines GSL, a plurality of word lines WL, and a plurality of string selection lines SSL. The row decoder circuit 112 operates under the control of the control logic circuit 116. The row decoder circuit 112 may receive a row address RA from the input and output circuit 114. The row decoder circuit 112 may decode the received row address RA, and may control voltages to be applied to the string selection lines SSL, the word lines WL, and the ground selection lines GSL based on the decoded row address RA.

[0040] The page buffer circuit 113 is connected to the memory cell array 111 through a plurality of bit lines BL. The page buffer circuit 113 is connected to the input and output circuit 114 through a plurality of data lines DL. The page buffer circuit 113 operates under the control of the control logic circuit 116.

[0041] In a write operation, the page buffer circuit 113 may store data bits to be programmed to the memory cell. The page buffer circuit 113 may apply voltages to a plurality of bit lines BL based on the stored data bits. For example, the page buffer circuit 113 may be used as a write driver. In a read operation or a verify read operation, the page buffer circuit 113 may sense the voltage of the bit line BL and may store the sensed result. For example, the page buffer circuit 113 may be used as a sense amplifier.

[0042] The input and output circuit 114 is connected to the page buffer circuit 113 through a plurality of data lines DL. The input and output circuit 114 may be connected to the controller 120 through the first to eighth data input and output lines DQ1 to DQ8. For example, the first to eighth data input and output lines DQ1 to DQ8 may include a reference Figure 1 Describes the data input and output lines DQ.

[0043] The input and output circuit 114 may output the data bits read by the page buffer circuit 113 as data signals to the controller 120 through the first to eighth data input and output lines DQ1 to DQ8. In addition, the input and output circuit 114 may transmit the data signals received from the controller 120 through the first to eighth data input and output lines DQ1 to DQ8 to the page buffer circuit 113 as data bits.

[0044] The input and output circuit 114 may receive an address through the first to eighth data input and output lines DQ1 to DQ8. The input and output circuit 114 may transmit a row address RA of the received address to the row decoder circuit 112. The input and output circuit 114 may store a data bit to the page buffer circuit 113 or may read a data bit stored in the page buffer circuit 113 by using a column address of the received address.

[0045] The input and output circuit 114 may receive a command CMD through the first to eighth data input and output lines DQ1 to DQ8. The input and output circuit 114 may transmit the received command CMD to the control logic circuit 116. The input and output circuit 114 may receive a data strobe signal DQS from the controller 120. The input and output circuit 114 may latch a data signal received through the first to eighth data input and output lines DQ1 to DQ8 as a data bit in synchronization with the data strobe signal DQS.

[0046] The input and output circuit 114 may output a data strobe signal DQS to the controller 120. The input and output circuit 114 may output the data strobe signal DQS in synchronization with a timing at which a data bit is transmitted as a data signal through the first to eighth data input and output lines DQ1 to DQ8. The data strobe signal DQS may be received and output through a portion of the control line CT (e.g., a data strobe line).

[0047] For example, when a data signal is transmitted from the controller 120 to the nonvolatile memory device 110, the data strobe signal DQS may be controlled by the controller 120. When a data signal is transmitted from the nonvolatile memory device 110 to the controller 120, the data strobe signal DQS may be controlled by the nonvolatile memory device 110.

[0048] The input and output circuit 114 may output a ready / busy signal (R / B) to the controller 120. For example, when the input and output circuit 114 receives a command, an address, or a data bit from the controller 120, the input and output circuit 114 may output a ready / busy signal (R / B) indicating a ready state. When the input and output circuit 114 cannot receive a command, an address, or a data bit from the controller 120, the input and output circuit 114 may output a ready / busy signal (R / B) indicating a busy state. The ready / busy signal (R / B) may be output through a portion of the control line CT.

[0049] After verifying the read operation, the success-failure check circuit (PFC) 115 may receive the sensing result from the page buffer circuit 113. The success-failure check circuit 115 may determine whether the write (or erase) is successful or failed based on the received sensing result. The result of determining success or failure is provided to the control logic circuit 116.

[0050] The control logic circuit 116 may receive an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal / WE, a read enable signal / RE, and a chip enable signal / CE from the controller 120. The address latch enable signal ALE, the command latch enable signal CLE, the write enable signal / WE, the read enable signal / RE, and the chip enable signal / CE may be received through a portion of a control line CT.

[0051] The address latch enable signal ALE indicates that the data signal input through the first data input and output line DQ1 to the eighth data input and output line DQ8 corresponds to an address. If the address latch enable signal ALE is activated, the control logic circuit 116 may process the data signal received through the first data input and output line DQ1 to the eighth data input and output line DQ8 as an address. For example, the control logic circuit 116 may control the nonvolatile memory device 110 so that the row address RA is sent to the row decoder circuit 112.

[0052] The command latch enable signal CLE indicates that the data signal input through the first data input and output line DQ1 to the eighth data input and output line DQ8 corresponds to the command CMD. If the command latch enable signal CLE is activated, the control logic circuit 116 may process the data signal received through the first data input and output line DQ1 to the eighth data input and output line DQ8 as the command CMD. For example, the control logic circuit 116 may acquire the command CMD stored in the input and output circuit 114, and may execute the acquired command CMD.

[0053] When a command CMD or an address is received through the first to eighth data input and output lines DQ1 to DQ8, the write enable signal / WE may indicate a timing of storing (or latching) data bits of the first to eighth data input and output lines DQ1 to DQ8. The read enable signal / RE may be used for the controller 120 to provide any clock to the nonvolatile memory device 110 in a read (or output) operation.

[0054] For example, in a read operation, the controller 120 may allow the read enable signal / RE to be periodically switched to a high level and a low level. The control logic circuit 116 may send the read enable signal / RE to the input and output circuit 114. The input and output circuit 114 may delay the read enable signal / RE to generate a data strobe signal DQS. The input and output circuit 114 may send the data signal synchronously with the data strobe signal DQS generated thereby through the first data input and output line DQ1 to the eighth data input and output line DQ8.

[0055] The chip enable signal / CE may activate the nonvolatile memory device 110. When the controller 120 activates the chip enable signal / CE, the nonvolatile memory device 110 may receive data signals transmitted through the first to eighth data input and output lines DQ1 to DQ8. When the controller 120 deactivates the chip enable signal / CE, the nonvolatile memory device 110 may ignore data signals transmitted through the first to eighth data input and output lines DQ1 to DQ8.

[0056] The control logic circuit 116 may include an output trainer 117. The output trainer 117 may perform a training operation on the data signal outputted by the input and output circuit 114 through the first to eighth data input and output lines DQ1 to DQ8 in a read operation. The training operation will be described more fully later with reference to the accompanying drawings.

[0057] Figure 3 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flowchart of a method for operating a storage device. Figures 1 to 3 In operation S110, the storage device 100 may perform a training operation with a first step and a second step. The nonvolatile memory device 110 or the controller 120 may perform a training operation while adjusting a delay with a first step and a second step when transmitting a data signal. By performing a training operation with two or more steps, the time spent performing the training operation may be reduced.

[0058] In operation S120, the memory device 100 may adjust the delay of the data strobe signal DQS based on the result of the training operation, and may verify the delay of the data signal transmitted through the first to eighth data input and output lines DQ1 to DQ8. For example, the nonvolatile memory device 110 or the controller 120 may verify whether the delay of the data signal aligned by the training operation is distorted or offset. The reliability of the memory device 100 may be improved by verifying the delay of the data signal.

[0059] In operation S130, the memory device 100 may adjust the delay of the data strobe signal DQS based on the change of the data strobe signal DQS. For example, the nonvolatile memory device 110 or the controller 120 may adjust the delay of the data strobe signal DQS based on the change of the length of one cycle of the data strobe signal DQS. Therefore, the distortion or offset of the timing of transmitting the data signal due to the change of the data strobe signal DQS can be compensated.

[0060] Figure 4 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 The storage device performs a training operation with a first stride and a second stride ( Figure 3Flow chart of an example of operation S110). Figure 1 , Figure 2 and Figure 4 In operation S210 , the nonvolatile memory device 110 or the controller 120 may transmit a data signal together with a data strobe signal DQS.

[0061] For example, the training operation may include read training and write training. Read training may be performed to align the timing of the data strobe signal DQS and the data signal sent by the nonvolatile memory device 110. Write training may be performed to align the timing of the data strobe signal DQS and the data signal sent by the controller 120.

[0062] In read training, the output trainer 117 of the nonvolatile memory device 110 may output a specific data bit as a data signal to the controller 120 through the first to eighth data input and output lines DQ1 to DQ8 under the control of the controller 120. The nonvolatile memory device 110 may transmit a data strobe signal DQS together with the data signal.

[0063] In the write training, the input and output trainer 122 of the controller 120 may output a specific data bit as a data signal to the nonvolatile memory device 110 through the first to eighth data input and output lines DQ1 to DQ8. The controller 120 may output a data strobe signal DQS together with the data signal to the nonvolatile memory device 110. The nonvolatile memory device 110 may latch the data signal in synchronization with the data strobe signal DQS, and may store the latched data signal.

[0064] In operation S220 , the controller 120 may determine whether the first success occurs. For example, in read training, the controller 120 may latch the data signal as a data bit in synchronization with the data strobe signal DQS received from the nonvolatile memory device 110 .

[0065] When the latched data bits match the specific data bits (e.g., when the specific data bits are accurately identified), the input and output trainer 122 of the controller 120 may determine success. When at least one of the latched data bits does not match the corresponding data bit of the specific data bits (e.g., when at least one of the specific data bits is not accurately identified), the input and output trainer 122 of the controller 120 may determine failure.

[0066] In write training, the controller 120 may request data bits from the nonvolatile memory device 110. The nonvolatile memory device 110 may transmit the stored data bits as second data signals to the controller 120 through the first to eighth data input and output lines DQ1 to DQ8. The nonvolatile memory device 110 may transmit a data strobe signal DQS together with the second data signals to the controller 120.

[0067] The controller 120 may latch the second data signal synchronously with the data strobe signal DQS, and may store the latched second data signal as a second data bit. When the second data bit matches the specific data bit, the input and output trainer 122 of the controller 120 may determine success. When at least one of the second data bits does not match the corresponding data bit in the specific data bits, the input and output trainer 122 of the controller 120 may determine failure.

[0068] When it is determined that it is unsuccessful in operation S220, operation S230 is performed. In operation S230, the memory device 100 may adjust the delay of the data signal in the first step. For example, in the read training, the output trainer 117 of the nonvolatile memory device 110 may increase the delay of the data signal to be transmitted in the first step. In the write training, the input and output trainer 122 of the controller 120 may increase the delay of the data signal to be transmitted in the first step. Then, operation S210 is performed again.

[0069] When the first determination is successful in operation S220, operation S240 is performed. In operation S240, the memory device 100 may recover the delay of the data signal, and may adjust the delay of the data signal in a second step. For example, the output trainer 117 (in read training) or the input and output trainer 122 (in write training) may recover the delay of the data signal by reducing the delay of the data signal by as much as the first step.

[0070] Then, the output trainer 117 or the input and output trainer 122 may increase the delay of the data signal by the second step size. For example, the second step size may be smaller than the first step size.

[0071] In operation S250, the memory device 100 may transmit the data signal together with the data strobe signal DQS. The output trainer 117 (in read training) or the input and output trainer 122 (in write training) may transmit the data signal having a delay adjusted by the second step.

[0072] As in operation S220 , in operation S260 , the input and output trainer 122 of the controller 120 may determine whether success is detected for the first time after the delay starts to be adjusted in the second step.

[0073] When failure is determined in operation S260, operation S270 is performed. As in operation S230, in operation S270, the memory device 100 may increase the delay of the data signal by the second step. Then, operation S250 is performed again.

[0074] When the first determination is successful in operation S260, operation S280 is performed. In operation S280, the input and output trainer 122 of the controller 120 may confirm a delay corresponding to a first boundary of the data signal.

[0075] Figure 5 1 shows a method of determining a delay corresponding to a first boundary of a specific data signal (eg, Figure 4 An example of operation S260). Figure 1 , Figure 2 and Figure 5 , the controller 120 or the nonvolatile memory device 110 may fix the delay of the data strobe signal DQS, and may repeatedly transmit the data strobe signal DQS and the data signal DS while adjusting the delay of the data signal DS.

[0076] After the leading period has passed, the data strobe signal DQS may start to transition to a high level or a low level. In the read training, the controller 120 may recognize the data signal DS in synchronization with the target timing Ttar of the data strobe signal DQS. In other words, when the effective period (e.g., the period represented by the hexagon) overlaps with the target timing Ttar, the controller 120 may accurately (or correctly) recognize the data signal DS.

[0077] In the write training, the nonvolatile memory device 110 can recognize the data signal DS in synchronization with the target timing Ttar of the data strobe signal DQS. In other words, when the effective period (e.g., the period represented by the hexagon) overlaps with the target timing Ttar, the nonvolatile memory device 110 can accurately (or correctly) recognize the data signal DS and can return an accurate (or correct) second data signal to the controller 120.

[0078] At the first timing T1, the controller 120 or the nonvolatile memory device 110 may adjust the delay to “0” to transmit the data signal DS, or may transmit the data signal DS with an initial delay of “0.” Since the valid period of the data signal DS does not overlap with the target timing Ttar, the controller 120 may determine failure.

[0079] The controller 120 or the nonvolatile memory device 110 may increase the delay of the data signal DS by as much as the first step ST1. For example, the delay of the first step ST1 may be "4". At the second timing T2, the controller 120 or the nonvolatile memory device 110 may send the data signal DS with a delay of "4". Since the valid period of the data signal DS does not overlap with the target timing Ttar, the controller 120 may determine a failure.

[0080] The controller 120 or the nonvolatile memory device 110 may increase the delay of the data signal DS by the first step ST1. At the third timing T3, the controller 120 or the nonvolatile memory device 110 may send the data signal DS with a delay of "8". Since the valid period of the data signal DS does not overlap with the target timing Ttar, the controller 120 may determine a failure.

[0081] The controller 120 or the nonvolatile memory device 110 may increase the delay of the data signal DS by the first step ST1. At the fourth timing T4, the controller 120 or the nonvolatile memory device 110 may send the data signal DS with a delay of "12". Since the effective period of the data signal DS overlaps with the target timing Ttar, the controller 120 may determine success.

[0082] The training for finding the first success with the first step may be a rough training. After finding the position of the first success through the rough training, the precise training for finding the first success with the second step may be performed.

[0083] The controller 120 or the nonvolatile memory device 110 may restore the delay of the data signal DS to the immediately previous delay (i.e., the previous delay), for example, "8". In addition, the controller 120 or the nonvolatile memory device 110 may increase the delay of the data signal DS by as much as the second step ST2. For example, the delay of the second step ST2 may be "1". At the fifth timing T5, the controller 120 or the nonvolatile memory device 110 may send the data signal DS with a delay of "9". Since the valid period of the data signal DS does not overlap with the target timing Ttar, the controller 120 may determine a failure.

[0084] The controller 120 or the nonvolatile memory device 110 may increase the delay of the data signal DS by the second step ST2. At the sixth timing T6, the controller 120 or the nonvolatile memory device 110 may send the data signal DS with a delay of "10". Since the effective period of the data signal DS overlaps with the target timing Ttar, the controller 120 may determine success.

[0085] The controller 120 may confirm that the delay "9" or "10" corresponds to the first boundary (e.g., the right boundary) of the data signal DS. In this way, the process of finding the first boundary may be performed on each of the data signals of the first data input and output line DQ1 to the eighth data input and output line DQ8. The controller 120 may confirm the delays of the data signals respectively corresponding to the first boundary (e.g., the right boundary).

[0086] As in reference Figure 4 and Figure 5 As described above, a second boundary (eg, left boundary) of the data signal can be confirmed. Figure 4 and Figure 5 As described above, after the first boundary is confirmed, the controller 120 or the nonvolatile memory device 110 may search for the second boundary of the data signal while further increasing the delay of the data signal.

[0087] For example, in Figure 4 In the case where the first success determined in operation S220 and operation S260 is replaced by the first failure, Figure 4 The method can be applied to the training for finding the second boundary of the data signal. Figure 5 As described above, the nonvolatile memory device 110 or the controller 120 may transmit the data signal DS and the data strobe signal DQS while increasing the delay with the first step ST1.

[0088] When the effective period of the data signal DS passes the target timing Ttar, the controller 120 may determine a failure. The nonvolatile memory device 110 or the controller 120 may restore the delay of the data signal DS to the immediately previous delay, and may look for the first failure while increasing the delay by the second step ST2. The delay when the first failure is identified in the precise training may be confirmed as the delay corresponding to the second boundary of the data signal DS.

[0089] The controller 120 may calculate a delay corresponding to the center of the data signal from a delay corresponding to a first boundary of the data signal and a delay corresponding to a second boundary of the data signal. The input and output trainer 122 of the controller 120 may set the delay of the data signal of the input and output circuit 114 of the nonvolatile memory device 110 to the delay corresponding to the center of the data signal calculated in the read training.

[0090] The input and output trainer 122 of the controller 120 may set the delay of the data signal of the memory interface 121 to the delay corresponding to the center of the data signal calculated in the write training. When the delay is set, the center of the data signal may be aligned with the target timing Ttar of the data strobe signal DQS.

[0091] exist Figure 5 In the embodiment of the present invention, a description is given that the delay of the data signal is adjusted by using the first step ST1 and the second step ST2. However, the delay of the data signal may be adjusted by using three or more steps.

[0092] Figure 6 An exemplary embodiment according to the inventive concept is shown Figure 2 In an exemplary embodiment of the inventive concept, a component that outputs a signal to the controller 120 among a plurality of components of the input and output circuit 114 is Figure 6 Reference Figure 2 and Figure 6 The input and output circuit 114 includes a first data input and output pad (pad, or referred to as a pad) DQP1 to an eighth data input and output pad DQP8, a data selection pad DQSP, a first output delay circuit 114_1 to a ninth output delay circuit 114_9 and a buffer 114_10.

[0093] The first to eighth data input and output pads DQP1 to DQP8 may be connected to the first to eighth data input and output lines DQ1 to DQ8. The data strobe pad DQSP may be connected to a control line transmitting a data strobe signal DQS.

[0094] The first to eighth output delay circuits 114_1 to 114_8 are connected to the first to eighth data input and output pads DQP1 to DQP8, respectively. The first to eighth output delay circuits 114_1 to 114_8 may transmit data bits as data signals from the buffer 114_10 to the first to eighth data input and output pads DQP1 to DQP8, respectively. The first to eighth output delay circuits 114_1 to 114_8 may receive first to eighth output delay control signals ODC1 to ODC8, respectively, from the control logic circuit 116.

[0095] The first to eighth output delay circuits 114_1 to 114_8 may individually control the timing of outputting data signals (or the delay of data signals) in response to the first to eighth output delay control signals ODC1 to ODC8. For example, the first output delay circuit 114_1 may adjust the timing of sending data bits from the buffer 114_10 as data signals (e.g., may adjust the delay of data signals) in response to the first output delay control signal ODC1.

[0096] In the read training, the first to eighth output delay circuits 114_1 to 114_8 may control the delay of the data signal individually with the first step ST1 or the second step ST2 in response to the first to eighth output delay control signals ODC1 to ODC8. After the read training is completed, the first to eighth output delay circuits 114_1 to 114_8 may confirm the delay of the data signal in response to the first to eighth output delay control signals ODC1 to ODC8.

[0097] The ninth output delay circuit 114_9 may delay the read enable signal / RE received from the control logic circuit 116 and may output the delayed read enable signal / RE as the data strobe signal DQS to the data strobe pad DQSP. The ninth output delay circuit 114_9 may adjust the delay of the data strobe signal DQS in response to the ninth output delay control signal ODC9.

[0098] The buffer 114_10 may transmit the data bits to the first to eighth output delay circuits 114_1 to 114_8. For example, in a training operation, the data bits DB transmitted from the control logic circuit 116 may be stored in the buffer 114_10 and may be provided to the output delay circuits 114_1 to 114_8. In a general operation where a training operation is not performed, the data "DATA" transmitted from the page buffer circuit 113 may be stored in the buffer 114_10 and may be provided to the output delay circuits 114_1 to 114_8.

[0099] Figure 7 An exemplary embodiment according to the inventive concept is shown Figure 6 Output delay circuit. Figure 1 , Figure 2 , Figure 6 and Figure 7 , the output delay circuit 114_1 may include a first delay group DG1, a second delay group DG2, and a multiplexer MUX. The first delay group DG1 and the second delay group DG2 may be connected in sequence. The data bits sent from the buffer 114_10 may be input to the first delay group DG1. The output of the first delay group DG1 may be sent to the second delay group DG2.

[0100] Each of the first delay group DG1 and the second delay group DG2 may include four delay cells "D". Each of the first delay group DG1 and the second delay group DG2 may increase the delay of the data signal by the first step ST1. The delay of the first step ST1 may correspond to the delay of the four delay cells "D". In other words, the delay of the first step ST1 may be "4". Each delay cell "D" may increase the delay of the data signal by the second step ST2. In other words, the delay of the second step ST2 may be "1".

[0101] The multiplexer MUX can receive data bits output from the buffer 114_10, data bits delayed by the first delay group DG1 and the second delay group DG2, and data bits delayed by the delay units "D" in the first delay group DG1 and the second delay group DG2 (for example, data bits with different delays).

[0102] The multiplexer MUX may transmit one of the received data bits as a data signal to the data input and output pad DQP1 in response to the first output delay control signal ODC1. In other words, the control logic circuit 116 or the output trainer 117 may adjust the timing of the output data bit of the output delay circuit 114_1 by adjusting the data bit selected by the output delay control signal ODC1 (e.g., may adjust the delay of the data bit).

[0103] exist Figure 7 Only the output delay circuit 114_1 is shown, but the remaining output delay circuits 114_2 to 114_8 may also have the same Figure 7 The output trainer 117 of the control logic circuit 116 can individually control the timing of the first output delay circuit 114_1 to the eighth output delay circuit 114_8 sending the data signal (for example, the delay of the data signal) and the timing of the ninth output delay circuit 114_9 sending the data selection signal DQS by individually adjusting the first output delay control signal ODC1 to the ninth output delay control signal ODC9.

[0104] exist Figure 7 Only two delay groups are shown in FIG. 1 , but the number of delay groups included in the output delay circuit 114_1 is not limited thereto. Figure 7 2 shows an example in which one delay group includes four delay units, but the number of delay units included in one delay group is not limited thereto.

[0105] Figure 8 An exemplary embodiment according to the inventive concept is shown Figure 1 In an exemplary embodiment of the inventive concept, components among the plurality of components of the memory interface 121 associated with a case where the controller 120 transmits a signal to the nonvolatile memory device 110 are Figure 8 Reference Figure 1 and Figure 8 , the memory interface 121 includes first to eighth data input and output pads DQP1 to DQP8, a data strobe pad DQSP, first to eighth input delay circuits 121_1 to 121_8, and a data strobe signal (DQS) generator 121_9.

[0106] The first to eighth data input and output pads DQP1 to DQP8 are connected to the first to eighth data input and output lines DQ1 to DQ8. The data strobe pad DQSP is connected to a control line transmitting a data strobe signal DQS.

[0107] The first to eighth input delay circuits 121_1 to 121_8 are connected to the first to eighth data input and output pads DQP1 to DQP8, respectively. In the training operation, the first to eighth input delay circuits 121_1 to 121_8 may transmit the data bits received from the memory 123 through the input and output trainer 122 as data signals to the first to eighth data input and output pads DQP1 to DQP8, respectively. In the general operation (not the training operation), the first to eighth input delay circuits 121_1 to 121_8 may transmit the data bits requested by the controller 120 as data signals to the first to eighth data input and output pads DQP1 to DQP8, respectively.

[0108] In the training operation, the first to eighth input delay circuits 121_1 to 121_8 may receive first to eighth input delay control signals IDC1 to IDC8 from the input and output trainer 122 , respectively.

[0109] The first to eighth input delay circuits 121_1 to 121_8 may individually control the timing of transmitting the data signal (e.g., the delay of the data signal) in response to the input delay control signals IDC1 to IDC8. For example, the first input delay circuit 121_1 may adjust the timing of transmitting the data signal from the input and output trainer 122 (e.g., the delay of the data signal) in response to the first input delay control signal IDC1. In an exemplary embodiment of the inventive concept, the first to eighth input delay circuits 121_1 to 121_8 may have the same Figure 7 The structure shown in is basically the same structure.

[0110] In the write training, the first to eighth input delay circuits 121_1 to 121_8 may control the delay of the data signal individually with the first step ST1 or the second step ST2 in response to the first to eighth input delay control signals IDC1 to IDC8. After the write training is completed, the first to eighth input delay circuits 121_1 to 121_8 may confirm the delay of the data signal in response to the first to eighth input delay control signals IDC1 to IDC8.

[0111] The data strobe signal generator 121_9 may receive a clock CLK. The clock CLK may be generated within the controller 120, or may be provided from an external device to the controller 120. The data strobe signal generator 121_9 may generate a data strobe signal DQS by using the clock CLK.

[0112] The data strobe signal generator 121_9 may receive a ninth input delay control signal IDC9 from the input and output trainer 122. In response to the ninth input delay control signal IDC9, the data strobe signal generator 121_9 may adjust the timing of transmitting the data strobe signal DQS (e.g., may adjust the delay of the data strobe signal DQS). In an exemplary embodiment of the inventive concept, the data strobe signal generator 121_9 may have a Figure 7 The structure shown in is basically the same structure.

[0113] Fig. 9 An example of aligning the delay of the data signal of the first data input and output line to the eighth data input and output line with the data strobe signal according to an exemplary embodiment of the inventive concept is shown. Fig. 9 As shown in , when the data signal is aligned with the data strobe signal DQS, the nonvolatile memory device 110 or the controller 120 may transmit the data strobe signal DQS and the data signal. The center of the data signal may be synchronized with the edge at which the data strobe signal DQS switches.

[0114] In an exemplary embodiment of the inventive concept, valid periods of data signals may differ from each other due to structural characteristics or process variations of the input and output circuit 114 or the memory interface 121. After read training is completed, the controller 120 may store delays corresponding to first and second boundaries of the data signal having the shortest valid period.

[0115] For example, the controller 120 may store a delay (dashed line) corresponding to a first boundary of a data signal of the fifth data input and output line DQ5 having the shortest valid period, or a delay (dotted line) obtained by subtracting a delay corresponding to a margin from a relevant delay (dashed line), as a first verification value.

[0116] The controller 120 may store a delay (dashed line) corresponding to a second boundary of the data signal of the fifth data input and output line DQ5 having the shortest valid period, or a delay (dotted line) obtained by adding a delay corresponding to a margin and a related delay (dashed line), as a second verification value.

[0117] After the write training is completed, the controller 120 may store the first verification value and the second verification value. The controller 120 may verify whether the delay of the data signal is changed or distorted by using the first verification value and the second verification value.

[0118] Fig.10 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flowchart of a method for verifying the delay of a data signal in a storage device. Figure 1 , Figure 2 and Fig.10 In operation S310, after a training operation (eg, read training or write training) is completed, the controller 120 may store verification values ​​(eg, a first verification value and a second verification value).

[0119] In operation S320, the controller 120 may determine whether a verification event occurs. For example, when a read error occurs or when an error occurs when sending data, the controller 120 may determine that a verification event occurs. When it is determined that no verification event occurs, Fig.10 The process ends without verification. When a verification event occurs, operation S330 is performed.

[0120] In operation S330, the memory device 100 may verify the delay of the data signal by using the verification value. When it is determined in operation S340 that a delay error occurs, operation S350 is performed. In operation S350, the memory device 100 may perform a training operation (e.g., read training or write training) again, and may align the delay of the data signal again.

[0121] When it is determined in operation S340 that no delay error occurs, operation S360 is performed. In operation S360, the storage device 100 may perform error processing or error coping. For example, the storage device 100 may execute a code given for error processing, may reset some components, or may reset all components.

[0122] Fig.11 An example of changing the delay of a data signal based on a result of comparing a first verification value with a second verification value according to an exemplary embodiment of the inventive concept is shown. Fig. 9 When a verification event occurs, the nonvolatile memory device 110 or the controller 120 can set a delay of the data strobe signal DQS by using the first verification value and the second verification value, and can determine whether the data is accurately (or correctly) transmitted.

[0123] In an exemplary embodiment of the inventive concept, a boundary (dashed line) of the fifth data input and output line DQ5 is used as an example of a first verification value and a second verification value. Fig.11 is shown in .

[0124] The nonvolatile memory device 110 or the controller 120 may adjust the delay of the data strobe signal DQS to the first verification value, and may transmit the first data strobe signal DQS1 and the data signal. In this case, the data signal of the fifth data input and output line DQ5 is not accurately (or correctly) recognized in the controller 120 or the nonvolatile memory device 110. When at least one of the data signals is not accurately recognized, it is determined that the delay of the data signal is advanced or increased.

[0125] The nonvolatile memory device 110 or the controller 120 may adjust the delay of the data strobe signal DQS to the second verification value, and may transmit the second data strobe signal DQS2 and the data signal. In this case, the data signal is accurately (or correctly) recognized in the controller 120 or the nonvolatile memory device 110. When at least one of the data signals is not accurately recognized, it is determined that the delay of the data signal is advanced or increased.

[0126] Fig.12 is a diagram showing an exemplary embodiment according to the inventive concept Figure 1 A flowchart of an example of a memory device adjusting a delay of a data strobe signal based on a change in the data strobe signal. Figure 1 , Figure 2 and Fig.12 , in operation S410, the controller 120 may store the length of one cycle of the data strobe signal DQS of the training operation.

[0127] In operation S420, the controller 120 may determine whether an adjustment event occurs. For example, when the length of one cycle of the data strobe signal DQS changes by a threshold value or more, or when the temperature changes by a threshold value or more, an adjustment event may occur. When it is determined that no adjustment event occurs, Fig.12 The process ends. When an adjustment event occurs, operation S430 is performed. In operation S430, the controller 120 may adjust the delay of the data strobe signal DQS based on the difference between the stored length and the current length of the data strobe signal DQS.

[0128] Fig.13 An exemplary embodiment according to the inventive concept is shown Figure 1 An example of a memory device measuring the length of one cycle of a data strobe signal. Figure 1 , Figure 2 and Fig.13 , the controller 120 may measure the length of one cycle of the data strobe signal DQS as a locked value.

[0129] For example, the controller 120 may detect the number of delay units corresponding to one cycle of the data strobe signal DQS as a lock value. For example, when performing a training operation, the lock value may be "100". In other words, one cycle of the data strobe signal DQS may be represented as a delay of "100".

[0130] One cycle of the data strobe signal DQS may be represented as a phase of 360°. When the training operation is completed, the data strobe signal DQS may be delayed by as much as 90° relative to the data signal (e.g., the data signal of the first data input and output line DQ1). When the data strobe signal DQS is delayed by as much as 90°, the switching timing of the data strobe signal DQS may be aligned with the center of the data signal.

[0131] For example, when the locked value of the data strobe signal DQS is "100", the delay between the data signal and the data strobe signal DQS can be adjusted to "25" corresponding to 1 / 4 of "100". The timing at which the data strobe signal DQS starts to transition can be determined according to the total delay of the data strobe signal DQS. For example, the total delay of the data strobe signal DQS can be "30". The timing at which the data signal starts to be sent can be determined according to the delay of the data signal. For example, the delay of the data signal can be "5".

[0132] However, as the length (or frequency) of one cycle of the data strobe signal DQS changes, the data signal and the data strobe signal DQS may be misaligned.

[0133] Fig.14 An example in which the locked value of the data strobe signal is reduced according to an exemplary embodiment of the inventive concept is shown. Figure 1 , Figure 2 and Fig.14 , the latch value of the data strobe signal DQS decreases from "100" to "80". The valid period of the data signal (e.g., the valid period of the data signal of the first data input and output line DQ1) may decrease at substantially the same rate as the latch value of the data strobe signal DQS decreases.

[0134] Even if the lock value of the data strobe signal DQS is reduced, the delay of the data strobe signal DQS and the delay of the data signal may be maintained. In other words, the timing at which the data strobe signal DQS starts to transition may correspond to a delay of "30", and the timing at which the data signal starts to be transmitted may correspond to a delay of "5". In this case, Fig.14 As shown in , the transition timing of the data strobe signal DQS and the center of the data signal may not be aligned.

[0135] Fig.15An example of adjusting the delay of a data signal based on a change of a data strobe signal according to an exemplary embodiment of the inventive concept is shown. Figure 1 , Figure 2 and Fig.15 , when the locked value of the data strobe signal DQS is reduced by as much as “20”, the total delay of the data strobe signal DQS may be reduced by as much as “5” corresponding to 1 / 4 of “20”.

[0136] In the case where the delay of the data strobe signal DQS is reduced by as much as "5", the delay difference between the data strobe signal DQS and the data signal (e.g., the data signal of the first data input and output line DQ1) may be "20". The delay of "20" may correspond to 1 / 4 of the length of one cycle of the data strobe signal DQS, and may correspond to a phase of 90°. Therefore, the switching timing of the data strobe signal DQS and the center of the data signal may be aligned again.

[0137] Fig.16 FIG. 2 shows an example in which a locked value of a data strobe signal is increased according to an exemplary embodiment of the inventive concept. Referring to FIG. Figure 1 , Figure 2 and Fig.16 , the latch value of the data strobe signal DQS increases from “100” to “120”. The valid period of the data signal (eg, the valid period of the data signal of the first data input and output line DQ1) may increase at substantially the same rate as the latch value of the data strobe signal DQS increases.

[0138] Even if the lock value of the data strobe signal DQS increases, the delay of the data strobe signal DQS and the delay of the data signal may be maintained. In other words, the timing at which the data strobe signal DQS starts to transition may correspond to the delay "30", and the timing at which the data signal starts to transition may correspond to the delay "5". In this case, Fig.16 As shown in , the transition timing of the data strobe signal DQS and the center of the data signal may not be aligned.

[0139] Fig.17 An example of adjusting the delay of a data signal based on a change of a data strobe signal according to an exemplary embodiment of the inventive concept is shown. Figure 1 , Figure 2 and Fig.17 , when the locked value of the data strobe signal DQS increases by as much as “20”, the total delay of the data strobe signal DQS may increase by as much as “5” corresponding to 1 / 4 of “20”.

[0140] In the case where the delay of the data strobe signal DQS increases by as much as "5", the delay difference between the data strobe signal DQS and the data signal (e.g., the data signal of the first data input and output line DQ1) may be "30". The delay of "30" may correspond to 1 / 4 of the length of one cycle of the data strobe signal DQS, and may correspond to a phase of 90°. Therefore, the switching timing of the data strobe signal DQS and the center of the data signal may be aligned again.

[0141] Reference Figures 13 to 17 A description is given of adjusting the delay of the data strobe signal DQS based on a change in the length (or frequency) of one cycle of the data strobe signal DQS. However, instead of the data strobe signal DQS, the delay of the data signal may be similarly adjusted.

[0142] For example, when the delay of the data strobe signal DQS needs to be reduced by “5” (refer to Fig.14 and Fig.15 ), instead of the data strobe signal DQS, the delay of the data signal can be increased by as much as "5". When the delay of the data strobe signal DQS needs to be increased by as much as "5" (refer to Fig.16 and Fig.17 ), replacing the data select signal DQS, the delay of the data signal can be reduced by as much as "5".

[0143] As described above, the memory device 100 according to the exemplary embodiment of the inventive concept can perform the training operation with the first step and the second step. Therefore, the time required for the training operation is reduced. In addition, the memory device 100 according to the exemplary embodiment of the inventive concept can verify the delay of the data signal using the first verification value and the second verification value. Therefore, the reliability of the memory device 100 is improved.

[0144] In addition, the memory device 100 according to an exemplary embodiment of the inventive concept can dynamically adjust the delay of the data strobe signal DQS based on the change in the length (or frequency) of the cycle of the data strobe signal DQS. Therefore, in the case where the length (or frequency) of the cycle of the data strobe signal DQS changes intentionally or unintentionally, the data signal and the data strobe signal DQS can be aligned without performing the training operation again.

[0145] In the exemplary embodiments of the above inventive concept, components are described by using blocks. Blocks can be implemented using various hardware devices (such as integrated circuits, application specific ICs (ASICs), field programmable gate arrays (FPGAs), or complex programmable logic devices (CPLDs), firmware driven in hardware devices, software (such as applications), or a combination of hardware devices and software. In addition, blocks may include circuits implemented using semiconductor elements in integrated circuits or intellectual property (IP) blocks.

[0146] According to an exemplary embodiment of the inventive concept, a training operation is performed by using a rough training using a first stride and a fine training using a second stride. In addition, a verification value is stored after the training operation is completed, and whether the delay of a data signal is changed is verified by using the verification value. In addition, when one cycle of a data strobe signal changes, the delay of the data signal is adjusted. Therefore, a storage device that performs a training operation with a reduced time, verifies, and dynamically adjusts the delay of a data signal is provided.

[0147] While the inventive concept has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications in form and details may be made thereto without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A storage device, comprising: a non-volatile memory device; as well as a controller configured to exchange data signals with the nonvolatile memory device through data input and output lines and to exchange data strobe signals with the nonvolatile memory device through data strobe lines, Wherein, in the training operation, at least one of the nonvolatile memory device and the controller is configured to: perform a coarse training of adjusting the delay of the timing of sending the data signal with a first step and a fine training of adjusting the delay of the timing of sending the data signal with a second step smaller than the first step, The training operation includes reading training, In the read training, the nonvolatile memory device sends the data signal and the data strobe signal to the controller while adjusting the delay of the data signal. When the data signal is accurately recognized in the controller for the first time, the nonvolatile memory device reduces the delay of the data signal by a first step, increases the delay of the data signal by a second step, and sends the data signal and a data strobe signal to the controller.

2. The storage device according to claim 1, wherein: The controller recognizes the data signal synchronously with the data strobe signal by latching the data signal into a latched data bit, wherein, when the data signal is not accurately recognized in the controller, the nonvolatile memory device transmits the data signal and the data strobe signal to the controller while increasing the delay of the data signal by a first step, and Among them, when the latched data bit matches the specific data bit, the data signal is accurately identified.

3. The storage device according to claim 1, wherein: After the nonvolatile memory device increases the delay of the data signal by the second step, when the data signal is not accurately recognized in the controller, the nonvolatile memory device increases the delay of the data signal by the second step and transmits the data signal and the data strobe signal to the controller.

4. The storage device according to claim 3, wherein: After the precise training of increasing the delay of the data signal by the second step is started, when the data signal is accurately recognized in the controller for the first time, the controller recognizes the boundary of the data signal.

5. The storage device according to claim 1, wherein: The training operation includes writing training, In the write training, the controller sends a data signal and a data strobe signal to the nonvolatile memory device while adjusting the delay of the data signal, and receives a second data signal and a second data strobe signal corresponding to the data signal from the nonvolatile memory device. wherein the controller identifies the second data signal synchronously with the second data strobe signal by latching the second data signal as a latched data bit, wherein, when the second data signal is not accurately recognized in the controller, the controller sends the data signal and the data strobe signal to the nonvolatile memory device while increasing the delay of the data signal by a first step, and receives a second data signal and a second data strobe signal corresponding to the data signal from the nonvolatile memory device, wherein, when the second data signal is accurately recognized in the controller for the first time, the controller reduces the delay of the data signal by the first step, increases the delay of the data signal by the second step, sends the data signal and the data strobe signal to the nonvolatile memory device, and receives the second data signal and the second data strobe signal from the nonvolatile memory device, and When the latched data bit matches the specific data bit, the second data signal is accurately identified.

6. The storage device according to claim 1, wherein: The training operation includes writing training, In the write training, the controller sends a data signal and a data strobe signal to the nonvolatile memory device while adjusting the delay of the data signal, and receives a second data signal and a second data strobe signal corresponding to the data signal from the nonvolatile memory device. wherein the controller identifies the second data signal synchronously with the second data strobe signal, wherein when the second data signal is accurately identified in the controller, the controller sends the data signal and the data strobe signal to the nonvolatile memory device while increasing the delay of the data signal by a first step, and receives a second data signal and a second data strobe signal corresponding to the data signal from the nonvolatile memory device, and Wherein, when the second data signal is not accurately identified in the controller for the first time, the controller reduces the delay of the data signal by the first step, increases the delay of the data signal by the second step, sends the data signal and the data selection signal to the non-volatile memory device, and receives the second data signal and the second data selection signal from the non-volatile memory device.

7. A storage device, comprising: a non-volatile memory device; as well as a controller configured to exchange data signals with the nonvolatile memory device through data input and output lines and to exchange data strobe signals with the nonvolatile memory device through data strobe lines, Wherein, in the training operation, at least one of the nonvolatile memory device and the controller is configured to: perform a coarse training of adjusting the delay of the timing of sending the data signal with a first step and a fine training of adjusting the delay of the timing of sending the data signal with a second step smaller than the first step, The training operation includes reading training, In the read training, the nonvolatile memory device sends the data signal and the data strobe signal to the controller while adjusting the delay of the data signal. When the data signal is not accurately recognized in the controller for the first time, the nonvolatile memory device reduces the delay of the data signal by a first step, increases the delay of the data signal by a second step, and sends the data signal and a data strobe signal to the controller.

8. The storage device according to claim 7, wherein: The controller recognizes the data signal synchronously with the data strobe signal by latching the data signal into a latched data bit, wherein, when the data signal is accurately recognized in the controller, the nonvolatile memory device transmits the data signal and the data strobe signal to the controller while increasing the delay of the data signal by a first step, and Among them, when the latched data bit matches the specific data bit, the data signal is accurately identified.

9. A storage device, comprising: a non-volatile memory device; as well as a controller configured to exchange a plurality of data signals with the nonvolatile memory device through a plurality of data input and output lines and to exchange a data strobe signal with the nonvolatile memory device through a data strobe line, Wherein, in the training operation, the controller and the non-volatile memory device are configured to: align the plurality of center positions of the plurality of data signals with the timing of the transition of the data strobe signal, The controller stores information about a plurality of boundaries of a signal having a minimum width among the plurality of data signals, and After the training operation is completed, the controller is configured to: verify the alignment of the plurality of center positions of the plurality of data signals with the timing of the transition of the data strobe signal by using the information of the plurality of boundaries, Wherein, in the training operation, at least one of the nonvolatile memory device and the controller is configured to: perform a coarse training of adjusting a plurality of delays of a plurality of timings of sending the plurality of data signals with a first step and a fine training of adjusting a plurality of delays of the plurality of timings of sending the plurality of data signals with a second step smaller than the first step, The training operation includes reading training, wherein, in the read training, the nonvolatile memory device sends the plurality of data signals and a data strobe signal to the controller while adjusting the plurality of delays of the plurality of data signals, Wherein, when the multiple data signals are accurately identified in the controller for the first time, the non-volatile memory device reduces the multiple delays of the multiple data signals by a first step, increases the multiple delays of the multiple data signals by a second step, and sends the multiple data signals and a data selection signal to the controller.

10. The storage device according to claim 9, wherein: The nonvolatile memory device generates a second data strobe signal by adjusting a delay of the data strobe signal using at least one of the plurality of pieces of information of the boundaries, and transmits the second data strobe signal and the plurality of data signals to a controller.

11. The storage device according to claim 10, wherein: The controller identifies the plurality of data signals in synchronization with a second data strobe signal by latching the plurality of data signals into a plurality of latched data bits, wherein when at least one of the plurality of data signals is not accurately recognized in the controller, the controller performs the training operation again, and Wherein, when the plurality of latched data bits match specific data bits, the plurality of data signals are accurately identified.

12. The storage device according to claim 9, wherein: The controller generates a second data strobe signal by adjusting a delay of the data strobe signal using at least one of the plurality of pieces of information of the boundaries, and transmits the second data strobe signal and the plurality of data signals to the nonvolatile memory device.

13. The storage device according to claim 12, wherein: The controller receives a plurality of second data signals corresponding to the plurality of data signals and a data strobe signal from the nonvolatile memory device, identifies the plurality of second data signals in synchronization with the data strobe signal by latching the plurality of second data signals into a plurality of latched data bits, wherein when at least one of the plurality of second data signals is not accurately recognized in the controller, the controller performs the training operation again, and Wherein, when the plurality of latched data bits match specific data bits, the plurality of second data signals are accurately identified.

14. A storage device, comprising: a non-volatile memory device; as well as a controller configured to: exchange data signals with the nonvolatile memory device through data input and output lines, and exchange data strobe signals with the nonvolatile memory device through data strobe lines, Wherein, in the training operation, the controller and the non-volatile memory device are configured to: align the center position of the data signal with the timing of the transition of the data strobe signal by adjusting the first delay of sending the data signal, Wherein, at least one of the controller and the non-volatile memory device is configured to: adjust the second delay of the data strobe signal based on a change in the length of one cycle of the data strobe signal, Wherein, in the training operation, at least one of the nonvolatile memory device and the controller is configured to: perform a coarse training of adjusting a first delay of a timing of sending the data signal with a first step and a fine training of adjusting the first delay of a timing of sending the data signal with a second step smaller than the first step, The training operation includes reading training, Wherein, in the read training, the nonvolatile memory device sends the data signal and the data strobe signal to the controller while adjusting the first delay of the data signal, When the data signal is accurately identified in the controller for the first time, the nonvolatile memory device reduces the first delay of the data signal by a first step, increases the first delay of the data signal by a second step, and sends the data signal and a data selection signal to the controller.

15. The storage device according to claim 14, wherein: The at least one of the controller and the nonvolatile memory device reduces a second delay of the data strobe signal when the length of the one cycle decreases.

16. The storage device according to claim 14, wherein: The at least one of the controller and the nonvolatile memory device increases a second delay of the data strobe signal when the length of the one cycle increases.

17. The storage device according to claim 14, wherein: The controller calculates a delay of the delay unit corresponding to the length of the one cycle of the data strobe signal as a lock value, and adjusts a second delay of the data strobe signal based on a change in the lock value.

18. The storage device according to claim 14, wherein: The nonvolatile memory device and the controller exchange a plurality of data signals including the data signal through a plurality of data input and output lines including the data input and output lines, Wherein, in the training operation, the controller and the non-volatile memory device are configured to: align the plurality of center positions of the plurality of data signals with the timing of the transition of the data strobe signal, The controller stores information about a plurality of boundaries of a signal having a minimum width among the plurality of data signals, and After the training operation is completed, the controller is configured to verify the alignment of the plurality of center positions of the plurality of data signals with the timing of the transition of the data strobe signal by using the information of the plurality of boundaries.

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