Electronic device and method of forming the same

Abstract

The present invention is entitled "Electronic device and method of forming the same". The present invention discloses an electronic device, which may include a semiconductor layer and a contact structure forming an ohmic contact with the layer. In one embodiment, the semiconductor layer may include a III-N material, and the contact structure includes a first phase and a second phase, wherein the first phase includes Al, the second phase includes a metal, and the first phase contacts the semiconductor layer. In another embodiment, the semiconductor layer may be a single crystal layer having a surface along a crystal plane. The contact structure may include a polycrystalline material, the polycrystalline material including a crystal having a surface in contact with a surface of the single crystal layer, wherein the lattice mismatch between the surface of the single crystal layer and the surface of the crystal is at most 20%.

Description

Technical Field

[0001] This disclosure relates to electronic devices and methods of forming electronic devices, and more particularly, to electronic devices including a contact structure contact layer and methods of forming the same.

[0002] Related Art

[0003] Power transistors have a relatively large current flowing through the active region of the transistor when the transistor is in the on state. The on-state resistance between the source and drain in a power transistor can cause power loss within the transistor. The contact resistance between a conductive structure (e.g., a source electrode or a drain electrode) and the underlying layer is a part of the on-state resistance, and thus, a lower contact resistance results in less power loss within the transistor. Many contact structures may include a bulk conductive film, such as an Al alloy, and have at least one other film above or below the bulk conductive film. Such other films may be adhesion films, diffusion barrier films, anti-reflection films, protective films, etc. There have been many attempts to improve the conductive structure by selecting a specific sequence of films with specific compositions and thicknesses. Even with all the choices of film sequence, composition, and thickness, the contact resistance may still not be low enough. There is a need to further improve (reduce) the contact resistance. Summary of the Invention

[0004] The problem to be solved by the present invention is to reduce the contact resistance of a contact structure that forms an ohmic contact with an underlying semiconductor without causing excessive stress or other significant adverse effects within the contact structure.

[0005] In one aspect, an electronic device is provided. The electronic device includes a semiconductor layer and a contact structure that forms an ohmic contact with the semiconductor layer. The contact structure includes a first phase and a second phase different from the first phase, wherein the first phase contains Al, the second phase contains a metal, and the first phase contacts the semiconductor layer.

[0006] In one embodiment, the second phase contains Al 3 Me, Me 2 AlN, MeN, or a combination thereof, where Me is a metal.

[0007] In another embodiment, the semiconductor layer contains Al (1-x) Ga x N, where 0 < x ≤ 0.3, the second phase contacts the semiconductor layer and contains Al 3 Me, where Me includes Ti, Zr, Hf, or Ta, the contact structure includes a first film that contacts the semiconductor layer and includes the first phase and the second phase, and the ratio of Al to Al 3 Me in the first film is at least 35%, and the electronic device includes a high electron mobility transistor that includes the semiconductor layer and the contact structure.

[0008] In another embodiment, the electronic device has a plurality of contact structures having the same configuration and an average contact resistance of at most 0.5 Ω·mm.

[0009] In one aspect, an electronic device is provided. The electronic device includes a single-crystalline layer having a surface along a crystal plane; and a contact structure forming an ohmic contact with the single-crystalline layer, wherein the contact structure includes a polycrystalline material including a first crystal having a first surface in contact with the surface of the single-crystalline layer, and the lattice mismatch between the surface of the single-crystalline layer and the first surface of the first crystal is at most 20%.

[0010] In one embodiment, the single-crystalline layer includes a III-N material having a hexagonal lattice structure, the surface of the single-crystalline layer is along the (0002) crystal plane, the first crystal has a cubic lattice structure, and the surface of the crystal is along the (111) crystal plane.

[0011] In another embodiment, the single-crystalline layer includes Al (1-x) Ga x N, where 0 < x ≤ 0.3, and the surface is along the (0002) crystal plane, the conductive structure includes a film that contacts the single-crystalline layer and includes an Al phase and an Al 3 Me phase, where Me includes Ti, Zr, Hf, or Ta, the Al phase includes a first crystal and a second crystal, where the first surface of the first crystal is along the (111) crystal plane, and the second surface of the second crystal is along the (200) crystal plane, the film has a ratio of at least 35% of Al to Al 3 Me, and the electronic device includes a high electron mobility transistor including the single-crystalline layer and the contact structure.

[0012] In another embodiment, the electronic device has a plurality of contact structures having the same configuration and an average contact resistance of at most 0.5 Ω·mm.

[0013] In a further aspect, a method of forming an electronic device is provided. The method includes cleaning the surface of a semiconductor layer, where the surface is along a crystal plane; forming a contact structure including Al and a metal; and annealing the semiconductor layer and the contact structure. After annealing, the contact structure includes a first phase and a second phase different from the first phase, the first phase includes Al, the second phase includes the metal, and the first phase contacts the surface of the semiconductor layer.

[0014] In one embodiment, forming the contact structure includes forming a metal-containing film, wherein the metal-containing film is polycrystalline and includes a first crystal having an epitaxial or fibrous texture aligned with a surface of the semiconductor layer, and the lattice mismatch between the surface of the semiconductor layer and the surface of the first crystal is at most 20%. Forming the contact structure may also include forming an Al-containing film over the surface of the metal-containing film, wherein when formed, the Al-containing film is separated from the semiconductor layer by at least the metal-containing film, the Al-containing film includes at least 90 atomic % Al, the Al-containing film is polycrystalline and includes a second crystal having an epitaxial or fibrous texture aligned with a surface of the metal-containing film, and the lattice mismatch between the surface of the semiconductor layer and the surface of the second crystal is at most 20%.

[0015] The technical effects achieved by the present invention may include a contact structure comprising different phases within the contact structure, wherein an Al-containing phase contacts an underlying semiconductor layer, contains crystals having surfaces aligned with surfaces of an underlying single crystal layer, or a combination of these phases and crystal alignments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The embodiments are shown by way of example in the drawings and are not limited thereto.

[0017] Figure 1 An illustration of a cross-sectional view of a portion of a workpiece including a semiconductor layer, an insulating layer, and a contact opening extending through the insulating layer.

[0018] Figure 2 According to one embodiment, after forming the conductive layer Figure 1 Illustration of a cross-sectional view of a workpiece.

[0019] Figure 3 According to another embodiment, after forming the conductive layer Figure 1 Illustration of a cross-sectional view of a workpiece.

[0020] Figure 4 comprising after patterning the patterned conductive layer to form a contact structure Figure 2 or 3 is an illustration of a cross-sectional view of a workpiece.

[0021] Figure 5 Included are graphs of contact resistance for different relative Al contents within the bulk conductive film.

[0022] Figure 6 Included are graphs of contact resistance for contacts with specific contact dimensions at different annealing temperatures.

[0023] Figure 7 Included is a graph of the contact resistance of a contact having another specific contact size at different annealing temperatures.

[0024] Figure 8 Included are graphs of contact resistance for different contact sizes for specific relative Al contents within the bulk conductive film.

[0025] Fig. 9 Included are graphs of contact resistance over annealing duration for specific samples and annealing temperatures.

[0026] Fig.10 Included are graphs of XRD data showing the presence and absence of material within the conductive layer over a range of temperatures.

[0027] Fig.11 Included are graphs of XRD data that show the presence and absence of a material within another conductive layer over a range of temperatures.

[0028] Fig.12 Included are graphs of XRD data showing the presence and absence of material within another conductive layer over a range of temperatures.

[0029] Fig.13 Included are graphs of XRD data showing the presence and absence of material within a conductive layer over a range of temperatures.

[0030] Fig.14 Included are graphs of XRD data showing the presence and absence of material within the conductive layer over a range of temperatures.

[0031] Fig.15 Included are graphs of XRD data that show the presence and absence of a material within another conductive layer over a range of temperatures.

[0032] Fig.16 Included are graphs of XRD data showing the presence and absence of material within another conductive layer over a range of temperatures.

[0033] Fig.17 Included are graphs of XRD data showing the presence and absence of material within a conductive layer over a range of temperatures.

[0034] Fig.18 An illustration of a cross-sectional view of a portion of a workpiece including a high electron mobility transistor structure having a contact structure.

[0035] The skilled person will appreciate that the elements in the drawings are illustrated for simplicity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to help improve understanding of the embodiments of the present invention. DETAILED DESCRIPTION

[0036] The following description in conjunction with the accompanying drawings is provided to help understand the teachings disclosed herein. The following discussion will focus on the specific implementation and implementation of the teachings. This emphasis is provided to help describe the teachings and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other implementations may be adopted based on the teachings as disclosed in this application.

[0037] III-V material is intended to mean a material comprising at least one element of Group 13 and at least one element of Group 15. III-N material is intended to mean a semiconductor material comprising at least one element of Group 13 and nitrogen.

[0038] The term "alloy" is intended to mean a mixture of at least two different metallic elements, the mixture being substantially free (less than 0.1 wt %) of intermetallic compounds.

[0039] The term "compound" is intended to mean a molecule comprising at least two different elements.

[0040] The term "metal" or any variation thereof is intended to mean a material that includes elements in any of Groups 1 to 12, in Groups 13 to 16, along the line defined by atomic numbers 13 (Al), 31 (Ga), 50 (Sn), 51 (Sb), and 84 (Po) and below. Metals do not include Si or Ge.

[0041] The term "power transistor" is intended to mean a transistor that is designed to have a drain-source current (Ids) of at least 0.1 A when the transistor is in its on-state.

[0042] The terms "comprises," "comprising," "including," "having," or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a method, article, or apparatus that includes a list of features is not necessarily limited to only those features but may include other features not expressly listed or inherent to such method, article, or apparatus. In addition, unless expressly specified to the contrary, "or" refers to an inclusive or and not an exclusive or. For example, a condition A or B is satisfied by any of the following: A is true (or present) and B is false (or absent), A is false (or absent) and B is true (or present), and both A and B are true (or present).

[0043] In addition, "a" or "an" is used to describe the elements and components described herein. This is for convenience only and to give a general sense of the scope of the invention. The description should be considered to include one, at least one, or the singular also includes the plural, and vice versa, unless it is clearly intended to be contrary. For example, when a single item is described herein, more than one item can be used in place of the single item. Similarly, where more than one item is described herein, a single item can be used in place of the more than one item.

[0044] The group numbers correspond to the columns in the periodic table, which is based on the November 28, 2016 edition of the IUPAC periodic table.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs. The materials, methods, and examples are illustrative only and are not intended to be limiting. Where not described herein, many details regarding specific materials and processing actions are conventional and can be found in textbooks and other sources in the semiconductor and electronics fields.

[0046] A contact structure can be formed, which includes a crystal having a surface along a crystal plane, which is aligned with the surface along the crystal plane of the bottom layer that contacts the contact structure. A cleaning operation can be performed to ensure that substantially all oxides and other contaminants are removed before any film of the conductive layer is deposited for the contact structure. The thickness of the body conductive film can be selected so that even if the contact film is deposited before the body conductive film is deposited, a specific phase (such as an Al phase) contacts the bottom layer. The body conductive film itself or the reaction between the materials in either or both of the contact film and the capping film can react and form a separate phase in the body conductive film in addition to the main phase. Although not required in all embodiments, both the main phase and the separate phase can contact the surface of the bottom layer. At least one of the two phases may have a minimum contact resistance when contacting the bottom layer. These concepts will be better understood by the following description in conjunction with the accompanying drawings.

[0047] In one aspect, an electronic device may include a layer including a III-N material and a contact structure forming an ohmic contact with the layer. The contact structure may include a first phase and a second phase different from the first phase, the first phase may include Al, the second phase may include a metal, and the first phase may contact the layer.

[0048] In another aspect, an electronic device may include a single crystal layer having a surface along a crystal plane and a contact structure forming an ohmic contact with the single crystal layer. The contact structure may include a polycrystalline material including a first crystal having a first surface in contact with the surface of the single crystal layer, wherein the lattice mismatch between the surface of the single crystal layer and the first surface of the first crystal is at most 20%.

[0049] In another aspect, a method of forming an electronic device may include cleaning a surface of a semiconductor layer, wherein the surface is along a crystal plane; forming a contact structure comprising Al and a metal; and annealing the layer and the contact structure. After annealing, the contact structure may include a first phase and a second phase different from the first phase, the first phase may include Al, the second phase may include the metal, and the first phase may contact the surface of the layer.

[0050] Figure 1 The workpiece includes a cross-sectional view of a portion of a workpiece, the workpiece including a semiconductor layer 102, an insulating layer 122, and a contact opening 124 extending through the insulating layer 122. The semiconductor layer 102 may be a substrate (eg, a semiconductor wafer, not shown) or a layer covering the substrate 100, such as Figure 1 The surface of semiconductor layer 102 may include single crystal materials, such as Si, SiC, III-V semiconductor materials, or II-VI semiconductor materials. In one embodiment, the III-V semiconductor material may be a III-N material, such as In a Al b Ga c N, where a+b+c=1. On a relative basis, low contact resistance may be more difficult to achieve as the content of In and Al increases relative to Ga. In another embodiment, semiconductor layer 102 may include a double heterostructure that includes a combination of different III-N compounds. The concepts described herein may be advantageous for any or all of the materials previously described in connection with layer 102.

[0051] The insulating layer 122 may include a single film or multiple films. The single film or each of these films may include an oxide, a nitride, or an oxynitride. In one embodiment, the insulating layer 122 may have a thickness in the range of 20nm to 2000nm. In a specific embodiment, the insulating layer 122 may be an interlayer dielectric (ILD) layer.

[0052] A masking layer (not shown) may be formed over the insulating layer 122. The insulating layer 122 may be patterned to define a contact opening 124 that extends through the insulating layer 122 and exposes the surface 104 of the semiconductor layer 102 along the bottom of the contact opening 124. Some or all of the semiconductor layer 102 is also removed. When all of the semiconductor layer 102 below the contact opening 124 is removed, the underlying semiconductor layer (not shown) may be exposed. Figure 1 As shown, the semiconductor layer 102 is not removed or is removed very little within the contact opening 124. The surface 104 of the semiconductor layer 102 may be disposed along a crystal plane. For example, Si has a cubic lattice structure, and the surface 104 may be disposed along a (100) or (111) crystal plane. The interplanar spacing of Si along the (100) crystal plane is 0.543 nm, and the interplanar spacing of Si along the (111) crystal plane is 0.313 nm.a Al b Ga c N has a hexagonal lattice structure, and the surface 104 may be placed along (0002). In one embodiment, the interplanar spacing of AlN along the (0002) crystal plane is 0.25 nm, the interplanar spacing of GaN along the (0002) crystal plane is 0.259 nm, and the interplanar spacing of InN along the (0002) crystal plane is 0.285 nm. Vegard's law can be used to calculate the InN ratio for any composition within the contour conditions corresponding to different binary III-N. a Al b Ga c The interplanar spacing of ternary and quaternary compounds of N. Other materials may have different lattice structures and interplanar spacings. For 3C-GaN along the (111) crystal plane, the interplanar spacing is 0.261nm, for 2H-GaN along the (0002) crystal plane, the interplanar spacing is 0.259nm, for 4H-SiC along the (0004) crystal plane, the interplanar spacing is 0.251nm, and for 6H-SiC along the (0006) crystal plane, the interplanar spacing is 0.251nm. The significance of interplanar spacing will become more apparent later in this specification. The masking layer can be removed after patterning the insulating layer 122. In a specific embodiment, the masking layer can be removed by ashing using an oxygen-containing plasma.

[0053] During patterning of the insulating layer 122 or removal of the masking layer, oxides or contaminants may form along the surface 104 of the semiconductor layer 102. A cleaning operation may be performed to remove residual oxides or contaminants that may form along the surface 104. The cleaning operation may include exposing the surface 104 to a solvent comprising HCl, HF (with or without a buffer such as NH 4 F), (CH 3 ) 4 A solution of NOH (tetramethylammonium hydroxide or TMAH) or the like. A range of cleaning solutions can be used. For example, HF solution can be used to remove oxides, and HCl solution can be used to remove metal contamination.

[0054] In another embodiment, a cleaning operation may be performed within a deposition or reaction chamber. For example, the workpiece (including the semiconductor layer 102 along the bottom of the contact opening 124) is exposed to a reducing environment. The reducing environment may contain a reducing gas, an inert gas, or a combination thereof. In a specific embodiment, the reducing environment may contain up to 4 mol % H 2 (H in air 2 explosion limit) and the remaining inert gas or gases (Ar, He, N 2In another specific embodiment, the reducing environment may include one or more inert gases at a temperature above room temperature (e.g., greater than 50° C.) without a reducing agent. In another example, a plasma formed from an inert gas (such as Ar, He, etc.) may be directed along the surface 104. For example, in a sputtering tool, the plasma may be directed to the workpiece rather than the sputtering target to physically remove oxides or another contaminant. This method may use low power to keep damage to the surface relatively low.

[0055] The inventors have discovered that a conductive structure can be formed that can be advantageously aligned with the surface 104 within the contact opening 124 to further reduce contact resistance. The crystal structures of layer 102 and the conductive material can be aligned if their lattice parameters match closely enough (e.g., within 20%). A conductive material having a hexagonal lattice structure can have a similar lattice structure to In if the lattice mismatch along the a-axis is limited (e.g., less than 20%). a Al b Ga c Conductive materials with cubic lattices (body-centered cubic (BCC), face-centered cubic (FCC), or simple cubic) can form an epitaxial or fibrous structure with In along the

[110] direction if the lattice mismatch between the cubic and hexagonal lattices a-axis along the

[110] direction is limited (up to 20%). a Al b Ga c The epitaxial or fibrous structure of the N hexagonal lattice is aligned. In one embodiment, the a-axis of AlN has a lattice constant of 0.311 nm, the a-axis of GaN has a lattice constant of 0.318 nm, and the a-axis of InN has a lattice constant of 0.353 nm. Vegard's law can be used to calculate the InN constant for any composition within the contour conditions corresponding to different binary III-N. a Al b Ga c Lattice constants along the a-axis for ternary and quaternary compounds of N.

[0056] The following is a table of crystal parameters of AlN, GaN and InN and some conductive materials as the semiconductor layer 102. As used herein, lattice mismatch is:

[0057] in

[0058] LM is the lattice mismatch (expressed as an absolute value),

[0059] dsemi is the lattice constant of the semiconductor layer 102 along the surface 104, and

[0060] dcond is the closest distance between two atoms of a specific conductive material and a crystal plane. In the case where the crystal lattice of the specific conductive material is hexagonal, dcond is the lattice constant of the hexagonal crystal. In the case where the crystal lattice is cubic, dcond is the closest distance between two atoms of the specific conductive material in the (111) crystal plane, and therefore along the

[110] direction.

[0061] m is an integer: 1 when the crystal lattice of the specific conductive material is a hexagonal crystal type or a face-centered cubic crystal type, and 2 when the crystal lattice of the specific conductive material is a body-centered cubic crystal type.

[0062] Table 1 – Crystal parameters

[0063]

[0064]

[0065] The lattice mismatch in Table 1 is related to AlN, GaN, and InN along the (0002) crystal plane. When the lattice mismatch is up to 20%, the conductive material may have an epitaxial or fibrous texture aligned with the surface 104. Referring to Table 1, Al, α-Ti, Zr, Hf, and fcc-Ta may be aligned with Al. z Ga (1-z) N is aligned, where 0≤z≤1, and due to the high lattice mismatch, β-Ti, α-Ta, V, Nb, Mo and α-W cannot be aligned with Al along the (111) plane. z Ga (1-z) N(0002) crystal plane alignment. Al, Ti, Zr, Hf and fcc-Ta with In a Al b Ga c Alignment of N is easier for low In content (a<0.2) because the lattice mismatch is much lower than in the case of pure InN (a=1). After reading this specification, a skilled person will be able to determine which materials and crystal orientations have acceptable lattice mismatch for a specific composition of semiconductor layer 102 and interplanar spacing along surface 104.

[0066] The alignment of thin films, such as layer 102 and conductive material, is based on the specific interface structure between the lattices of layer 102 and conductive material. These interfaces are characterized by lattice mismatch. It is expected that low lattice mismatch is conducive to forming a nearly perfect interface between layer 102 and conductive material. The alignment of the crystal planes in conductive material and layer 102 with the same interplanar spacing is characterized by epitaxial or fiber texture.

[0067] The lattice parameters of layer 102 and the conductive material are such that the (0002) hexagonal plane of layer 102 is identical to the (111) FCC plane of the conductive material, both of which are hexagonally close-packed, and in this particular case, the interplanar spacings are similar. The interplanar spacings of AlN along the (0002) plane are 0.25 nm, the interplanar spacings of GaN along the (0002) plane are 0.259 nm, and the interplanar spacings of InN along the (0002) plane are 0.285 nm, which are very close to the Al (111) interplanar spacings of 0.233 nm or the fcc-Ta (111) interplanar spacings of 0.243 nm, with a mismatch of at most 20%. Therefore, when layer 102 and the conductive material are joined along the hexagonal close-packed planes, the resulting interface is completely coherent.

[0068] The lattice parameters of layer 102 and the conductive material are such that (i) the (0002) hexagonal plane of layer 102 and (ii) the (111) FCC or (0002) hexagonal plane of the conductive material (depending on the specific conductive material) are very close, and in this specific case, the interplanar spacing is also similar. The interplanar spacing of Ti (0002) 0.234 nm, Zr (0002) 0.257 nm, and Hf (0002) 0.253 nm is very similar to the interplanar spacing of AlN, GaN, and InN, with a mismatch of up to 20%. Therefore, when layer 102 and the conductive material are joined along a hexagonal close-packed plane, the resulting interface is completely coherent.

[0069] A conductive layer is formed over the insulating layer 122 and within the contact opening 124. The conductive layer may include a single film or a plurality of films. Figure 2 In the embodiment, the conductive layer 200 may include a contact film 202, a body conductive film 204 and a capping film 206, which may be an anti-reflection film, a protective film, etc. z Ga (1-z) With respect to the N semiconductor layer 102 and the surface 104 along the (0002) crystal plane, the contact film 202 may include Ti, Zr, Hf, or Ta.

[0070] The contact film 202 may comprise a metal. The contact film 202 may be deposited so that the (0002) crystal plane of α-Ti, Zr, or Hf or the (111) crystal plane of fcc-Ta is aligned with the surface 104 of the layer 102. As will be discussed in more detail later in this specification, data indicate that the contact film 202 is epitaxially or fibrously textured and aligned with the semiconductor layer 102 when deposited. In one embodiment, the contact film 202 may be formed by sputtering deposition. In another embodiment, the contact film 202 may be formed using molecular beam epitaxy or atomic layer deposition.

[0071] The bulk conductive film 204 may include Al. In one embodiment, the bulk conductive film may include at least 90 atomic % Al or at least 95 atomic % Al. The bulk conductive film may include one or more other materials, such as Cu, Si, W, etc., and these other materials may constitute up to 5 atomic % of the bulk conductive film. Compared with the (200) crystal plane of Al, the (111) crystal plane of Al is closer to the (200) crystal plane of Al. z Ga (1-z) The (0002) crystal plane of N and the (0002) crystal plane of Ti, Zr or Hf or the (111) crystal plane of fcc-Ta (depending on the specific metal used for contact film 202) have a lower lattice mismatch. As will be discussed in more detail later in this specification, the data show that the bulk conductive film 204 has a lower lattice mismatch with Al when deposited. z Ga (1-z) The (0002) crystal plane of N is aligned with the contact film 202. In one embodiment, the bulk conductive film 204 may be formed by sputtering deposition. The bulk conductive film 204 has some Al crystals with surfaces along (200), thereby maintaining a lower strain in the bulk conductive film 204 than in the case where all the bulk conductive film 204 is a single crystal Al film with its lower surface along the (111) crystal plane. Therefore, the bulk conductive film 204 is polycrystalline, some of the Al crystals have surfaces along the (111) crystal plane, and other Al crystals have surfaces along the (200) crystal plane.

[0072] The capping film 206 is optional and may be used as an anti-reflection film, a protective film, etc. The capping film 206 may have one or more films containing one or more metals (e.g., Ti, Ta, W, TiW, Pt, Pd, Ni, etc.) or containing metal nitrides (TiN, TaN, WN, etc.). When the capping film 206 contains a metal or a metal nitride, either or both of them may react with Al in the bulk conductive layer 204, and therefore, the thickness of the bulk conductive film 204 may need to take into account the formation of Al during subsequent annealing. 3 Me, Me 2 Some Al in the bulk conductive film 204 of AlN, MeN or a combination thereof. The capping film 206 may be sputter deposited. When a metal target is used to sputter deposit a metal nitride, some ions (e.g., Ar + ) may cause some Me-N bonds to break, thereby allowing Me atoms to be deposited with the metal nitride film. Similarly, when reactive sputtering is used, some Me atoms may be deposited with the metal nitride film. Therefore, the thickness of the bulk conductive film 204 may need to take into account the intentional or unintentional incorporation of Me atoms outside of the compound within the capping film 206.

[0073] The thicknesses of films 202, 204, and 206 may be at least partially dependent on each other. Turning to the bulk conductive film 204, its thickness may depend on one or more considerations. The lower limit of the thickness of the bulk conductive film 204 may depend on the thickness and composition of the contact film 202, and potentially on the thickness and composition of the capping film 206. More specifically, during subsequent annealing, metal atoms within the contact film 202, the capping film 206, or both may react with Al within the bulk conductive film 204 to form Al. 3 Me, Me 2 AlN, MeN or a combination thereof, where Me is a metal. Even if all metal atoms have reacted, the thickness of the bulk conductive film 204 can have a certain thickness so that some Al remains outside the metal compound. This allows the Al in the bulk conductive film 204 to make direct contact with the semiconductor layer 102 along the surface 104 during subsequent annealing.

[0074] The relative content of Al and metal in the contact film 202 and the bulk conductive film can be used to determine the thickness. The relative content of free Al (expressed as atomic %) can be given by the following formula:

[0075] Al 相对 % = Al 游离 / (Al 总 +Me 总 )*100%,

[0076] in:

[0077] Al 相对 % is the relative content of Al,

[0078] Al 游离 It is Al phase (not any compound with metal Me such as Al 3 Me, Me 2 The number of Al atoms / unit area in a part of AlN, MeN, etc.

[0079] Al 总 is the total number of Al atoms per unit area in the films 202, 204, and 206, either in the form of free Al or in the form of a compound with any other element.

[0080] Me 总 Me in the membranes 202, 204 and 206 in the form of free Me or in the form of a compound with Al (Al 3 Me, Me 2 The total number of metal atoms / unit area in the form of AlN, MeN, etc.

[0081] Unit area for Al 游离 、Al 总 and me 总is the same area (e.g. mm -2 、cm -2 wait).

[0082] In one embodiment, Al 相对 % is at least 35%, at least 40% or at least 45%, and in another embodiment, Al 相对 % is at most 100% (in embodiments where contact film 202 and capping film 206 are not used), at most 97% or at most 95%. In a specific embodiment, the Al along surface 104 相对 The percentage of % may be in the range of 80% to 95%. The significance of these values ​​will become more apparent later in this specification. 相对 % may affect the thickness of one or both of the contact film 202 and the bulk conductive film 204 .

[0083] In one embodiment, the thickness of the contact film 202 is less than 10% of the thickness of the bulk conductive film 204, and in a specific embodiment, less than 2% of the bulk conductive film 204. The thickness of the contact film 202 may be in the range of 1 nm to 10 nm. In one embodiment, the thickness of the bulk conductive film 204 may be in the range of 50 nm to 900 nm, and in a specific embodiment, the thickness of the bulk conductive film 204 may be in the range of 100 nm to 500 nm.

[0084] The thickness of the capping film 206 may depend on the function that the capping film 206 is to provide. For example, when the capping film 206 is an anti-reflective film, the thickness may be a function of the wavelength of radiation used to pattern the masking layer used to define the conductive layer 200 formed subsequently, or when the capping film 206 is a protective film, the thickness may have a sufficient value to fully prevent water vapor in the air from reaching the body conductive film 204, etc. In one embodiment, the capping film 206 may be in the range of 1nm to 100nm, and in a specific embodiment, the thickness of the capping film 206 may be in the range of 5nm to 30nm. Depending on the composition of the capping film 206, the thickness of the body conductive film 204 may or may not be significantly affected. As previously described, the thickness of the body conductive film 204 is sufficient to ensure that not all Al reacts with one or more materials within the films 202 and 206.

[0085] The considerations of the thickness of films 202, 204 and 206 and the possible range of thickness are described above. The actual thickness used may depend on the application. Therefore, the numerical value of the thickness of films 202, 204 and 206 is exemplary and not limited to the present invention. After reading this specification, the technician will understand that the thickness of films 202, 204 and 206 may be thinner or thicker than the values ​​described above.

[0086] In another embodiment, different conductive layers may be used. Figure 3 Another embodiment is included, which includes a conductive layer 300, which includes a bulk conductive film 304 and a capping layer 206. The bulk conductive layer 304 may include an alloy of Al and a metal, wherein the metal content, in terms of atoms, does not exceed 10 atomic % of the total atomic content of the metal in the bulk conductive film 304. In another embodiment, the metal content does not exceed 5 atomic % or 2 atomic %. In another embodiment, the metal content is at least 0.01 atomic % of the Al content. The remainder of the bulk conductive film may be Al or almost entirely Al (e.g., the remainder may be at least 98 atomic % Al). The bulk conductive film 304 may be formed by co-sputtering using separate Al-containing and metal-containing targets or by sputtering using a target containing an alloy of Al and a metal element at its desired content level as previously described. The Al-containing target or alloy target may contain one or more other elements, such as Cu, Si, W, etc., in an amount relative to Al as previously discussed.

[0087] The thickness of the bulk conductive film 304 may be in the range of 50 nm to 900 nm, and in a specific embodiment, the thickness of the bulk conductive film 304 may be in the range of 100 nm to 500 nm. Figure 2 Similar to the illustrated embodiment, the capping film 206 in the conductive layer 300 is optional. The composition, thickness, and other considerations previously described for the capping film 206 apply to the conductive layer 300.

[0088] The conductive layer 200 or 300 may be patterned and then annealed to form the contact structure 400, such as Figure 4 The contact structure 400 extends through the insulating layer 122 within the contact opening 124 and contacts the surface 104 of the semiconductor layer 102. In one embodiment, the removal may be performed using an etching technique or another conventional removal technique.

[0089] The workpiece including the contact structure 400 is annealed. The properties of the conductive layer can be affected by the temperature and duration of the annealing. A relatively low annealing temperature can be used at such annealing temperature for a relatively long duration, and a relatively high annealing temperature can be used at such temperature for a relatively short duration.

[0090] See also Figure 2 and Figure 3 , part or all of the metal in the contact film 202 or the bulk conductive film 304 and, when applicable, in the capping film 206 may react with Al in the bulk conductive film 204 or 304 to form Al 3 Me, Me 2 AlN, MeN or a combination thereof, wherein Me is a metal. Figure 4In the illustrated embodiment, the contact structure 400 includes an annealed conductor film 404 that includes a solid Me-Al phase 4042 and a solid Al phase 4044. The Me-Al phase 4042 may include Al 3 Me, Me 2 AlN, MeN, or a combination thereof. In addition to Al, Al phase 4044 may also include Cu, Si, or another element present in bulk conductive film 204 or 304 when deposited. Al phase 4044 may include at least 90 atomic % or at least 95 atomic % Al.

[0091] The Me-Al phase 4042 may include discrete portions at least partially surrounded by the Al phase 4044. Figure 4 In the embodiment shown, each of phases 4042 and 4044 comprises crystals that contact a semiconductor material (such as a III-N material) along surface 104 of semiconductor layer 102. In one embodiment, surface 104 of semiconductor layer 102 comprises Al z Ga (1-z) N, and the surface 104 is along the (0002) crystal plane, and the bulk conductive film 404 is polycrystalline and includes Al crystals (“Al 111 crystals”), these surfaces are z Ga (1-z) The (0002) crystal plane of N is in contact with the Al 0.25 Ga 0.75 The Al content is about 9.6% for N and about 9.8% for GaN, so in the finished device the Al crystal has a surface along the (111) crystal plane aligned with the crystal lattice of the semiconductor layer 102. This alignment can achieve lower contact resistance.

[0092] In the finished device, the percentage of the surface 104 in contact with the Al phase 4044 can be varied. As described herein, in general, a higher percentage of the Al phase 4044 in contact along the surface 104 of the semiconductor layer 102 provides a lower and more consistent (lower standard deviation) contact resistance. Along the surface 104, the Al phase 4044 occupies at least 1%, at least 5%, or at least 10% of the surface 104, and in another embodiment, the Al phase 4044 occupies up to 100% of the surface 104 (without the Me-Al phase along the surface 104), up to 95%, or up to 90%. In a specific embodiment, the area of ​​the surface 104 occupied by the Al phase 4044 is in the range of 50% to 95%.

[0093] Some annealing temperatures and durations at annealing temperatures are provided below for the purpose of guidance, not to limit the actual annealing temperature and duration used. In one embodiment, the annealing temperature may be at least 500°C, at least 525°C, or at least 550°C, and in another embodiment, the annealing temperature may be at most 950°C, at most 925°C, or at most 900°C. In a specific embodiment, the annealing temperature is in the range of 550°C to 800°C. In one embodiment, the duration at the annealing temperature may be at least 30s, at least 45s, or at least 60s, and in another embodiment, the duration is at most 300s, at most 270s, or at most 240s. In a specific embodiment, the duration is in the range of 60s to 180s. The annealing temperature and duration may be outside the above values. After reading this specification, the technician will be able to determine the annealing temperature and duration that meet the specific application needs or requirements.

[0094] In another embodiment, the patterning and annealing operations may be reversed. Specifically, the conductive layer 200 or 300 may be annealed first and then patterned to form the conductive layer. Figure 4 4. In another embodiment (not shown), the capping film 206 may be formed later in the process sequence. After forming the conductor film 204 or 304, the annealing described previously may be performed before forming the capping film 206. After performing the annealing, the capping film 206 may be formed, and the resulting conductive layer may be patterned to form a conductive structure.

[0095] Figures 5 to 9 Including for different Al 相对 % value, annealing temperature, contact opening size and annealing duration. The contact structure is based on Figure 2 The conductive layer 200 shown in FIG. Figure 4 A contact structure 400 is shown. Figure 5 Including for different Al 相对 % value at temperatures ranging from 500°C to 950°C. The contacts have an area size of 100 μm × 100 μm and the annealing time is 90 s. 相对 When the percentage of Al is 20%, the average contact resistance is higher than 0.5Ω*mm for all annealing temperatures, and the standard deviation of the contact resistance is relatively high at temperatures of 500°C and at least 650°C. 相对 When % is 33%, Figure 5 The average contact resistance at each annealing temperature listed is higher than 0.5Ω*mm and is comparable to that of higher Al 相对 % values, the standard deviation is relatively high; however, it is higher than that of 20% Al 相对% is significantly better. For 48%, 64% and 81% Al 相对 %, the average contact resistance and standard deviation are even lower for many annealing temperatures. 相对 When % is 100% (no contact film 202 or no contact film 202 and capping film 206), the average contact resistance and standard deviation may increase. Figure 5 It can be seen that at 100%, the average contact resistance is greater than 0.5Ω*mm and is similar to Al 相对 The standard deviations are relatively high for all annealing temperatures compared to the samples with values ​​ranging from 48% to 81%.

[0096] Figure 6 and Figure 7 is similar, except that a smaller contact area is used and Al 相对 % is in the range of 81% to 97%. The annealing temperature is in the range of 570° C. to 850° C., and the duration of each annealing is 90 seconds. Figure 6 The contact area is 2 μm × 100 μm, and Figure 7 The contact area is 6 μm × 100 μm. 相对 % value, for different annealing temperatures, Al 相对 The average contact resistance and standard deviation when % is 97% between Al 相对 % is 100% and Al 相对 % is 93% between the average contact resistance and the standard deviation. Al 相对 The average contact resistance and standard deviation of 81%, 90%, and 93% Al2O3 are similar to each other at lower annealing temperatures, and at higher annealing temperatures, 93% Al2O3 has a 相对 % than 90% Al 相对 % is slightly better (lower average contact resistance and standard deviation), which in turn is better than 81% Al 相对 % is slightly better.

[0097] Figure 8 Including Al 相对 % is 81%, 90% and 93%. The annealing temperature is 570°C and the duration is 90s. The contact area ranges from 1.5 microns × 100 microns to 100 microns × 100 microns. For each Al 相对 %, the average contact resistance and standard deviation decrease with the increase of contact area. In general, for a specific contact area, in Al 相对 The average contact resistance and standard deviation are better when the % increases from 81% to 93%.

[0098] Fig. 9A graph is included showing the effect of annealing temperature of different durations on contact resistance for different bulk conductive film 204 compositions and sputtering conditions. AlCu refers to a bulk conductive film containing about 99.5 atomic % Al and about 0.5 atomic % Cu, and AlCuW refers to a bulk conductive film containing about 98.5 atomic % Al, about 1 atomic % Cu, and about 0.5 atomic % W. The contact area is 6 microns by 100 microns, and AlCuW is about 10 microns. 相对 % is 80%. 相对 % is 81%. It can be seen from AlCu sputtered at 350°C ("AlCu at 350°C") that for temperatures between 500°C and 570°C, the contact resistance is improved by longer annealing times. Although the contact resistance at lower temperatures and relatively short durations does not appear in these graphs, substantially longer annealing times (such as 10 minutes or longer) may provide acceptable contact resistance even at temperatures as low as 500°C. At temperatures in the range of 550°C to 570°C, an annealing time of 60s is sufficient to make the average contact resistance less than 0.5Ω*mm. When the annealing temperature is 520°C and the duration is 240s, the annealing temperature is 530°C and the duration is 150s, and the annealing temperature is 540°C and the duration is 120s, an average contact resistance of up to 0.5Ω*mm can be achieved.

[0099] One example has a bulk conductive film 204 comprising AlCu and is sputtered without applying any external heat to the substrate chuck (AlCu at 50° C.) and the annealing temperature is 570° C. For the same annealing duration, the AlCu sample at 350° C. performs better than the AlCu sample at 50° C. In general, the sputtering conditions, such as substrate temperature, pressure, and power, have no significant effect on the contact resistance.

[0100] Improvement (reduction) in contact resistance can help reduce on-state resistance (Rdson). Reduction in Rdson can be particularly significant in power transistors because lower Rdson causes less energy loss when current flows through the transistor when the power transistor is in the on-state. The following description presents a high electron mobility transistor (HEMT) to provide a specific embodiment in which the contact structure provides lower contact resistance, thereby providing lower Rdson and higher on-state Ids.

[0101] As previously described, either or both of the contact film and the bulk conductive layer may be aligned with the underlying film or underlying layer when deposited. Figures 10 to 17 Included are graphs of X-ray diffraction (XRD) data for different compositions of the conductive layer. Figures 10 to 17The data in are based on in situ XRD measurements where each sample was ramped at 1°C per second and the XRD was continuously monitored. Therefore, the conductive layer as deposited can always be read on the left hand side of each graph. In the following examples, the semiconductor layer is Al 0.25 Ga 0.75 The present invention is described in detail in detail below. The present invention is described in detail in detail below. The present invention is described in detail in detail below. The present invention is described in detail below. The present invention is described in detail below. The present invention is described in detail below.

[0102] Fig.10 The XRD data of the conductive layer includes Ti for the contact layer 202, Al for the conductor film 204, and TiN as the capping film 206. In this specific example, Al 相对 % is 74%. Along the left hand side, data for Ti(0002), Al(111), TiN(111), and TiN(200) can be seen. The Ti(0002) and Al(111) signals overlap. The presence of Ti(0002) corresponds to the presence of Al(111) along the surface 104 of the semiconductor layer 102. 0.25 Ga 0.75 The hexagonal α-Ti phase of the contact film 202 is aligned with N(0002), and the Al(111) of the conductor film 204 is aligned with Ti(0002) of the contact film 202.

[0103] At about 400℃, with Al 3 The corresponding data for Ti(113) become apparent at about 450°C. 3 Ti(004) becomes apparent, and at about 480°C, Al 3 Ti(113) and Al 3 Ti(004) and Al 3 A secondary signal of Ti(200) becomes apparent, and finally Ti(0002)+Al(111). Therefore, all Ti and Al in the contact film and bulk conductive film are consumed, and therefore, substantially all of the annealed bulk conductive film is Al. 3 Ti. TiN(111) and TiN(200) are still present, so the conductive layer includes annealed Al 3 Ti bulk conductive film and TiN capping layer. When further heated at about 800°C and above, Ti 2 AlN(10-13) becomes apparent. Therefore, some Al 3 Ti reacts with excess Ti compared to Al and with Al 0.25 Ga0.75 N or TiN reacts to form Ti 2 AlN. Therefore, the conductive layer contains Ti as the annealed contact film 2 AlN, lower Al content in annealed conductive film 3 Ti and the remaining TiN portion as the annealed capping film.

[0104] Fig.10 The data in 2010 indicate that insufficient Al may be present in the bulk conductive film 202 during deposition because substantially all of the Al is consumed to form Al 3 Ti, which has a higher resistivity than Al in the bulk conductive film 202. Al 3 Ti has a square lattice structure and will not react with Al 0.25 Ga 0.75 N alignment.

[0105] See also Fig.11 , when deposited, the conductive layer resembles Fig.10 , the difference is Al 相对 The Ti(0002) in the contact film 202 is present, and the Ti(0002) in the contact film 202 is in contact with the Al(0002) along the surface 104 of the semiconductor layer 102. 0.25 Ga 0.75 N(0002) is aligned, and Al(111) of the conductor film 204 is aligned with Ti(0002) of the contact film 202 .

[0106] and Fig.10 Different, in Fig.11 In the graph, the coincidence signals of Ti(0002) and Al(111) are still obvious up to about 650°C. In fact, Ti(0002), which again corresponds to the hexagonal α-Ti phase, disappears at about 480°C and is completely consumed to form Al(111). 3 The excess of Ti(113), Al(111) and the secondary peak of Al(200) remain until Al melts at about 660℃. Fig.13 In the TEM images, it will be demonstrated that when the sample cools and the Al recrystallizes, the Al(111) and Al(200) signals reappear. Thus, Al is present at all temperatures because Al(111) is deposited in an amount such that even when all Ti(0002) is consumed in the reaction with Al(111), Al(111) is present. 3 Ti(113) is no longer evident at about 700°C and reorients to Al 3 Ti(004). TiN(111) and TiN(200) are visible in the capping film 206 at all temperatures. Therefore, at annealing temperatures of about 480°C and above, the annealed conductor film contains Al and Al 3Ti, and the annealed capping film contains TiN. Al(111) orientation and Al 0.25 Ga 0.75 The minimum lattice mismatch of N of about 9.5% indicates that Al and Al 0.25 Ga 0.75 N epitaxial or fiber structure alignment.

[0107] See also Fig.12 , when deposited, the conductive layer resembles Fig.11 , the difference is that the contact film 202 and the body conductive film 204 are reversed. The Al(111) of the conductive film and the Al(111) along the surface 104 of the semiconductor layer 102 0.25 Ga 0.75 N(0002) is aligned. Al(200) of the bulk conductive film 204 can also be seen.

[0108] Fig.12 The Al(111) is present until the remaining Al melts, including Ti(0002) (see α-Ti), Al(111), and Al(200) until about 660°C. Therefore, Al(111) is present until the remaining Al melts, because Al(111) is deposited in an amount such that even when all Ti(0002) is consumed in the reaction with Al(111), Al(111) is present. 3 Ti(113) becomes apparent at about 320°C, and Al 3 Ti(113) is no longer noticeable at about 700°C. Al 3 Ti(004) becomes apparent at a temperature of about 650°C. TiN(111) and TiN(200) in the capping film 206 are visible at all temperatures. Thus, at annealing temperatures of about 480°C and above, the annealed conductor film contains Al and Al 3 Ti, and the annealed capping film contains TiN. Al(111) orientation and Al 0.25 Ga 0.75 The minimum lattice mismatch of N of about 9.5% indicates that Al and Al 0.25 Ga 0.75 N epitaxial or fiber structure alignment.

[0109] See also Fig.13 , when deposited, the conductive layer resembles Fig.11 , except that there is no contact film 202. The Al(111) of the conductor film and the Al(111) along the surface 104 of the semiconductor layer 102 0.25 Ga 0.75 N(0002) is aligned. Al(200) of the bulk conductive film 204 can also be seen.

[0110] Fig.13Contains TiN(111) and TiN(200) at all temperatures. The signals of Al(111) and Al(200) are no longer visible at about 660°C due to melting of Al. After cooling, Al solidifies, and Al(111) and Al(200) become present. Al 3 Ti(113) is relatively weak at relatively high temperatures. Therefore, a relatively small amount of Ti from the capping film reacts with Al. The Al(111) orientation and the 0.25 Ga 0.75 The minimum lattice mismatch of N of about 9.5% indicates that Al and Al 0.25 Ga 0.75 N epitaxial or fiber structure alignment.

[0111] See also Fig.14 , the bulk conductive film 304 is deposited as Al 相对 The Ti(0002) and Al(111) in the contact film 202 and the Al(0002) along the surface 104 of the semiconductor layer 102 are mixed. 0.25 Ga 0.75 N(0002) is aligned. Fig.14 The materials seen are similar to Fig.12 .

[0112] Fig.14 The Ti(0002) (see α-Ti), Al(111) and Al(200) are formed until about 660°C. When all Ti is consumed in the reaction with Al(111) and Al(200) to form Al 3 When Ti(113) is present, the signal of Ti(0002) disappears at about 480°C, and the signals of excess Al(111) and Al(200) disappear at about 660°C due to Al melting. 3 Ti(113) and Al 3 The signal of Ti(004) becomes apparent at approximately 350°C and 660°C. Therefore, all Ti(0002) is consumed in the reaction with Al. After cooling, when Al cools below its melting point, the signal ( Fig.14 (not shown) reappears. Al(111) along Al 0.25 Ga 0.75 N exists on the surface. Al(111) orientation and Al 0.25 Ga 0.75 The minimum lattice mismatch of N of about 9.5% indicates that Al and Al 0.25 Ga 0.75 N epitaxial or fiber structure alignment.

[0113] See also Fig.15, when deposited, the conductive layer resembles Fig.11 , the difference is that Ta replaces Ti in the contact film 202, and Al 相对 % is 91%. During deposition, the signals of Ta(111), Al(111), TiN(111) and TiN(200) are more obvious, and Ta(111) corresponds to the fcc-Ta phase. At a temperature of about 500°C, the signals of Ta(111) and Al(111) become weak, and Al(111) 3 Ta(112) and Al 3 Ta(020) appears. Ta(111) is completely consumed in the reaction with Al(111) at about 630°C to form Al 3 Ta. When Al melts, the remaining Al(111) disappears. Other Al 3 Ta signal appears at higher temperature: Al 3 Ta(004) appears at about 630℃, and Al 3 Ta(013) appears at about 680°C. TiN(111) remains evident over the entire temperature range. Therefore, at annealing temperatures of about 500°C and above, the annealed conductor film contains Al and Al 3 Ta, and the annealed capping film contains TiN. Al(111) orientation and Al 0.25 Ga 0.75 The minimum lattice mismatch of N of about 9.5% indicates that Al and Al 0.25 Ga 0.75 N epitaxial or fiber structure alignment.

[0114] See also Fig.16 , when deposited, the conductive layer resembles Fig.11 , the difference is that Zr replaces Ti in the contact film 202, and Al 相对 % is 85%. During deposition, the signals of Al(111), TiN(111), Zr(0002) and Zr(10-10) are more obvious. Starting from a temperature of about 450°C, the signals of Al(111), Zr(0002) and Zr(10-10) become weak, and the signals of Al(111), TiN(111), Zr(0002) and Zr(10-10) become weak. 3 Zr(114) and Al 3 At about 580°C, all Zr(0002) and Zr(10-10) are consumed in the reaction with Al(111) to form Al 3 Zr. The remaining Al(111) signal is replaced by Al 3 The Zr(114) signal covers the Al until it melts at about 650°C. From about 700°C and above, the Al 3 Zr(114) and Al 3Zr(020) reorients to Al 3 Zr(008). Therefore, at annealing temperatures of about 580°C and above, the annealed conductor film contains Al and Al 3 Zr, and the annealed capping film contains TiN. Al(111) orientation and Al 0.25 Ga 0.75 The minimum lattice mismatch of N of about 9.5% indicates that Al and Al 0.25 Ga 0.75 N epitaxial or fiber structure alignment.

[0115] See also Fig.17 , when deposited, the conductive layer resembles Fig.11 , the difference is that Hf replaces Ti in the contact film 202, and Al 相对 % is 85%. During deposition, the signals of Al(111), TiN(111), Hf(0002) and Hf(10-10) are more obvious. At a temperature of about 460°C, Hf(0002) and Hf(10-10) disappear, and Al 3 Hf(114) becomes obvious and overlaps with the Al(111) signal. When Al melts at about 650℃, the remaining Al(111) disappears. 3 Hf(015) and Al 3 The secondary signal of Hf(020) is also obvious. From about 700℃ and above, Al 3 Hf(114) and Al 3 Hf(020) reorients to Al 3 Hf(008). Therefore, at annealing temperatures of about 460°C and above, the annealed conductor film contains Al and Al 3 Hf, and the annealed capping film contains TiN. Al(111) orientation and Al 0.25 Ga 0.75 The minimum lattice mismatch of N of about 9.5% indicates that Al and Al 0.25 Ga 0.75 N epitaxial or fiber structure alignment.

[0116] In summary, the XRD data and the small lattice constant mismatch indicate that, as deposited, the contact film 202, the bulk conductive film 204, and the bulk conductive film 304 are aligned with the underlying layer or film. Furthermore, different metals can be used to achieve alignment and still achieve alignment. After annealing, the Al phase 4044 has a (111) orientation, which, along with its alignment with the Al 0.25 Ga 0.75 The minimum lattice mismatch of about 9.5% between N and Al indicates that 0.25 Ga 0.75 N epitaxial or fiber structure alignment.

[0117] Exemplary electronic devices that may utilize the concepts described herein may include a transistor, a resistor, a capacitor, or another electronic component requiring a low resistance ohmic contact.The following description of a HEMT structure is intended to illustrate and not to limit the scope of the invention as defined by the appended claims.

[0118] Fig.18 A cross-sectional view of a portion of a workpiece 1800 is included, the workpiece including a HEMT structure. Below is a description of the physical structure. Details related to exemplary formation methods other than the formation of source, gate, and drain electrodes are described in U.S. Patent Application No. 15 / 893,328, filed on February 9, 2018, and incorporated herein by reference.

[0119] The workpiece 1800 includes a substrate 1810, a semiconductor stack 1820, a gate electrode 1834, an insulating layer 1840, and electrodes 1862, 1864, and 1866. The substrate 1810 may include silicon, sapphire (single crystal Al 2 O 3 ), silicon carbide (SiC), aluminum nitride (AlN), gallium oxide (Ga 2 O 3 ), spinel (MgAl 2 O 4 ), another suitable substantially single-crystalline material, etc. The specific material and crystal orientation along the major surface may be selected based on the composition of the semiconductor stack 1820 that will be subsequently formed over the substrate 1810 .

[0120] The semiconductor stack 1820 may include a buffer layer 1822, a channel layer 1824, and a barrier layer 1826. Each layer within the semiconductor stack 1820 may include a III-N material, and in a specific embodiment, may include Al x Ga (1-x) N, where 0≤x≤1. The composition of the buffer layer 1822 may depend on the composition of the channel layer 1824. The composition of the buffer layer 1822 may vary with thickness, such that the closer the buffer layer 1822 is to the substrate 1810, the higher its aluminum content is, and the closer it is to the channel layer 1824, the higher its gallium content is. In a specific embodiment, the cation (metal atom) content in the buffer layer 1822 near the substrate 1810 may be 10 atomic % to 100 atomic % Al, with the remainder being Ga, and the cation content in the buffer layer 1822 near the channel layer 1824 may be 0 atomic % to 50 atomic % Al, with the remainder being Ga. The buffer layer 1822 may have a thickness in the range of approximately 1 micron to 5 microns.

[0121] The channel layer 1824 may include Al y Ga (1-y)N, where 0≤y≤0.1, and has a thickness in the range of about 10 nm to 4000 nm and in a specific embodiment in the range of 100 nm to 1200 nm. In another specific embodiment, the thickness may be in the range of 20 nm to 90 nm. In a specific embodiment, the channel layer 1824 is a GaN layer, which may be doped with an electron donor (n-type) dopant or an electron acceptor (p-type) dopant.

[0122] The barrier layer 1826 may include a III-V material. In one embodiment, the barrier layer 1826 may include Al z Ga (1-z) N, wherein 0.02≤z≤0.5, and in one specific embodiment, 0.11≤z≤0.3. The barrier layer 1826 may have a thickness in the range of about 2 nm to 30 nm. The barrier layer 1826 has a hexagonal lattice structure and a surface 1828 along a (0002) crystal plane.

[0123] In one embodiment, the HEMT may be an enhancement mode transistor, and the gate electrode 1834 may include a doping concentration of 1×10 18 atoms / cm 3 Up to 1×10 21 atoms / cm 3 The gate electrode 1834 may have a thickness in the range of 20 nm to 300 nm. In another embodiment, the p-type GaN may be replaced with a gate dielectric layer and a metal gate electrode. In another embodiment, the HEMT may be a depletion mode transistor. In such a transistor, a relatively thin dielectric layer may be used that still allows the two-dimensional electron gas to be under the gate structure (e.g., approximately 1 nm to 50 nm thick) and the metal gate electrode. The remaining description is based on a gate electrode 1834 comprising a p-type GaN material.

[0124] The insulating layer 1840 may include one or more insulating films, which may include nitrides, oxides, or oxynitrides. In one embodiment, the insulating layer 1840 may include a single silicon nitride insulating film. In another embodiment, the insulating layer 1840 may include a dielectric film, an etch stop film, and a passivation film, wherein the etch stop film has a different composition than the dielectric film and the passivation film. In a specific embodiment, the dielectric film and the passivation film may include silicon nitride, and the etch stop film may include aluminum oxide or a transition metal oxide. Different numbers or different groups of compositions may be used for the films within the insulating layer 1840. The insulating layer 1840 may have a thickness in the range of 5nm to 500nm.

[0125] The insulating layer 1840 is patterned to define contact openings 1842 and 1846, which partially expose the barrier layer 1826. Some or all of the barrier layer 1826 may also be removed. Fig.18 As shown, no or very little barrier layer 1826 is removed within the contact opening. The surface of barrier layer 1826, or if exposed, the channel layer 1824 along the bottom of contact opening 1842 is along the (0002) crystal plane. Drain electrode 1862 and source electrode 1866 are specific embodiments of contact structures that may include materials and be formed as previously described.

[0126] A gate contact opening 1844 may be formed in the insulating layer 1840, and a gate interconnect 1864 may be formed within the gate contact opening 1844, such as Fig.18 As shown. The gate interconnect 1864 may include a conductive layer that may be the same or different from the conductive layer used for the drain electrode 1862 and the source electrode 1866. The number and composition of the films within the conductive layer of the gate interconnect 1864 may depend on the needs or requirements of the specific application. After reading this specification, the technician will be able to determine the composition of the conductive layer of the gate interconnect 1864 customized for their device. The conductive layer may have a thickness in the range of 50nm to 900nm. In another embodiment, the conductive layer may be thinner or thicker than described in the aforementioned range. The conductive layer is patterned to form the gate interconnect 1864.

[0127] One or more interconnect levels and passivation layers may be formed over the workpiece. Each interconnect level may include an interlayer dielectric layer and an interconnect. A conductive layer may be used at each interconnect level. The conductive layer may be the same or different from other conductive layers previously described in this specification. After forming the interconnect levels and passivation layers, an anneal may be performed. The execution of the anneal previously described may be postponed to this time, or an anneal separate from the anneal previously described may be performed. If a separate anneal is performed, the separate anneal may be performed using the same or different parameters as the anneal previously described. A substantially completed electronic device has been formed.

[0128] Embodiments as described herein can help reduce contact resistance. Techniques previously described allow crystals within a contact structure to have surfaces along crystal planes that align with surfaces along crystal planes of an underlying layer that contacts the contact structure. Conventional techniques for depositing the conductive layer are performed to deposit the conductive layer as quickly as possible while keeping particles and non-uniformities acceptably low. Cleaning operations can be performed to ensure that substantially all oxides and other contaminants are removed prior to depositing any films within the conductive layer.

[0129] The thickness of the bulk conductive film can be selected so that even if the contact film is deposited before the bulk conductive film is deposited, a specific phase (such as an Al phase) contacts the underlying layer. The bulk conductive film itself or the reaction between the bulk conductive film and the materials in either or both of the contact film and the capping film can react and form a separate phase in the bulk conductive film in addition to the main phase (such as an Al-containing phase). Although not required in all embodiments, both the main phase and the separate phase can contact the surface of the underlying layer. At least one of the two phases can have the lowest contact resistance when contacting the underlying layer.

[0130] The order of the method for forming the contact structure can be customized for a specific embodiment. For example, an anneal can be formed before or after patterning the conductive layer to define the shape of the contact structure. The anneal can be performed after patterning and before forming any additional interconnect levels. In another embodiment, the anneal can be postponed until after the last interconnect level is formed. Therefore, after reading this specification, the skilled person will be able to determine the specific order of method operations for a specific application. No additional deposition, annealing or masking steps are required.

[0131] Many different aspects and embodiments are possible. Some of those aspects and embodiments are described below. After reading this specification, the skilled person will recognize that those aspects and embodiments are only exemplary and do not limit the scope of the invention. Embodiments can be according to any one or more of the following listed projects.

[0132] Embodiment 1. An electronic device may include a semiconductor layer and a contact structure forming an ohmic contact with the semiconductor layer. The contact structure may include a first phase and a second phase different from the first phase, wherein the first phase includes Al, the second phase includes a metal, and the first phase contacts the semiconductor layer.

[0133] Embodiment 2. The electronic device of Embodiment 1, wherein the interface between the semiconductor layer and the contact structure is free of oxide.

[0134] Embodiment 3. The electronic device according to embodiment 1, wherein the second phase comprises Al 3 Me, Me 2 AlN, MeN or a combination thereof, wherein Me is a metal.

[0135] Embodiment 4. The electronic device according to Embodiment 3, wherein the metal comprises Ti, Zr, Hf or Ta.

[0136] Embodiment 5. The electronic device according to Embodiment 3, wherein the contact structure comprises a first film in contact with the semiconductor layer, and Al in the first film is in contact with Al 3 The ratio of Me is at least 35%.

[0137] Embodiment 6. The electronic device according to Embodiment 1, wherein the contact structure comprises a first film that contacts the semiconductor layer and comprises a first phase and a second phase; and a capping film covering the first film.

[0138] Embodiment 7. The electronic device of Embodiment 6, wherein the first phase contacts the III-N material within the semiconductor layer.

[0139] Embodiment 8. According to the electronic device of Embodiment 1, the contact structure contacts the semiconductor layer within the contact opening, and along the surface of the semiconductor layer within the contact opening, at least 1% of the surface of the semiconductor layer contacts the first phase of the conductive structure.

[0140] Embodiment 9. The electronic device according to embodiment 1, wherein the semiconductor layer comprises In a Al b Ga c N, where a+b+c=1, or a double heterostructure comprising a combination of different III-N compounds.

[0141] Embodiment 10. The electronic device according to Embodiment 1, wherein the electronic device comprises a high electron mobility transistor, the high electron mobility transistor comprising a semiconductor layer and a contact structure.

[0142] Embodiment 11. The electronic device of embodiment 1, wherein the electronic device has a plurality of contact structures having the same configuration and an average contact resistance of at most 0.5 Ω*mm.

[0143] Embodiment 12. The electronic device according to embodiment 1, wherein:

[0144] The semiconductor layer contains Al (1-x) Ga x N, where 0 <x≤0.3,

[0145] The second phase contacts the semiconductor layer and contains Al 3 Me, wherein Me includes Ti, Zr, Hf or Ta,

[0146] The contact structure includes a first film in contact with the semiconductor layer, and Al in the first film is in contact with Al 3 Me ratio is at least 35%,

[0147] The contact structure includes:

[0148] a first film that contacts the semiconductor layer and includes a first phase and a second phase; and

[0149] a cover film covering the first film, and

[0150] The electronic device includes a high electron mobility transistor, and the high electron mobility transistor includes a semiconductor layer and a contact structure.

[0151] Embodiment 13. The electronic device may include a single crystal layer having a surface along a crystal plane; and a contact structure that forms an ohmic contact with the single crystal layer. The contact structure may include a polycrystalline material that includes a first crystal having a first surface in contact with the surface of the single crystal layer, and the lattice mismatch between the surface of the single crystal layer and the first surface of the first crystal may be at most 20%.

[0152] Embodiment 14. The electronic device according to Embodiment 13, wherein the single crystal layer includes a III-N material.

[0153] Embodiment 15. The electronic device according to Embodiment 14, wherein the III-N material has a hexagonal lattice structure, the surface of the single crystal layer is along the (0002) crystal plane, the first crystal has a cubic lattice structure, and the surface of the crystal is along the (111) crystal plane.

[0154] Embodiment 16. The electronic device according to Embodiment 13, wherein the polycrystalline material includes a second crystal having a second surface along a crystal plane different from the first surface of the first crystal.

[0155] Embodiment 17. The electronic device according to Embodiment 13, wherein the electronic device includes a high electron mobility transistor, and the high electron mobility transistor includes a single crystal layer and a contact structure.

[0156] Embodiment 18. The electronic device according to Embodiment 13, wherein:

[0157] the single crystal layer includes Al (1-x) Ga x N, where 0 < x ≤ 0.3, and the surface is along the (0002) crystal plane,

[0158] the conductive structure includes a film having an Al phase and an Al 3 Me phase, where Me includes Ti, Zr, Hf, or Ta,

[0159] the Al phase includes a first crystal and a second crystal, where the first surface of the first crystal is along the (111) crystal plane, and the second surface of the second crystal is along the (200) crystal plane,

[0160] the ratio of Al to Al 3 Me in the film is at least 35%,

[0161] the contact structure includes:

[0162] a first film that is in contact with the single crystal layer and includes a first phase and a second phase; and

[0163] a cover film covering the first film, and

[0164] The electronic device includes a high electron mobility transistor including a single crystal layer and a contact structure.

[0165] Embodiment 19. A method of forming an electronic device, comprising:

[0166] cleaning a surface of the semiconductor layer, wherein the surface is along a crystal plane;

[0167] forming a contact structure including Al and metal; and

[0168] The semiconductor layer and the contact structure are annealed, wherein after the annealing:

[0169] The contact structure includes a first phase and a second phase different from the first phase,

[0170] The first phase contains Al,

[0171] The second phase contains metal, and

[0172] The first phase contacts a surface of the semiconductor layer.

[0173] Embodiment 20. The method of Embodiment 19, wherein forming the contact structure comprises:

[0174] A metal-containing film is formed, wherein:

[0175] The metal-containing film is polycrystalline and includes first crystals having an epitaxial or fibrous texture aligned with a surface of the semiconductor layer, and

[0176] a lattice mismatch between a surface of the semiconductor layer and a surface of the first crystal of at most 20%; and

[0177] An Al-containing film is formed over a surface of the metal-containing film, wherein when formed:

[0178] The Al-containing film is separated from the semiconductor layer by at least a metal-containing film, and

[0179] The Al-containing film comprises at least 90 atomic % Al, the Al-containing film is polycrystalline and comprises second crystals having an epitaxial or fibrous texture aligned with a surface of the metal-containing film,

[0180] The lattice mismatch between the surface of the semiconductor layer and the surface of the second crystal is at most 20%.

[0181] It should be noted that not all activities described above in the general description or examples are required, that a portion of a specific activity may not be required, and that one or more additional activities may be performed in addition to those described. Also, the order in which the activities are listed is not necessarily the order in which the activities are performed.

[0182] Beneficial effects, other advantages, and solutions to problems have been described above with respect to specific embodiments. However, these beneficial effects, advantages, solutions to problems, and any features that may cause any beneficial effect, advantage, or solution to occur or become more obvious should not be construed as key, required, or essential features of any or all claims.

[0183] The description and illustration of the embodiments described herein are intended to provide a general understanding of the structures of various embodiments. The description and illustration are not intended to be used as an exhaustive and comprehensive description of all elements and features of the equipment and systems using the structures or methods described herein. A separate embodiment may also be provided in a single embodiment in combination, whereas various features described in the context of a single embodiment for the sake of simplicity may also be provided individually or in any sub-combination. In addition, reference to values ​​expressed as ranges includes all values ​​within the range. Many other embodiments are apparent only to the technician after reading this specification. Other embodiments may be used and derived from the present disclosure so that structural replacement, logical replacement or other changes may be performed without departing from the scope of the present disclosure. Therefore, the present disclosure should be considered exemplary, not restrictive.

Claims

1. An electronic device, comprising: A semiconductor layer, wherein the semiconductor layer is a single crystal layer including a III-N material having a hexagonal lattice structure, and the single crystal layer has a surface along a (0002) crystal plane; and a contact structure forming an ohmic contact with the semiconductor layer, wherein the contact structure comprises a first phase and a second phase different from the first phase, in: The first phase comprises Al, the second phase comprises a metal, The first phase includes a first crystal having a first surface that contacts the surface of the single crystal layer, and The first crystal has a cubic lattice structure, and the first surface of the crystal is along a (111) crystal plane.

2. The electronic device of claim 1, wherein the second phase comprises Al3Me, Me2AlN, MeN, or a combination thereof, wherein Me is the metal.

3. The electronic device according to claim 1, wherein: The semiconductor layer includes Al (1-x) Ga x N, where 0 <x≤0.3, The second phase contacts the semiconductor layer and comprises Al3Me, wherein Me comprises Ti, Zr, Hf or Ta, The contact structure includes a first film that contacts the semiconductor layer and includes the first phase and the second phase, and a ratio of Al to Al3Me in the first film is at least 35%, and The electronic device includes a high electron mobility transistor, and the high electron mobility transistor includes the semiconductor layer and the contact structure. 4 . The electronic device according to claim 1 , wherein the electronic device has a plurality of contact structures having the same configuration and an average contact resistance of at most 0.5 Ω*mm.

5. An electronic device comprising: a single crystal layer having a surface along a crystal plane; and A plurality of contact structures, wherein the plurality of contact structures form ohmic contacts with the single crystal layer, wherein: Each of the contact structures comprises a polycrystalline material including a first crystal having a first surface in contact with the surface of the single crystal layer, The lattice mismatch between the surface of the single crystal layer and the first surface of the first crystal is at most 20%, and The plurality of contact structures have the same configuration and an average contact resistance of at most 0.5 Ω*mm.

6. The electronic device according to claim 5, wherein the single crystal layer comprises a III-N material having a hexagonal lattice structure, the surface of the single crystal layer is along a (0002) crystal plane, the first crystal has a cubic lattice structure, and the surface of the crystal is along a (111) crystal plane.

7. The electronic device according to claim 5, wherein: The single crystal layer contains Al (1-x) Ga x N, where 0 < x ≤ 0.3, and the surface is along the (0002) crystal plane, The conductive structure includes a film, the film is in contact with the single crystal layer and includes an Al phase and an Al3Me phase, wherein Me includes Ti, Zr, Hf or Ta, The Al phase includes the first crystal and the second crystal, wherein the first surface of the first crystal is along a (111) crystal plane, and the second surface of the second crystal is along a (200) crystal plane, The film has an Al to Al3Me ratio of at least 35%, and The electronic device includes a high electron mobility transistor, and the high electron mobility transistor includes the single crystal layer and the contact structure.

8. An electronic device comprising: Semiconductor layer; and A contact structure, the contact structure comprising a first film in contact with the semiconductor layer and forming an ohmic contact with the semiconductor layer, wherein: The first film comprises a first phase and a second phase different from the first phase, wherein: The first phase includes Al and contacts the semiconductor layer, The second phase comprises a metal, and Al 相对 % is at least 80%, of which: <h2 style=";text-align:left;direction:ltr">Al<h2 style=";text-align:left;direction:ltr"> 相对 <h2 style=";text-align:left;direction:ltr"> %=Al<h2 style=";text-align:left;direction:ltr"> 游离 <h2 style=";text-align:left;direction:ltr"> / (Al<h2 style=";text-align:left;direction:ltr"> 总 <h2 style=";text-align:left;direction:ltr"> +Me<h2 style=";text-align:left;direction:ltr"> 总 <h2 style=";text-align:left;direction:ltr"> )*100%, Al 游离 is the number of Al atoms per unit area in the first phase, Al 总 is the total number of Al atoms per unit area in the contact structure, and Me 总 is the total number of metal atoms per unit area in the contact structure.

9. The electronic device according to claim 8, wherein the semiconductor layer comprises In a Al b Ga c N, where a+b+c=1.

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