A low lattice mismatch MISHEMT interface buffer layer and its preparation method and MISHEMT device containing the same

Abstract

The present invention discloses a low lattice mismatch MISHEMT interface buffer layer, a preparation method thereof, and a MISHEMT device containing the same, relating to the field of semiconductor technology. The interface buffer layer is disposed below a gate dielectric layer and comprises: a first AlGaN layer; a second AlGaN layer, the second AlGaN layer being deposited on the upper surface of the first AlGaN layer; a third AlGaN layer, the third AlGaN layer being deposited on the upper surface of the second AlGaN layer; and an AlN layer, the AlN layer being deposited between the third AlGaN layer and the gate dielectric layer; the Al content in the first AlGaN layer, the second AlGaN layer, and the third AlGaN layer increasing in sequence. The interface buffer layer provided by the present invention significantly reduces the lattice mismatch between adjacent materials, with the overall lattice mismatch being far less than 2.4%, and can effectively reduce deep energy level defects caused by energy level arrangement mutations.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and more particularly to a low lattice mismatch MISHEMT interface buffer layer, a preparation method thereof, and a MISHEMT device containing the same. Background Art

[0002] Gallium nitride (GaN), as a member of the third-generation semiconductor material system, has unique advantages such as adjustable wide bandgap, high breakdown electric field, and high saturation velocity. At the same time, high electron mobility transistors (HEMTs) can effectively utilize the characteristics of GaN materials to achieve high-performance high-frequency power devices, making GaN-based HEMTs a research hotspot.

[0003] Based on the different gate contact structures, GaN-based HEMT devices can be divided into two categories: one is the traditional GaN-based HEMT device, which uses a Schottky gate contact; the other is the GaN-based insulated gate HEMT device, which adds a layer of insulating material between the gate electrode and the nitride semiconductor material on the basis of the traditional HEMT device structure to form a metal-insulator-semiconductor high electron mobility transistor (MISHEMT).

[0004] Existing conventional MISHEMT devices such as Figure 1 and Figure 2 As shown, Figure 1 The structure shown lacks an interface buffer layer and instead places a gate dielectric directly between the nitride semiconductor (p-GaN) and the gate electrode. However, this structure has the following drawbacks: Because the gate dielectric is typically amorphous, the interface defect density between the single-crystalline p-GaN and the gate dielectric is high, which in turn affects the device's electrical properties.

[0005] Therefore, how to optimize the interface defects between p-GaN and the gate dielectric layer to improve the electrical properties of GaN HEMT devices is a problem to be solved. Summary of the Invention

[0006] In view of this, one of the objectives of the present invention is to provide a low lattice mismatch MISHEMT interface buffer layer to solve the problems in the prior art.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] A low lattice mismatch MISHEMT interface buffer layer, wherein the interface buffer layer is arranged below a gate dielectric layer, and the interface buffer layer comprises:

[0009] a first AlGaN layer;

[0010] a second AlGaN layer, deposited on an upper surface of the first AlGaN layer;

[0011] a third AlGaN layer, the third AlGaN layer being deposited on an upper surface of the second AlGaN layer;

[0012] an AlN layer, the AlN layer being deposited between the third AlGaN layer and the gate dielectric layer;

[0013] The Al contents in the first AlGaN layer, the second AlGaN layer, and the third AlGaN layer increase sequentially.

[0014] In the present invention, for a MISHEMT device with a p-GaN layer on top, the interface buffer layer is arranged between the p-GaN layer and the gate dielectric layer; for a depletion-type MISHEMT device without a p-GaN layer on top, the interface buffer layer can be directly arranged between the AlGaN barrier layer and the gate dielectric layer. Regardless of whether it is a p-GaN layer or an AlGaN barrier layer, its composition includes GaN.

[0015] By placing an AlN layer beneath the gate dielectric, the conduction band gap between AlN and GaN reaches as high as 1.8eV. Using AlN as the interface buffer layer for GaN HEMMTs can effectively reduce leakage current. However, the high lattice mismatch between AlN and GaN, exceeding 2.4%, directly impacts electron mobility. Furthermore, the different thermal expansion coefficients of AlN and GaN mean that subsequent annealing can generate stress at the interface, resulting in poor contact quality.

[0016] Therefore, the present invention further provides three AlGaN buffer layers at the bottom of AlN. The Al content in the three AlGaN layers increases from bottom to top, which effectively solves the lattice mismatch problem between AlN and GaN; and also solves the band gap mutation problem between AlN and GaN.

[0017] Furthermore, the first AlGaN layer is deposited on the upper surface of the p-GaN layer; that is, it is preferably suitable for a MISHEMT device with a p-GaN layer provided on the top;

[0018] The Al content in the first AlGaN layer is 5%-35%; the Al content in the second AlGaN layer is 25%-65%; and the Al content in the third AlGaN layer is 55%-95%.

[0019] Among them, p-GaN, or p-type gallium nitride, is a material formed by doping gallium nitride (GaN) with a p-type dopant. The commonly used p-type dopant is Mg (magnesium). In addition, C, Be, and Ca dopants with relatively low ionization energy can also achieve p-type doping effects under different conditions, and no specific restrictions are imposed here.

[0020] Optionally, the number of AlGaN layers in the interface buffer layer may be set to only two, or four or even more, to achieve the lowest interface defects.

[0021] Furthermore, the atomic ratio of Al to Ga in the first AlGaN layer is 3:7; the atomic ratio of Al to Ga in the second AlGaN layer is 6:4; and the atomic ratio of Al to Ga in the third AlGaN layer is 9:1.

[0022] Optionally, the atomic ratio of Al to Ga in each AlGaN layer can also be adjusted to achieve the lowest interface defects.

[0023] Furthermore, the thickness of the first AlGaN layer is 0.5-1.5 nm; the thickness of the second AlGaN layer is 0.5-1.5 nm; and the thickness of the third AlGaN layer is 1-2 nm.

[0024] A second object of the present invention is to provide a method for preparing the low lattice mismatch MISHEMT interface buffer layer, comprising the following steps:

[0025] 1) depositing a first AlGaN layer on the p-GaN layer;

[0026] 2) performing a first annealing treatment; specifically, the annealing treatment may be performed after each super cycle of depositing the first AlGaN layer, or after the entire deposition of the first AlGaN layer is completed;

[0027] 3) depositing a second AlGaN layer on the first AlGaN layer;

[0028] 4) performing a second annealing treatment; specifically, the annealing treatment may be performed after each super cycle of depositing the second AlGaN layer, or after the entire second AlGaN layer is deposited;

[0029] 5) depositing a third AlGaN layer on the second AlGaN layer;

[0030] 6) performing a third annealing treatment; similarly, the annealing treatment may be performed after each super cycle of depositing the third AlGaN layer, or after the entire deposition of the third AlGaN layer is completed;

[0031] 7) depositing an AlN layer on the third AlGaN layer;

[0032] 8) Perform the fourth annealing treatment;

[0033] 9) depositing a gate dielectric layer on the AlN layer;

[0034] 10) Carry out the fifth annealing treatment to obtain the product.

[0035] Furthermore, in step 1), the first AlGaN layer is specifically prepared by ALD deposition. When the first AlGaN layer is deposited by ALD, each super cycle includes 2 to 5 GaN cycles, 1 to 4 AlN cycles, and 2 to 4 GaN cycles in sequence until the first AlGaN layer of the desired thickness is deposited;

[0036] In step 3), specifically, a second AlGaN layer is prepared by ALD deposition. When the second AlGaN layer is deposited by ALD, each super cycle includes 1 to 3 GaN cycles, 4 to 7 AlN cycles, and 1 to 3 GaN cycles in sequence until the second AlGaN layer of the desired thickness is deposited;

[0037] In step 5), specifically, the third AlGaN layer is prepared by ALD deposition. When the third AlGaN layer is deposited by ALD, each super cycle includes 1 to 4 GaN cycles and 6 to 9 AlN cycles in sequence until the third AlGaN layer of the desired thickness is obtained.

[0038] Furthermore, in step 1), the first AlGaN layer is specifically prepared by ALD deposition. When the first AlGaN layer is deposited by ALD, each super cycle includes four GaN cycles, three AlN cycles, and three GaN cycles in sequence until the first AlGaN layer of the desired thickness is deposited;

[0039] In step 3), specifically, a second AlGaN layer is prepared by ALD deposition. When the second AlGaN layer is deposited by ALD, each super cycle includes 2 GaN cycles, 6 AlN cycles, and 2 GaN cycles in sequence until the second AlGaN layer of the desired thickness is deposited;

[0040] In step 5), specifically, the third AlGaN layer is prepared by ALD deposition. When the third AlGaN layer is deposited by ALD, each super cycle includes 1 GaN cycle and 9 AlN cycles in sequence until the third AlGaN layer of the desired thickness is obtained.

[0041] Optionally, each super-cycle within each AlGaN layer can be flexibly varied. For example, when depositing the first AlGaN layer, each super-cycle can include, in sequence, 3 GaN + 3 AlN + 4 GaN layers; or 2 GaN + 3 AlN + 5 GaN layers; until the first AlGaN layer of the desired thickness is deposited; or alternately, and so on. It is understood that when depositing the second AlGaN layer, each super-cycle can also be adjusted to minimize interface defects; as long as the first and second super-cycles in the first and second AlGaN layers are both GaN layers.

[0042] Furthermore, the first annealing treatment, the second annealing treatment and the third annealing treatment are specifically in-situ nitrogen annealing at original temperature in the ALD chamber for 1-10 minutes, or nitrogen plasma treatment for 5-600 seconds.

[0043] In step 8), the fourth annealing treatment can be to take out the sample and place it in a peripheral annealing device for high-temperature annealing; the specific annealing temperature is 400-800° C., the annealing environment is nitrogen, and the annealing time is 1-3 hours.

[0044] In step 10), the fifth annealing treatment is a low-temperature annealing treatment, specifically the annealing temperature is ≤300° C., the annealing environment is air or vacuum, and the annealing time is ≤1 hour.

[0045] Through the above deposition method, the first and last ends of each super cycle in the first AlGaN layer and the second AlGaN layer are GaN layers, which is also the key to improving the contact quality and lattice quality of each layer of the interface buffer layer.

[0046] Moreover, the three AlGaN layers, the AlN layer and the gate dielectric layer can all be prepared by ALD, which simplifies the preparation method, helps to reduce device production costs and improve production efficiency.

[0047] The preparation method provided by the present invention can set different annealing processes after the three AlGaN layers (the first AlGaN layer, the second AlGaN layer and the third AlGaN layer) and the AlN layer, making the annealing optimization process more flexible and significantly improving the overall quality of the interface buffer layer.

[0048] By setting multiple annealing steps for the interface buffer layer, the material parameters such as the degree of element diffusion and lattice structure in each layer can be effectively controlled.

[0049] A third object of the present invention is to provide a MISHEMT device comprising any of the above-mentioned low lattice mismatch MISHEMT interface buffer layers.

[0050] Furthermore, the device includes an epitaxial substrate layer, an epitaxial buffer layer, a GaN channel layer, an AlGaN barrier layer, and a source electrode, a drain electrode, and a p-GaN layer arranged in sequence from bottom to top, wherein the source electrode and the drain electrode are respectively located on the left and right sides of the p-GaN layer, the interface buffer layer is arranged on the p-GaN layer, a gate dielectric layer is arranged on the upper surface of the interface buffer layer, and a gate electrode is arranged on the gate dielectric layer.

[0051] Furthermore, the epitaxial substrate material is one of silicon wafer, sapphire, GaN, and SiC; the gate dielectric layer is obtained by stacking one or more of Ta2O5, Al2O3, HfO2, and SiN.

[0052] Furthermore, the epitaxial buffer layer, GaN channel layer, AlGaN barrier layer, and p-GaN layer can be produced by epitaxial methods such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE), and the present invention does not impose any specific limitations thereto.

[0053] Furthermore, the gate electrode, source electrode, and drain electrode are prepared by at least one of atomic layer deposition (ALD), magnetron sputtering, electron beam evaporation, and thermal evaporation. Different preparation methods may be used for different electrodes.

[0054] Furthermore, the source electrode and the drain electrode may be made of a metal or a semiconductor material with good conductivity, or a stacked structure of multiple materials, and are required to easily form a good ohmic contact with AlGaN.

[0055] Furthermore, the gate electrode may be a metal or a semiconductor material with good conductivity, or a stacked structure of multiple materials, and is required to easily form a Schottky contact with the gate dielectric layer.

[0056] In the present invention, the thickness of the epitaxial substrate layer is 800um~1200um; the thickness of the epitaxial buffer layer is 4000nm~6000nm; the thickness of the GaN channel layer is 100nm~300nm; the thickness of the AlGaN barrier layer is 5nm~50nm; the thickness of the p-GaN layer is 50nm~300nm; and the thickness of the AlN layer is 1nm~10nm.

[0057] Compared with the prior art, the present invention has the following advantages:

[0058] (1) The lattice mismatch between the p-GaN layer, the first AlGaN layer, the second AlGaN layer, the third AlGaN layer, and the adjacent AlN layer is greatly reduced, and the overall lattice mismatch is much less than 2.4%.

[0059] (2) The band gaps between the p-GaN layer, the first AlGaN layer, the second AlGaN layer, the third AlGaN layer, and the AlN layer present a step-like gradual change structure, which effectively reduces the deep energy level defects caused by the sudden change of energy level arrangement.

[0060] (3) After the first AlGaN layer, the second AlGaN layer, the third AlGaN layer, and the AlN layer are grown, the annealing method, annealing temperature, annealing atmosphere, and annealing time are adjusted respectively. The annealing conditions are more flexible and have better effect on interface modification.

[0061] (4) The beginning and end of each super-cycle in the first AlGaN layer and the second AlGaN layer are GaN, which avoids the generation of defects between super-cycles during annealing. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 Schematic diagram of the structure of a conventional MISHEMT device in the prior art; wherein S represents the source electrode, D represents the drain electrode; and S represents the gate electrode.

[0063] Figure 2 for Figure 1 Schematic diagram of the enlarged structure at point A in the middle.

[0064] Figure 3 Schematic diagram of the structure in which an AlN layer is provided only between the p-GaN layer and the gate dielectric layer of the MISHEMT device.

[0065] Figure 4 for Figure 3 Schematic diagram of the enlarged structure at point A in the middle.

[0066] Figure 5 This is a schematic structural diagram of the present invention in which an AlN layer and multiple AlGaN layers are arranged between the p-GaN layer and the gate dielectric layer.

[0067] Figure 6 for Figure 5 Schematic diagram of the enlarged structure at point A in the middle. DETAILED DESCRIPTION

[0068] The following description sets forth numerous specific details to facilitate a thorough understanding of the present invention. However, the present invention can be implemented in many other ways than those described herein, and those skilled in the art may make similar modifications without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific implementations disclosed below.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0070] Unless otherwise specified, the materials and reagents used in the present invention can be obtained from commercial products in the art.

[0071] Example 1

[0072] A MISHEMT device having a multi-layer AlGaN layer in an interface buffer layer, the structure of which is as follows Figure 5 and Figure 6 As shown, the preparation method includes:

[0073] S1. Depositing an epitaxial buffer layer, a GaN channel layer, and an AlGaN barrier layer on the epitaxial substrate layer in sequence; then depositing a source electrode at one end of the AlGaN barrier layer, a drain electrode at the other end, and a p-GaN layer in the middle; wherein the epitaxial substrate layer has a thickness of approximately 1000 μm; the epitaxial buffer layer has a thickness of approximately 5000 nm; the GaN channel layer has a thickness of 200 nm; the AlGaN barrier layer has a thickness of 20 nm; and the p-GaN layer has a thickness of 100 nm.

[0074] S2. Depositing an interface buffer layer, which covers the entire p-GaN layer. At the same time, the interface buffer layer is deposited and covered on the upper surface of the AlGaN barrier layer between the source electrode and the p-GaN layer, the upper surface of the AlGaN barrier layer between the drain electrode and the p-GaN layer, and the source and drain electrodes. Furthermore, the interface buffer layer is deposited and covered on the outer ends of the source and drain electrodes, extending downward to the epitaxial ends of the epitaxial buffer layer. Of course, gaps are left on the source and drain electrodes for connection to external circuits.

[0075] Specifically, the deposition process of the interface buffer layer includes:

[0076] S21. Depositing a first AlGaN layer (AlGaN-1) on the p-GaN layer using ALD, wherein the molar content of Al in the film layer is 30%; specifically, during deposition, each supercycle includes 4 GaN + 3 AlN + 3 GaN; until a first AlGaN layer having a thickness of about 1 nm is deposited;

[0077] When depositing the first AlGaN layer, a first annealing treatment is performed. During the first annealing, the layer can be annealed in situ in the ALD chamber at the original temperature for 5 minutes after each super cycle.

[0078] S22, forming a second AlGaN layer (AlGaN-2) on the first AlGaN layer by using ALD, wherein the molar content of Al in the film layer is 60%; specifically, during deposition, each super cycle includes 2 GaN + 6 AlN + 2 GaN; until a second AlGaN layer having a thickness of about 1 nm is deposited;

[0079] When depositing the second AlGaN layer, a second annealing process is performed. During the second annealing process, nitrogen plasma treatment may be used for 100 seconds after each super cycle.

[0080] S23, forming a third AlGaN layer (AlGaN-3) on the second AlGaN layer by ALD, wherein the molar content of Al in the film layer is 90%; specifically, during deposition, each super cycle includes 1 GaN + 9 AlN; until the third AlGaN layer having a thickness of about 1.5 nm is deposited;

[0081] When depositing the third AlGaN layer, a third annealing treatment is performed. During the third annealing, nitrogen plasma treatment can be used for 100 seconds after partial super-cycling, and then in-situ nitrogen annealing at original temperature in the ALD chamber for 5 minutes after partial super-cycling;

[0082] S24, depositing an AlN layer on the third AlGaN layer using an ALD device to obtain an AlN layer with a thickness of 5 nm;

[0083] S25, performing a fourth annealing on the interface buffer layer; the fourth annealing may be performed by taking out the sample and placing it in a peripheral annealing device for high-temperature annealing; the annealing temperature is 700° C., the annealing environment is nitrogen, and the annealing time is 2 hours;

[0084] S26, forming a gate dielectric layer on the AlN layer by using ALD;

[0085] S27, low temperature annealing treatment; the specific temperature is 200 ° C, the annealing environment is vacuum, and the annealing time is 40 minutes;

[0086] S3. Prepare a gate electrode on the gate dielectric layer.

[0087] Thus, a MISHEMT device containing multiple AlGaN layers is obtained.

[0088] In this embodiment, the lattice mismatch between adjacent materials of the p-GaN layer, AlGaN-1, AlGaN-2, AlGaN-3, and AlN layer is less than 0.5%, and the overall lattice mismatch is much less than 2.4%.

[0089] Comparative Example 1

[0090] The difference between this embodiment and embodiment 1 is that the interface buffer layer does not include the first AlGaN layer, the second AlGaN layer and the third AlGaN layer; the prepared MISHEMT device is as follows Figure 3 and Figure 4 shown.

[0091] In this embodiment, the lattice mismatch between p-GaN and AlN exceeds 2.4%, specifically 2.7%.

[0092] Comparative Example 2

[0093] The only difference between this embodiment and embodiment 1 is that when preparing the interface buffer layer,

[0094] In step S21, when preparing the first AlGaN layer, each super cycle includes 7 GaN + 3 AlN;

[0095] In step S22 , when preparing the second AlGaN layer, each super cycle includes 4 GaN+6 AlN.

[0096] The rest of the steps are the same.

[0097] In this embodiment, the lattice mismatch between adjacent materials of the p-GaN layer, AlGaN-1, AlGaN-2, AlGaN-3, and AlN layer is greater than 2.2%, and the overall lattice mismatch is 2.5%.

[0098] Comparative Example 3

[0099] The only difference between this embodiment and embodiment 1 is that when preparing the interface buffer layer,

[0100] In step S21 , when preparing the first AlGaN layer, each super cycle includes 1 GaN + 9 AlN;

[0101] In step S22, when preparing the second AlGaN layer, each super cycle includes 4 GaN + 6 AlN;

[0102] In step S23 , when preparing the third AlGaN layer, each super cycle includes 4 GaN+3 AlN+3 GaN.

[0103] The rest of the steps are the same.

[0104] In this embodiment, the lattice mismatch between adjacent materials of the p-GaN layer, AlGaN-1, AlGaN-2, AlGaN-3, and AlN layer is greater than 2.2%, and the overall lattice mismatch is 2.4%.

[0105] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A MISHEMT device containing a low lattice mismatch MISHEMT interface buffer layer, characterized in that: The device comprises an epitaxial substrate layer, an epitaxial buffer layer, a GaN channel layer, an AlGaN barrier layer, and a source electrode, a drain electrode, and a p-GaN layer arranged in sequence from bottom to top, wherein the source electrode and the drain electrode are respectively located on the left and right sides of the p-GaN layer, an interface buffer layer is provided on the p-GaN layer, a gate dielectric layer is provided on the upper surface of the interface buffer layer, and a gate electrode is provided on the gate dielectric layer; The interface buffer layer is disposed below the gate dielectric layer, and the interface buffer layer includes: a first AlGaN layer; a second AlGaN layer, deposited on an upper surface of the first AlGaN layer; a third AlGaN layer, the third AlGaN layer being deposited on an upper surface of the second AlGaN layer; an AlN layer, the AlN layer being deposited between the third AlGaN layer and the gate dielectric layer; The Al contents in the first AlGaN layer, the second AlGaN layer, and the third AlGaN layer increase sequentially.

2. The MISHEMT device according to claim 1, characterized in that The first AlGaN layer is deposited on the upper surface of the p-GaN layer; The Al content in the first AlGaN layer is 5%-35%; the Al content in the second AlGaN layer is 25%-65%; and the Al content in the third AlGaN layer is 55%-95%.

3. The MISHEMT device according to claim 1, characterized in that The atomic ratio of Al to Ga in the first AlGaN layer is 3:7; the atomic ratio of Al to Ga in the second AlGaN layer is 6:4; and the atomic ratio of Al to Ga in the third AlGaN layer is 9:

1.

4. The MISHEMT device according to claim 1, characterized in that The thickness of the first AlGaN layer is 0.5-1.5 nm; the thickness of the second AlGaN layer is 0.5-1.5 nm; and the thickness of the third AlGaN layer is 1-2 nm.

5. The MISHEMT device according to claim 1, characterized in that The epitaxial substrate material is one of silicon wafer, sapphire, GaN, and SiC; the gate dielectric layer is obtained by stacking one or more of Ta2O5, Al2O3, HfO2, and SiN.

6. The method for preparing a MISHEMT device according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1. Depositing an epitaxial buffer layer, a GaN channel layer, and an AlGaN barrier layer on the epitaxial substrate layer in sequence; then depositing a source electrode at one end of the AlGaN barrier layer, a drain electrode at the other end, and a p-GaN layer in the middle; S2. Depositing an interface buffer layer, where the interface buffer layer covers the entire p-GaN layer. At the same time, the interface buffer layer is deposited and covered on the upper surface of the AlGaN barrier layer between the source electrode and the p-GaN layer, the upper surface of the AlGaN barrier layer between the drain electrode and the p-GaN layer, and the source and drain electrodes. Furthermore, the interface buffer layer is deposited and covered on the outer ends of the source and drain electrodes, extending downward to the epitaxial ends of the epitaxial buffer layer. The deposition process of the interface buffer layer includes: 1) depositing a first AlGaN layer on the p-GaN layer; 2) Perform the first annealing treatment; 3) depositing a second AlGaN layer on the first AlGaN layer; 4) Perform a second annealing treatment; 5) depositing a third AlGaN layer on the second AlGaN layer; 6) Perform a third annealing treatment; 7) depositing an AlN layer on the third AlGaN layer; 8) Perform the fourth annealing treatment; 9) depositing a gate dielectric layer on the AlN layer; 10) Carry out the fifth annealing treatment to obtain the product.

7. The preparation method according to claim 6, characterized in that In step 1), specifically, a first AlGaN layer is deposited by ALD. When depositing the first AlGaN layer by ALD, each super cycle includes 2 to 5 GaN cycles, 1 to 4 AlN cycles, and 2 to 4 GaN cycles in sequence until the first AlGaN layer of the desired thickness is deposited. In step 3), specifically, a second AlGaN layer is prepared by ALD deposition. When the second AlGaN layer is deposited by ALD, each super cycle includes 1 to 3 GaN cycles, 4 to 7 AlN cycles, and 1 to 3 GaN cycles in sequence until the second AlGaN layer of the desired thickness is deposited; In step 5), specifically, the third AlGaN layer is prepared by ALD deposition. When the third AlGaN layer is deposited by ALD, each super cycle includes 1 to 4 GaN cycles and 6 to 9 AlN cycles in sequence until the third AlGaN layer of the desired thickness is obtained.

8. The preparation method according to claim 6, characterized in that The first annealing treatment, the second annealing treatment and the third annealing treatment are specifically in-situ nitrogen annealing at original temperature in the ALD chamber for 1-10 minutes, or nitrogen plasma treatment for 5-600 seconds.

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