A device and method for performing vector comparison operations

Abstract

The present disclosure provides a device and method for performing vector comparison operations. In an embodiment of the present disclosure, when performing vector comparison operations, it is necessary to determine the dependency between instructions. After determining the dependency of the instructions, the vector comparison operation is performed based on the dependency. Using the above method, the complete process of performing vector comparison operation instructions through customized hardware circuits is realized, that is, the vector comparison operation can be realized through a vector comparison instruction.

Description

[0001] Related Applications Citations

[0002] This application is a divisional application of the invention patent application with application number 201610266782.2, application date April 26, 2016, and invention name “A device and method for performing vector comparison operations”. Technical Field

[0003] The present disclosure relates to the field of computer instruction operations, and in particular to a device and method for performing vector comparison operations. Background Art

[0004] Vector comparison, that is, for two vectors of the same length, the corresponding elements are compared, and the comparison results form a new output vector. In the field of deep learning, there is a need to compare the size of two vectors. In the restricted Boltzmann machine of artificial neural networks, there is such a step, which requires sampling a vector composed of a group of neurons, that is, comparing each neuron in the vector with a random number. If the value of the neuron is greater than the vector, it is 1, otherwise it is 0. For example, if a group of 32-bit single-precision floating-point numbers is converted to 16-bit half-precision floating-point numbers, if the random carry method is selected, the truncated part needs to be compared with a random number that satisfies a certain distribution, and if it is greater than the random number, it is selected by 1. This also requires a comparison operation on the two vector data.

[0005] In the prior art, one of the most commonly used methods for implementing vector comparison operations is to compare one by one on a general-purpose CPU, which has low execution efficiency.

[0006] Another prior art is to perform vector comparison operations on a graphics processing unit (GPU), wherein operations are performed by using a general register file and a general stream processing unit to execute general SIMD instructions. However, in the above solution, the GPU on-chip cache is too small, and when performing large-scale vector comparison operations, it is necessary to continuously transfer data off-chip, and the off-chip bandwidth becomes the main performance bottleneck.

[0007] In summary, existing general-purpose processors and graphics processors are unable to efficiently process large-scale vector comparison operations. Summary of the invention

[0008] In view of this, the present disclosure proposes a technical solution for performing vector comparison operations.

[0009] According to one aspect of the present disclosure, a method for performing a vector comparison operation is provided. The method includes determining whether there is a dependency relationship between a first instruction obtained and a second instruction to be executed that was previously obtained, the dependency relationship indicating the processing order of the instructions, and the first instruction and the second instruction are instructions for performing a vector comparison operation. The method also includes storing the first instruction in response to the existence of the dependency relationship between the first instruction and the second instruction. The method also includes providing the stored first instruction to the vector comparison unit for performing the vector comparison operation in response to the second instruction having been executed.

[0010] In some embodiments, determining whether there is a dependency relationship between a first instruction fetched and a second instruction to be executed that was previously fetched includes: determining a first storage address of a first vector stored in an operation domain of the first instruction; determining a second storage address of a second vector stored in an operation domain of the second instruction; comparing the first storage address and the second storage address; and in response to the first storage address and the second storage address being the same, determining that there is a dependency relationship between the first instruction and the second instruction.

[0011] In some embodiments, the method further comprises, in response to determining that the dependency does not exist, providing the first instruction to a vector comparison unit for directly performing the vector comparison operation.

[0012] In some embodiments, the first instruction or the second instruction includes an operation code and multiple operation fields, wherein the operation code is used to indicate the type of vector comparison operation, and the multiple operation fields include an immediate number and / or a register number, and the immediate number and the register number are used to determine the vector length, the starting address of the two vectors to be compared, and the storage address of the comparison result vector.

[0013] In some embodiments, the first instruction or the second instruction is a greater than or equal to operation instruction, and the greater than or equal to operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is greater than or equal to the value of the latter vector.

[0014] In some embodiments, the first instruction or the second instruction is a less than or equal to operation instruction, and the less than or equal to operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is less than or equal to the value of the latter vector.

[0015] In some embodiments, the first instruction or the second instruction is a greater than operation instruction, which is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is greater than the value of the latter vector.

[0016] In some embodiments, the first instruction or the second instruction is a less than operation instruction, which is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is less than the value of the latter vector.

[0017] In some embodiments, the first instruction or the second instruction is an equal operation instruction, which is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is equal to the value of the latter vector.

[0018] In some embodiments, the first instruction or the second instruction is a inequality operation instruction, which is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is not equal to the value of the latter vector.

[0019] In some embodiments, the method also includes obtaining the first instruction from an instruction cache unit; decoding the first instruction; obtaining a register number from an operation domain of the decoded first instruction; and storing scalar data stored in a register unit corresponding to the register number in the first instruction, the scalar data including the starting address and vector length of two vectors to be compared, and the storage address of the comparison result vector.

[0020] In some embodiments, the register unit is a scalar register file, comprising a plurality of scalar registers for storing scalar data associated with instructions for the vector comparison operation.

[0021] According to the second aspect of the present disclosure, a device for performing a vector comparison operation is provided. The device includes a dependency processing unit, configured to determine whether there is a dependency relationship between a first instruction acquired and a second instruction to be executed previously acquired, the dependency relationship indicating the processing order of the instructions, the first instruction and the second instruction being instructions for performing a vector comparison operation; and a storage queue module, configured to: in response to the existence of the dependency relationship between the first instruction and the second instruction, store the first instruction; and in response to the second instruction having been executed, provide the stored first instruction to the vector comparison unit for performing the vector comparison operation.

[0022] In some embodiments, the dependency processing unit is further configured to: determine a first storage address of a first vector stored in an operation domain of the first instruction; determine a second storage address of a second vector stored in an operation domain of the second instruction; compare the first storage address and the second storage address; and in response to the first storage address and the second storage address being the same, determine that a dependency exists between the first instruction and the second instruction.

[0023] In some embodiments, the dependency handling unit is further configured to, in response to determining that the dependency does not exist, provide the first instruction to a vector comparison unit for directly performing the vector comparison operation.

[0024] In some embodiments, the first instruction or the second instruction includes an operation code and multiple operation fields, wherein the operation code is used to indicate the type of vector comparison operation, and the multiple operation fields include an immediate number and / or a register number, and the immediate number and the register number are used to determine the vector length, the starting address of the two vectors to be compared, and the storage address of the comparison result vector.

[0025] In some embodiments, the first instruction or the second instruction is a greater than or equal to operation instruction, and the greater than or equal to operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is greater than or equal to the value of the latter vector.

[0026] In some embodiments, the first instruction or the second instruction is a less than or equal to operation instruction, and the less than or equal to operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is less than or equal to the value of the latter vector.

[0027] In some embodiments, the first instruction or the second instruction is a greater than operation instruction, which is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is greater than the value of the latter vector.

[0028] In some embodiments, the first instruction or the second instruction is a less than operation instruction, which is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is less than the value of the latter vector.

[0029] In some embodiments, the first instruction or the second instruction is an equal operation instruction, which is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is equal to the value of the latter vector.

[0030] In some embodiments, the first instruction or the second instruction is a inequality operation instruction, which is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is not equal to the value of the latter vector.

[0031] In some embodiments, the device also includes an instruction fetch module, configured to obtain the first instruction from an instruction cache unit; a decoding module, configured to decode the first instruction; an instruction queue module, configured to obtain a register number from an operation domain of the decoded first instruction; and store the scalar data stored in the register unit corresponding to the register number in the first instruction, the scalar data including the starting address and vector length of the two vectors to be compared, and the storage address of the comparison result vector.

[0032] In some embodiments, the register unit is a scalar register file, which includes a plurality of scalar registers and is used to store the scalar data associated with the instruction for the vector comparison operation.

[0033] According to the third aspect of the present disclosure, an artificial intelligence chip is provided, wherein the chip is used to execute any one of the method steps in the first aspect.

[0034] The present disclosure provides a device and method for performing vector comparison operations, which can support vector comparison operations of any length according to instructions, and also have excellent execution performance. The device can perform a series of vector comparison operations according to instructions, including but not limited to greater than or equal to, greater than, equal to, not equal to, less than, and less than or equal to, and can flexibly support vector data of different lengths.

[0035] According to a fourth aspect of the present disclosure, there is provided a device for performing a vector comparison operation, comprising:

[0036] A storage unit, used for storing vector data related to a vector comparison operation instruction;

[0037] A register unit, used to store scalar data related to vector comparison operation instructions;

[0038] A control unit, used for decoding the vector comparison operation instruction and controlling the operation process of the vector comparison operation instruction;

[0039] A vector comparison unit, used for performing a vector comparison operation on two input vector data to be compared according to the decoded vector comparison operation instruction;

[0040] Wherein, the vector comparison unit is a customized hardware circuit.

[0041] Preferably, the scalar data stored in the register unit includes the starting address of the input vector to be compared, the storage address of the comparison result output vector, and the length of the input vector to be compared related to the vector comparison operation instruction; wherein the starting address of the input vector to be compared and the storage address of the comparison result output vector are the addresses in the storage unit.

[0042] Preferably, the control unit comprises:

[0043] The instruction queue module is used to sequentially store the decoded vector comparison operation instructions and obtain scalar data related to the vector comparison operation instructions.

[0044] Preferably, the control unit comprises:

[0045] The dependency processing unit is used to determine whether there is a dependency relationship between the current vector comparison operation instruction and the previously unexecuted operation instruction before the vector comparison unit obtains the current vector comparison operation instruction.

[0046] Preferably, the control unit comprises:

[0047] The storage queue module is used to temporarily store the current vector comparison operation instruction when there is a dependency relationship between the current vector comparison operation instruction and the previously unexecuted operation instruction, and send the temporarily stored vector comparison operation instruction to the vector comparison unit when the dependency relationship is eliminated.

[0048] Preferably, the device further comprises:

[0049] An instruction cache unit, used for storing vector operation instructions to be executed;

[0050] The input-output unit is used to store vector data related to the vector comparison operation instruction in the storage unit, or to obtain the comparison result output vector of the vector comparison operation instruction from the storage unit.

[0051] Preferably, the vector comparison operation instruction includes an operation code and an operation field;

[0052] The operation code is used to indicate the execution of a vector comparison operation;

[0053] The operation field includes an immediate value and / or a register number, indicating scalar data related to the vector comparison operation, wherein the register number points to the register unit address.

[0054] Preferably, the storage unit is a high-speed temporary storage memory.

[0055] According to a fifth aspect of the present disclosure, there is provided a device for performing a vector comparison operation, comprising:

[0056] The instruction fetch module is used to fetch the next vector comparison operation instruction to be executed from the instruction sequence and transmit the vector comparison operation instruction to the decoding module;

[0057] A decoding module, used for decoding the vector comparison operation instruction and transmitting the decoded vector comparison operation instruction to the instruction queue module;

[0058] An instruction queue module is used to temporarily store the decoded vector comparison operation instruction and obtain scalar data related to the vector comparison operation instruction from the vector comparison operation instruction or the scalar register; after obtaining the scalar data, the vector comparison operation instruction is sent to the dependency processing unit;

[0059] A scalar register file, comprising a plurality of scalar registers, for storing scalar data related to a vector comparison operation instruction;

[0060] A dependency processing unit, used to determine whether there is a dependency relationship between the vector comparison operation instruction and a previously unexecuted operation instruction; if there is a dependency relationship, the vector comparison operation instruction is sent to a storage queue module; if there is no dependency relationship, the vector comparison operation instruction is sent to a vector comparison unit;

[0061] A storage queue module, used for storing vector comparison operation instructions having a dependency relationship with previous operation instructions, and sending the vector comparison operation instructions to the vector comparison unit after the dependency relationship is released;

[0062] A vector comparison unit, used for performing a vector comparison operation on input vector data according to a received vector comparison operation instruction;

[0063] A high-speed temporary storage memory, used for storing input vectors to be compared and comparison result output vectors;

[0064] The input-output access module is used to directly access the high-speed temporary storage memory and is responsible for reading the input vector to be compared and writing the comparison result output vector from the high-speed temporary storage memory.

[0065] Preferably, the vector comparison unit is a customized hardware circuit.

[0066] According to a sixth aspect of the present disclosure, a method for performing a vector comparison operation is provided, the method comprising:

[0067] The value fetching module fetches the next vector comparison operation instruction to be executed from the instruction sequence, and transmits the vector comparison operation instruction to the decoding module;

[0068] The decoding module decodes the vector comparison operation instruction and transmits the decoded vector comparison operation instruction to the instruction queue module;

[0069] The instruction queue module temporarily stores the decoded vector comparison operation instruction, and obtains scalar data related to the vector comparison instruction operation from the vector comparison operation instruction or the scalar register; after obtaining the scalar data, the vector comparison operation instruction is sent to the dependency processing unit;

[0070] The dependency processing unit determines whether there is a dependency relationship between the vector comparison operation instruction and the previously unexecuted operation instruction; if there is a dependency relationship, the vector comparison operation instruction is sent to the storage queue module; if there is no dependency relationship, the vector comparison operation instruction is sent to the vector comparison unit;

[0071] The storage queue module stores the vector comparison operation instruction that has a dependency relationship with the previous operation instruction, and sends the vector comparison operation instruction to the vector comparison unit after the dependency relationship is released;

[0072] The vector comparison unit retrieves the input vector to be compared from the high-speed temporary storage memory through the input-output access module according to the received vector comparison operation instruction, then performs a vector comparison operation on the input vector to be compared, and writes the comparison result output vector into the high-speed temporary storage memory through the input-output access module.

[0073] The device and method for performing vector comparison operations provided by the present disclosure implement the complete process of vector comparison operation instructions through a customized hardware circuit, that is, the vector comparison operation can be implemented through a vector comparison instruction. The present disclosure also temporarily stores the vector data involved in the calculation in a high-speed scratchpad memory (Scratchpad Memory), so that vector data of different widths can be supported more flexibly and effectively during the operation process. At the same time, the customized vector comparison unit can more efficiently implement various comparison operations. The instructions used in the present disclosure are easy to use.

[0074] The present disclosure can be applied to the following scenarios (including but not limited to): various electronic products such as data processing, robots, computers, printers, scanners, telephones, tablet computers, smart terminals, mobile phones, driving recorders, navigators, sensors, cameras, cloud servers, cameras, camcorders, projectors, watches, headphones, mobile storage, wearable devices, etc.; various means of transportation such as airplanes, ships, and vehicles; various household appliances such as televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; and various medical equipment such as magnetic resonance imaging, B-ultrasound, and electrocardiographs.

[0075] By deducing the technical features in the claims, the beneficial effects of the technical problems in the corresponding background technologies can be achieved. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] The accompanying drawings, which are included in and constitute a part of the specification, illustrate exemplary embodiments, features and aspects of the present disclosure together with the specification, and are used to explain the principles of the present disclosure. In the exemplary embodiments of the present disclosure, the same reference numerals generally represent the same components.

[0077] Figure 1 It is a structural schematic diagram of a device for performing vector comparison operations provided by the present disclosure.

[0078] Figure 2 It is a format diagram of the vector comparison primitive instruction provided by the present disclosure.

[0079] Figure 3 It is a schematic diagram of the structure of a device for performing vector comparison operations provided by an embodiment of the present disclosure.

[0080] Figure 4 It is a flow chart of a vector comparison operation device provided by an embodiment of the present disclosure executing a vector comparison primitive instruction. DETAILED DESCRIPTION

[0081] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0082] Figure 1 is a schematic diagram of a structure of a device for performing vector comparison operations provided by the present disclosure, such as Figure 1 As shown, the vector comparison operation device includes:

[0083] A storage unit for storing vector data related to vector comparison operation instructions. In one embodiment, the storage unit may be a high-speed scratchpad memory that can support vector data of different sizes. The present disclosure temporarily stores the necessary calculation data in the high-speed scratchpad memory, so that the computing device can more flexibly and effectively support data of different widths during the vector operation. The vector data related to the vector comparison operation instruction includes input vector data to be compared and comparison result output vector data. The present disclosure temporarily stores the vector data involved in the operation in the high-speed scratchpad memory, so that data of different widths can be more flexibly and effectively supported during the vector operation. The high-speed scratchpad memory can be implemented by various different storage devices such as SRAM, DRAM, eDRAM, memristor, 3D-DRAM and non-volatile storage.

[0084] A register unit is used to store scalar data related to vector comparison operation instructions, wherein the scalar data includes the starting address and length of the input vector data to be compared, the storage address of the comparison result output vector data and other related parameters, wherein the address of the input vector data and the storage address of the output vector data are the addresses where the vectors are stored in the storage unit; in one embodiment, the register unit can be a scalar register stack, which provides the scalar registers required in the operation process, and the scalar registers not only store the vector storage addresses, but also store other scalar data.

[0085] The control unit is used to decode the vector comparison operation instruction and control the execution process of the vector comparison operation instruction; it mainly controls the execution process of the vector comparison operation instruction by controlling the behavior of each module in the device. In one embodiment, the control unit reads the prepared instruction, decodes it to generate a control signal, and sends it to other modules in the device, and the other modules perform corresponding operations according to the obtained control signal.

[0086] A vector comparison unit, which implements a specified comparison operation on input vector data according to an instruction. This unit is a vector operation unit, and performs the same operation on all input data at the same time. In one embodiment, the vector comparison unit obtains the starting address and length of two vectors to be compared according to the vector comparison operation instruction, obtains the two vectors to be compared from the storage unit, and compares the corresponding elements in the two vectors to be compared. When the condition is met, the corresponding position of the comparison result output vector is set to 1, otherwise it is set to 0 to obtain the comparison result. The vector comparison unit described in the present disclosure is a customized hardware circuit, including but not limited to FPGA, CGRA, application-specific integrated circuit ASIC, analog circuit and memristor, etc.; the vector comparison unit can complete the comparison operation of vectors of arbitrary length by cooperating with other modules in the device.

[0087] The present disclosure provides a vector comparison operation device, which controls the specific comparison operation mode and the address and length of vector data through instructions. The operation device mainly includes a storage unit, a register unit, a control unit and a comparison operation unit. The storage unit stores vectors, the register unit stores vector storage addresses and other scalar parameters, the control unit performs decoding operations, controls various modules according to instructions, and the comparison operation unit obtains the length, address and other parameters of the vector in the instruction or from the register unit according to the instruction, and then obtains the corresponding vector data in the storage unit according to the address and length, and then performs comparison operations on the vector. Depending on the instructions, comparison operations such as greater than or equal to, greater than, equal to, not equal to, less than and less than or equal to can be performed. The present disclosure temporarily stores the vector data involved in the calculation in a high-speed temporary storage memory, so that vector data of different widths can be supported more flexibly and effectively during the operation process.

[0088] According to an embodiment of the present disclosure, the vector comparison operation device further includes: an instruction cache unit for storing vector comparison operation instructions to be executed. During the execution process, the vector comparison original instruction is also cached in the instruction cache unit. When an instruction is executed, the instruction will be submitted.

[0089] Figure 2 FIG. 4 shows a schematic diagram of the format of a vector comparison operation instruction in the present disclosure, such as Figure 2 As shown, the vector comparison operation instruction includes an operation code and multiple operation fields, wherein the operation code is used to indicate which vector comparison operation is to be performed, such as comparison operations such as greater than or equal to, greater than, equal to, not equal to, less than, and less than or equal to; and the operation field is used to store scalar data related to the vector comparison operation, including an immediate number and a register number, and the register number points to a specific register unit; the immediate number and the register unit are used to store the starting address and length of the vector to be compared, the storage address of the output vector, etc. According to the instruction, the device can obtain the scalar data related to the instruction directly from the instruction or by accessing the register number provided by the instruction. The starting address of the vector to be compared and the storage address of the output vector are both addresses in the storage unit.

[0090] According to one embodiment of the present disclosure, the control unit of the vector comparison device also includes: an instruction queue module, which is used to sequentially store the decoded vector comparison operation instructions, which obtains scalar data related to the vector comparison operation instructions through the operation field in the vector comparison operation instructions, such as the starting address and length of the vector to be compared, etc., fills it into the vector comparison operation instructions and sends it to the dependency processing unit.

[0091] According to one embodiment of the present disclosure, the control unit of the device further includes: a dependency processing unit, which is used to determine whether the vector comparison operation instruction has a dependency relationship with the previously unexecuted operation instruction before the vector comparison operation unit obtains the vector comparison original instruction, such as whether the same vector storage address is accessed. If so, the vector comparison operation instruction is stored in the storage queue module. After the operation instruction with which it has a dependency relationship is executed, the storage queue module provides the vector comparison operation instruction to the vector comparison operation unit; otherwise, the vector comparison operation instruction is directly provided to the vector comparison operation unit. Specifically, when the vector comparison operation instruction accesses the high-speed temporary storage memory, the previous and next instructions may access the same storage space. In order to ensure the correctness of the instruction execution result, if the current instruction is detected to have a dependency relationship with the data of the previous instruction, the instruction must wait in the storage queue until the dependency relationship is eliminated.

[0092] According to one embodiment of the present disclosure, the control unit of the device also includes: a storage queue module, which includes an ordered queue, and instructions that have data dependencies on previous instructions are stored in the ordered queue until the dependency is eliminated. After the dependency is eliminated, it provides the operation instructions to the vector comparison operation unit.

[0093] According to an embodiment of the present disclosure, the device further includes: an input-output unit, which is used to store the vector in the storage unit, or to obtain the vector comparison operation result from the storage unit. The input-output unit can directly store the vector data from the memory or write the vector data.

[0094] According to an implementation of the present disclosure, the instruction design of the device is such that one instruction can complete a complete vector comparison operation.

[0095] In the process of executing the vector comparison operation of the device, the device takes out the instruction for decoding, and then sends it to the instruction queue for storage. According to the decoding result, the various parameters in the instruction are obtained. These parameters can be directly written in the operation domain of the instruction (i.e., the immediate value), or read from the specified register according to the register number in the instruction operation domain. The advantage of using registers to store parameters is that there is no need to change the instruction itself. As long as the value in the register is changed by the instruction, most of the loops can be realized, thus greatly saving the number of instructions required to solve certain practical problems. After all the operands, the dependency processing unit will determine whether the data actually needed by the instruction has a dependency relationship with the previous instruction, which determines whether this instruction can be immediately sent to the operation unit for execution. Once it is found that there is a dependency relationship with the previous data, the instruction must wait until the instruction it depends on is executed before it can be sent to the operation unit for execution. In the customized operation unit, the instruction will be executed quickly, and the result, that is, the generated random vector, will be written back to the address provided by the instruction, and the instruction will be executed.

[0096] This device can execute the following vector comparison operation instructions:

[0097] Greater than or equal to operation instruction (GE), according to which the device can obtain the parameters of the instruction directly from the instruction or by accessing the register number provided by the instruction, including the length of the vector, the starting address of the two vectors and the storage address of the output vector, and then read the two vector data, compare the elements at all positions in the vector in the vector comparison operation unit, if the value of the previous vector at a certain position is greater than or equal to the value of the next vector, then set the value of the comparison result vector at this position to 1, otherwise set it to 0. Finally, write the comparison result back to the specified storage address of the high-speed temporary storage memory.

[0098] Less than or equal to operation instruction (LE), according to which the device can obtain the parameters of the instruction directly from the instruction or by accessing the register number provided by the instruction, including the length of the vector, the starting address of the two vectors and the storage address of the output vector, and then read the two vector data, compare the elements at all positions in the vector in the vector comparison operation unit, if the value of the previous vector at a certain position is less than or equal to the value of the latter vector, then set the value of the comparison result vector at this position to 1, otherwise set it to 0. Finally, write the comparison result back to the specified storage address of the value high-speed temporary storage memory.

[0099] Greater than operation instruction (GT), according to which the device can obtain the parameters of the instruction directly from the instruction or by accessing the register number provided by the instruction, including the length of the vector, the starting address of the two vectors and the storage address of the output vector, and then read the two vector data, compare the elements at all positions in the vector in the vector comparison operation unit, if the value of the previous vector at a certain position is greater than the value of the latter vector, then set the value of the comparison result vector at this position to 1, otherwise set it to 0. Finally, write the comparison result back to the specified storage address of the value high-speed temporary storage memory.

[0100] Less than operation instruction (LT), according to which the device can obtain the parameters of the instruction directly from the instruction or by accessing the register number provided by the instruction, including the length of the vector, the starting address of the two vectors and the storage address of the output vector, and then read the two vector data, compare the elements at all positions in the vector in the vector comparison operation unit, if the value of the previous vector at a certain position is less than the value of the latter vector, then set the value of the comparison result vector at this position to 1, otherwise set it to 0. Finally, write the comparison result back to the specified storage address of the value high-speed temporary storage memory.

[0101] Equal operation instruction (EQ), according to which the device can obtain the parameters of the instruction directly from the instruction or by accessing the register number provided by the instruction, including the length of the vector, the starting address of the two vectors and the storage address of the output vector, and then read the two vector data, compare the elements at all positions in the vector in the vector comparison operation unit, if the value of the previous vector at a certain position is equal to the value of the latter vector, then set the value of the comparison result vector at this position to 1, otherwise set it to 0. Finally, write the comparison result back to the specified storage address of the value high-speed temporary storage memory.

[0102] Not equal to the operation instruction (UEQ), according to which the device can obtain the parameters of the instruction directly from the instruction or by accessing the register number provided by the instruction, including the length of the vector, the starting address of the two vectors and the storage address of the output vector, and then read the two vector data, compare the elements at all positions in the vector in the vector comparison operation unit, if the value of the previous vector at a certain position is not equal to the value of the latter vector, then set the value of the comparison result vector at this position to 1, otherwise set it to 0. Finally, write the comparison result back to the specified storage address of the value high-speed temporary storage memory.

[0103] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0104] Figure 3 is a schematic diagram of the structure of a device for performing vector comparison operations provided by an embodiment of the present disclosure, such as Figure 3As shown, the device includes an instruction fetch module, a decoding module, an instruction queue module, a scalar register stack, a dependency processing unit, a storage queue module, a vector comparison operation unit, a high-speed temporary register, and an IO memory access module;

[0105] The instruction fetch module is responsible for fetching the next instruction to be executed from the instruction sequence and passing it to the decoding module;

[0106] The decoding module is responsible for decoding the instructions and passing the decoded instructions to the instruction queue;

[0107] Instruction queue module, which is used to temporarily store instructions obtained from the decoding module and obtain the data corresponding to the instruction operation from the instruction or scalar register, including the starting address and size of the vector data and some scalar constants. After obtaining the data, the instruction is sent to the dependency processing unit;

[0108] Scalar register file, providing scalar registers required during the operation;

[0109] The dependency processing unit is used to process the possible storage dependency between the vector comparison operation instruction and the previously unexecuted instruction. The vector comparison operation instruction will access the high-speed temporary storage memory to obtain the vector to be compared, and the previous and subsequent instructions may access the same storage space. In order to ensure the correctness of the instruction execution result, if the current instruction is detected to have a dependency relationship with the data of the previous instruction, the instruction is sent to the storage queue module to wait until the dependency relationship is eliminated. That is, it is detected whether the storage interval of the input data of this instruction overlaps with the storage interval of the output data of the previously unexecuted instruction. The storage interval is determined by the starting address and data length. If there is an overlap, it means that this instruction actually requires the execution result of the previous instruction as input, so it must wait until that instruction is executed before this instruction can start execution. In this process, the instruction is actually temporarily stored in the storage queue module.

[0110] A storage queue module, which is an ordered queue. Instructions that have data dependencies with previous instructions are stored in the queue until the storage relationship is eliminated. The vector comparison operation instructions after the dependency is eliminated are sent to the vector comparison operation unit.

[0111] A vector comparison operation unit, which is responsible for performing comparison operations of two vectors to be compared, including comparison operations of greater than or equal to, greater than, less than or equal to, less than, equal to, and not equal to; the vector comparison operation unit is implemented as a customized hardware circuit;

[0112] A high-speed temporary register, which is a temporary storage device dedicated to vector data and can support vector data of different sizes; the high-speed temporary register is mainly used to store vector data to be compared and vector data of comparison operation results;

[0113] IO memory access module, which is used to directly access the high-speed temporary storage memory and is responsible for reading data from or writing data to the high-speed temporary storage memory.

[0114] Figure 4 FIG. 1 is a flow chart of a vector comparison operation device according to an embodiment of the present disclosure executing a vector comparison operation instruction. Figure 4 As shown, the process of executing a vector comparison operation instruction includes:

[0115] S1, the instruction fetch module fetches the vector comparison operation instruction and sends the vector comparison operation instruction to the decoding module.

[0116] S2, the decoding module decodes the vector comparison operation instruction and sends the vector comparison operation instruction to the instruction queue module.

[0117] S3, in the instruction queue module, the scalar data corresponding to the operation domain in the vector comparison operation instruction is obtained from the vector comparison operation instruction itself or from the scalar register stack, including the starting address of the two input vectors to be compared, the input vector length, and the output vector address.

[0118] S4, after obtaining the required scalar data, the vector comparison operation instruction is sent to the dependency processing unit.

[0119] S5, the dependency processing unit analyzes whether the vector comparison operation instruction has a data dependency with the previous instruction that has not yet been executed. If there is a dependency, the vector comparison operation instruction is sent to the storage queue to wait until it no longer has a data dependency with the previous instruction that has not yet been executed. If there is no dependency, the vector comparison original instruction is sent to the vector comparison operation unit.

[0120] S6, the vector comparison operation unit fetches a part of the two vector data to be compared from the high-speed register according to the starting addresses and lengths of the two vectors to be compared in the vector comparison operation instruction.

[0121] S7, the vector comparison unit compares the elements at all positions in a part of the two vector data to be compared at the same time, and when two elements at a certain position are equal, sets the corresponding position of the output result to 1 or 0.

[0122] S8, go to step S6, the vector comparison unit continues to take out the next part of the two vector data to be compared for comparison, until the operation of whether the two vectors to be compared are equal is completed.

[0123] S9, after the operation is completed, the result vector is written back to the specified address of the high-speed temporary storage memory.

[0124] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily required by the present application.

[0125] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0126] In the several embodiments provided in the present application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical or other forms.

[0127] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0128] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above integrated unit may be implemented in the form of hardware or in the form of a software program module.

[0129] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or CD-ROM and other media that can store program codes.

[0130] Those skilled in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, and the memory can include: a flash drive, a read-only memory (English: Read-Only Memory, referred to as: ROM), a random access memory (English: Random Access Memory, referred to as: RAM), a disk or an optical disk, etc. In summary, the present disclosure provides a vector comparison operation device, which, in conjunction with corresponding instructions, can well solve the increasing number of comparison operations on vectors in the current computer field. Compared with existing traditional solutions, the present disclosure can have the advantages of easy use, flexible supported vector length, sufficient on-chip cache, etc.

[0131] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for performing a vector comparison operation, comprising: Determine whether there is a dependency relationship between the acquired first instruction and a previously acquired second instruction to be executed, wherein the dependency relationship indicates a processing order of the instructions and is used to determine whether the first instruction can be immediately sent to a vector comparison unit for processing, wherein the first instruction and the second instruction are instructions for performing a vector comparison operation; In response to the dependency relationship between the first instruction and the second instruction, storing the first instruction; and In response to the second instruction having been executed, providing the stored first instruction to the vector comparison unit for performing the vector comparison operation; Determining whether there is a dependency relationship between the acquired first instruction and the previously acquired second instruction to be executed includes: determining a first storage address of a first vector stored in an operation field of the first instruction; determining a second storage address of a second vector stored in an operation field of the second instruction; comparing the first storage address and the second storage address; and In response to the first storage address and the second storage address overlapping, it is determined that a dependency relationship exists between the first instruction and the second instruction. 2 . The method of claim 1 , wherein the first storage address and the second storage address overlap comprises the first storage address and the second storage address being the same.

3. The method according to claim 1, further comprising: In response to determining that the dependency relationship does not exist, providing the first instruction to a vector comparison unit for directly performing the vector comparison operation.

4. The method according to claim 1, wherein the first instruction or the second instruction comprises an operation code and a plurality of operation fields, wherein the operation code is used to indicate the type of the vector comparison operation, and the plurality of operation fields comprise an immediate number and / or a register number, and the immediate number and the register number are used to determine the vector length, the starting address of the two vectors to be compared, and the storage address of the comparison result vector.

5. The method according to claim 4, wherein the first instruction or the second instruction is a greater than or equal to operation instruction, and the greater than or equal to operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is greater than or equal to the value of the latter vector.

6. The method according to claim 4, wherein the first instruction or the second instruction is a less than or equal to operation instruction, and the less than or equal to operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is less than or equal to the value of the latter vector.

7. The method according to claim 4, wherein the first instruction or the second instruction is a greater than operation instruction, and the greater than operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is greater than the value of the latter vector.

8. The method according to claim 4, wherein the first instruction or the second instruction is a less than operation instruction, and the less than operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is less than the value of the latter vector.

9. The method according to claim 4, wherein the first instruction or the second instruction is an equal operation instruction, and the equal operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is equal to the value of the latter vector.

10. The method according to claim 4, wherein the first instruction or the second instruction is a inequality operation instruction, and the inequality operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is not equal to the value of the latter vector.

11. The method according to claim 4, further comprising: Obtain the first instruction from an instruction cache unit; Decoding the first instruction; Obtaining a register number from an operation field of the decoded first instruction; as well as The scalar data stored in the register unit corresponding to the register number is stored in the first instruction, wherein the scalar data includes the starting address and vector length of the two vectors to be compared and the storage address of the comparison result vector. 12 . The method according to claim 11 , wherein the register unit is a scalar register file, comprising a plurality of scalar registers for storing scalar data associated with instructions for the vector comparison operation.

13. An apparatus for performing a vector comparison operation, comprising: a dependency processing unit configured to determine whether there is a dependency between the acquired first instruction and a previously acquired second instruction to be executed, wherein the dependency indicates a processing order of the instructions and is used to determine whether the first instruction can be immediately sent to the vector comparison unit for processing, wherein the first instruction and the second instruction are instructions for performing a vector comparison operation; as well as The storage queue module is configured as follows: In response to the dependency relationship between the first instruction and the second instruction, storing the first instruction; and In response to the second instruction having been executed, providing the stored first instruction to the vector comparison unit for performing the vector comparison operation; The dependency processing unit is further configured to: determining a first storage address of a first vector stored in an operation field of the first instruction; determining a second storage address of a second vector stored in an operation field of the second instruction; comparing the first storage address and the second storage address; as well as In response to the first storage address and the second storage address overlapping, it is determined that a dependency relationship exists between the first instruction and the second instruction.

14. The apparatus of claim 13, wherein the first storage address and the second storage address overlap comprises the first storage address and the second storage address being the same.

15. The device according to claim 13, wherein: The dependency handling unit is further configured to, in response to determining that the dependency does not exist, provide the first instruction to a vector comparison unit for directly performing the vector comparison operation.

16. The apparatus according to claim 13, wherein the first instruction or the second instruction comprises an operation code and a plurality of operation fields, wherein the operation code is used to indicate the type of the vector comparison operation, the plurality of operation fields comprise an immediate number and / or a register number, the immediate number and the register number are used to determine the vector length, the starting address of the two vectors to be compared, and the storage address of the comparison result vector.

17. The device according to claim 16, wherein the first instruction or the second instruction is a greater than or equal to operation instruction, and the greater than or equal to operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is greater than or equal to the value of the latter vector.

18. The device according to claim 16, wherein the first instruction or the second instruction is a less than or equal to operation instruction, and the less than or equal to operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is less than or equal to the value of the latter vector.

19. The device according to claim 16, wherein the first instruction or the second instruction is a greater than operation instruction, and the greater than operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is greater than the value of the latter vector.

20. The device according to claim 16, wherein the first instruction or the second instruction is a less than operation instruction, and the less than operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is less than the value of the latter vector.

21. The device according to claim 16, wherein the first instruction or the second instruction is an equal operation instruction, and the equal operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is equal to the value of the latter vector.

22. The device according to claim 16, wherein the first instruction or the second instruction is a inequality operation instruction, and the inequality operation instruction is used to compare the elements at all positions in the two vectors to be compared and set the value of the comparison result vector at a certain position to 1 when the value of the previous vector is not equal to the value of the latter vector.

23. The apparatus of claim 16, further comprising: An instruction fetch module, configured to fetch the first instruction from an instruction cache unit; A decoding module, configured to decode the first instruction; The instruction queue module is configured to obtain a register number from an operation field of the first decoded instruction; and store scalar data stored in a register unit corresponding to the register number in the first instruction, wherein the scalar data includes a starting address and a vector length of two vectors to be compared, and a storage address of a comparison result vector. 24 . The apparatus according to claim 23 , wherein the register unit is a scalar register file, the scalar register file comprising a plurality of scalar registers and used to store the scalar data associated with the instruction for the vector comparison operation.

25. An artificial intelligence chip, characterized in that The chip is used to execute the steps of the method according to any one of claims 1-12.

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