Passivation structure and method of manufacturing a semiconductor device including the passivation structure

Abstract

A passivation structure may include: a first passivation pattern on an upper surface of a semiconductor chip disposed on a semiconductor substrate; and a second passivation pattern arranged on a scribe line of the semiconductor substrate adjacent to the semiconductor chip. The second passivation pattern is spaced apart from the first passivation pattern to form a crack stopping groove between the second passivation pattern and the first passivation pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0138820 filed on November 13, 2018 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to a passivation structure and a method of manufacturing a semiconductor device including the passivation structure. More particularly, example embodiments relate to a passivation structure for protecting a semiconductor chip on a semiconductor substrate and a method of manufacturing a semiconductor device including the passivation structure. Background Art

[0004] Generally, the passivation layer can protect a plurality of semiconductor chips on the semiconductor substrate. In order to form a semiconductor package using the semiconductor chips, the semiconductor substrate can be sawed along scribe lines.

[0005] The cutting process may use a blade or a laser. The cutting process using a blade may include sawing the passivation layer and the scribe line on the scribe line using a blade. The cutting process using a laser may include attaching a die attach film to the passivation layer, irradiating a laser to the passivation layer and the scribe line to form a cutting line, pulling the die attach film along the cutting line to separate the semiconductor chips, and partially removing the lower surface of the semiconductor substrate using a grinder.

[0006] According to the related art, when a semiconductor substrate is sawed using a blade, cracks generated in the passivation layer by the blade may spread to the semiconductor chip through the passivation layer on the semiconductor chip, because the portion of the passivation layer on the scribe line and the portion of the passivation layer on the semiconductor chip may be connected to each other. The cracks may damage the semiconductor chip. Therefore, when a cutting process using a blade is applied to a semiconductor substrate, a passivation layer may not be formed on the scribe line to prevent the cracks from spreading.

[0007] When a semiconductor substrate is sawed using a laser under the condition that a passivation layer is formed on the scribe line, although the semiconductor chips can be connected to each other through the die attach film, the positions of the semiconductor chips may be adjacent to each other. Therefore, the semiconductor chips may collide with each other during the grinding process, and the semiconductor chips may be damaged. Therefore, when a cutting process using a laser is applied to a semiconductor substrate, a passivation layer may be formed on the scribe line to prevent damage to the semiconductor chips.

[0008] As a result, depending on the structure of the passivation layer, only one of a dicing process using a blade and a sawing process using a laser may be applied to the semiconductor substrate. Summary of the invention

[0009] Example embodiments provide a passivation structure to which a cutting process using a blade and a laser may be applied.

[0010] Example embodiments also provide a method of manufacturing a semiconductor device including the above passivation structure.

[0011] According to some embodiments, the present invention relates to a passivation structure, comprising: a first passivation pattern on an upper surface of a semiconductor chip disposed on a semiconductor substrate; and a second passivation pattern arranged on a scribe line of the semiconductor substrate adjacent to the semiconductor chip. The second passivation pattern is spaced apart from the first passivation pattern to form a crack stopping groove between the second passivation pattern and the first passivation pattern.

[0012] According to some embodiments, the present invention relates to a passivation structure, comprising: a plurality of first passivation patterns, each of the first passivation patterns being arranged on an upper surface of a corresponding semiconductor chip among a plurality of semiconductor chips provided on a semiconductor substrate; and a second passivation pattern, arranged on a scribe line of the semiconductor substrate for separating the semiconductor chips, wherein the second passivation pattern can be spaced apart from each first passivation pattern to form a crack preventing groove between the second passivation pattern and each of the first passivation patterns.

[0013] According to some embodiments, the present disclosure relates to a method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate having a scribe line; forming a plurality of semiconductor chips on an upper surface of the semiconductor substrate; forming a plurality of first passivation patterns, each of the first passivation patterns being arranged on an upper surface of a corresponding semiconductor chip among the plurality of semiconductor chips; and forming a second passivation pattern arranged on the upper surface of the scribe line, wherein the second passivation pattern can be spaced apart from each first passivation pattern to form a crack stopping groove between the second passivation pattern and the first passivation pattern.

[0014] According to some embodiments, the present disclosure relates to a method for manufacturing a semiconductor device, the method comprising: forming a plurality of first passivation patterns, each of the first passivation patterns being arranged on an upper surface of a corresponding semiconductor chip of a plurality of semiconductor chips provided on a semiconductor substrate; forming a second passivation pattern on a scribe line of the semiconductor substrate for separating the semiconductor chips, the second passivation pattern being spaced apart from each first passivation pattern; and cutting the semiconductor substrate along the scribe line to provide cut semiconductor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 15Represents non-limiting example embodiments described herein.

[0016] Figure 1 is a plan view showing a semiconductor device according to an example embodiment;

[0017] Figure 2 is along Figure 1 A cross-sectional view taken along line II-II';

[0018] Figure 3 is a plan view showing a semiconductor device according to an example embodiment;

[0019] Figure 4 is along Figure 3 A cross-sectional view taken along line IV-IV';

[0020] Figure 5 is a plan view showing a semiconductor device according to an example embodiment;

[0021] Figure 6 is along Figure 5 A cross-sectional view taken along line VI-VI';

[0022] Figures 7 to 9 is a cross-sectional view illustrating a method of cutting a semiconductor substrate using a blade according to example embodiments; and

[0023] Figures 10 to 15 is a cross-sectional view illustrating a method of cutting a semiconductor substrate using a laser according to example embodiments. DETAILED DESCRIPTION

[0024] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0025] Semiconductor Devices

[0026] Figure 1 is a plan view showing a semiconductor device according to an example embodiment, Figure 2 is along Figure 1 A partial cross-sectional view taken along line II-II'. Figure 2 Not shown Figure 1 Features further to the left of the leftmost semiconductor chip 120 and further to the right of the rightmost semiconductor chip 120 are shown in FIG.

[0027] refer to Figure 1 and Figure 2 , the semiconductor device of this example embodiment may include a semiconductor substrate 110 , a plurality of semiconductor chips 120 , and a passivation structure 130 .

[0028] Unless the context indicates otherwise, it should be understood that references to "uncut chips" refer to semiconductor devices that have not yet been separated (e.g., separated from a wafer) to form individual semiconductor chips, and references to "cut chips" refer to semiconductor devices that have been separated (e.g., separated from a wafer) to form individual semiconductor chips. As used herein, references to "chips" or "semiconductor chips" by themselves (i.e., without modifiers such as "cut") will be understood to refer to semiconductor devices implemented in a portion of a wafer that have not yet been cut from a wafer to form individual semiconductor chips.

[0029] The semiconductor chip 120 may be formed on the upper surface of the semiconductor substrate 110. The semiconductor chip 120 may be separated by the scribe lanes 112 of the semiconductor substrate 110. The scribe lanes 112 may include: a first subset of the scribe lanes 112 extending longitudinally along a first direction, and a second subset of the scribe lanes 112 extending longitudinally along a second direction perpendicular to the first direction. The first subset and the second subset of the scribe lanes 112 may intersect with each other, thereby forming a grid pattern. Therefore, the scribe lanes 112 may be configured to surround each semiconductor chip 120 in the semiconductor chip 120.

[0030] In an example embodiment, each semiconductor chip 120 in the semiconductor chips 120 may have a rectangular cross-sectional shape. Therefore, each semiconductor chip 120 in the semiconductor chips 120 may have four side surfaces. The semiconductor chips 120 may be arranged to be spaced apart from each other with a consistent gap in the longitudinal direction and the lateral direction. Therefore, the scribe lanes 112 for separating the semiconductor chips 120 may have a cross shape. For example, the scribe lanes 112 may have a rectangular frame shape, which is configured to surround each semiconductor chip 120 in the semiconductor chips 120. In some embodiments, the scribe lanes 112 between adjacent semiconductor chips 120 may have a consistent width. For example, the scribe lanes 112 may correspond to the consistent gaps between adjacent semiconductor chips 120.

[0031] The passivation structure 130 may include a plurality of first passivation patterns 132 and second passivation patterns 134. The passivation structure 130 may include photosensitive polyimide (PSPI).

[0032] Each of the first passivation patterns 132 may be arranged on the upper surface of the semiconductor chip 120. The first passivation pattern 132 may have a size substantially the same as that of the upper surface of the semiconductor chip 120. In example embodiments, since the semiconductor chip 120 may have a rectangular shape when viewed in a plan view, each of the first passivation patterns 132 may also have a rectangular shape when viewed in a plan view. When viewed in a cross section, each of the semiconductor chips 120 may have a rectangular shape, and each of the first passivation patterns 132 may have a trapezoidal shape, wherein the width of the bottom surface of the first passivation pattern 132 corresponds to the width of the semiconductor chip 120 on which the first passivation pattern 132 may be disposed. The shape of the first passivation pattern 132 may be changed according to the shape of the semiconductor chip 120.

[0033] The second passivation pattern 134 may be formed on the upper surface of the scribe lane 112. The second passivation pattern 134 may have an upper surface substantially coplanar with an upper surface of the first passivation pattern 132. For example, the first passivation pattern 132 and the second passivation pattern 134 may have the same thickness. Alternatively, the upper surface of the second passivation pattern 134 may be located on a plane different from the plane where the upper surface of the first passivation pattern 132 may be located.

[0034] The second passivation pattern 134 may be spaced apart from the first passivation pattern 132. For example, the second passivation pattern 134 may have an outer side surface spaced apart from the inner side surface of the first passivation pattern 132. Therefore, a crack stopping groove 136 may be formed between the first passivation pattern 132 and the second passivation pattern 134. The crack stopping groove 136 may function to separate the first passivation pattern 132 and the second passivation pattern 134 from each other. In addition, due to the crack stopping groove 136, the second passivation pattern 134 may have a width smaller than the width of the scribe lane 112.

[0035] In example embodiments, since the scribe lane 112 may have a rectangular frame shape configured to surround the semiconductor chip 120, the second passivation pattern 134 may also have a rectangular frame shape. For example, the second passivation pattern 134 may include linear segments that together surround each of the semiconductor chips 120. In some embodiments, when the second passivation pattern 134 has a rectangular frame shape, the portion of the second passivation pattern 134 surrounding a given semiconductor chip 120 may include four linear segments that are connected together and surround the four side surfaces of the rectangular semiconductor chip 120. Therefore, the crack-stopping groove 136 between the first passivation pattern 132 and the second passivation pattern 134 may also have a rectangular frame shape. For example, the crack-stopping groove 136 may surround each of the semiconductor chips 120 and may be disposed between the first passivation pattern 132 and the segment of the second passivation pattern 134 surrounding the semiconductor chip 120.

[0036] In example embodiments, the crack stopping groove 136 may have an upper width and a lower width different from the upper width. The upper width of the crack stopping groove 136 may be wider or narrower than the lower width of the crack stopping groove 136. For example, with respect to the top surface of the semiconductor substrate 110, the inner side surface 133 of the first passivation pattern 132 may have a gradually inclined shape in an upward direction toward the center portion of the semiconductor chip 120. In contrast, the outer side surface of the second passivation pattern 134 may have a vertical shape (for example, the outer side surface may be perpendicular to the top surface of the semiconductor substrate 110). In this case, the upper width of the crack stopping groove 136 may gradually increase from the lower width. As an alternative example, with respect to the top surface of the semiconductor substrate 110, the inner side surface 133 of the first passivation pattern 132 may have a gradually inclined shape in an upward direction toward the edge portion of the semiconductor chip 120. In contrast, the outer side surface of the second passivation pattern 134 may have a vertical shape (for example, the outer side surface may be perpendicular to the top surface of the semiconductor substrate 110). In this case, the upper width of the crack-stopping groove 136 may be gradually reduced to the lower width.

[0037] In addition, the outer side surface of the second passivation pattern 134 may have other shapes as well as a vertical shape. For example, the outer side surface of the second passivation pattern 134 may have an inclined shape relative to the top surface of the semiconductor substrate 110, and the inclined shape may be inclined outward or inward. For example, the inner side surface of the first passivation pattern 132 and the outer side surface of the second passivation pattern 134 for defining the crack-stopping groove 136 may not be limited to a specific shape.

[0038] When the scribe lane 112 and the second passivation pattern 134 may be cut using a blade, cracks may be generated in the second passivation pattern 134. The cracks in the second passivation pattern 134 may not extend through the crack stopping groove 136. Therefore, the cracks may not spread into the first passivation pattern 132. Therefore, the cracks may not spread into the semiconductor chip 120 under the first passivation pattern 132.

[0039] When the scribe lanes 112 and the second passivation pattern 134 may be cut using a laser under the condition that the die attach film may be attached to the upper surfaces of the first passivation pattern 132 and the second passivation pattern 134, the second passivation pattern 134 attached to the die attach film may remain on the scribe lanes 112. Therefore, during a process in which the lower surface of the semiconductor substrate 110 may be ground to partially remove the lower surface of the semiconductor substrate 110, the remaining second passivation pattern 134 on the scribe lanes 134 may prevent the semiconductor chips 120 (particularly, corners of the semiconductor chips 120) from colliding with each other.

[0040] Therefore, the semiconductor substrate 110 is sawed by any one of the cutting processes using a blade and a laser to prevent damage of the semiconductor chip 120. For example, the cutting process may be performed by sawing, laser cutting, or other methods.

[0041] Figure 3 is a plan view showing a semiconductor device according to an example embodiment, Figure 4 is along Figure 3 For example, in the section view taken along line IV-IV' Figure 4 Not shown Figure 3 Features further to the left of the leftmost semiconductor chip 120 and further to the right of the rightmost semiconductor chip 120 are shown in FIG.

[0042] In addition to the first passivation pattern and the crack stopping groove, the semiconductor device of this example embodiment may include Figure 1 and Figure 2 Therefore, the same reference numerals may refer to the same elements, and any further illustration and / or discussion of the same elements may be omitted herein for the sake of brevity.

[0043] refer to Figure 3 and Figure 4, the first passivation pattern 132a may have an inner side surface 133a substantially parallel to the outer side surface of the second passivation pattern 134. In this case, the crack stopping groove 136a may have the same width in the vertical direction. For example, the width of the crack stopping groove 136a may be substantially uniform from the bottom area to the top area of ​​the crack stopping groove 136a. However, as described above, the inner side surface 133a of the first passivation pattern 132a and the outer side surface of the second passivation pattern 134 for defining the crack stopping groove 136a may not be limited to a specific shape.

[0044] Figure 5 is a plan view showing a semiconductor device according to an example embodiment, Figure 6 is along Figure 5 Partial cross-sectional view taken along line VI-VI'.

[0045] In addition to further including a test element group, the semiconductor device of this example embodiment may include Figure 1 and Figure 2 Therefore, the same reference numerals may refer to the same elements, and any further illustration and / or discussion of the same elements may be omitted herein for the sake of brevity.

[0046] refer to Figure 5 and Figure 6 , a test element group (TEG) 140 may be arranged on an upper surface of the scribe lane 112. The TEG 140 may be used to test electrical characteristics of the semiconductor chip 120. Therefore, the TEG 140 may be electrically connected to the semiconductor chip 120.

[0047] The TEG 140 may include a plurality of test pads 142 and a plurality of test lines 144. The test pads 142 may be connected to each other through the test lines 144. The test pads 142 may include aluminum. The test lines 144 may include copper.

[0048] The second passivation pattern 134 may cover the TEG 140. Therefore, the test pad 142 and the test line 144 may not be exposed, so that the test pad 142 and the test line 144 may not contact the air. Therefore, corrosion of the test pad 142 and the test line 144 may be suppressed. Specifically, since the test line 144 may be covered by the second passivation pattern 134, corrosion of the test line 144 including copper may be suppressed.

[0049] Method for cutting semiconductor substrate

[0050] Figures 7 to 9 is a partial cross-sectional view showing a method of cutting a semiconductor substrate using a blade according to an example embodiment. Figures 7 to 9In the figure, features further to the left of the leftmost semiconductor chip 120 and further to the right of the rightmost semiconductor chip 120 may not be shown. Figures 7 to 9 The partial cross section may correspond to the Figure 1 A view taken along line I-I'.

[0051] refer to Figure 7 , a passivation layer 138 may be formed on the upper surface of the semiconductor substrate 110. Specifically, the passivation layer 138 may be formed on the upper surface of the semiconductor chip 120 and the upper surface of the scribe lane 112. In some embodiments, the scribe lane 112 may include an area of ​​the semiconductor substrate 110 in which no circuit may be formed (e.g., no transistor may be formed) and / or a circuit that is part of an integrated circuit of the uncut semiconductor chip 120 and may not exchange signals with the integrated circuit of the uncut semiconductor chip 120 may not be formed (e.g., no transistor may be formed).

[0052] refer to Figure 8 , the passivation layer 138 may be patterned to form the first passivation pattern 132 and the second passivation pattern 134. Specifically, the passivation layer 138 may be etched until the upper surface of the scribe lane 112 may be exposed to form the first passivation pattern 132 and the second passivation pattern 134. A crack stopping groove 136 may be formed between each of the first passivation patterns 132 and the second passivation pattern 134 by the etching process.

[0053] Each of the first passivation patterns 132 may be disposed on an upper surface of the semiconductor chip 120. The second passivation pattern 134 may be disposed on an upper surface of the scribe lane 112. Figure 1 and Figure 2 The shapes and functions of the first and second passivation patterns 132 and 134 and the crack-stopping groove 136 are explained. Therefore, any further explanation on the shapes and functions of the first and second passivation patterns 132 and 134 and the crack-stopping groove 136 may be omitted for the sake of brevity.

[0054] Alternatively, Figure 3 and Figure 4 The first passivation pattern 132a and the crack stopping groove 136a may be formed on the upper surface of the semiconductor chip 120. In addition, Figure 5 and Figure 6 The TEG 140 may be formed on an upper surface of the scribe lane 112. The TEG 140 may be covered by the second passivation pattern 134.

[0055] refer to Fig. 9, the blade 150 may be positioned above the second passivation pattern 134. In some embodiments, the blade 150 may be centered above a centerline of the second passivation pattern 134. The blade 150 may cut the second passivation pattern 134 and the scribe lane 112.

[0056] During the cutting of the passivation pattern 134 and the scribing lane 112 using the blade 150, cracks may be generated in the second passivation pattern 134 and / or the scribing lane 112. The crack-stopping groove 136 may stop the spread of the cracks. Therefore, the cracks may not spread into the first passivation pattern 132. Therefore, the cracks may also not spread into the semiconductor chip 120 under the first passivation pattern 132.

[0057] Similarly, refer to Figure 3 and Figure 4 In the embodiment, the preventing groove 136a can prevent the crack from spreading, and the crack may not spread into the first passivation pattern 132a. Therefore, the crack may not spread into the semiconductor chip 120 under the first passivation pattern 132a.

[0058] Figures 10 to 15 is a cross-sectional view illustrating a method of cutting a semiconductor substrate using a laser according to example embodiments.

[0059] refer to Fig.10 , a passivation layer 138 may be formed on an upper surface of the semiconductor substrate 110 . Specifically, the passivation layer 138 may be formed on an upper surface of the semiconductor chip 120 and an upper surface of the scribe lane 112 .

[0060] refer to Fig.11 , the passivation layer 138 may be patterned to form the first passivation pattern 132 and the second passivation pattern 134. Specifically, the passivation layer 138 may be etched until the upper surface of the scribe lane 112 may be exposed to form the first passivation pattern 132 and the second passivation pattern 134. A crack stopping groove 136 may be formed between each of the first passivation patterns 132 and the second passivation pattern 134 by the etching process.

[0061] Each of the first passivation patterns 132 may be disposed on an upper surface of the semiconductor chip 120. The second passivation pattern 134 may be disposed on an upper surface of the scribe lane 112. Figure 1 and Figure 2 The shapes and functions of the first and second passivation patterns 132 and 134 and the crack-stopping groove 136 are explained. Therefore, any further explanation on the shapes and functions of the first and second passivation patterns 132 and 134 and the crack-stopping groove 136 may be omitted herein for the sake of brevity.

[0062] Alternatively, Figure 3 and Figure 4 The first passivation pattern 132a and the crack stopping groove 136a may be formed on the upper surface of the semiconductor chip 120. In addition, Figure 5 and Figure 6 The TEG 140 may be formed on an upper surface of the scribe lane 112. The TEG 140 may be covered by the second passivation pattern 134.

[0063] Reference Fig.12 , the die attach film 160 may be attached to upper surfaces of the first passivation pattern 132 and the second passivation pattern 134. The die attach film 160 may include a flexible film.

[0064] Reference Fig.13 , the laser irradiator 170 located under the semiconductor substrate 110 may irradiate laser light to the scribe lane 112. The laser light may be incident to the scribe lane 112 and the second passivation pattern 134. In contrast, the laser light may not be incident to the die attach film 160.

[0065] Reference Fig.14 , a cutting line 172 may be formed in the scribe lane 112 and the second passivation pattern 134 by irradiation of laser. On the contrary, since the laser may not be incident on the die attach film 160, a cutting line may not be formed in the die attach film 160. The scribe lane 112 and the second passivation pattern 134 may be separated along the cutting line 172. Therefore, the semiconductor chip 120 may also be separated along the cutting line 172.

[0066] However, since the semiconductor chips 120 may be connected to each other via the first passivation pattern 132, the semiconductor chips 120 may not be completely separated. Since the die attach film 160 may include a flexible material, the semiconductor chip 120 may be slightly movable. The semiconductor chip 120 may be movable in each direction. Therefore, the corners of the semiconductor chip 120 may enter the scribing lane 112, so that the positions of the corners of the semiconductor chip 120 may be adjacent to each other. The corners of the semiconductor chip 120 may collide with each other and cause damage to the semiconductor chip 120.

[0067] However, since the separated second passivation pattern 134 may be attached to the die attach film 160, the separated second passivation pattern 134 may remain in the scribe lane 112. Therefore, the separated second passivation pattern 134 may prevent contact between the semiconductor chips 120 in the scribe lane 112. Therefore, the corners of the semiconductor chips 120 may not collide with each other, thereby preventing damage to the semiconductor chips 120.

[0068] Reference Fig.15, the lower surface of the semiconductor substrate 110 may be partially removed to reduce the thickness of each of the semiconductor chips 120. The lower surface of the semiconductor substrate 110 may be removed through a grinding process.

[0069] During the grinding process, collision of the semiconductor chips may also be generated. However, as described above, the separated second passivation pattern 134 can suppress contact between the semiconductor chips 120 in the scribe lane 112 to prevent damage to the semiconductor chips 120.

[0070] According to example embodiments, the first passivation pattern on the semiconductor chip may be separated from the second passivation pattern on the scribing lane. When a blade may be used to saw the semiconductor substrate, the cracks generated by the blade in the second passivation pattern may not diffuse into the first passivation pattern. Therefore, the cracks may not diffuse into the semiconductor chip below the first passivation pattern. In addition, when a laser may be used to saw the semiconductor substrate, the second passivation pattern may remain on the scribing lane. Therefore, the remaining second passivation pattern on the scribing lane may prevent the semiconductor chips from colliding with each other during the grinding process. Therefore, the cutting process using a blade and a laser can be applied to the semiconductor substrate without damaging the semiconductor chip.

[0071] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that various modifications may be made in the example embodiments without substantially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the present invention as defined in the claims. In the claims, means-plus-function clauses are intended to cover structures described herein as performing the functions described, and include not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A passivation structure comprising: a first passivation pattern on an upper surface of a semiconductor chip disposed on a semiconductor substrate; as well as a second passivation pattern arranged on a scribe line of the semiconductor substrate adjacent to the semiconductor chip, wherein the second passivation pattern is spaced apart from the first passivation pattern to form a crack stopping groove between the second passivation pattern and the first passivation pattern, The first passivation pattern covers the upper surface of the semiconductor chip, and the width of the bottom surface of the first passivation pattern is equal to the width of the semiconductor chip.

2. The passivation structure according to claim 1, wherein: The scribe line extends along the second passivation pattern.

3. The passivation structure according to claim 1, wherein: The semiconductor chip has four side surfaces, and the scribe lanes extend along the four side surfaces.

4. The passivation structure according to claim 1, wherein: The width of the scribe line is greater than the width of the second passivation pattern.

5. The passivation structure according to claim 1, wherein: The first passivation pattern and the second passivation pattern include photosensitive polyimide (PSPI).

6. The passivation structure according to claim 1, wherein: The crack-stopping groove has a lower width and an upper width greater than the lower width.

7. The passivation structure according to claim 1, wherein: The crack-preventing groove has a substantially uniform width.

8. A passivation structure comprising: a plurality of first passivation patterns, each of the first passivation patterns being arranged on an upper surface of a corresponding semiconductor chip of a plurality of semiconductor chips disposed on the semiconductor substrate; as well as a second passivation pattern arranged on a scribe line of the semiconductor substrate to separate the semiconductor chips; wherein the second passivation pattern is spaced apart from each of the first passivation patterns to form a crack stopping groove between the second passivation pattern and each of the first passivation patterns, Each of the first passivation patterns covers an upper surface of the corresponding semiconductor chip, and a width of a bottom surface of each of the first passivation patterns is equal to a width of the corresponding semiconductor chip.

9. The passivation structure according to claim 8, wherein: The width of the second passivation pattern on each scribe line is smaller than the width of the scribe line.

10. The passivation structure according to claim 8, wherein: The scribe lane is configured to surround each of the plurality of semiconductor chips, and the second passivation pattern extends along the scribe lane.

11. The passivation structure according to claim 10, wherein: Each of the semiconductor chips has a rectangular shape, and the second passivation pattern extends along the scribe lanes and is configured to surround four side surfaces of each rectangular semiconductor chip.

12. The passivation structure according to claim 8, wherein: The crack-stopping groove has a lower width and an upper width greater than the lower width.

13. The passivation structure according to claim 12, wherein: The upper width gradually increases from the lower width.

14. The passivation structure according to claim 8, wherein: The crack preventing groove has a uniform width.

15. The passivation structure according to claim 8, wherein: The first passivation pattern and the second passivation pattern include photosensitive polyimide (PSPI).

16. A method for manufacturing a semiconductor device, comprising: providing a semiconductor substrate having scribe lines; forming a plurality of semiconductor chips on the upper surface of the semiconductor substrate; forming a plurality of first passivation patterns, each of the first passivation patterns being arranged on an upper surface of a corresponding semiconductor chip among the plurality of semiconductor chips; as well as forming a second passivation pattern disposed on an upper surface of the scribe line street, wherein the second passivation pattern is spaced apart from each of the first passivation patterns to form a crack stopping groove between the second passivation pattern and the first passivation pattern, Each of the first passivation patterns covers an upper surface of the corresponding semiconductor chip, and a width of a bottom surface of each of the first passivation patterns is equal to a width of the corresponding semiconductor chip.

17. The method according to claim 16, further comprising: At least one test element group (TEG) is provided, the TEG being arranged on an upper surface of at least one of the scribe lanes and being covered by the second passivation pattern.

18. The method according to claim 17, wherein: The TEG comprises: at least two test pads arranged on an upper surface of at least one of the scribe lanes; and A test line is connected between the at least two test pads.

19. The method according to claim 18, wherein: The test wire comprises copper.

20. The method according to claim 16, wherein: For each scribe line where the second passivation pattern is arranged, a width of the second passivation pattern is smaller than a width of the scribe line.

21. The method according to claim 16, wherein: The scribe lane is configured to surround each of the plurality of semiconductor chips, and the second passivation pattern extends along the scribe lane.

22. The method according to claim 21, wherein: Each of the semiconductor chips has a rectangular shape, and the second passivation pattern extends along the scribe lanes and is configured to surround four side surfaces of each rectangular semiconductor chip.

23. The method according to claim 16, wherein: The crack-stopping groove has a lower width and an upper width greater than the lower width.

24. The method according to claim 23, wherein: The upper width gradually increases from the lower width.

25. The method of claim 16, wherein: The crack preventing groove has a uniform width.

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