Phase-locked loop sampler and reset

Abstract

Disclosed are systems, methods, and circuits for synchronizing a reference signal and an output signal of a phase-locked loop (PLL). The method includes continuously generating, by a clock detection circuit connected to the PLL, a clock detection signal indicating whether a reference signal of the PLL is present or missing. The method also includes continuously sampling and storing a voltage from a loop filter of the PLL by a loop sampler circuit connected to the PLL when the reference signal is present. In addition, the method includes configuring a charge pump of the PLL to a high impedance state when the clock detection signal indicates that the reference signal is missing, thereby disabling the charge pump. In addition, the method includes supplying a voltage to the PLL to maintain the frequency of the output signal of the PLL when the reference signal is missing.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Provisional Patent Application No. 62 / 571,736, filed on October 12, 2017, which is hereby incorporated by reference in its entirety. Technical Field

[0003] According to one or more embodiments, the present disclosure relates generally to phase locked loops (PLLs), and more particularly, for example, to systems and methods for generating stable clock signals. Background Art

[0004] Phase-locked loops (PLLs) are used in a wide variety of electronic devices. In operation, a PLL generates an output clock signal that is phase-locked (i.e., synchronized) with a reference clock. If the PLL loses the reference clock, the output clock signal of the PLL that tracks the reference clock may decrease to zero (0) Hertz (Hz) or another low frequency. For many applications, it is desirable that the PLL generate a stable output clock signal even during a loss of the reference clock signal. Therefore, there remains a need to improve the stability of the PLL output clock signal during an unexpected loss of the reference clock signal. Summary of the invention

[0005] The present disclosure provides a method and system for improving the stability of a PLL output clock signal during an interruption or loss of a reference clock signal. In one or more embodiments, a method includes continuously generating a clock detection signal indicating whether a reference clock signal input to the PLL is present or lost by a clock detection circuit connected to the PLL. The method also includes continuously sampling and storing a control voltage from a loop filter of the PLL by a loop sampler circuit connected to the PLL when the reference clock signal exists. When the reference clock signal is lost, the method includes supplying the stored control voltage to the PLL to stabilize the output signal of the PLL. In one or more embodiments, the PLL includes a charge pump and the method includes disabling the charge pump, such as by configuring the charge pump to a high impedance state, when the clock detection signal indicates that the reference signal is lost.

[0006] In one or more embodiments, when the reference signal is present, a voltage is sampled from a capacitor of the loop filter and stored on a first capacitor of the loop sampler circuit; and when the clock detection signal indicates that the reference signal is missing, a voltage is supplied to the loop filter.

[0007] In one or more embodiments, when the reference signal is present, a voltage is sampled from the output of the loop filter and stored on a second capacitor of the loop sampler circuit; and when the reference signal is lost, the voltage is supplied to the input of the voltage controlled oscillator (VCO) of the PLL. In one or more embodiments, when the reference signal is present, a second voltage is sampled from the capacitor of the loop filter and stored on a first capacitor of the loop sampler circuit; and when the clock detection signal indicates that the reference signal is lost, the second voltage is supplied to the loop filter.

[0008] In one or more embodiments, the method further includes receiving a reference signal by a pulse generator circuit of the loop sampler circuit and generating a pulse indicating a sampling period for sampling the voltage. In at least one embodiment, the pulse generator circuit samples a falling edge of the reference signal, and a phase-frequency detector of the PLL aligns the reference signal with a phase of a rising edge of a feedback signal of the PLL. The pulse successively opens and closes a switch of the loop sampler circuit to sample the voltage, which is stored on a capacitor of the loop sampler circuit.

[0009] In at least one embodiment, the method further comprises continuously detecting, by the clock detection circuit, the reference signal; and generating, by the clock detection circuit, a clock detection signal indicating a loss of the reference signal after a predetermined amount of time when the reference signal is not detected. In one or more embodiments, the voltage is supplied to the PLL via a voltage buffer of the loop sampler circuit.

[0010] In one or more embodiments, a system includes a phase-locked loop (PLL), a clock detection circuit, and a loop sampler circuit, wherein the phase-locked loop (PLL) is operable to synchronize a reference signal and an output signal. The clock detection circuit is connected to the PLL and is operable to generate a clock detection signal indicating whether a reference signal of the PLL is present or missing. The loop sampler circuit is connected to the PLL and the clock detection circuit and is operable to sample and store a voltage from a loop filter of the PLL when a reference signal is present. In one or more embodiments, when the reference signal is lost, the charge pump of the PLL is disabled, and the stored voltage is supplied to the PLL to maintain a stable PLL output signal.

[0011] The scope of the present disclosure is defined by the claims, which are incorporated into this section by reference. A more complete understanding of the present disclosure and the realization of its additional advantages will be given to those skilled in the art by considering the following detailed description of one or more embodiments. Reference will be made to the attached sheets of the accompanying drawings, which will first be briefly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Various aspects of the present disclosure and its advantages may be better understood with reference to the following drawings and the detailed description that follows. It should be appreciated that the same reference numerals are used to identify the same elements illustrated in one or more of the drawings, wherein the illustrations in the drawings are for the purpose of illustrating embodiments of the present disclosure, and not for the purpose of limiting the embodiments of the present disclosure. The components in the drawings are not necessarily to scale, but emphasis is placed on clearly illustrating the principles of the present disclosure.

[0013] Figure 1 is a diagram illustrating a first exemplary PLL and clock resetter circuit according to one or more embodiments of the present disclosure.

[0014] Figure 2 is a diagram illustrating a second exemplary PLL and clock resetter circuit according to one or more embodiments of the present disclosure.

[0015] Figure 3 is a diagram illustrating an exemplary pulse generator circuit according to one or more embodiments of the present disclosure.

[0016] Figure 4 is a diagram illustrating one or more embodiments of the present disclosure Figure 1 A flow chart of an exemplary operation of the PLL and clock resetter circuit.

[0017] Figure 5 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 A flow chart of an exemplary operation of the PLL and clock resetter circuit.

[0018] Figure 6 is a graph illustrating exemplary measured control voltages during operation of various PLL and clock resetter circuits according to one or more embodiments of the present disclosure.

[0019] Figure 7 is a graph illustrating exemplary responses to a loss of a reference clock signal by various PLL and clock restorer circuits according to one or more embodiments of the present disclosure.

[0020] Figure 8 is a diagram illustrating an exemplary implementation of a PLL and a clock resetter circuit in an audio processing device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0021] Disclosed herein are systems and methods for improving the stability of a phase-locked loop (PLL) circuit during an unexpected loss of a reference clock input. In various embodiments, the disclosed systems and methods allow a PLL to respond gracefully to an unexpected loss of a reference clock to maintain a stable output.

[0022] PLLs are used in a variety of systems (e.g., very large scale integration (VLSI) chips) to generate one or more high frequency master clock signals. In various embodiments, the PLL receives a reference clock signal and generates one or more output signals, such as a higher frequency output clock signal. The reference clock signal input to the PLL may stop and be restarted by an external clock source without warning, which may adversely affect the operation of one or more system components. When the reference clock signal input to the PLL is lost, the output clock signal of the PLL that tracks the reference clock signal will also be lost because the output decreases toward zero (0) Hertz (Hz) or another low frequency. The systems and methods disclosed herein allow the PLL to respond gracefully and maintain a stable output signal during the loss of the reference clock signal.

[0023] According to various embodiments of the present disclosure, a PLL and clock reset circuit includes a PLL, a clock detection circuit, and a loop sampler circuit. During operation of the PLL, the loop sampler circuit samples and stores a control voltage of the PLL. When a reference clock is lost, the circuit of the present disclosure utilizes the stored control voltage to maintain a relatively stable output frequency until the reference clock signal is restored.

[0024] Figure 1 1 is a diagram illustrating a first exemplary PLL and clock resetter circuit 100 according to one or more embodiments of the present disclosure. In the illustrated embodiment, the PLL and clock resetter circuit 100 includes a PLL 102, a clock detection circuit 110, and a loop sampler circuit 180. The PLL 102 includes a phase detector 130, a charge pump 140, a loop filter 150 (e.g., a loop filter circuit), a voltage controlled oscillator (VCO) 160, and a frequency divider 164. The phase detector 130 is coupled to a reference clock 104, which provides a reference signal 106 that is input to the phase detector 130. The phase detector 130 is also arranged to receive a feedback signal 166. In one or more embodiments, the VCO 160 generates an output signal 162, which is input to the frequency divider 164 to generate the feedback signal 166. In one embodiment, the frequency divider 164 is a one-to-N divide-by-counter that divides the frequency of the output signal 162 by a number N to produce the feedback signal 166. For example, if the output signal 162 has a frequency of 160 megahertz (MHz) and the one-to-N divide-by-N counter has N equal to 16, the feedback signal 166 will have a frequency of 10 MHz.

[0025] In one embodiment, the phase detector 130 is a phase-frequency detector operable to compare the phase and frequency of the reference signal 106 and the feedback signal 166, and output a control signal to accordingly adjust the feedback signal 166 to have a phase and frequency that are synchronized with the phase and frequency of the reference signal 106. For example, in various embodiments, the phase detector 130 aligns the phases of the rising edges of the reference signal 106 and the feedback signal 166 by generating a control signal to adjust the feedback signal 166.

[0026] The control signal generated by the phase detector 130 is output to the charge pump 140. In various embodiments, the phase detector 130 generates an "up" voltage signal 131 that is input to the charge pump 140 and passes through the loop filter 150 to increase the voltage and frequency of the VCO 160, and generates a "down" voltage signal 132 that is input to the charge pump 140 and passes through the loop filter 150 to decrease the voltage and frequency of the VCO 160. The VCO 160 generates an output signal 162 that may be provided to one or more electronic components (not shown) as a PLL output clock signal 170.

[0027] The PLL 102 operates as a feedback loop to lock the phase and frequency of the output signal 162 to the phase and frequency of the reference signal 106. When the reference signal 106 is lost (e.g., if the reference clock 104 is not operating), the PLL 102 output signal 162 will adjust toward the value maintained at the reference input to the phase detector 130, which may have a frequency of 0 Hz (or another low frequency value), until the reference signal 106 is restored. In various embodiments disclosed herein, the clock detection circuit 110 and the loop sampler circuit 180 operate to generate a consistent output signal 162 from the PLL 102 even during periods when the reference clock signal 106 is lost.

[0028] The clock detection circuit 110 is operable to detect whether the reference signal 106 is present or missing and output a corresponding clock detection signal 112. In the illustrated embodiment, the clock detection circuit 110 is coupled to the reference clock 104 to receive the reference signal 106 input to the phase detector 130. The clock detection circuit 110 detects the presence or absence of the reference signal 106 and outputs a corresponding clock detection signal (clk_detect) 112. In one embodiment, the clock detection signal 112 is a flag set to 1 if the reference clock signal 106 is detected by the clock detection circuit 110, and is a flag set to 0 if the reference clock signal 106 is determined to be missing by the clock detection circuit 110. The output of the clock detection circuit 110 is coupled to the charge pump 140 of the PLL 102 and the buffer switch 192 of the loop sampler circuit 180, which is operable in response to the clock detection signal 112.

[0029] When the reference signal 106 is lost, the loop sampler circuit 180 is operable to sample the control voltage from the PLL 102 and provide the sampled voltage to the PLL 102 to drive the VCO 160. In the illustrated embodiment, the loop sampler circuit 180 includes a pulse generator 182, a control voltage switch 186 (also referred to herein as a sampling switch), a control voltage capacitor 188 connected to ground, a control voltage buffer 190 (e.g., a buffer amplifier), and a buffer switch 192. The buffer switch 192 is coupled between the control voltage buffer 190 and a capacitor (C) of the loop filter 150 and is controlled by the clock detection signal 112. In various embodiments, the buffer switch is controlled based on the detection state of the reference signal, such that the buffer switch is open when the clock detection signal is set to 1 (determining that the reference signal 106 is present), and the buffer switch is closed when the clock detection signal is set to 0 (determining that the reference signal 106 is lost).

[0030] The pulse generator 182 is coupled to receive the reference signal 106 input to the PLL 102. In operation, the pulse generator 182 uses the reference signal 106 as an input to generate a sampling pulse 184 (samp_clk) to control a control voltage switch 186. The control voltage switch 186 is coupled between the loop filter capacitor (C) and a control voltage capacitor 188 of the loop sampler circuit 180, and is successively opened and closed by the sampling pulse 184. When the control voltage switch 186 is closed, the control voltage (vcap) from the capacitor (C) within the loop filter 150 is sampled and stored on the control voltage capacitor 188.

[0031] In various embodiments, the pulse generator 182 generates a narrow sampled pulse from the falling edge of the reference signal 106. As previously discussed, the phase detector 130 of the illustrated embodiment is operable to align the phases of the rising edges of the reference signal 106 and the feedback signal 166. Thus, in these embodiments, the control voltage (vcap) is sampled on the falling edge of the reference signal 106 to limit interference with the operation of the PLL 102.

[0032] During operation of the PLL and clock resetter circuit 100, a reference signal 106 from a reference clock 104 is input to the clock detection circuit 110 and the pulse generator 182. When the reference signal 106 is present, the clock detection circuit 110 sets the clock detection signal 112 to indicate that the reference signal 106 is present (e.g., clk_detect=1). The clock detection signal 112 is output to the charge pump 140 and the buffer switch 192. The charge pump 140 receives the clock detection signal 112 and remains operational when the clock detection signal 112 indicates that the reference signal 106 is present. The buffer switch 192 is controlled by the clock detection signal 112 and remains open when the clock detection signal 112 indicates that the reference signal 106 is present. Thus, when reference signal 106 is present, PLL 102 operates to generate a PLL output clock signal 170 having a phase and frequency synchronized with the phase and frequency of reference signal 106 , and loop sampler circuit 180 samples a control voltage (vcap) from a capacitor (C) of loop filter 150 on a falling edge of reference signal 106 .

[0033] If the reference signal 106 is lost (e.g., if the reference clock 104 is not running), the clock detection circuit 110 changes the clock detection signal 112 to indicate that the reference signal 106 is lost (e.g., sets clk_detect=0). In various embodiments, the clock detection circuit 110 is operable to determine that the reference signal 106 is lost if the reference signal 106 is not detected at the clock detection circuit 110 for a predetermined time interval. In these embodiments, this "delay period" may be a short period that is set to minimize false "missing signal" triggers (e.g., due to jitter in the valid signal) and is based on other system requirements. In one embodiment, when the reference signal 106 is detected by the clock detection circuit 110, the clock detection circuit 110 is operable to change the clock detection signal to "1" without delay.

[0034] When the clock detection circuit 110 determines that the reference signal 106 has been lost, the charge pump 140 is disabled by the clk_detect signal 112. For example, in one or more embodiments, when the clk_detect signal 112 is set to 1, the charge pump 140 is operational, and when it receives the clk_detect signal 112 set to 0, the charge pump 140 enters a high impedance (Hi-Z) state, thereby disabling the charge pump 140.

[0035] The clock detect signal 112 is also provided to the loop sampler circuit 180 to control the buffer switch 192. When the clk_detect signal 112 is set to 1 (indicating that the reference signal 106 is present), the buffer switch 192 is maintained in the open position. When the clk_detect signal 112 is set to 0 (indicating that the reference signal 106 has been lost), the buffer switch 192 is closed, thereby coupling the control voltage capacitor 188 and the control voltage buffer 190 to the capacitor (C) of the loop filter 150. Because the reference signal 106 has been lost, the pulse generator 182 no longer receives an input signal and will no longer generate sampling pulses 184 to drive the control voltage switch 186. Therefore, the control voltage switch 186 remains open and the sampling of the control voltage (Vcap) stops. The control voltage (Vcap) stored on the control voltage capacitor 188 is coupled to the loop filter 150 (through the control voltage buffer 190 and the buffer switch 192) to charge the capacitor (C) to the last sampled control voltage. Thus, capacitor (C) is operable to drive VCO 160, thereby allowing output signal 162 to remain relatively stable even if reference signal 106 has been lost. When reference signal 106 is restored, pulse generator 182 will generate sampling clock signal 284, and sampling will continue through switches 286 and 294.

[0036] In various embodiments, the PLL and clock resetter circuit 100 may be configured between two or more operating modes. For example, the PLL and clock resetter circuit 100 may be operated in a standard PLL mode by disabling the clock detection circuit 110 (e.g., setting the clock detection signal 112 to output “1” even if the reference clock signal is missing) and, optionally, disabling sampling by the control voltage switch 186 and the control voltage capacitor 188 by disabling the pulse generator 182.

[0037] Figure 2 2 is a diagram illustrating a second exemplary PLL and clock reset circuit 200 according to one or more embodiments of the present disclosure. As illustrated, the PLL and clock reset circuit 200 may include a PLL circuit such as reference Figure 1 The PLL 102 is depicted, which includes a phase detector 130, a charge pump 140, a loop filter 150, and a VCO 160 coupled to the reference clock 104 to receive the reference signal 106. A clock detection circuit 210 is coupled to the reference clock 104 to receive the reference signal 106 and generates a clk_detect signal 212 indicating whether the reference signal 106 is "present" or has been determined to be "missing".

[0038] The loop sampler circuit 280 includes a pulse generator circuit 282, a first control voltage switch 286, a first control voltage capacitor 288, a first voltage buffer 290, a buffer switch 292, a second control voltage switch 294, a second control voltage capacitor 296, and a second voltage buffer 298. In operation of the PLL 102, the clock detection circuit 210 receives the reference signal 106 and generates a clock detection signal 212 (clk_detect) indicating the presence of the reference signal 106. The clock detection signal 212 is sent to the charge pump 140, which is maintained in the normal operating mode, and to the buffer switch 292, which remains open.

[0039] The pulse generator circuit 282 receives the reference signal 106 from the reference clock 104 and generates a narrow sampling pulse from the falling edge of the reference signal 106 to produce a sampling clock signal 284 (samp_clk). In one or more embodiments, the phase detector 130 aligns the phases of the reference signal 106 and the rising edge of the feedback signal 166. By sampling on the falling edge of the reference signal 106, the pulse generator circuit 282 limits the interference of the operation of the PLL 102. The sampling clock signal 284 controls the successive opening and closing of the first control voltage switch 286 and the second control voltage switch 294 during the operation of the PLL 102. During the switching of the first control voltage switch 286, the control voltage (vcap) of the capacitor (C) of the loop filter 150 is sampled and stored on the first control voltage capacitor 288. During the switching of the second control voltage switch 294, the control voltage (vctrl) output from the loop filter 150 for input to the VCO 160 is sampled and stored on the second control voltage capacitor 296.

[0040] When the reference signal 106 is lost, the clock detection circuit 210 first detects that no signal is received, and then monitors the input signal during a predetermined time interval to confirm that the signal has been lost (e.g., to confirm that the detected signal loss is not the result of jitter). After the predetermined time interval, if the reference signal 106 is still lost, the clock detection circuit 210 sets the clock detection signal 212 to 0 to indicate that the reference signal has been lost. The clock detection signal 212 is sent to the charge pump 140 to configure the charge pump 140 to a high impedance (Hi-Z) state, thereby disabling the charge pump 140. The clock detection signal 212 is also sent to the buffer switch 292 to close the buffer switch 292 until the clock detection signal is changed to indicate that the reference signal 106 is present. In one embodiment, when the reference signal 106 is detected by the clock detection circuit 210, the clock detection circuit 210 is operable to change the clock detection signal to "1" without delay.

[0041] When the reference signal 106 is lost, the pulse generator circuit 282 no longer receives an input signal, and therefore no longer generates the sampling clock signal 284. Therefore, both the first control voltage switch 286 and the second control voltage switch 294 remain open. The control voltage (vctrl) stored on the second control voltage capacitor 296 is input to the VCO 160 through the second voltage buffer 298, thereby allowing the output signal 162 to remain relatively stable when the reference signal 106 is lost. In addition, the closed buffer switch 292 couples the control voltage (vcap) stored on the first control voltage capacitor 288 to the capacitor (C) of the loop filter 150 to maintain the charge at the previous control voltage (vcap) level, thereby allowing the PLL 102 to maintain operation when the reference signal 106 is present again.

[0042] In various embodiments, the PLL and clock resetter circuit 200 may be configured between two or more operating modes. For example, the PLL and clock resetter circuit 200 may be configured between two or more operating modes by disabling the clock detection circuit 210 (e.g., setting the clock detection signal 212 to output "1" even if the reference clock signal is lost) and, optionally, by disabling the pulse generator circuit 282 by disabling sampling by switches 186 and 294 and capacitors 288 and 296, respectively. The PLL and clock resetter circuit 200 may also be configured to operate in accordance with the standard PLL mode by disabling sampling of the control voltage (vctrl) during operation and closing the second control voltage switch 294. Figure 1 The embodiment of the present invention is operated.

[0043] Figure 3 is a diagram illustrating an exemplary pulse generator circuit 300 according to one or more embodiments of the present disclosure. The pulse generator circuit 300 may be implemented as Figure 1 The pulse generator 182 in the embodiment of Figure 2 The pulse generator circuit 282 in the embodiment of the present invention may be implemented in other embodiments. As shown, the pulse generator circuit 300 includes a logic delay 330, an inverter 340, and a "NOR" gate 350. During operation, the reference clock 104 ( Figure 3 The reference signal input 106 (ref_clk) (not shown) is input to the pulse generator circuit 300. As shown in the clock diagram 360, the pulse generator circuit 300 is operable to generate a narrow sampling pulse from the falling edge of the reference signal 106 to produce a sampling clock signal 320 (samp_clk) that in many embodiments allows the PLL control voltage(s) to be sampled without interfering with the operation of the PLL.

[0044] Figure 4 is a diagram illustrating one or more embodiments of the present disclosure Figure 1 4. A flow chart of an exemplary operation 400 of a PLL and a clock resetter circuit of a PLL. During operation of the PLL to generate an output clock signal, in step 405, a clock detection circuit coupled to a reference signal determines whether the reference signal is lost. If the clock detection circuit determines that the reference signal is present, then in step 415, the clock detection circuit generates a clock detection signal indicating the presence of the reference signal. In step 420, the loop sampler circuit continuously samples the control voltage from the PLL and stores the sampled voltage in step 425. Steps 415, 420, and 425 are continuously performed until it is determined in step 405 that the reference signal is lost.

[0045] If the clock detection circuit determines that the reference signal is lost (step 405), then in step 435, the clock detection circuit generates a clock detection signal indicating that the reference clock is lost. In step 440, the charge pump of the PLL is disabled, such as by configuring the charge pump to enter a high impedance state. In step 445, the stored voltage is supplied to the loop filter of the PLL to maintain the frequency of the output signal of the PLL. In step 460, the clock detection circuit determines whether the reference signal is present. When the reference signal is lost, the stored voltage is supplied to the loop filter. When the reference signal is detected by the clock detection circuit, in step 415, the clock detection signal is changed to indicate that the reference clock is present.

[0046] Figure 5 is a diagram illustrating one or more embodiments of the present disclosure Figure 2 Flowchart of an exemplary operation 500 of a PLL and a clock resetter circuit of a PLL. During operation of the PLL to generate a stable output clock signal, in step 505, a clock detection circuit coupled to a reference signal determines whether the reference signal is lost. If the clock detection circuit determines that the reference signal is not lost, then in step 515, the clock detection circuit generates a clock detection signal indicating the presence of a reference clock. In step 520, a loop sampler circuit connected to the PLL continuously samples a first control voltage from a loop filter of the PLL. Then in step 525, the loop sampler circuit stores the first control voltage. In step 530, the loop sampler circuit continuously samples a second control voltage from the output of the loop filter. Then in step 535, the loop sampler circuit stores the second voltage, and the method repeats to step 505. Steps 515, 520, 525, 530, and 535 are performed continuously until it is determined in step 505 that the reference signal is lost.

[0047] If the clock detection circuit determines that the reference signal is lost (step 505), then in step 545, the clock detection circuit generates a clock detection signal indicating that the reference signal is lost. In step 550, the charge pump of the PLL is maintained in a disabled state, such as by entering a high impedance state. In step 555, a first control voltage is supplied to a loop filter of the PLL. In step 560, a second control voltage is supplied to a voltage controlled oscillator of the PLL to maintain the frequency of the output signal of the PLL. When the reference signal is detected again by the clock detection circuit (step 575), in step 515, the clock detection signal is changed to indicate that the reference clock is present.

[0048] Figure 6 6 is a graph 600 illustrating an exemplary measured control voltage during operation of various PLL and clock reset circuits according to one or more embodiments of the present disclosure. A measured control voltage (vctrl) 610, a sampled control voltage 620 stored by a loop sampler circuit, an exemplary reference clock pulse 630, and an exemplary sampled clock pulse 640 generated by a pulse generator circuit of the loop sampler circuit are illustrated. As illustrated, the reference clock pulse 630 is sampled on its falling edge to produce the sampled clock pulse 640. The figure also shows that the loop sampler circuit samples and stores the control voltage 610 on each pulse until the next sampled clock pulse to produce the sampled control voltage 620.

[0049] Figure 7 7 is a graph 700 illustrating an exemplary response to a loss in a reference signal by various PLL and clock restorer circuits according to one or more embodiments of the present disclosure. As illustrated, the graph shows that during a loss of a reference clock signal 740 generated by a reference clock 750, the frequency of the output signal for the PLL 710 drops and remains low frequency until the reference clock signal 740 is restored. Figure 1 The output voltage of the PLL and clock recovery circuit is represented by curve 720. When the reference clock signal 740 is lost, the output frequency drops until the clock detection circuit determines that the signal is lost. After the clock detection signal is set to indicate that the reference signal is lost, after a predetermined time delay has elapsed, the output signal recovers to the previous frequency and remains relatively stable. Figure 2 The output frequency of the PLL and clock recovery circuit is represented by curve 730. In this embodiment, the frequency remains relatively stable throughout the duration of the loss of the reference clock signal 740.

[0050] Figure 8800 is a diagram illustrating an exemplary system on a chip (SOC) that may employ the disclosed PLL and clock resetter circuits according to at least one embodiment of the present disclosure. In the figure, the SOC is an audio device 800 for processing audio input and output signals that may be used in a variety of devices such as mobile phones, tablet computers, laptop computers, desktop computers, televisions, wearable devices, or other devices that perform audio input or output processing. The audio device 800 includes a PLL / clock resetter 810, such as Figure 1 or Figure 2 800 . The PLL / clock resetter 810 receives a reference clock (rclk) (which may be a master clock signal received from other components of the device) and outputs at least one output clock signal for timing and synchronization of various components of the audio device 800 (such as an audio circuit 820, a digital signal processor (DSP) 830, and a bus interface 840). The audio circuit 820 may include an audio input circuit (such as an anti-aliasing filter 822 and an analog-to-digital converter 824) for receiving and processing audio input signals from one or more sensors (such as a microphone 852). The audio circuit 820 may also include an audio output circuit (such as a digital audio converter 826) and a driver amplifier 828 for receiving a digital audio signal from the DSP 830 and driving one or more speakers 850. The DSP 830 may be a programmable DSP that is operable to perform digital signal processing functions of the audio device 800. The bus interface 840 communicates with other system components, such as a system computer processor of the system device. In many applications (such as voice over IP applications or applications that process voice commands), audio input / output processing may be performed in real time and may include communication with other devices through the bus interface 840. In such systems, the loss of a reference clock signal may affect the ability of the audio device 800 to perform necessary audio processing and communication (such as by causing the device to miss voice commands). Therefore, embodiments of the disclosed PLL / clock reset 810 allow for stable operation of the audio circuit 820, DSP 830, and bus interface 840 (e.g., even during loss of a reference signal).

[0051] In the illustrated embodiment, the audio device also includes control logic 812 for control and configuration of the PLL / clock resetter 810. In one embodiment, Figure 1 The PLL and clock reset circuit 100 can be configured to operate in multiple modes. For example, the PLL and clock reset circuit 100 can include a PLL mode and a clock reset mode. In one embodiment, the PLL mode can be selected by setting the clock detection signal to 1 and / or disengaging the sampling circuit. Figure 2In an embodiment of the present invention, it is contemplated that the PLL mode may be achieved by closing the second switch and disabling sampling. Figure 1 An embodiment can be achieved by closing Figure 2 The second switch but maintains Figure 1 These and other configurations can be implemented according to embodiments of the present disclosure.

[0052] Where applicable, hardware, software, or a combination of hardware and software may be used to implement the various embodiments provided by the present disclosure. In addition, where applicable, without departing from the scope of the present disclosure, the various hardware components and / or software components set forth herein may be combined into composite components comprising software, hardware, and / or both. Where applicable, without departing from the scope of the present disclosure, the various hardware components and / or software components set forth herein may be separated into subcomponents comprising software, hardware, or both. In addition, where applicable, it is envisioned that software components may be implemented as hardware components, and vice versa.

[0053] Software (such as program code and / or data) according to the present disclosure may be stored on one or more computer-readable media. It is also contemplated that the software identified herein may be implemented using one or more general or special-purpose computers and / or computer systems, networked and / or otherwise. Where applicable, the order of the various steps described herein may be changed, combined into composite steps, and / or separated into sub-steps to provide the features described herein.

[0054] The foregoing disclosure is not intended to limit the disclosure to the precise form disclosed or to the particular field of use. Therefore, it is contemplated that various alternative embodiments and / or modifications of the disclosure are possible in light of the present disclosure, whether explicitly described or implied herein. Having thus described embodiments of the disclosure, it will be appreciated by those of ordinary skill in the art that changes may be made in form and detail without departing from the scope of the disclosure. Therefore, the disclosure is limited only by the claims.

Claims

1. A method for improving the stability of an output signal, comprising: synchronizing an output signal of a phase-locked loop (PLL) circuit with a reference signal; Detecting a state of the reference signal and generating a corresponding clock detection signal; When the reference signal exists, sampling and storing the control voltage of the PLL; as well as supplying a stored control voltage to the PLL to stabilize the output signal when the clock detection signal indicates that the reference signal is lost, wherein the PLL circuit comprises a voltage controlled oscillator (VCO) and a loop filter circuit operable to supply the control voltage to an input of the VCO; wherein sampling and storing the control voltage of the PLL further comprises sampling the control voltage from an output of the loop filter and storing the sampled control voltage on a second capacitor of a loop sampler circuit; and Wherein supplying the control voltage to the PLL further comprises coupling the second capacitor of the loop sampler circuit to the input of the VCO.

2. The method of claim 1 , wherein the PLL circuit comprises a loop filter circuit, the loop filter circuit comprising a loop filter capacitor; wherein sampling and storing the control voltage of the PLL further comprises sampling the control voltage from the loop filter capacitor and storing the sampled control voltage on a first capacitor of a loop sampler circuit; and Wherein supplying the stored control voltage to the PLL further comprises coupling the loop filter capacitor to the first capacitor of the loop sampler circuit.

3. The method of claim 1 , wherein the loop filter circuit comprises a loop filter capacitor, and wherein sampling and storing the control voltage of the PLL further comprises sampling a loop filter capacitor voltage from the loop filter capacitor and storing the sampled loop filter capacitor voltage on a first capacitor of the loop sampler circuit; and Wherein supplying the control voltage to the PLL further comprises coupling the loop filter capacitor to the first capacitor of the loop sampler circuit.

4. The method of claim 3 , wherein synchronizing the output signal of the PLL circuit with the reference signal further comprises aligning rising edges of the reference signal and the output signal, and wherein sampling and storing the control voltage of the PLL when the reference signal is present further comprises receiving the reference signal at a pulse generator circuit and generating a sampling pulse aligned with a falling edge of the reference signal.

5. The method of claim 4 , wherein the loop sampler circuit further comprises a sampling switch coupled to receive the sampling pulse, the method further comprising successively opening and closing the sampling switch to sample the control voltage from the PLL, wherein the control voltage is sampled when the sampling switch is closed.

6. The method according to claim 1, wherein detecting the state of the reference signal and generating a corresponding clock detection signal further comprises: receiving the reference signal as an input to a clock detection circuit, the clock detection circuit being operable to output the clock detection signal indicative of the presence of the reference signal; as well as An absence of the reference signal is detected at the input to the clock detection circuit for a predetermined time interval and the corresponding clock detection signal is output indicating that the reference signal is missing.

7. The method of claim 6, wherein supplying the stored control voltage to the PLL to stabilize the output signal when the clock detection signal indicates that the reference signal is lost further comprises: A switch of a loop sampler circuit is controlled using the clock detection signal, wherein the switch is opened when the corresponding clock detection signal is present, and wherein the switch is closed when the corresponding clock detection signal is missing.

8. The method of claim 7, wherein the control voltage is supplied to the PLL via a voltage buffer of the loop sampler circuit.

9. The method of claim 6, wherein the PLL circuit comprises a charge pump coupled to the clock detection circuit to receive the clock detection signal, the method further comprising disabling the charge pump when the clock detection signal indicates that the reference signal is missing.

10. A system for improving the stability of an output signal, comprising: a phase-locked loop (PLL) operable to synchronize a reference signal with an output signal; a clock detection circuit coupled to receive the reference signal and operable to generate a clock detection signal indicating whether the reference signal of the PLL is present or missing; as well as a loop sampler circuit connected to the PLL, wherein the loop sampler circuit is operable to sample and store a control voltage from a loop filter of the PLL when the reference signal is present; as well as wherein when the reference signal is lost, a stored control voltage is supplied to the PLL to stabilize the output signal of the PLL until the reference signal exists, wherein when the reference signal is present, the voltage is sampled from the output of the loop filter and stored on a second capacitor of the loop sampler circuit; as well as Wherein when the reference signal is lost, the voltage is supplied to the input of a voltage controlled oscillator (VCO) of the PLL.

11. The system of claim 10, wherein when the reference signal is present, the voltage is sampled from a capacitor of the loop filter and stored on a first capacitor of the loop sampler circuit; and Wherein when the clock detection signal indicates that the reference signal is lost, the voltage is supplied to the loop filter.

12. The system of claim 10, wherein when the reference signal is present, a second voltage is sampled from a capacitor of the loop filter and stored on a first capacitor of the loop sampler circuit; and Wherein when the clock detection signal indicates that the reference signal is lost, the second voltage is supplied to the loop filter.

13. The system of claim 10, wherein a pulse generator circuit of the loop sampler circuit is operable to receive the reference signal and to sample the reference signal to generate a pulse indicative of a sampling period for the sampling of the voltage.

14. The system of claim 13, wherein the pulse generator circuit is operable to sample a falling edge of the reference signal, and The phase-frequency detector of the PLL is operable to align the phases of the reference signal and the rising edges of the feedback signal of the PLL.

15. The system of claim 13, wherein a switch of the loop sampler circuit is operable to sample the voltage by successively opening and closing according to the pulse.

16. The system of claim 10, wherein the voltage is stored on a capacitor of the loop sampler circuit.

17. The system of claim 10, wherein the clock detection circuit is operable to continuously detect a reference signal; and The clock detection circuit is operable to generate the clock detection signal indicating a loss of the reference signal a predetermined amount of time after the clock detection circuit no longer detects the reference signal.

18. The system of claim 10, wherein the PLL further comprises a charge pump arranged to receive the clock detection signal, wherein the charge pump is operable when the clock detection signal indicates that the reference signal is present, and wherein the charge pump is disabled when the clock detection signal indicates that the reference signal is missing.

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