Decimal frequency division all-digital phase-locked loop based on DTC and edge time domain compensation algorithm

Abstract

The invention relates to a fractional frequency division all-digital phase-locked loop based on a DTC and an edge time domain compensation algorithm, and belongs to the field of radio frequency integrated circuit design. The whole circuit structure comprises a time-to-digital converter (TDC), a digital loop filter (DLF), a digital controlled oscillator (DCO), a programmable frequency divider (MMD), a Sigma-delta modulator and a digital-to-digital converter (DTC). A fractional frequency division function is realized by combining a programmable frequency divider MMD, a Sigma-delta modulator and a digital time converter DTC, a quantization noise optimization circuit is designed mainly by adopting a time domain compensation method, a low fractional spurious effect is realized by combining the DTC, and then signals of fractional frequency division are output and integrated in a phase-locked loop. In a phase-locked loop, a signal output by a Sigma-delta modulator is integrated with a frequency division signal, then a DTC performs time domain compensation according to the signal output by the Sigma-delta modulator, and then transmits the signal to a TDC for phase comparison with a reference signal to control the frequency output of a DCO, so that the high-performance all-digital phase-locked loop circuit with low decimal stray is realized.

Description

Technical Field

[0001] The invention belongs to the field of radio frequency integrated circuit design, and relates to a fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm. Background Art

[0002] Phase-locked loop (PLL) is a frequency synthesizer, which is mainly a negative feedback control system that can generate the target frequency. In high-performance system-on-chip (SoC), phase-locked loop plays an important role in clock generation, distribution and synchronization. With the development of integrated circuits and the demand for higher clock frequency accuracy and higher performance inside the chip, fractional frequency phase-locked loops with high frequency resolution phase-locked synthesis and good noise characteristics have become the mainstream technical means in the market. In addition, the phase-locked loops implemented by analog circuits in the early days are not conducive to integration as the process is refined. Therefore, digital phase-locked loops have received widespread attention in recent years. Among them, the all-digital phase-locked loop (ADPLL) is a closed-loop feedback system, and the control signals between each module are digital signals, which improves the circuit integration, locking speed and portability, and reduces the cost of the circuit. At the same time, the low phase noise, low spurious local oscillator or low jitter clock signal provided by ADPLL has an important impact on the sensitivity of the system.

[0003] In order to achieve fast locking and break through the limitations of integer-division all-digital phase-locked loops in frequency modulation resolution and loop bandwidth, fractional-division all-digital phase-locked loops based on ΔΣ modulators have been widely used. They achieve fractional frequency division of the input signal by periodic averaging, thereby improving the flexibility of the reference signal and the divider. However, due to the quantization error of the instantaneous integer division ratio, this frequency division method introduces a large amount of quantization noise into the system, resulting in a decrease in the purity of the output spectrum, which limits its application in high-precision applications.

[0004] In response to the noise problem introduced by quantization error in the fractional frequency division structure, the main focus of the present invention is to use DTC combined with an edge time domain compensation algorithm to eliminate the influence of quantization noise on the circuit, and to design a digital circuit with high resolution, simple structure and the ability to suppress quantization noise to achieve the effect of low fractional spurious. Summary of the invention

[0005] In view of this, an object of the present invention is to provide a fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm, comprising:

[0008] A time-to-digital converter TDC, used for converting the phase difference between the input signal and the feedback signal into a digital signal;

[0009] The digital loop filter DLF is used to filter out high-frequency components and noise in the digital signal and generate a digital control signal proportional to the phase difference;

[0010] A digitally controlled oscillator DCO, used to change the frequency of an output signal according to a digital control signal;

[0011] A programmable frequency divider MMD, used for dividing the output signal of the DCO into a low frequency range of the reference clock;

[0012] The digital time converter DTC is used to perform time domain compensation on the divided signal according to the output signal of the MMD to eliminate quantization noise.

[0013] The MMD using ΔΣ modulator for fractional frequency division is combined with the DTC structure based on the adjacent edge interpolation time domain compensation algorithm to eliminate the quantization noise generated by fractional frequency division, achieving the effect of ultra-low fractional spurious. The workflow of the entire circuit is that the system continuously compares the phase of the input signal ref and the feedback signal f_out, and digitizes the phase difference between the two through TDC to detect the phase error between the two. Subsequently, TDC transmits the digital output signal to DLF to filter out high-frequency components and noise, and generates a digital control signal proportional to the phase difference between the two, which is used as the input of DCO to change the output frequency of the digitally controlled oscillator. In order to improve the effective frequency accuracy of the digitally controlled oscillator, there is another ΔΣ modulator in the digitally controlled oscillator. Then, the output signal of DCO is fed back to the divider to divide it into the low frequency range of the reference clock. According to the change of the control word of the ΔΣ modulator to adjust the fractional frequency division, the DTC is adjusted to change the phase of the divider output signal to reduce the quantization error of the feedback signal, so that the phase error between ref and f_out is continuously reduced, that is, the digital value of the phase difference output by TDC is 0. When the ADPLL system enters the locked state, it will generate an output signal f_out with a frequency of (N+.F)×ref, where N is the integer bit of the division ratio and F is the fractional bit of the division ratio. When the ADPLL loop is locked, the output signal frequency will be strictly synchronized with the input signal frequency, and it also has frequency tracking characteristics. Among them, the fractional frequency division function is completed by the ΔΣ modulator dynamically controlling the MMD for periodic averaging. The MMD for fractional frequency division using the ΔΣ modulator is combined with the DTC structure based on the adjacent edge interpolation time domain compensation algorithm to eliminate the quantization noise generated by the fractional frequency division, achieving ultra-low fractional spurious effects and precise frequency synchronization and tracking.

[0014] Furthermore, the digital-to-time converter DTC is placed in the feedback path to timely offset the frequency division jitter introduced by the quantization noise, and realize a fractional frequency division signal with low fractional spurious and stable output frequency. In fractional frequency division, the ΔΣ modulator can output a specific frequency division ratio based on the externally input fractional frequency division value and the quantization result. Due to error accumulation and quantization step size limitations, the instantaneous integer frequency division result output by the ΔΣ modulator still has a fixed error with the target frequency. When DTC is used to perform time domain compensation for different quantization errors in different periods, the quantization error can be effectively reduced or even completely eliminated in theory, so that the standard deviation of the quantization result is reduced and closer to the target frequency division output value, that is, the quantization error is reduced through time domain compensation.

[0015] Furthermore, the delay compensation control algorithm is based on adjacent edge difference compensation, delays each rising edge of Tdiv, and calculates the difference between the delays of two adjacent rising edges to obtain the required positive or negative delay. In theory, if Tdiv is compensated as a reference period through DTC, each divided signal needs to be delayed.

[0016] Furthermore, the delay compensation has no negative value. According to the actual DTC circuit, a reference delay value of 198ps is selected, and the delay amount to be compensated for each cycle is calculated accordingly. Based on the above method, the difference between the rising edges of adjacent cycles is used to achieve the corresponding delay compensation, thereby effectively reducing the quantization noise.

[0017] Furthermore, the DTC structure is generally a single-ended structure, and a combination of coarse quantization and fine quantization delay control is used to achieve a more accurate delay selection. The coarse quantization stage uses a tuned RC network, and the fine quantization stage uses an NOR gate network without output connection to achieve the delay control function. The output of the frequency divider is transmitted to the DTC, and the input buffer is used to convert it into a square wave signal. The DTC changes the delay amount T in the time domain through a digital control code. delay Set it according to the following formula:

[0018] T delay =DCW·Δt

[0019] Among them, DCW is the delay control word, and Δt is the delay resolution.

[0020] Furthermore, the DLF structure organically combines the characteristics of proportional-integral control and low-pass filtering, uses the fast response and integral effect of the proportional-integral filter to achieve precise adjustment of the input signal, and uses the smoothing of the low-pass filter to reduce the interference of high-frequency noise to achieve stable output. The proportional-integral loop controller adjusts different proportions under the feedback of different phase differences and the lead-lag relationship of the signal to quickly lock the vibration frequency of the DCO.

[0021] The beneficial effects of the present invention are:

[0022] 1. The delay compensation control algorithm is used to compensate for the difference between adjacent edges of the feedback signal to eliminate the quantization noise caused by the fractional divider, achieving the effect of low fractional spurious;

[0023] 2. An improved DLF is adopted, which organically combines the characteristics of the proportional-integral filter and the low-pass filter. The proportional-integral loop controller adjusts different proportions under the feedback of different phase differences and the lead-lag relationship of the signal to quickly lock the vibration frequency of the DCO, improve the locking speed and achieve noise suppression.

[0024] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0026] Figure 1 It is a schematic diagram of the basic framework of an I-type structure all-digital phase-locked loop of a fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm in the embodiment;

[0027] Figure 2 It is a schematic diagram of the overall circuit framework of a fractional-frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm in the embodiment;

[0028] Figure 3 It is a DLF circuit implementation framework of a fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm in the embodiment;

[0029] Figure 4 It is a DTC actual circuit implementation diagram of a fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm in the embodiment;

[0030] Figure 5 Schematic diagram of a second-order ΔΣ modulator of a fractional-frequency fully digital phase-locked loop based on DTC and edge time domain compensation algorithm in an embodiment. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0032] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0033] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0034] Please refer to Figure 1 to Figure 5The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm adopts an I-type structure, and the loop includes: a time digital converter (TDC), a digital loop filter (DLF), a digitally controlled oscillator (DCO), a programmable frequency divider (MMD) and a digital time converter (DTC). The MMD using a ΔΣ modulator for fractional frequency division is combined with the DTC structure based on the adjacent edge interpolation time domain compensation algorithm to eliminate the quantization noise generated by the fractional frequency division, thereby achieving an ultra-low fractional spurious effect. The working process of the entire circuit is that the system continuously compares the phase of the input signal ref and the feedback signal f_out, and digitizes the phase difference between the two through the TDC to detect the phase error between the two. Subsequently, the TDC transmits the digital output signal to the DLF to filter out the high-frequency components and noise, and generates a digital control signal proportional to the phase difference between the two, which is used as the input of the DCO to change the output frequency of the digitally controlled oscillator. In order to improve the effective frequency accuracy of the digitally controlled oscillator, there is another ΔΣ modulator in the digitally controlled oscillator. Then, the output signal of DCO is fed back to the frequency divider so that it is divided into the low frequency range of the reference clock. According to the change of the control word of the ΔΣ modulator to adjust the fractional frequency division, the DTC is adjusted to change the phase of the frequency divider output signal to reduce the quantization error of the feedback signal, so that the phase error between ref and f_out is continuously reduced, that is, the phase difference digital value output by TDC is 0. When the ADPLL system enters the locked state, an output signal f_out with a frequency of (N+.F)×ref is generated, where N is the integer bit of the frequency division ratio and F is the fractional bit of the frequency division ratio. The fractional frequency division function of the entire system is mainly completed by the ΔΣ modulator dynamically controlling the frequency division ratio of the programmable frequency divider. When the ADPLL loop is locked, the output signal frequency will be strictly synchronized with the input signal frequency and have a frequency tracking characteristic. The digital time converter DTC is placed in the feedback path to timely offset the frequency division jitter introduced by the quantization noise, and realize a fractional frequency division signal with low fractional spurious and stable output frequency. In fractional frequency division, the ΔΣ modulator can output a specific frequency division ratio based on the fractional frequency division value input externally and the quantization result. Due to error accumulation and quantization step size limitations, the instantaneous integer division result output by the ΔΣ modulator still has a fixed error with the target frequency. When DTC is used to perform time domain compensation for different quantization errors in different periods, the quantization error can be effectively reduced or even completely eliminated in theory, so that the standard deviation of the quantization result is reduced and closer to the target division output value, that is, the quantization error is reduced through time domain compensation. The delay compensation control algorithm is based on adjacent edge difference compensation, and performs a delay operation on each rising edge of Tdiv. At the same time, the delay amount of two adjacent rising edges is calculated to obtain the required positive or negative delay amount. In theory, Tdiv is compensated as a reference period through DTC, and each divided signal needs to be delayed compensated.The delay compensation has no negative value. According to the actual DTC circuit, a reference delay value of 198ps is selected, and the delay amount that needs to be compensated for each cycle is calculated based on this. Based on the above method, the corresponding delay compensation is achieved by taking the difference between the rising edges of adjacent cycles, which is an effective reduction in quantization noise. The DTC structure is generally a single-ended structure, and a combination of coarse quantization level and fine quantization level delay control is used to achieve higher precision delay selection. Among them, the coarse quantization level uses a tuned RC network, and the fine quantization level uses an OR gate network with no output connection to realize the delay control function. The output of the divider is transmitted to the DTC, and an input buffer is used to convert it into a square wave signal. The DTC changes the delay amount T in the time domain through a digital control code. delay Set it according to the following formula:

[0035] T delay =DCW·Δt

[0036] Wherein, DCW is the delay control word, and Δt is the delay resolution. The DLF structure organically combines the characteristics of proportional integral control and low-pass filtering, uses the fast response and integral effect of the proportional integral filter to achieve precise adjustment of the input signal, and uses the smoothing processing of the low-pass filter to reduce the interference of high-frequency noise to achieve stable output. The proportional integral loop controller adjusts different proportions under the feedback of different phase differences and the lead-lag relationship of the signal to quickly lock the vibration frequency of the DCO.

[0037] Table 1 shows the output sequence results of the second-order ΔΣ modulator with an input division ratio of 20.25. It can be seen that when the input reference period is 16ns, the corresponding DTC instantaneous compensation time is obtained according to the adjacent edge time domain compensation algorithm, thereby achieving the purpose of reducing quantization noise.

[0038] Table 1

[0039]

[0040] It can be seen from the above that the present invention has the advantages of improving locking speed and noise suppression technology.

[0041] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm, characterized by: include: A time-to-digital converter TDC, used for converting the phase difference between the input signal and the feedback signal into a digital signal; The digital loop filter DLF is used to filter out high-frequency components and noise in the digital signal and generate a digital control signal proportional to the phase difference; A digitally controlled oscillator DCO, used to change the frequency of an output signal according to a digital control signal; A programmable frequency divider MMD, used for dividing the output signal of the DCO into a low frequency range of the reference clock; The digital time converter DTC is used to perform time domain compensation on the divided signal according to the output signal of the MMD to eliminate quantization noise.

2. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 1, characterized in that: The digital time converter DTC adopts a single-ended structure and includes a coarse quantization level and a fine quantization level delay control unit.

3. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 2, characterized in that: The coarse quantization level delay control unit uses a tuned RC network to implement a delay control function.

4. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 2, characterized in that: The fine quantization level delay control unit uses a NOR gate network without output connection to realize the delay control function.

5. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 1, characterized in that: The programmable frequency divider MMD comprises a ΔΣ modulator, which is used for outputting a specific frequency division ratio according to a fractional frequency division value input externally.

6. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 1, characterized in that: The input signal of the digital-to-time converter DTC is the output signal of the MMD.

7. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 1, characterized in that: The output signal of the digital-to-time converter DTC is used to perform time domain compensation on the output signal of the MMD to reduce the quantization error of the feedback signal.

8. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 1, characterized in that: The digital loop filter DLF includes a proportional-integral loop controller and a low-pass filter.

9. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 8, characterized in that: The proportional-integral loop controller is used to adjust different proportions according to the output signal of the TDC to lock the vibration frequency of the DCO.

10. The fractional frequency all-digital phase-locked loop based on DTC and edge time domain compensation algorithm according to claim 8, characterized in that: The low-pass filter is used to smooth the output signal of the TDC to reduce the interference of high-frequency noise.

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