Through silicon via detection circuit and method, integrated circuit
By designing a through-silicon detection circuit including input module and comparison module, the problem of through-silicon fault detection in 3D integrated circuits is solved, effective detection of through-silicon connectivity is achieved, and the reliability of the chip is improved.
Patent Information
- Application Number
- CN201811367326.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2018-11-16
- Publication Date
- 2025-04-04
- Estimated Expiration
- 2038-11-16
AI Technical Summary
Through-silicon holes in 3D integrated circuits are prone to failure during the manufacturing and binding process, affecting chip performance, and it is difficult for the prior art to effectively detect the connectivity of through-silicon holes.
A through-silicon detection circuit is designed, including an input module and a comparison module. The first switching unit is controlled to be turned on through the first detection control signal, and the first power supply signal is transmitted to the through-silicon hole. The comparison module compares the signal and reference signal at the through-silicon end to determine whether there is a fault in the through-silicon hole.
It realizes effective detection of the connectivity of through-silicon in 3D integrated circuits, with a simple structure and is suitable for large-scale integrated circuits, improving the reliability of the chip.
Smart Images
Figure CN111198316B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a through silicon via detection circuit and method, and an integrated circuit. Background Art
[0002] With the development and progress of technology, 3D chips are being used more and more widely. 3D chips use TSV (Through-Silicon Vias) to connect multiple layers of silicon wafers. TSV is prone to failure during the manufacturing and bonding process, and TSV failure is bound to affect the performance of 3D chips.
[0003] At present, for 3D integrated circuits with a small number of TSVs, an interposer is often not set in the stacking layer. For 3D integrated circuits with a large number of TSVs, an interposer is usually set in the stacking structure. The multi-layer stacking layers communicate through TSV interconnections, but TSVs are prone to failure during the manufacturing and binding process, so it is necessary to detect the connectivity of TSVs.
[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0005] The purpose of the present disclosure is to provide a through silicon via detection circuit and method, and an integrated circuit, so as to detect the connectivity of through silicon vias in a 3D integrated circuit.
[0006] According to a first aspect of the present disclosure, a through silicon via detection circuit is provided, the through silicon via detection circuit comprising:
[0007] The input module comprises a first switch unit, a control end of which is connected to a first detection control signal, a first end of which is connected to a first power supply end, and a second end of which is connected to a first end of a through silicon via, and is used for transmitting the first power supply signal to the first end of the through silicon via in response to the first detection control signal;
[0008] A comparison module has a first input terminal connected to the second terminal of the through silicon via and a second input terminal connected to a reference signal, and is used to compare the signal at the second terminal of the through silicon via with the reference signal.
[0009] According to an embodiment of the present disclosure, the input module is disposed on a first chip layer, the comparison module is disposed on a second chip layer, and the first chip layer and the second chip layer are connected via a through silicon via.
[0010] According to one embodiment of the present disclosure, N input modules are arranged on the first chip layer, each of the N input modules is correspondingly connected to the first end of a through silicon via string, the second end of the through silicon via string is connected to the first input end of the comparison module, and the through silicon via string includes a plurality of through silicon vias connected in series.
[0011] According to one embodiment of the present disclosure, the comparison module includes:
[0012] There are N comparison units, wherein the first input end of each comparison unit in the N comparison units is respectively connected to the second end of a through silicon via string, and the second input ends of the N comparison units are connected to the reference signal.
[0013] According to an embodiment of the present disclosure, the through silicon via detection circuit further includes:
[0014] Output modules, including:
[0015] a trigger, connected to the output control signal, the clock signal terminal and the first node, and configured to transmit the output control signal to the first node in response to the clock signal;
[0016] a second switch unit, connected to the second end of the TSV string, the first node and the first input end of the comparison module, and configured to be turned on in response to the signal output by the trigger to transmit the signal of the second end of the TSV string to the first input end of the comparison module;
[0017] According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
[0018] N output modules, the first end of the second switch unit of each of the N output modules is respectively connected to the second end of a through silicon via string, the second end of the second switch unit of each of the N output modules is connected to the first input end of the comparison module, the N output modules are arranged in the order of the through silicon via strings connected to them, and the output end of the trigger in the previous output module is connected to the input end of the trigger in the next output module;
[0019] The comparison module comprises:
[0020] A comparison unit, the second ends of the N second switch units are connected to the first input end of the comparison unit, and the second input end of the comparison unit is connected to the reference signal.
[0021] According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
[0022] N output modules, the first end of the second switch unit of each of the N output modules is respectively connected to the second end of a through silicon via string, the second end of the second switch unit of each of the N output modules is connected to the first input end of the comparison module, and the input ends of the triggers in the N output modules are all connected to the output control signal;
[0023] The comparison module comprises:
[0024] There are N comparing units, and second ends of the N second switch units are respectively connected to the first input ends of the corresponding comparing units, and second ends of the N comparing units are connected to the reference signal.
[0025] According to one embodiment of the present disclosure, the input module further includes:
[0026] A third switch unit, having a control end connected to a second detection control signal, a first end connected to the second end of the first switch unit, and a second end connected to the first end of the through silicon via, for transmitting the signal at the second end of the first switch unit to the first end of the through silicon via in response to the second detection control signal.
[0027] According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
[0028] M′N input modules, each of which is connected to a first end of a through silicon via;
[0029] M′N through silicon vias form N through silicon via strings, each of the through silicon via strings has M through silicon vias connected in series, and the second end of each of the through silicon via strings is connected to an output module;
[0030] The signal input end of the through silicon via string is the first end, and the signal output end is the second end.
[0031] According to an embodiment of the present disclosure, the through silicon via detection circuit further includes:
[0032] The selection module is used to transmit the first detection control signal to the control end of the first switch unit on one chip layer among the M chip layers according to the selection control signal, and transmit the second detection control signal to the control end of the third switch unit corresponding to one through silicon via string among the N through silicon via strings.
[0033] According to an embodiment of the present disclosure, the through silicon via detection circuit further includes:
[0034] A first detection through silicon via, wherein one end of the first detection through silicon via is connected to the first detection control signal output end of the selection module, and the other end of the first detection through silicon via is connected to the control end of the first switch unit;
[0035] A second detection through silicon via, wherein one end of the second detection through silicon via is connected to the second detection control signal output end of the selection module, and the other end is connected to the control end of the third switch unit.
[0036] According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
[0037] M first detection through silicon vias, wherein a first end of each first detection through silicon via is connected to control ends of a plurality of first switch units in a chip layer;
[0038] The selection module transmits a first detection control signal to a second end of the first detection TSV according to a selection control signal.
[0039] According to an embodiment of the present disclosure, the through silicon via detection circuit includes:
[0040] N second detection TSVs, wherein a first end of each second detection TSV is connected to control ends of a plurality of third switch units corresponding to a TSV string;
[0041] The selection module transmits the second detection control signal to a second end of the second detection TSV according to a selection control signal.
[0042] According to an embodiment of the present disclosure, the comparison module and the output module are arranged on a base chip layer of an integrated circuit.
[0043] According to an embodiment of the present disclosure, the comparison module and the output module are arranged in a top chip layer of the integrated circuit, and the top chip layer is a chip layer farthest from the base chip layer among the multiple chip layers.
[0044] According to a second aspect of the present disclosure, a through silicon via detection method is provided, the through silicon via detection method comprising:
[0045] The first switch unit is turned on by the first detection control signal, and the first power supply signal is transmitted to the first input terminal of the comparison module via the first switch unit and the through silicon via;
[0046] transmitting a reference signal to a second input terminal of the comparison module;
[0047] The comparison module compares the signals input from the first input terminal and the second input terminal to determine whether the TSV has a fault.
[0048] According to a third aspect of the present disclosure, an integrated circuit is provided, comprising the above-mentioned through silicon via detection circuit.
[0049] The through silicon via detection circuit provided by the present disclosure controls the conduction of the first switch unit through a first detection control signal, transmits the first power signal at the first end of the first switch unit to the first input end of the comparison module through the through silicon via connected to the second end of the first switch unit, inputs a reference signal to the second input end of the comparison module, and compares the input signals of the first input end and the second input end of the comparison module. If the signals inputted at the first input end and the second input end of the comparison module are different, the through silicon via is a faulty through silicon via, thereby realizing the detection of the connectivity of the through silicon via, and has a simple structure and is suitable for large-scale integrated circuits.
[0050] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the attached drawings.
[0052] Figure 1a is a schematic diagram of a fault-free TSV;
[0053] Figure 1b Schematic diagram of a hole-failed TSV;
[0054] Figure 1c Schematic diagram of a TSV with leakage fault;
[0055] Figure 2 A schematic diagram of a first through silicon via detection circuit provided for an exemplary embodiment of the present disclosure;
[0056] Figure 3 A schematic diagram of a second through silicon via detection circuit provided for an exemplary embodiment of the present disclosure;
[0057] Figure 4 A schematic diagram of a third through silicon via detection circuit provided for an exemplary embodiment of the present disclosure;
[0058] Figure 5 A schematic diagram of a fourth through silicon via detection circuit provided for an exemplary embodiment of the present disclosure;
[0059] Figure 6 A schematic diagram of a fifth through silicon via detection circuit provided for an exemplary embodiment of the present disclosure;
[0060] Figure 7 A schematic diagram of a sixth through silicon via detection circuit provided by an exemplary embodiment of the present disclosure;
[0061] Figure 8 A schematic diagram of a seventh through silicon via detection circuit provided by an exemplary embodiment of the present disclosure;
[0062] Fig. 9 A schematic diagram of an eighth through silicon via detection circuit provided for an exemplary embodiment of the present disclosure;
[0063] Fig.10 A schematic diagram of a ninth through silicon via detection circuit provided by an exemplary embodiment of the present disclosure;
[0064] Fig.11 A schematic diagram of an input module provided for an exemplary embodiment of the present disclosure;
[0065] Fig.12 A schematic diagram of an output module provided for an exemplary embodiment of the present disclosure;
[0066] Fig.13 A schematic diagram of a selection module provided for an exemplary embodiment of the present disclosure;
[0067] Fig.14 A flow chart of a through silicon via detection method provided in accordance with an exemplary embodiment of the present disclosure.
[0068] In the figure:
[0069] 100, input module; 110, first switch unit; 120, third switch unit; 200, comparison module; 300, through silicon via; 400, output module; 410, trigger; 420, second switch unit; 500, selection module; 600, first detection through silicon via; 700, second detection through silicon via.
[0070] VDD, first power supply signal; Vref, reference signal; DCS1, first detection control signal; DCS2, second detection control signal; CLK, clock signal; OCS, output control signal. DETAILED DESCRIPTION
[0071] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar parts, and thus their repeated description will be omitted.
[0072] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, devices, steps, etc. may be adopted. In other cases, known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.
[0073] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or these functional entities or parts of functional entities may be implemented in one or more software hardened modules, or these functional entities may be implemented in different networks and / or processor devices and / or microcontroller devices.
[0074] In the related art, a fault-free TSV such as Figure 1a As shown, TSV usually exists as follows Figure 1b Hole failure as shown, or Figure 1c The leakage fault shown. When there is a hole or leakage fault in the TSV, the signal passing through the TSV will change.
[0075] The exemplary embodiment of the present disclosure first provides a through silicon via detection circuit, such as Figure 2 As shown, the silicon through via detection circuit includes an input module 100 and a comparison module 200; the input module 100 includes a first switch unit 110, a control end connected to the first detection control signal DCS1 end, a first end connected to the first power supply end, and a second end connected to the first end of the silicon through via, and is used to respond to the first detection control signal DCS1 and conduct to transmit the first power supply signal VDD to the first end of the silicon through via; the first input end of the comparison module 200 is connected to the second end of the silicon through via, and the second input end is connected to the reference signal, and is used to compare the signal at the second end of the silicon through via with the reference signal Vref.
[0076] The comparison module 200 is used to compare the reference signal Vref and the signal flowing through the silicon via. In practical applications, the voltage of the first power signal VDD and the parameters of the first switch unit 110 can be adjusted so that the signal input to the silicon via is the same as the reference signal Vref. After the signal input to the silicon via flows through the silicon via, it is input to the first input terminal of the comparison module 200, and the second input module 100 inputs the second input terminal of the comparison module 200. The comparison module 200 compares the signals input to the first input terminal and the second input terminal. If they are the same, the silicon via is fault-free, and if they are different, the silicon via is faulty. Among them, when the difference between the signals input to the first input terminal and the second input terminal of the comparison module 200 is within a preset range, the signals input to the first input terminal and the second input terminal of the comparison module 200 can be considered to be the same.
[0077] The TSVs described in the embodiments of the present disclosure may be TSVs connecting adjacent chip layers, or may be TSV strings connected in series connecting non-adjacent chip layers, and the embodiments of the present disclosure do not specifically limit this.
[0078] The TSV detection circuit provided by the present disclosure controls the conduction of the first switch unit 110 through the first detection control signal DCS1, transmits the first power signal VDD at the first end of the first switch unit 110 to the first input end of the comparison module 200 through the TSV connected to the second end of the first switch unit 110, inputs the reference signal Vref to the second input end of the comparison module 200, and compares the input signals of the first input end and the second input end of the comparison module 200. If the input signals of the first input end and the second input end of the comparison module 200 are different, the TSV is a faulty TSV, thereby realizing the detection of the connectivity of the TSV, and has a simple structure, which is suitable for large-scale integrated circuits.
[0079] Since the through silicon via is used to connect different chip layers, the input module 100 is arranged on the first chip layer, and the comparison module 200 is arranged on the second chip layer, and the first chip layer and the second chip layer are connected through the through silicon via.
[0080] like Figure 3 As shown, when N through silicon vias are provided on a chip layer, N input modules 100 can be provided on the chip layer, each of the N input modules 100 is correspondingly connected to a first end of a through silicon via string, a second end of the through silicon via string is connected to a first input end of the comparison module 200, and the through silicon via string includes a plurality of through silicon vias connected in series.
[0081] Accordingly, the comparison module 200 may include: N comparison units, wherein a first input terminal of each of the N comparison units is respectively connected to a second terminal of a through silicon via string, and a second input terminal of the N comparison units is connected to a reference signal.
[0082] Further, such as Figure 4 As shown, the TSV detection circuit further includes: an output module 400, which is arranged between the TSV and the comparison module 200. Fig.12 As shown, the output module 400 may include a trigger 410 and a second switch unit 420; the trigger 410 is connected to the output control signal OCS terminal, the clock signal CLK terminal and the first node, and is used to transmit the output control signal OCS to the first node in response to the clock signal CLK; the second switch unit 420 is connected to the second end of the silicon via string, the output end of the trigger 410 and the first input end of the comparison module 200, and is used to be turned on in response to the signal output by the trigger 410 to transmit the signal at the second end of the silicon via string to the first input end of the comparison module 200.
[0083] The comparison module 200 and the output module 400 are arranged in the base chip layer of the integrated circuit; or, the comparison module 200 and the output module 400 are arranged in the top chip layer of the integrated circuit, and the top chip layer is a chip layer farthest from the base chip layer among the multiple chip layers. In other words, the second chip layer can be the base layer or the top layer of the 3D integrated circuit. When the second chip layer is the base layer of the 3D integrated circuit, that is to say, the comparison module 200 is located in the base layer, and at this time, the detection of silicon vias from bottom to top is supported. When the second chip layer is the top layer of the 3D integrated circuit, that is to say, the comparison module 200 is located in the top layer, and at this time, the detection of silicon vias from top to bottom is supported.
[0084] Under the control of the clock signal CLK, the trigger 410 transmits the output control signal OCS to the control end of the second switch unit 420 to turn on the second switch unit 420. The second switch unit 420 transmits the signal at the second end of the through silicon via to the first input end of the comparison module 200. The input end of the trigger 410 can be connected to an AND gate, and the two input ends of the AND gate are respectively input with the output control signal OCS and the detection enable signal EN. When both ends have signal inputs, the output control signal OCS is input to the trigger 410.
[0085] Further, such as Figure 5 As shown, when the through silicon via detection circuit includes N input modules 100, the through silicon via detection circuit may also include N output modules 400, the first end of the second switch unit 420 of each of the N output modules 400 is respectively connected to the second end of a through silicon via string, and the second end of the second switch unit 420 of each of the N output modules 400 is connected to the first input end of the comparison module 200.
[0086] In a feasible implementation manner provided by the embodiment of the present disclosure, as Figure 6 and Fig. 9As shown, the comparison module 200 may include a comparison unit, the second ends of the N second switch units 420 are connected to the first input end of the comparison unit, and the second input end of the comparison unit is connected to the reference signal. At this time, the second end of the second switch unit of each output module in the N output modules in the silicon through hole is connected to the first input end of the comparison module, and the N output modules are arranged in the order of the silicon through hole strings to which they are connected, the output end of the trigger in the previous output module is connected to the input end of the trigger in the next output module, and the input end of the trigger of the first output module in the output module sequence is connected to the output control signal. Through the scan chain formed by the triggers 410 in the multiple output modules, the scan chain is controlled by the clock signal CLK to sequentially output the output control signal OCS to control a second switch unit 420 to turn on, and the signal of the silicon through hole corresponding to the second switch unit 420 is transmitted to the first input end of the comparison module 200, and the connectivity of the silicon through hole is detected in turn. The number of comparison units in the circuit is reduced, the circuit structure is simplified, and the cost is saved.
[0087] In a feasible implementation manner provided by the embodiment of the present disclosure, as Figure 5 and Figure 7 As shown, the comparison module 200 includes: N comparison units, the second ends of the N second switch units 420 are respectively connected to the first input end of a comparison unit, the second ends of the N comparison units are connected to the reference signal, and the input ends of the triggers in the N output modules are all connected to the output control signal. Each output module is connected to a comparison unit, the detection result is intuitive, convenient for subsequent analysis, and simple to control.
[0088] Further, such as Fig.11 As shown, the input module 100 further includes: a third switch unit 120, the control end of which is connected to the second detection control signal DSC2 end, the first end of which is connected to the second end of the first switch unit 110, and the second end of which is connected to the first end of the through silicon via, and is used to respond to the second detection control signal and conduct to transmit the signal at the second end of the first switch unit 110 to the first end of the through silicon via. When the first switch unit 110 and the third switch unit 120 are turned on at the same time, the first power supply signal VDD is input to the through silicon via.
[0089] In practical applications, 3D integrated circuits usually include multiple stacked layers, and adjacent stacked layers need to be connected by multiple through-silicon vias. Figure 7As shown, in order to detect a detection integrated circuit including M stacked layers and each stacked layer including N through silicon vias, the through silicon via detection circuit may include: M′N input modules 100, each input module 100 is connected to the first end of a through silicon via; the M′N through silicon vias form N through silicon via strings, each through silicon via string has M through silicon vias connected in series, and the second end of each of the through silicon via strings is connected to an output module; wherein the signal input end of the through silicon via string is the first end, and the signal output end is the second end.
[0090] The comparison module 200 may be arranged in the base layer or the top layer of the 3D integrated circuit. The first detection control signal DCS1 may be provided to the first switch unit 110 in one or more layers of the M stacked layers, and the second detection control signal DSC2 may be provided to one or more corresponding third switch units 120 in the N through silicon via strings, thereby selecting to detect one or more through silicon via strings, and some through silicon vias in a through silicon via string may be selected for detection.
[0091] For example, for a 3D integrated circuit with a four-layer stacking structure, there are four through silicon vias in adjacent stacking layers, and the upper end of each through silicon via is connected to the input module 100. The output module 400 and the comparison module 200 are located in the base layer. The first detection control signal DCS1 can be output to the control end of the first switch unit 110 in the third stacking layer, and the second detection control signal DSC2 can be transmitted to the third switch unit 120 corresponding to the second column of through silicon vias. At this time, the through silicon vias between the third layer and the fourth layer in the second column of through silicon via strings are detected.
[0092] Further, such as Figure 8 As shown, the comparison module 200 can be set on both the base chip layer and the top chip layer of the integrated circuit, that is, the comparison module 200 is connected to both ends of the through silicon via string, the first input end of the comparison module on the base chip layer is connected to one end of the through silicon via string through the output module 400, and the first input end of the comparison module 200 on the top chip layer is connected to the other end of the through silicon via string through the fourth switch unit, and the fourth switch unit is turned on in response to the control signal to transmit the signal on the through silicon via string to the comparison module 200, and the second input ends of all the comparison modules 200 are connected to the reference signal. At this time, you can choose to test from top to bottom or from bottom to top according to the test requirements. The comparison module 200 on the base chip layer is used for the top-down test, and the comparison module 200 on the top chip layer is used for the bottom-up test.
[0093] In order to transmit the first detection control signal DCS1 to the control end of the corresponding first switch unit 110, and transmit the second detection control signal DSC2 to the control end of the corresponding third switch unit 120. Fig.10 and 13As shown, the silicon via detection circuit also includes: a selection module 500, which is used to transmit the first detection control signal DCS1 to the control end of the first switch unit 110 on one of the M stacking layers according to the selection control signal, and transmit the second detection control signal DSC2 to the control end of the third switch unit 120 corresponding to one of the N silicon via strings.
[0094] Among them, the selection module 500 may include a first selection unit and a second selection unit, the first selection unit is used to select the control end of the first selection unit in a stacking layer among the multi-layer stacking layers to transmit the first detection control signal DCS1; the second selection unit is used to select the control end of the third switch unit 120 corresponding to a silicon via string among multiple silicon via strings to transmit the second detection control signal DSC2.
[0095] The first selection unit and the second selection unit can be selectors, which select the input signal to be transmitted to one of the multiple output terminals by selecting the control signal. Each output terminal of the selector in the first selection unit can be connected to an AND gate, and the other input terminal of the AND gate is connected to the detection enable signal EN.
[0096] For example, the through silicon vias in the 3D integrated circuit can be numbered according to the stacked layer in which they are located and their positions in each layer. For example, the through silicon vias can be numbered in the manner shown in Table 1, and then the selection module 500 selects the corresponding numbers to transmit the first detection control signal DCS1 and the second detection control signal DSC2 to the first switch unit 110 and the third switch unit 120 connected to the through silicon vias corresponding to the numbers.
[0097] Table 1
[0098] 11 12 13 14 … 1N 21 22 23 24 … 2N 31 32 33 34 … 3N … … … … … … M1 M2 M3 M4 … MN
[0099] Furthermore, the TSV detection circuit further includes a first detection TSV 600 and a second detection TSV 700, wherein one end of the first detection TSV is connected to the output end of the first detection control signal DCS1 of the selection module 500, and the other end is connected to the control end of the first switch unit 110; one end of the second detection TSV 700 is connected to the output end of the second detection control signal DSC2 of the selection module 500, and the other end is connected to the control end of the third switch unit 120. The first detection TSV 600 is used to transmit the first detection control signal DCS1 to the control end of the corresponding first switch unit 110, and the second detection TSV 700 is used to transmit the second detection control signal DSC2 to the control end of the corresponding third switch unit 120.
[0100] The TSV detection circuit may include: M first detection TSVs 600, wherein the first end of each first detection TSV 600 is connected to the control ends of a plurality of first switch units 110 in a chip layer; and the selection module 500 transmits the first detection control signal DCS1 to the second end of the first detection TSV 600 according to the selection control signal. Each of the M first detection TSVs 600 is connected to a stacking layer, and the control ends of the first switch units 110 of all the input modules 100 in the stacking layer are connected to the first detection TSV 600.
[0101] The TSV detection circuit may include: N second detection TSVs 700, wherein the first end of each second detection TSV 700 is connected to the control end of a plurality of third switch units 120 corresponding to a TSV string; the selection module 500 transmits the second detection control signal DSC2 to the second end of a second detection TSV 700 according to the selection control signal. Each of the N second detection TSVs 700 is connected to a TSV string, and the control ends of the second switch units 420 of the plurality of input modules 100 corresponding to the TSV are all connected to the second detection TSV 700.
[0102] It should be noted that the first detection silicon via 600 and the second detection silicon via 700 described in the embodiment of the present disclosure are also silicon vias, and are fault-free silicon vias that have been tested. The first switch unit 110, the second switch unit 420 and the third switch unit 120 described in the embodiment of the present disclosure can be transistors, or components such as transmission gates. The first end and the second end of the silicon via described in the embodiment of the present disclosure refer to the two ends of the silicon via, respectively, and the first end can be the upper end or the lower end, which is not specifically limited in the embodiment of the present disclosure. M and N described in the embodiment of the present disclosure are both positive integers greater than or equal to 1.
[0103] The TSV detection circuit provided in the embodiment of the present disclosure can cooperate with the repair circuit to increase the reliability of the TSV. The faulty TSV is discovered by the TSV detection circuit used in the present disclosure, and then the faulty TSV is replaced by the repair circuit in the related technology, especially the TSV provided by the redundancy mechanism.
[0104] In an exemplary embodiment of the present disclosure, a through silicon via detection method is also provided. Fig.14 As shown, the through silicon via detection method includes:
[0105] Step S1, using the first detection control signal DCS1 to turn on the first switch unit 110, and the first power signal VDD is transmitted to the first input terminal of the comparison module 200 via the first switch unit 110 and the through silicon via;
[0106] Step S2, transmitting the reference signal Vref to the second input terminal of the comparison module 200;
[0107] Step S3, comparing the signals input from the first input terminal and the signals input from the second input terminal by the comparison module 200 to determine whether the TSV has a fault.
[0108] In the exemplary embodiment of the present disclosure, an integrated circuit is also provided, including the through silicon via detection circuit described in the embodiment of the present disclosure. Of course, in practical applications, the integrated circuit may also include components such as a PCB board, a resistor and a capacitor, which are all prior arts and are not specifically limited in the embodiment of the present disclosure.
[0109] It should be noted that, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.
[0110] In addition, the above-mentioned figures are only schematic illustrations of the processes included in the method according to an exemplary embodiment of the present invention, and are not intended to be limiting. It is easy to understand that the processes shown in the above-mentioned figures do not indicate or limit the time sequence of these processes. In addition, it is also easy to understand that these processes can be performed synchronously or asynchronously, for example, in multiple modules.
[0111] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are to be considered as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.
[0112] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims
1. A through silicon via detection circuit, characterized in that: The through silicon via detection circuit comprises: The input module comprises a first switch unit, a control end of which is connected to a first detection control signal, a first end of which is connected to a first power supply end, and a second end of which is connected to a first end of a through silicon via, and is used for transmitting the first power supply signal to the first end of the through silicon via in response to the first detection control signal; A comparison module, wherein a first input terminal is connected to a second end of the through silicon via, and a second input terminal is connected to a reference signal, and is used to compare a signal at the second end of the through silicon via with the reference signal; An output module is provided between the through silicon via and the comparison module, and the output module comprises a trigger and a second switch unit.
2. The through silicon via detection circuit according to claim 1, characterized in that: The input module is arranged on a first chip layer, the comparison module is arranged on a second chip layer, and the first chip layer and the second chip layer are connected via through silicon vias.
3. The through silicon via detection circuit according to claim 2, characterized in that: N input modules are arranged on the first chip layer, each of the N input modules is correspondingly connected to the first end of a through silicon via string, the second end of the through silicon via string is connected to the first input end of the comparison module, and the through silicon via string includes a plurality of through silicon vias connected in series.
4. The through silicon via detection circuit according to claim 3, characterized in that: The comparison module comprises: There are N comparison units, wherein the first input end of each comparison unit in the N comparison units is respectively connected to the second end of a through silicon via string, and the second input ends of the N comparison units are connected to the reference signal.
5. The through silicon via detection circuit according to claim 3, characterized in that: The output module is configured as: The trigger is connected to the output control signal, the clock signal terminal and the first node, and is used to transmit the output control signal to the first node in response to the clock signal; The second switch unit is connected to the second end of the TSV string, the first node and the first input end of the comparison module, and is configured to be turned on in response to the signal output by the trigger to transmit the signal at the second end of the TSV string to the first input end of the comparison module.
6. The through silicon via detection circuit according to claim 5, characterized in that: The through silicon via detection circuit comprises: N output modules, the first end of the second switch unit of each of the N output modules is respectively connected to the second end of a through silicon via string, the second end of the second switch unit of each of the N output modules is connected to the first input end of the comparison module, the N output modules are arranged in the order of the through silicon via strings connected to them, and the output end of the trigger in the previous output module is connected to the input end of the trigger in the next output module; The comparison module comprises: A comparison unit, wherein the second terminals of the N second switch units are connected to the first input terminal of the comparison unit, and the second input terminal of the comparison unit is connected to the reference signal.
7. The through silicon via detection circuit according to claim 5, characterized in that: The through silicon via detection circuit comprises: N output modules, the first end of the second switch unit of each of the N output modules is respectively connected to the second end of a through silicon via string, the second end of the second switch unit of each of the N output modules is connected to the first input end of the comparison module, and the input ends of the triggers in the N output modules are all connected to the output control signal; The comparison module comprises: There are N comparison units, the second ends of the N second switch units are respectively connected to the first input ends of the corresponding comparison units, and the second ends of the N comparison units are connected to the reference signal.
8. The through silicon via detection circuit according to claim 6 or 7, characterized in that: The input module also includes: A third switch unit, having a control end connected to a second detection control signal, a first end connected to the second end of the first switch unit, and a second end connected to the first end of the through silicon via, for transmitting the signal at the second end of the first switch unit to the first end of the through silicon via in response to the second detection control signal.
9. The through silicon via detection circuit according to claim 8, used for an integrated circuit comprising M chip layers and each chip layer comprising N through silicon vias, characterized in that: The through silicon via detection circuit comprises: M*N input modules, each of which is connected to a first end of a through silicon via; M*N through silicon vias form N through silicon via strings, each of the through silicon via strings has M through silicon vias connected in series, and the second end of each of the through silicon via strings is connected to an output module; The signal input end of the through silicon via string is the first end, and the signal output end is the second end.
10. The through silicon via detection circuit according to claim 9, characterized in that: The through silicon via detection circuit further includes: The selection module is used to transmit the first detection control signal to the control end of the first switch unit on one chip layer among the M chip layers according to the selection control signal, and transmit the second detection control signal to the control end of the third switch unit corresponding to one through silicon via string among the N through silicon via strings.
11. The through silicon via detection circuit according to claim 10, characterized in that: The through silicon via detection circuit further includes: A first detection through silicon via, wherein one end of the first detection through silicon via is connected to the first detection control signal output end of the selection module, and the other end of the first detection through silicon via is connected to the control end of the first switch unit; A second detection through silicon via, wherein one end of the second detection through silicon via is connected to the second detection control signal output end of the selection module, and the other end is connected to the control end of the third switch unit.
12. The through silicon via detection circuit according to claim 11, characterized in that: The through silicon via detection circuit comprises: M first detection through silicon vias, wherein a first end of each first detection through silicon via is connected to control ends of a plurality of first switch units in a chip layer; The selection module transmits a first detection control signal to a second end of the first detection TSV according to a selection control signal.
13. The through silicon via detection circuit according to claim 11, characterized in that: The through silicon via detection circuit comprises: N second detection TSVs, wherein a first end of each second detection TSV is connected to control ends of a plurality of third switch units corresponding to a TSV string; The selection module transmits the second detection control signal to a second end of the second detection TSV according to a selection control signal.
14. The through silicon via detection circuit according to claim 5, characterized in that: The comparison module and the output module are arranged on a base chip layer of an integrated circuit.
15. The through silicon via detection circuit according to claim 5, characterized in that: The comparison module and the output module are arranged in a top chip layer of the integrated circuit, and the top chip layer is a chip layer farthest from the base chip layer among the multiple chip layers.
16. A through silicon via detection method, used in the through silicon via detection circuit according to any one of claims 1 to 15, characterized in that: The through silicon via detection method comprises: The first detection control signal is used to turn on the first switch unit, and the first power supply signal is transmitted to the first input terminal of the comparison module via the first switch unit and the through silicon via; transmitting a reference signal to a second input terminal of the comparison module; The comparison module compares the signals input from the first input terminal and the second input terminal to determine whether the TSV has a fault.
17. An integrated circuit, characterized in that: The invention comprises a through silicon via detection circuit as described in any one of claims 1-15.
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