Method for manufacturing a polysilicon layer, display device, and method for manufacturing a display device

Abstract

A method for manufacturing a polysilicon layer, a display device, and a method for manufacturing a display device are disclosed. The method for manufacturing a polysilicon layer for a display device includes the following steps: forming an amorphous silicon layer on a substrate; cleaning the amorphous silicon layer with hydrofluoric acid; rinsing the amorphous silicon layer with hydrogenated deionized water; and irradiating the amorphous silicon layer with a laser beam to form a polysilicon layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2018 - 0142225, filed on November 19, 2018, which is incorporated herein by reference in its entirety for all purposes as if fully set forth herein. Technical Field

[0003] Exemplary implementations of the present invention generally relate to a method of manufacturing a substrate for a display device, and more particularly, to a method of manufacturing a substrate having a polysilicon layer, a display device using the method, and a method of manufacturing a display device. Background Art

[0004] An active - matrix (AM) type organic light - emitting display device may include a pixel circuit in each pixel, and the pixel circuit may include a thin - film transistor (TFT) using silicon. The TFT may be formed of amorphous silicon or polysilicon.

[0005] Since the active layer having a source, a drain, and a channel is formed of amorphous silicon (a - Si), the amorphous silicon TFT used in the pixel circuit may have a low electron mobility of 1 cm 2 / Vs or less. Therefore, amorphous silicon TFTs have recently been replaced by polysilicon (poly - Si) TFTs. The polysilicon TFT has a higher electron mobility and more stable light resistance than the amorphous silicon TFT. Therefore, the polysilicon TFT may be suitable for use as the active layer of a driving TFT and / or a switching TFT of an AM type organic light - emitting display device.

[0006] Polysilicon can be manufactured according to several methods. These methods can generally be classified as methods of depositing polysilicon or methods of depositing amorphous silicon and crystallizing the amorphous silicon.

[0007] Examples of methods of depositing polysilicon include chemical vapor deposition (CVD), sputtering, vacuum evaporation, etc.

[0008] Examples of methods of depositing amorphous silicon and crystallizing the amorphous silicon include solid - phase crystallization (SPC), excimer laser crystallization (ELC), metal - induced crystallization (MIC), metal - induced lateral crystallization (MILC), sequential lateral solidification (SLS), etc.

[0009] The above information disclosed in this background art section is only for understanding the background of the inventive concept, and thus, it may include information that does not constitute prior art. Summary of the Invention

[0010] A method of manufacturing a polysilicon layer constructed according to the principles and exemplary implementations of the present invention can reduce the surface roughness of the polysilicon layer. For example, in a method of manufacturing a polysilicon layer according to some exemplary embodiments of the present invention, before crystallizing an amorphous silicon layer to form a polysilicon layer, the amorphous silicon layer can be cleaned with hydrofluoric acid and rinsed with hydrogenated deionized water to reduce the surface roughness of the polysilicon layer to produce a flatter surface.

[0011] In addition, a display device and a method of manufacturing the same constructed according to the principles and exemplary implementations of the present invention can reduce the surface roughness of an active pattern in a thin film transistor (TFT). Since the display device according to an exemplary embodiment includes a TFT having an active pattern with a low surface roughness, the threshold voltage of the TFT can be more uniform, and a gate insulating layer disposed on the active pattern can be protected from damage.

[0012] Additional features of the inventive concept will be set forth in the following description, and in part will be obvious from the description, or may be learned by practicing the inventive concept.

[0013] According to an aspect of the present invention, a method of manufacturing a polysilicon layer for a display device includes the steps of: forming an amorphous silicon layer on a substrate; cleaning the amorphous silicon layer with hydrofluoric acid; rinsing the amorphous silicon layer with hydrogenated deionized water; and irradiating the amorphous silicon layer with a laser beam to form a polysilicon layer.

[0014] The hydrofluoric acid may include hydrogen fluoride in an amount of about 0.5%.

[0015] The amorphous silicon layer may be cleaned for about 40 seconds to about 54 seconds.

[0016] During the step of forming the amorphous silicon layer, a native oxide layer may be formed on the amorphous silicon layer, and during the step of cleaning the amorphous silicon layer, the native oxide layer may be removed.

[0017] The hydrogenated deionized water may have a hydrogen concentration of about 1.0 ppm.

[0018] The laser beam may have an energy density in the range of about 450 mJ / cm 2 to about 500 mJ / cm 2 The range of the energy density is.

[0019] The width of the laser beam may be about 480 μm, and the scanning pitch of the laser beam may be in the range of about 9 μm to about 30 μm.

[0020] The polysilicon layer may have a surface roughness with a root mean square (RMS) value of about 4 nm or less.

[0021] After the step of forming the polysilicon layer, protrusions may be formed on the surface of the polysilicon layer, and the protrusions may have sharp tips.

[0022] The polysilicon layer may have a grain size in the range of about 150 nm to about 200 nm.

[0023] The polysilicon layer may have randomly arranged grains.

[0024] The method may further include the step of forming a buffer layer on the substrate before forming the amorphous silicon layer.

[0025] According to another aspect of the present invention, a display device includes a substrate, a thin film transistor disposed on the substrate, and a display element disposed on the thin film transistor. The thin film transistor may include an active pattern disposed on the substrate, a gate insulating layer disposed on the active pattern, and a gate electrode disposed on the gate insulating layer, and the active pattern has a surface roughness with a root mean square (RMS) value of about 4 nm or less.

[0026] Protrusions may be formed on the surface of the active pattern, and the protrusions may have sharp tips.

[0027] The active pattern may have a grain size in the range of about 150 nm to about 200 nm.

[0028] The active pattern may include randomly arranged grains.

[0029] The active pattern may include a source region, a drain region, and a channel region formed between the source region and the drain region.

[0030] The gate electrode may overlap the channel region of the active pattern.

[0031] The thin film transistor may further include a source electrode and a drain electrode disposed on the gate electrode, and the source electrode and the drain electrode are electrically connected to the source region and the drain region of the active pattern, respectively.

[0032] The display element may include a first electrode electrically connected to the thin film transistor, an emission layer disposed on the first electrode, and a second electrode disposed on the emission layer.

[0033] According to still another aspect of the present invention, a method of manufacturing a display device includes the steps of: forming an amorphous silicon layer on a substrate; cleaning the amorphous silicon layer with hydrofluoric acid; rinsing the amorphous silicon layer with hydrogenated deionized water; irradiating the amorphous silicon layer with a laser beam to form a polysilicon layer; etching the polysilicon layer to form a polysilicon pattern; forming a gate insulating layer on the polysilicon pattern; forming a gate electrode on the gate insulating layer; implanting ions in a part of the polysilicon pattern to form an active pattern; and forming a display element on the gate electrode.

[0034] The hydrofluoric acid may include about 0.5% by weight of hydrogen fluoride.

[0035] The step of cleaning the amorphous silicon layer may include: cleaning for about 40 seconds to about 54 seconds.

[0036] The step of rinsing the amorphous silicon layer with hydrogenated deionized water may include: rinsing with hydrogenated deionized water having a hydrogen concentration of about 1.0 ppm.

[0037] The step of irradiating the amorphous silicon layer with a laser beam may include: irradiating with a laser beam having an energy density in the range of about 450 mJ / cm 2 to about 500 mJ / cm 2 The method may further include the step of forming a source electrode and a drain electrode on the gate electrode, the source electrode and the drain electrode being electrically connected to the active pattern.

[0038] The step of forming a display element may include the steps of: forming a first electrode on the gate electrode, the first electrode being electrically connected to the active pattern; forming an emission layer on the first electrode; and forming a second electrode on the emission layer.

[0039] In a method of manufacturing a display device according to one or more embodiments, before crystallizing the amorphous silicon layer to form an active pattern, the amorphous silicon layer may be cleaned with hydrofluoric acid and rinsed with hydrogenated deionized water, which reduces the surface roughness of the active pattern.

[0040] It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory and are intended to provide further explanation of the claimed invention.

[0041] Brief Description of the Drawings The drawings are included to provide a further understanding of the invention and are incorporated into and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, are used to explain the inventive concept.

[0042]

[0043] Figure 1 is a flowchart showing a method of manufacturing a polysilicon layer according to the principles of the present invention.

[0044] Figure 2 Figure 3 , Figure 4 , Figure 6 and Figure 5

[0045] Figure 7

[0046] Figure 8 is a plan view of an exemplary embodiment of a crystallized polysilicon layer constructed according to the principles of the present invention.

[0046] Figure 8 is a cross-sectional view of a thin film transistor substrate constructed according to the principles of the present invention.

[0047] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 are cross-sectional views showing Figure 8 a manufacturing method of a thin film transistor substrate.

[0048] Figure 16 is an equivalent circuit diagram showing a representative pixel of a display device according to an exemplary embodiment.

[0049] Figure 17 is a cross-sectional view showing a display device constructed according to the principles of the present invention.

[0050] Figure 18 and Figure 19 are cross-sectional views showing Figure 17 an exemplary manufacturing method of the display device in DETAILED DESCRIPTION

[0051] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various exemplary embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, and they are non-limiting examples of a device or method that employs one or more of the inventive concepts disclosed herein. However, it will be apparent that the various exemplary embodiments may be practiced without specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. In addition, the various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shapes, configurations, and characteristics of the exemplary embodiments may be used or implemented in another exemplary embodiment.

[0052] Unless otherwise indicated, the exemplary embodiments shown are to be understood as providing exemplary features of some ways capable of implementing the inventive concept in practice. Accordingly, unless otherwise indicated, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or rearranged in other ways without departing from the inventive concept.

[0053] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless indicated, the presence or absence of cross-hatching or shading does not convey or imply any preference or requirement for a particular material, material property, dimension, scale, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements. Additionally, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of the elements may be exaggerated. When an exemplary embodiment can be implemented in a different manner, the specific process sequence may be performed differently from the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Also, the same reference numerals denote the same elements.

[0054] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. For this reason, the term "connected" can indicate a physical, electrical, and / or fluid connection with or without intervening elements. Additionally, the D1-axis, D2-axis, and D3-axis are not limited to the three axes of a rectangular coordinate system (such as the x-axis, y-axis, and z-axis) and can be interpreted in a broader sense. For example, the D1-axis, D2-axis, and D3-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0055] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these components should not be limited by these terms. These terms are used to distinguish one element from another. Thus, without departing from the teachings of this disclosure, the first element discussed below could be termed the second element.

[0056] Spatial relative terms such as "beneath", "below", "under", "lower", "above", "upper", "over", "higher", "side" (e.g., as in "sidewall") etc. may be used herein for descriptive purposes and, thus, to describe the relationship of one element to another as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as "beneath" or "below" other elements or features will then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation above and below. In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and, thus, the spatial relative descriptors used herein are to be interpreted accordingly.

[0057] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. Unless the context clearly dictates otherwise, the singular forms "a", "an", and "the" as used herein are also intended to include the plural forms. Additionally, when the terms "comprise", "comprising", "include", and / or "including" are used in this specification, they indicate the presence of the stated features, integers, steps, operations, elements, components, and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It is also noted that, as used herein, the terms "substantially", "about", and other similar terms are used as terms of approximation and not of degree, and, thus, are utilized to account for the inherent deviations of measured, calculated, and / or provided values that would be recognized by a person of ordinary skill in the art.

[0058] The various exemplary embodiments are described herein with reference to sectional views and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. As a result, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the exemplary embodiments disclosed herein should not necessarily be construed as being limited to the particular shapes shown, but include deviations in shapes resulting from, for example, manufacturing. In this manner, the regions shown in the figures are schematic in nature and the shapes of these regions may not reflect the actual shape of the regions of the device and, thus, are not necessarily intended to be limiting.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense.

[0060] Hereinafter, a method for manufacturing a polysilicon layer, a thin film transistor substrate and a method for manufacturing the same, and a display device and a method for manufacturing the same according to exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0061] Hereinafter, reference will be made to Figures 1 to 7 describe a method for manufacturing a polysilicon layer according to an exemplary embodiment.

[0062] Figure 1 is a flowchart showing a method for manufacturing a polysilicon layer according to the principles of the present invention. Figure 2 , Figure 3 , Figure 4 and Figure 6 are cross-sectional views showing a method for manufacturing a polysilicon layer according to the principles of the present invention, and Figure 5 is a perspective view showing a method for manufacturing a polysilicon layer according to the principles of the present invention.

[0063] Referring to Figure 1 and Figure 2 , an amorphous silicon layer 132 may be formed on a substrate 110 (S110).

[0064] The substrate 110 may be an insulating substrate including glass, quartz, ceramics, etc. In an exemplary embodiment, the substrate 110 may be an insulating flexible substrate including plastics (such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether ether ketone (PEEK), polycarbonate (PC), polyarylate, polyethersulfone (PES), polyimide (PI), etc.).

[0065] A buffer layer 120 may be formed on the substrate 110. The buffer layer 120 may provide a planarized surface above the substrate 110. The buffer layer 120 may prevent impurities from penetrating through the substrate 110 to above the substrate 110. For example, the buffer layer 120 may be formed of silicon oxide, silicon nitride, etc.

[0066] An amorphous silicon layer 132 may be formed on the buffer layer 120. The amorphous silicon layer 132 may be formed by methods such as low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, etc.

[0067] A native oxide layer NOL may be formed on the amorphous silicon layer 132. The native oxide layer NOL may be formed when the upper portion of the amorphous silicon layer 132 is exposed to air. When the native oxide layer NOL remains on the amorphous silicon layer 132, in a subsequent process for crystallizing the amorphous silicon layer 132 to form a polysilicon layer, protrusions having a relatively large thickness may be formed on the surface of the polysilicon layer through the native oxide layer NOL.

[0068] Referring to Figure 1 and Figure 3 , the amorphous silicon layer 132 may be cleaned (S120).

[0069] The amorphous silicon layer 132 may be cleaned using hydrofluoric acid 210. The hydrofluoric acid 210 may be an aqueous solution in which hydrogen fluoride (HF) is dissolved. For example, the hydrofluoric acid 210 may include about 0.5% by weight of hydrogen fluoride. The amorphous silicon layer 132 may be cleaned with the hydrofluoric acid 210 to remove the native oxide layer NOL formed on the amorphous silicon layer 132.

[0070] In an exemplary embodiment, the amorphous silicon layer 132 may be cleaned for about 40 seconds to about 54 seconds. If the cleaning time of the amorphous silicon layer 132 is less than about 40 seconds, the native oxide layer NOL formed on the amorphous silicon layer 132 may not be sufficiently removed. If the cleaning time of the amorphous silicon layer 132 is greater than about 54 seconds, the amorphous silicon layer 132 may be affected by the hydrofluoric acid 210.

[0071] Referring to Figure 1 and Figure 4 , the amorphous silicon layer 132 may be rinsed (S130).

[0072] The amorphous silicon layer 132 may be rinsed using hydrogenated deionized water 220. For example, the hydrogen concentration of the hydrogenated deionized water 220 may be about 1.0 ppm. For example, the hydrogenated deionized water 220 may be supplied to the amorphous silicon layer 132 via a spray 230 while moving a substrate 110 disposed below the fixed spray 230. The hydrofluoric acid 210 remaining on the amorphous silicon layer 132 may be removed by rinsing the amorphous silicon layer 132 with the hydrogenated deionized water 220.

[0073] If the amorphous silicon layer 132 is rinsed with deionized water without hydrogen, oxygen in the deionized water may remain on the amorphous silicon layer 132, and circular defects may be visible due to the oxygen after the crystallization process. However, in the illustrated embodiment, the amorphous silicon layer 132 may be rinsed with the hydrogenated deionized water 220, thereby preventing circular defects from being visible.

[0074] Referring to Figure 1 , Figure 5 and Figure 6, the amorphous silicon layer 132 can be irradiated with a laser beam 240 to form a polysilicon layer 134 (S140).

[0075] The polysilicon layer 134 can be formed by irradiating the amorphous silicon layer 132 with the laser beam 240. The laser 250 can intermittently generate the laser beam 240 to irradiate the amorphous silicon layer 132. For example, the laser 250 can be an excimer laser for generating a laser beam 240 having a relatively short wavelength, relatively high power, and relatively high efficiency. The excimer laser can include, for example, inert gases, inert gas halides, mercury halides, inert gas acid compounds, and polyatomic excimers. Examples of inert gases are Ar2, Kr2, and Xe2. Examples of inert gas halides are ArF, ArCl, KrF, KrCl, XeF, and XeCl. Examples of mercury halides are HgCl, HgBr, and HgI. Examples of inert gas acid compounds are ArO, KrO, and XeO. Examples of polyatomic excimers are Kr2F and Xe2F.

[0076] When moving the substrate 110 along the first direction D1, the amorphous silicon layer 132 can be crystallized into the polysilicon layer 134 by irradiating the amorphous silicon layer 132 with the laser beam 240 emitted from the laser 250. The laser 250 can irradiate the amorphous silicon layer 132 with a laser beam 240 having an energy density in the range of about 450 mJ / cm 2 to about 500 mJ / cm 2 . In an exemplary embodiment, the width WB of the laser beam 240 in the first direction D1 can be about 480 μm, and the scanning pitch of the laser beam 240 in the first direction D1 can be in the range of about 9 μm to about 30 μm. For example, when the scanning pitch is about 24 μm, the laser beam 240 can be irradiated onto a predetermined area of the amorphous silicon layer 132 about 24 times. As Figure 5 shown, the area where the crystallization process is performed using the laser beam 240 can be converted from the amorphous silicon layer 132 to the polysilicon layer 134.

[0077] When the laser beam 240 irradiates the solid amorphous silicon layer 132, the amorphous silicon layer 132 can absorb heat and become liquid. Then, the amorphous silicon layer 132 can release heat and become solid again. In this case, crystals can grow from the seed crystals, and the crystal grains 134a can be formed. When there is a difference in the cooling rate in the amorphous silicon layer 132 during the process of changing from liquid to solid, since the crystal grains 134a grow from the area with a high cooling rate towards the area with a slow cooling rate, the grain boundaries 134b can be formed in the area with a slow cooling rate.

[0078] Figure 7 is a plan view of an exemplary embodiment of a crystallized polysilicon layer constructed according to the principles of the present invention.

[0079] Referring toFigure 6 and Figure 7 Multiple grains 134a can be formed in the polysilicon layer 134. In a plan view, the grains 134a can be randomly arranged. In an exemplary embodiment, the size of each grain 134a can be in the range of about 150 nm to about 200 nm.

[0080] Protrusions 134c can be formed at the grain boundaries 134b on the surface of the polysilicon layer 134 on which the crystallization process has been performed. The amorphous silicon layer 132 melted by the laser beam 240 can be recrystallized around the grains 134a, so that the protrusions 134c can be formed at the grain boundaries 134b.

[0081] The protrusions 134c can protrude upward from the surface of the polysilicon layer 134 and can have sharp tips. The protrusions 134c can have a thickness (depth) TH corresponding to the distance from the surface of the polysilicon layer 134 to the end of the protrusions 134c.

[0082] The root mean square (RMS) value of the surface roughness of the polysilicon layer 134 can be about 4 nm or less. For example, the RMS value of the thickness of the protrusions 134c formed on the surface of the polysilicon layer 134 can be about 4 nm or less.

[0083] In the illustrated embodiment, a cleaning process using hydrofluoric acid 210 and a rinsing process using hydrogenated deionized water 220 can be performed before the crystallization process. Therefore, the thickness TH of the protrusions 134c formed on the surface of the polysilicon layer 134 can be reduced, and a polysilicon layer 134 with a relatively low surface roughness can be formed.

[0084] The cleaning process, rinsing process, and crystallization process for forming the polysilicon layer 134 are described above. However, in addition to the above processes, processes for forming the polysilicon layer 134 can be added, or some of the above processes can be omitted. The above processes can also be performed multiple times. For example, the crystallization process can be performed two or more times.

[0085] Hereinafter, reference will be made to Figures 8 to 15 to describe a thin film transistor substrate and a method of manufacturing the thin film transistor substrate.

[0086] Figure 8 is a cross-sectional view of a thin film transistor substrate constructed according to the principles of the present invention.

[0087] Referring to Figure 8, the thin - film transistor substrate 100 according to an exemplary embodiment may include a substrate 110 and a thin - film transistor TR disposed on the substrate 110. The thin - film transistor TR may include an active pattern AP, a gate insulating layer 140, a gate electrode GE, a source electrode SE, and a drain electrode DE stacked in sequence. The thin - film transistor TR may perform a switching operation of causing current to flow through the active pattern AP based on a signal applied to the gate electrode GE.

[0088] The thin - film transistor TR may have a top - gate structure in which the gate electrode GE is positioned above the active pattern AP. However, the exemplary embodiment is not limited thereto, and the thin - film transistor TR may have a bottom - gate structure in which the gate electrode GE is positioned below the active pattern AP.

[0089] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 are cross - sectional views showing Figure 8 the manufacturing method of the thin - film transistor substrate in

[0090] Referring to Figure 9 , an amorphous silicon layer 132 may be formed on the substrate 110.

[0091] The substrate 110 may be an insulating substrate including glass, quartz, ceramic, etc. In an exemplary embodiment, the substrate 110 may be an insulating flexible substrate including plastics (such as PET, PEN, PEEK, PC, polyarylate, PES, PI, etc.). For example, a barrier layer including silicon oxide, silicon nitride, amorphous silicon, etc. may be additionally formed on the substrate 110.

[0092] A buffer layer 120 may be formed on the substrate 110. The buffer layer 120 may provide a planarized surface above the substrate 110. The buffer layer 120 may prevent impurities from penetrating through the substrate 110 to above the substrate 110.

[0093] An amorphous silicon layer 132 may be formed on the buffer layer 120. The amorphous silicon layer 132 may be formed by methods such as LPCVD, APCVD, PECVD, sputtering, vacuum evaporation, etc. A native oxide layer may be formed on the amorphous silicon layer 132.

[0094] The amorphous silicon layer 132 can be cleaned using hydrofluoric acid. For example, the hydrofluoric acid can include hydrogen fluoride in an amount of about 0.5%. The amorphous silicon layer 132 can be cleaned with hydrofluoric acid to remove the native oxide layer formed on the amorphous silicon layer 132. In an exemplary embodiment, the amorphous silicon layer 132 can be cleaned for about 40 seconds to about 54 seconds.

[0095] The amorphous silicon layer 132 can be rinsed using hydrogenated deionized water. For example, the hydrogen concentration of the hydrogenated deionized water can be about 1.0 ppm. The hydrofluoric acid remaining on the amorphous silicon layer 132 can be removed by rinsing the amorphous silicon layer 132 with hydrogenated deionized water.

[0096] Referring Figure 10 , the amorphous silicon layer 132 can be crystallized to form a polycrystalline silicon layer 134.

[0097] The polycrystalline silicon layer 134 can be formed by irradiating the amorphous silicon layer 132 with a laser beam. The laser can intermittently generate a laser beam to irradiate the amorphous silicon layer 132.

[0098] The laser can be used to irradiate the amorphous silicon layer 132 with a laser beam having an energy density in the range of about 450 mJ / cm 2 to about 500 mJ / cm 2 . In an exemplary embodiment, the width of the laser beam can be about 480 μm, and the scan pitch of the laser beam can be in the range of about 9 μm to about 30 μm.

[0099] When the laser beam irradiates the solid amorphous silicon layer 132, the amorphous silicon layer 132 can absorb heat and become liquid. Then, the amorphous silicon layer 132 can release heat and become solid again. In this case, crystals can grow from the seed crystals, and crystal grains can be formed. When there is a difference in the cooling rate in the amorphous silicon layer 132 during the process of changing from liquid to solid, grain boundaries can be formed in the region with a slow cooling rate due to the growth of crystal grains from the region with a high cooling rate towards the region with a slow cooling rate.

[0100] Multiple crystal grains can be formed in the polycrystalline silicon layer 134. In a plan view, the crystal grains can be randomly arranged. In an exemplary embodiment, the size of the crystal grains can be in the range of about 150 nm to about 200 nm.

[0101] Protrusions can be formed at the grain boundaries on the surface of the polycrystalline silicon layer 134 on which the crystallization process has been performed. The protrusions can protrude upward from the surface of the polycrystalline silicon layer 134 and can have a sharp tip. The protrusions can have a thickness (depth) corresponding to the distance from the surface of the polycrystalline silicon layer 134 to the end of the protrusions.

[0102] The RMS value of the surface roughness of the polysilicon layer 134 may be about 4 nm or less. For example, the RMS value of the thickness of the protrusions formed on the surface of the polysilicon layer 134 may be about 4 nm or less.

[0103] Referring Figure 11 , the polysilicon layer 134 may be etched to form a polysilicon pattern 136. The polysilicon layer 134 may be etched by photolithography. For example, a photoresist pattern may be formed on the polysilicon layer 134 using an exposure process and a development process, and the polysilicon layer 134 may be etched using the photoresist pattern as an etch stop layer.

[0104] Referring Figure 12 , a gate insulating layer 140 may be formed on the polysilicon pattern 136. The gate insulating layer 140 may be disposed on the buffer layer 120 and may cover the polysilicon pattern 136. The gate insulating layer 140 may insulate the gate electrode GE from the polysilicon pattern 136. For example, the gate insulating layer 140 may be formed of silicon oxide, silicon nitride, etc.

[0105] In an exemplary embodiment, the polysilicon pattern 136 having an RMS value of surface roughness of about 4 nm or less may be formed such that the polysilicon pattern 136 may have a relatively low surface roughness. Accordingly, the influence of the protrusions formed on the surface of the polysilicon pattern 136 on the gate insulating layer 140 formed thereon may be minimized, and the gate insulating layer 140 may be relatively thin. For example, the thickness (depth) of the gate insulating layer 140 may be in the range of about 30 nm to about 200 nm.

[0106] Referring Figure 13 , the gate electrode GE may be formed on the gate insulating layer 140.

[0107] The gate electrode GE may overlap with the polysilicon pattern 136. The gate electrode GE may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers. For example, the gate electrode GE may include a three-layer of Mo, Al, and Mo, a two-layer of Cu and Ti, etc.

[0108] For example, a first metal layer and a photoresist pattern overlapping with the polysilicon pattern 136 may be formed on the gate insulating layer 140. Then, the first metal layer may be etched using the photoresist pattern to form the gate electrode GE.

[0109] Referring Figure 14 , ions may be implanted into a part of the polysilicon pattern 136 to form an active pattern AP.

[0110] The polysilicon pattern 136 can be partially doped by an ion implantation process such that an active pattern AP including a source region SR, a channel region CR, and a drain region DR can be formed. The ions can be n-type impurities or p-type impurities.

[0111] The ions can be undoped and remain in a portion of the polysilicon pattern 136 that overlaps with the gate electrode GE, thereby forming the channel region CR. The ion-doped portion of the polysilicon pattern 136 can have increased conductivity and can have conductive properties such that the source region SR and the drain region DR can be formed. The channel region CR can be formed between the source region SR and the drain region DR.

[0112] In an exemplary embodiment, by doping impurities at a concentration lower than that of the ion implantation process, low-concentration doped regions can be formed between the channel region CR and the source region SR and between the channel region CR and the drain region DR, respectively. The low-concentration doped regions can be used as buffers in the active pattern AP such that the electrical characteristics of the thin film transistor TR can be improved.

[0113] Referring to Figure 15 , an insulating intermediate layer 150 can be formed on the gate electrode GE. The insulating intermediate layer 150 can be disposed on the gate insulating layer 140 and can cover the gate electrode GE. The insulating intermediate layer 150 can insulate the source electrode SE and the drain electrode DE from the gate electrode GE.

[0114] The insulating intermediate layer 150 can include an inorganic insulating layer, an organic insulating layer, or a combination thereof. For example, the insulating intermediate layer 150 can include silicon oxide, silicon nitride, silicon carbide, or a combination thereof, and can also include insulating metal oxides such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. When the insulating intermediate layer 150 includes an organic insulating layer, the insulating intermediate layer 150 can include polyimide, polyamide, acrylic resin, phenolic resin, benzocyclobutene (BCB), etc.

[0115] Then, the insulating intermediate layer 150 and the gate insulating layer 140 can be partially etched to form a first contact hole CH1 and a second contact hole CH2 that respectively expose the source region SR and the drain region DR.

[0116] Referring to Figure 8 , the source electrode SE and the drain electrode DE that are respectively electrically connected to the source region SR and the drain region DR of the active pattern AP can be formed on the insulating intermediate layer 150.

[0117] For example, the second metal layer may be formed on the insulating intermediate layer 150 and patterned to form a source electrode SE in contact with the source region SR and a drain electrode DE in contact with the drain region DR. For example, each of the source electrode SE and the drain electrode DE may include Au, Ag, Al, Cu, Ni, Pt, Mg, Cr, W, Mo, Ti, or an alloy thereof, and may have a single-layer structure or a multi-layer structure including different metal layers. For example, each of the source electrode SE and the drain electrode DE may include a three-layer of Mo, Al, and Mo, a bilayer of Cu and Ti, etc.

[0118] In the illustrated embodiment, a cleaning process using hydrofluoric acid and a rinsing process using hydrogenated deionized water may be performed before the crystallization process so that a thin-film transistor TR having improved characteristics (such as threshold voltage, hysteresis, etc.) can be formed.

[0119] Hereinafter, reference will be made to Figures 16 to 19 a display device and a method of manufacturing the display device will be described.

[0120] Referring to Figure 16 , a display device according to an exemplary embodiment may include signal lines and a plurality of pixels PX connected to the signal lines and arranged in a substantially matrix form.

[0121] The signal lines may include gate lines GL for transmitting gate signals (or scan signals), data lines DL for transmitting data voltages, and a driving voltage line PL for transmitting a driving voltage ELVDD. The gate lines GL may extend along a substantially row direction. The data lines DL and the driving voltage line PL may cross the gate lines GL and may extend along a substantially column direction. Each pixel PX may include a driving transistor TR1, a switching transistor TR2, a storage capacitor CST, and an organic light-emitting diode OLED.

[0122] The driving transistor TR1 may include a control terminal connected to the switching transistor TR2, an input terminal connected to the driving voltage line PL, and an output terminal connected to the organic light-emitting diode OLED. The driving transistor TR1 may transmit an output current Id whose amplitude varies depending on the voltage between the control terminal and the output terminal of the driving transistor TR1 to the organic light-emitting diode OLED.

[0123] The switching transistor TR2 may include a control terminal connected to the gate line GL, an input terminal connected to the data line DL, and an output terminal connected to the driving transistor TR1. The switching transistor TR2 may transmit the data voltage applied to the data line DL to the driving transistor TR1 in response to a gate signal applied to the gate line GL.

[0124] The storage capacitor CST can be connected to the control terminal and the input terminal of the driving transistor TR1. The storage capacitor CST can store the data voltage applied to the control terminal of the driving transistor TR1 and can hold the data voltage after the switching transistor TR2 is turned off.

[0125] The organic light-emitting diode OLED can include an anode connected to the output terminal of the driving transistor TR1 and a cathode connected to the common voltage ELVSS. The organic light-emitting diode OLED can emit light with different brightness depending on the output current Id of the driving transistor TR1 to display an image.

[0126] In an exemplary embodiment, each pixel PX can include two thin-film transistors TR1 and TR2 and one storage capacitor CST. However, the exemplary embodiment is not limited thereto. For example, in other exemplary embodiments, each pixel PX can include three or more thin-film transistors and two or more capacitors.

[0127] Figure 17 is a cross-sectional view showing a display device according to an exemplary embodiment.

[0128] Referring to Figure 17 , a display device according to an exemplary embodiment can include a substrate 110, a thin-film transistor TR1 disposed on the substrate 110, and a display element disposed on the thin-film transistor TR1. In an exemplary embodiment, the display device can include an organic light-emitting diode OLED as the display element. However, the illustrated embodiment is not limited thereto, and in other exemplary embodiments, the display device can include a liquid crystal element, an electrophoretic element, an electro-wetting element, etc.

[0129] Figure 17 The thin-film transistor TR1 and the organic light-emitting diode OLED shown in Figure 16 can respectively correspond to the driving transistor TR1 and the organic light-emitting diode OLED shown in Figure 8 . A display device according to an exemplary embodiment can include a thin-film transistor substrate 100 according to the exemplary embodiment shown in

[0130] The organic light-emitting diode OLED can include a first electrode E1, an emission layer 180, and a second electrode E2 stacked in sequence. The organic light-emitting diode OLED can emit light based on the driving current received from the thin-film transistor TR1 to display an image.

[0131] Figure 18 and Figure 19 is a view showing Figure 17A cross-sectional view of an exemplary manufacturing method of a display device. Hereinafter, descriptions of elements of the manufacturing method of the display device according to an exemplary embodiment that are substantially the same as or similar to those of the manufacturing method of the thin-film transistor substrate according to the exemplary embodiment may not be repeated to avoid redundancy.

[0132] Referring to Figure 18 , a first electrode E1 may be formed on the thin-film transistor TR1.

[0133] First, a planarization layer (or passivation layer) 160 may be formed on the source electrode SE and the drain electrode DE. The planarization layer 160 may be disposed on the insulating intermediate layer 150 and may cover the source electrode SE and the drain electrode DE.

[0134] The planarization layer 160 may include an inorganic insulating layer, an organic insulating layer, or a combination thereof. For example, the planarization layer 160 may have a single-layer structure or a multi-layer structure including silicon nitride or silicon oxide. When the planarization layer 160 includes an organic insulating layer, the planarization layer 160 may include polyimide, polyamide, acrylic resin, phenolic resin, BCB, etc.

[0135] Then, the planarization layer 160 may be patterned to form a contact hole exposing the drain electrode DE.

[0136] Then, a first electrode E1 may be formed on the planarization layer 160. The first electrode E1 may be connected to the drain electrode DE. For example, a third metal layer may be formed on the planarization layer 160 and patterned to form the first electrode E1 in contact with the drain electrode DE.

[0137] The first electrode E1 may be a pixel electrode of the display device. Depending on the emission type of the display device, the first electrode E1 may be formed as a transmissive electrode or a reflective electrode. When the first electrode E1 is formed as a transmissive electrode, the first electrode E1 may include indium tin oxide (ITO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium oxide (In2O3), zinc oxide (ZnO), tin oxide (SnO2), etc. When the first electrode E1 is formed as a reflective electrode, the first electrode E1 may include Au, Ag, Al, Cu, Ni, Pt, Mg, Cr, W, Mo, Ti, etc., and may have a multi-layer structure including the materials used for the transmissive electrode.

[0138] Then, a pixel defining layer 170 may be formed on the planarization layer 160. The pixel defining layer 170 may have an opening exposing at least a part of the first electrode E1. For example, the pixel defining layer 170 may include an organic insulating material.

[0139] Referring to Figure 19 , an emission layer 180 may be formed on the first electrode E1.

[0140] The emission layer 180 may be formed on the upper surface of the first electrode E1 exposed by the opening of the pixel defining layer 170. For example, the emission layer 180 may be formed by methods such as screen printing, inkjet printing, evaporation coating, etc.

[0141] The emission layer 180 may include a low molecular weight polymer or a high molecular weight polymer. For example, the emission layer 180 may include copper phthalocyanine, N,N'-diphenylbenzidine, tris(8-hydroxyquinoline)aluminum, etc. as low molecular weight polymers. The emission layer 180 may include poly(3,4-ethylenedioxythiophene), polyaniline, polyphenylene vinylene, polyfluorene, etc. as high molecular weight polymers.

[0142] In an exemplary embodiment, the emission layer 180 may emit red light, green light, or blue light. In another exemplary embodiment, when the emission layer 180 emits white light, the emission layer 180 may have a multilayer structure including a red emission layer, a green emission layer, and a blue emission layer, or a single layer structure including a red emission material, a green emission material, and a blue emission material.

[0143] In an exemplary embodiment, a hole injection layer and / or a hole transport layer may also be formed between the first electrode E1 and the emission layer 180, or an electron transport layer and / or an electron injection layer may also be formed on the emission layer 180.

[0144] Refer to Figure 17 , a second electrode E2 may be formed on the emission layer 180.

[0145] The second electrode E2 may be a common electrode of the display device. Depending on the emission type of the display device, the second electrode E2 may be formed as a transmissive electrode or a reflective electrode. For example, when the second electrode E2 is formed as a transmissive electrode, the second electrode E2 may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a composition thereof.

[0146] The display device may be a top emission type in which light is emitted toward the second electrode E2. However, the exemplary embodiment is not limited thereto, and the display device may also be a bottom emission type.

[0147] The display device according to the exemplary embodiment may be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, MP3 players, etc.

[0148] Although specific exemplary embodiments and implementations of methods for manufacturing a polysilicon layer, a thin film transistor substrate and methods for manufacturing the same, and a display device and methods for manufacturing the same have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, it will be apparent to those of ordinary skill in the art that the inventive concept is not limited to these embodiments, but rather to the broader scope of the appended claims and various obvious variations and equivalent arrangements.

Claims

1. A method for manufacturing a polysilicon layer for a display device, the method comprising the following steps: Forming an amorphous silicon layer on a substrate; Cleaning the amorphous silicon layer with hydrofluoric acid; Rinsing the amorphous silicon layer with hydrogenated deionized water; And Irradiating the amorphous silicon layer with a laser beam to form a polysilicon layer, Among them, the laser beam has an energy density in the range of 450 mJ / cm 2 to 500 mJ / cm 2 , and wherein the polysilicon layer has a grain size in the range of 150 nm to 200 nm.

2. The method according to claim 1, wherein, The hydrofluoric acid includes 0.5% by weight of hydrogen fluoride.

3. The method according to claim 1, wherein, The amorphous silicon layer is cleaned for 40 seconds to 54 seconds.

4. The method according to claim 1, wherein, During the step of forming the amorphous silicon layer, a native oxide layer is formed on the amorphous silicon layer, and During the step of cleaning the amorphous silicon layer, the native oxide layer is removed.

5. The method according to claim 1, wherein The hydrogenated deionized water has a hydrogen concentration of 1.0 ppm.

6. The method according to claim 1, wherein The laser beam has a width of 480 μm, and The laser beam has a scan pitch in the range of 9 μm to 30 μm.

7. The method according to claim 1, wherein The polysilicon layer has a surface roughness with a root mean square value of 4 nm or less.

8. The method according to claim 1, wherein After the step of forming the polysilicon layer, protrusions are formed on the surface of the polysilicon layer, and The protrusions have sharp tips.

9. The method according to claim 1, wherein, The polysilicon layer has randomly arranged grains.

10. The method according to claim 1, further comprising the following steps: Forming a buffer layer on the substrate before forming the amorphous silicon layer.

11. A display device, comprising: A substrate; A thin film transistor disposed on the substrate; And A display element disposed on the thin film transistor, wherein the thin film transistor includes: An active pattern disposed on the substrate, the active pattern having a surface roughness with a root mean square value of 4 nm or less; A gate insulating layer disposed on the active pattern; and A gate electrode disposed on the gate insulating layer, Among them, the active pattern has a grain size in the range of 150 nm to 200 nm and is formed of a polysilicon layer obtained by irradiating an amorphous silicon layer with a laser beam having an energy density in the range of 450 mJ / cm 2 to 500 mJ / cm 2 .

12. The display device according to claim 11, wherein, Protrusions are formed on the surface of the active pattern, and The protrusions have sharp tips.

13. The display device according to claim 11, wherein, The active pattern includes randomly arranged grains.

14. The display device according to claim 11, wherein, The active pattern includes a source region, a drain region, and a channel region formed between the source region and the drain region.

15. The display device according to claim 14, wherein, The gate electrode overlaps the channel region of the active pattern.

16. The display device according to claim 14, wherein, The thin film transistor further includes: A source electrode and a drain electrode disposed on the gate electrode, the source electrode and the drain electrode being electrically connected to the source region and the drain region of the active pattern, respectively.

17. The display device according to claim 11, wherein, The display element includes: A first electrode electrically connected to the thin film transistor; An emission layer disposed on the first electrode; and A second electrode disposed on the emission layer.

18. A method for manufacturing a display device, the method comprising the following steps: Forming an amorphous silicon layer on a substrate; Cleaning the amorphous silicon layer with hydrofluoric acid; Rinsing the amorphous silicon layer with hydrogenated deionized water; Irradiating the amorphous silicon layer with a laser beam to form a polysilicon layer; Etching the polysilicon layer to form a polysilicon pattern; Forming a gate insulating layer on the polysilicon pattern; Forming a gate electrode on the gate insulating layer; Ion implantation is performed on a part of the polysilicon pattern to form an active pattern; and a display element is formed on the gate electrode, Among them, the step of irradiating the amorphous silicon layer with the laser beam includes: irradiating with the laser beam having an energy density in the range of 450 mJ / cm 2 to 500 mJ / cm 2 and wherein the polysilicon layer has a grain size in the range of 150 nm to 200 nm.

19. The method according to claim 18, wherein, The hydrofluoric acid includes 0.5% by weight of hydrogen fluoride.

20. The method according to claim 18, wherein The step of cleaning the amorphous silicon layer includes: cleaning for 40 seconds to 54 seconds.

21. The method according to claim 18, wherein The step of rinsing the amorphous silicon layer with the hydrogenated deionized water includes: rinsing with the hydrogenated deionized water having a hydrogen concentration of 1.0 ppm.

22. The method according to claim 18, further comprising the step of: forming a source electrode and a drain electrode on the gate electrode, the source electrode and the drain electrode being electrically connected to the active pattern.

23. The method according to claim 18, wherein The step of forming the display element includes the following steps: forming a first electrode on the gate electrode, the first electrode being electrically connected to the active pattern; forming an emission layer on the first electrode; and forming a second electrode on the emission layer.

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