Charge pump circuit with improved discharge and corresponding discharge method

Abstract

Embodiments of the present disclosure relate to a charge pump circuit with improved discharge and a corresponding discharge method. The charge pump circuit has a plurality of charge pump stages cascaded to each other between an input terminal and an output terminal to provide an output voltage having a boosted value relative to an input voltage. A clock generator is configured to generate a clock signal provided to the charge pump stage to perform a boost of the input voltage. An output voltage regulation feedback loop is coupled to the clock generator to perform regulation of the output voltage based on a feedback voltage. A discharge control stage is configured to control the discharge of the charge pump circuit by generating a first discharge control signal configured to disable the output voltage regulation feedback loop or a second discharge control signal configured to reduce the frequency of the clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian patent application serial number 102018000010482 filed on November 21, 2018, which is hereby incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to electronic systems and methods and, in particular embodiments, to a charge pump circuit with improved discharge and a corresponding method for improved discharge of a charge pump circuit. Background Art

[0004] As is known to all, charge pump circuits are often widely used in various electronic devices and applications to generate an output voltage value higher than a given input voltage by utilizing clocked charge transfer between capacitors used as charge accumulation elements (basically operating as a DC-DC boost converter).

[0005] In particular, in SoC (System on Chip) applications, it is often necessary to generate an internal high voltage in order to drive a specific circuit module to an appropriate voltage value for a specific operation. Typically, a charge pump circuit is used for this purpose.

[0006] A common example is the case of non-volatile memories, for example of the Flash or EEPROM type, in which programming and erasing operations are performed by applying high electric fields on the memory cell terminals, using voltages in the range of tens of volts. These voltages are generated internally by charge pump circuits, starting from a low value of the internal supply voltage (the so-called logic supply voltage VDD, whose value is for example comprised between 1 V and 1.35 V - for CMOS Flash devices in 90 nanometer technology).

[0007] Typical manufacturing processes for applications in which these internal high voltages are developed do not provide high voltage MOS transistors (i.e., transistors capable of sustaining high voltage values ​​between their conduction and control terminals). Therefore, the generation of the internal high voltage is usually managed using appropriate charge pump circuits (e.g., voltage doublers, Dickson charge pump circuits) with a "low voltage" architecture, which are usually composed of a series of boosting stages (e.g., voltage doublers).

[0008] Due to the lack of high voltage MOS transistors, charge pump architectures are usually designed to not exceed safe operating area (SOA) requirements (e.g. in terms of junction breakdown voltage and / or gate oxide degradation) using appropriate techniques to generate some kind of "internal self-cascading" to achieve high output voltages (i.e., each boost stage is protected by the previous stage in the series connection and therefore presents a low and sustainable voltage at both its input and output terminals).

[0009] Figure 1 A schematic block diagram of a known charge pump circuit 1 with a low voltage architecture is shown.

[0010] The charge pump circuit 1 has an input terminal IN, at which it receives an input voltage having a low value, such as a logic power supply voltage VDD, and an output terminal OUT, at which it supplies an output voltage Vout for a load (not shown here). The output voltage Vout has an appropriate boost value relative to the input voltage.

[0011] The charge pump circuit 1 includes a plurality of charge pump stages 2 (in this example, four in number, indicated by Stage 1, Stage 2, Stage 3, and Stage 4) cascaded (or connected in series) between an input terminal IN and an output terminal OUT. The charge pump circuit 1 also includes a clock generator 3 that provides a clock or phase signal CLK to each of the stages 2.

[0012] In this example, each stage 2 receives from a clock generator 3 a first clock signal CLK and a second clock signal CLKN, which have negative (or complementary) values ​​relative to each other, for example logical values ​​alternately equal to 0 V (ground, GND) or VDD.

[0013] There are intermediate nodes NS (noted NS1 - NS3 in the example) between consecutive stages 2 in the charge pump circuit 1 (intermediate nodes NS thus generally correspond to the output of the preceding charge pump stage Stagei-1 and to the input of the next charge pump stage Stagei).

[0014] Each charge pump stage Stagei is configured to boost the voltage at the output of the previous charge pump stage Stagei-1, for example to a value corresponding to the logic voltage VDD, thereby collectively contributing to the overall boosting of the input voltage.

[0015] In an exemplary solution not discussed in detail here, the charge pump stage 2 only envisages low-voltage transistors (e.g., with a maximum sustainable voltage not higher than the logic voltage VDD), and can be of the so-called latch type. Each charge pump stage 2 can include: a first pumping capacitor and a second pumping capacitor, receiving a first low-voltage clock signal CLK or a second low-voltage clock signal CLKN; and a latch circuit, which provides a switch designed to be able to selectively and alternately transfer the charge accumulated in the pumping capacitor from one stage to another. In particular, the transfer of charge is performed between the first pumping capacitors of consecutive stages in the first half cycle of the clock signal CLK, and between the second pumping capacitors of consecutive stages in the second half cycle of the same clock signal CLK, thereby ensuring a boosting effect between the corresponding input and output terminals.

[0016] The charge pump circuit 1 further comprises an output voltage detection stage 4 which is coupled to the output terminal OUT and is designed to provide a feedback voltage Vf according to the output voltage Vout.

[0017] In this example, the output voltage detection stage 4 implements a so-called "resistance ladder" and comprises a plurality of load elements 5, which in this example are connected in series between the output terminal OUT and a reference terminal (e.g., ground, GND), providing a voltage divider. The feedback voltage Vf is the voltage at the intermediate node COMP between the consecutive resistor elements 5 and is given by the corresponding division of the output voltage Vout.

[0018] The charge pump circuit 1 further comprises a comparator stage 6 implemented via an operational amplifier having a comparison input coupled to the output voltage detection stage 4 (coupled to the intermediate node COMP) to receive the feedback voltage Vf and a reference input receiving a reference voltage Vref having a suitable value.

[0019] The comparator stage 6 generates a stop signal St, which is provided to the clock generator 3, based on the comparison result between the feedback voltage Vf and the reference voltage Vref. In particular, a given value of the stop signal St, such as a high value (indicating that the desired value for the output voltage Vout set by the reference voltage Vref is reached), determines that the clock generator 3 stops the clock signal generation, and thereby stops the charge transfer of the boost operation between the charge pump stages 2.

[0020] Therefore, the output voltage detection stage 4 and the comparator stage 6 jointly implement a closed-loop regulation of the output voltage Vout of the charge pump circuit 1 based on the reference voltage Vref.

[0021] Even though the charge pump architecture discussed above is heavily used to generate a high voltage output, it is also necessary to have a similar method to discharge the charge pump circuit 1, i.e., its output terminal OUT and the intermediate node NS, when a low voltage value must be connected to the same output terminal OUT. For example, in non-volatile memory applications, read operations typically require a low voltage output, while programming operations typically require a boosted high voltage value.

[0022] Several methods of discharging a charge pump circuit (ie, output terminals and internal charge pump nodes) can be used and have been proposed. Discharging a charge pump circuit usually means using different and additional circuits including dedicated discharge modules, with corresponding increases in area usage and power consumption.

[0023] Figure 2 An example of a discharge circuit 8 is schematically shown, which is designed to be operably coupled in parallel to a charge pump circuit (eg, Figure 1 The charge pump circuit 1 is not shown in detail here).

[0024] A typical discharge technique is based on introducing complex external discharge stages (denoted by DISCH1, DISCH2, DISCH3, ..., DISCHn) to define different discharge paths relative to a fixed or variable supply (using controlled currents, or low resistance paths, or equivalent methods). This approach usually requires design attention to avoid problems with the safe operating area due to the need to be compatible with intermediate high voltage nodes or medium voltage nodes (such as NS1, NS2, ... or related nodes) of the charge pump stage.

[0025] Alternatively, a single output discharge structure (DISCH out, Figure 2 This means that control of the safe operating area is even more challenging. Summary of the invention

[0026] This general approach has a number of disadvantages:

[0027] Since it is required to connect the intermediate internal nodes of the charge pump (e.g., NS1, NS2, ... or related nodes) to the discharge path, this means connecting parasitic capacitance to the charge pump nodes, which may impair the performance of the charge pump;

[0028] All internal nodes of the charge pump circuit and the discharge path must respect the safe operating area requirements for all transistors in the circuit every time. This means that all nodes must move with the same dynamics in order not to determine unexpected voltage differences across the transistor terminals (independent of performance due to capacitive loads, performance of individual transistors, process / temperature variations); and

[0029] Using the above-described discharge method in a negative charge pump architecture may create other problems in managing the discharge path, for example due to parasitic diodes.

[0030] Embodiments of the present invention provide a solution which enables the drawbacks of the known techniques to be overcome. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] For a better understanding of the present invention, preferred embodiments of the present invention will now be described, by way of non-limiting examples only, with reference to the accompanying drawings, in which:

[0032] Figure 1 is a schematic block diagram of a known charge pump circuit;

[0033] Figure 2 yes Figure 1 A schematic diagram of a known discharge structure of a charge pump circuit;

[0034] Figure 3 is a schematic block diagram of a charge pump circuit with improved discharge according to an embodiment of the present solution;

[0035] Figure 4 is based on Figure 3 A flow chart of a discharge operation of a discharge method in a charge pump circuit;

[0036] Figure 5A and Figure 5B Shown with Figure 3 a diagram of quantities related to the operation of the charge pump circuit; and

[0037] Figure 6 Another aspect of the present solution is shown. Figure 3 A schematic block diagram of a charge pump circuit of a nonvolatile memory device. DETAILED DESCRIPTION

[0038] As will be discussed in detail below, one aspect of the present solution contemplates using already existing circuit stages and modules in the charge pump circuit (i.e., a clock generator and a closed-loop regulation stage for generating a clock signal) to achieve the discharge of the output terminal and the internal node, i.e., no additional discharge circuit is required. Appropriate control signals are generated and provided to the already existing charge pump circuit stages to control the discharge operation. Thus, a more efficient and easily integrated method is provided to manage the discharge of a common high voltage charge pump implemented in "low voltage" CMOS technology.

[0039] Figure 3 FIG. 2 shows a charge pump circuit 20 with improved discharge according to an embodiment of the present solution. The charge pump circuit 20 has substantially the same Figure 1A circuit architecture corresponding to the charge pump circuit 1 of FIG. 1 (so that elements corresponding to those already discussed are denoted by the same reference numerals and are not discussed in detail again).

[0040] Therefore, as previously referenced Figure 1 As discussed, the charge pump circuit 20 comprises:

[0041] a series of charge pump stages 2 connected in cascade between an input terminal IN receiving an input voltage VDD and an output terminal OUT providing an output voltage Vout;

[0042] a clock generator 3 which provides a clock signal CLK (in this example, first and second clock signals CLK and CLKN) to control the boosting operation of the charge pump stage 2, in particular the capacitive charge transfer for the voltage boosting effect; and

[0043] The output voltage regulation feedback loop is used to control the value of the output voltage Vout based on the reference voltage Vref. The output voltage regulation feedback loop includes an output voltage detection stage 4 and a comparator stage 6. When the desired value of the output voltage Vout set by the reference voltage Vref is reached, the comparator stage 6 provides a stop signal St to the clock generator 3 to stop the clock signal generation and thereby stop the charge transfer of the boost operation between the charge pump stages 2.

[0044] According to one aspect of some embodiments, the charge pump circuit 20 further includes a discharge control stage 22 configured to generate a discharge control signal to implement a discharge operation of the output voltage Vout (and a voltage at an intermediate node NS between the charge pump stages 2 ).

[0045] The discharge control stage 22 may be implemented by the control stage of the charge pump circuit 20 (whose management operation is known per se and will not be discussed in detail here), or may be implemented as a separate and additional control unit.

[0046] In particular, in one embodiment, the discharge control stage 22 is operably coupled to the charge pump circuit 20, in particular to the output voltage regulation feedback loop and the clock generator 3, and is configured to generate one or more of the following control signals (all having low voltage values):

[0047] a control signal Sc1 designed to increase the current load of the charge pump circuit 20 and thereby cause it to “overload” (as discussed in more detail below);

[0048] a control signal Sc2 designed to disable the output voltage regulation feedback loop (again, as discussed in more detail below); and

[0049] The control signal Sc3 is designed to reduce the frequency of the clock signal CLK that controls the clock operation of the charge pump circuit 20 .

[0050] In some embodiments, the control signal Sc1 is provided to the output voltage detection stage 4 and is designed to increase the current load on the output terminal OUT by bypassing or short-circuiting ("shorting") one or more load elements 5 of the same output voltage detection stage 4. In this example, when the control signal Sc1 is valid (asserted); the control signal Sc1 controls the opening / closing of the load switch 24, which is connected in parallel to a corresponding one of the load elements 5 (e.g., a resistor element of a resistor ladder coupled to the output terminal OUT). For example, in one embodiment, the control signal Sc1 is asserted by having a high value. When the control signal Sc1 is asserted, the load switch 24 is closed and the corresponding load element 5 is short-circuited, thereby causing an increase in the current load of the charge pump circuit 20 and a corresponding drop in the output voltage Vout.

[0051] In practice, the charge pump circuit 20 is typically designed to maintain a quiescent current of the output voltage detection stage 4 (a resistor ladder in this example), based on a qualitative relationship that can be given by:

[0052]

[0053] Wherein, CLK_Freq is the clock frequency of the clock generator 3, ie, the frequency of the clock signal CLK, Stage_Cap is the capacitance value of a single charge pump stage 2 of the charge pump circuit 20, and Iload is the output load current at the output terminal OUT.

[0054] As shown in the above expression [1], an increase in the output load current Iload causes a corresponding decrease in the output voltage Vout, thereby facilitating the discharge of the output terminal OUT of the charge pump circuit 20 .

[0055] It is emphasized that the load switch 24 can be coupled at any point between the ground reference GND and the intermediate node COMP on which the feedback voltage Vf is present (i.e., within the lower side of the resistor ladder); or, alternatively, at any point between the same intermediate node COMP and the output terminal OUT (i.e., within the upper side of the resistor ladder). One or more load switches 24 on the lower side and one or more load switches 24 on the upper side of the same resistor ladder can also be envisaged. The decision on where to place the load switch(es) 24 can depend, for example, on the voltage values ​​across the terminals of the same load switch(es) 24 that should comply with the SOA requirements (because in a typical embodiment, the load switches 24 are implemented with low-voltage CMOS transistors).

[0056] When the charge pump circuit 20 has to be discharged, the control signal Sc2 is supplied to the comparator stage 6 and is designed to disable the same comparator stage 6 (and the comparison operation between the feedback voltage Vf and the reference voltage Vref).

[0057] In particular, the comparator stage 6 is disabled (e.g., the control signal Sc2 is active (asserted), such as having a high value, for example) in order to keep the clock generator 3 free running during the discharge operation. Therefore, the clock generator 3 will continue clock signal generation throughout the discharge phase, even if the output voltage regulation feedback loop is disabled during the same discharge phase.

[0058] Control signal S c3 is provided to the clock generator 3 and is designed to cause a reduction in its clock frequency, i.e. the frequency of the clock signal CLK is reduced from a first frequency value CLK_Freq to a second frequency value CLK_Freq', wherein the second frequency value CLK_Freq' is lower than the first frequency value CLK_Freq. This frequency reduction can be obtained, for example, by reducing the current supplied to the clock generator oscillator without adding circuit modules.

[0059] Referring to the same expression [1] discussed above, it is apparent that a decrease in the frequency of the clock signal CLK causes a further overload of the charge pump circuit 20, which produces a further drop in the output voltage Vout.

[0060] In addition to increasing the load current Iload during discharge, the new frequency value therefore defines the timing and performance of the discharge operation. As shown in the above expression [1], the clock frequency CLK_Freq is related to the output voltage V out Directly proportional.

[0061] Without considering the contribution of the current load increase, in order to obtain the output voltage V out The desired reduction in frequency must be at most the output voltage V after discharge to retain the SOA requirement. out The expected value is the same as during normal high voltage operation output voltage V out In some embodiments, the design allows the output terminal OUT to be discharged and achieve the desired output voltage V out The maximum timing of the reduction is given to give a constraint on the minimum value for the same frequency reduction factor.

[0062] For example, possible values ​​of the frequency reduction factor are comprised between 10 and 20 (eg the second frequency value CLK_Freq′ is 1 / 10 or 1 / 20 of the first frequency value CLK_Freq).

[0063] It is emphasized that the proposed discharge technique uses a reduced clock frequency, but does not require stopping the clock generation (i.e., the second frequency value CLK_Freq' is higher than zero). In fact, since the charge pump circuit 20 is still working during the discharge phase (i.e., the voltage boosting effect is still operating), despite the performance degradation caused by the continuous presence of the clock signal CLK supplied to all charge pump stages 2, an "overload transfer effect" from the output terminal OUT to each charge pump stage 2 of the charge pump circuit 20 can be achieved. Therefore, all intermediate nodes NS (NS1, NS2, ...) of the same charge pump circuit 20 are discharged while maintaining an appropriate voltage difference between consecutive intermediate nodes NS.

[0064] In other words, unlike the discharge methods known in the art, the intermediate node NS also maintains a "self-cascade" architecture during the charge pump discharge, because the charge pump is still operating. This avoids problems in the safe operating area for all MOS transistors of the circuit.

[0065] refer to Figure 4 , possible operations of the charge pump circuit 20 are discussed with particular reference to a discharge process, according to an embodiment of the present invention.

[0066] As shown at step 30, the operation of the charge pump circuit 20 is started to establish a high voltage operation, that is, to generate a high value output voltage V at the output terminal OUT. out .

[0067] Therefore, as shown at step 31, the control signal managed by the discharge control stage 22 is set to an inactive state. For example, in this embodiment, the control signal S c1 , S c2 and S c3 is set to a low value ("0").

[0068] Then, as shown at step 32, high voltage operation of the charge pump circuit 20 is performed until it is determined (at step 33) that a discharge of the charge pump circuit 20 must be performed (because low voltage operation is required).

[0069] Then the discharge process of the charge pump circuit 20 begins. Specifically, at step 34, the discharge control stage 22 controls the signal S c1 is set to an active state in order to increase the load current Iload at the output terminal OUT of the same charge pump circuit 20 .

[0070] Then, at step 35, the same discharge control stage 22 controls the signal S c2 is set to the active state in order to disable the comparator stage 6 and maintain free running operation of the clock oscillator as long as the discharge operation is performed.

[0071] Then, at step 36, the discharge control stage 22 controls the signal S c3 is set to the active state, thereby causing a reduction in the clock frequency and thereby determining a further overloading of the charge pump circuit 20 .

[0072] Then, at step 37, the complete discharge of the charge pump circuit 20 is monitored, for example, by monitoring the elapse of a preset discharge time or the output voltage V out or monitors a suitable decrease in the voltage value of one or more intermediate nodes NS.

[0073] When the discharge is completed, the charge pump circuit 20 stops and uses the output voltage V out or the voltage of one or more intermediate nodes NS of the same charge pump circuit 20 to perform low voltage operation, as shown at step 38 .

[0074] If it is determined at step 39 that a new high voltage operation is to be performed, then at step 40 a new charge pump configuration is applied and operation then returns to step 30 for a new start of charge pump circuit 20 .

[0075] Otherwise, after the low voltage operation, as shown at step 41 , the operation of the charge pump circuit 20 is terminated.

[0076] Figure 5A As shown in the above reference Figure 4 Graph of the output voltage Vout and the voltages of the intermediate nodes NS1 - NS6 of the charge pump circuit 20 denoted V( NS1 )-V( NS6 ) during the operation in question (in this case with a number of charge pump stages 2 equal to 7).

[0077] Figure 5B The corresponding diagram shows the clock signal CLK generated by the clock generator 3.

[0078] like Figure 5A As shown in FIG. , after the charge pump circuit 20 is established for high voltage operation, the output voltage V out The voltage V(NS1)-V(NS6) at the intermediate nodes NS1-NS6 rises until it reaches the desired high value (in this case, the output voltage V out is approximately 20V, and the voltages at the intermediate nodes NS1-NS6 are correspondingly reduced values, with the difference between the intermediate voltage values ​​of each consecutive charge pump stage 2 being approximately 2V).

[0079] At the end of the high voltage operation, at time t d At , the discharge of the charge pump circuit 20 is performed, as discussed in detail above. Figure 5AAs shown in FIG. 1 , the output voltage Vout and the voltages V(NS1)-V(NS6) of the intermediate nodes NS1-NS6 decrease until they reach the desired low value (in this case, the output voltage V out A value of about 6.9 V, considering an SOA value of about 7 V), allows the circuit to operate safely and correctly in low voltage conditions after the discharge phase.

[0080] In particular, it can be noted that all intermediate charge pump voltages discharge correctly without adding to each other and all remain at the charge pump output voltage V out (In other words, during discharge, even if the mutual difference between the voltages V(NS1)-V(NS6) of the intermediate nodes NS1-NS6 decreases, the same voltage relationship is maintained throughout the discharge phase).

[0081] Figure 5B shows the time t from the start of the discharge phase d The frequency of the clock signal CLK initially decreases from a first frequency value CLK_Freq to a second frequency value CLK_Freq′, and the second frequency value CLK_Freq′ is lower than the first frequency value CLK_Freq (the second frequency value CLK_Freq′ controls the same discharge phase).

[0082] Advantages of some embodiments are clearly apparent from the foregoing description.

[0083] In any case, it is again emphasized that some embodiments provide the following advantages:

[0084] No additional circuitry is needed to manage the discharge operation, thereby eliminating the need for additional area and power consumption;

[0085] The intermediate node NS of the charge pump circuit 20 is not connected to an external node or external circuit for the discharge phase, thereby maintaining the symmetry of the charge pump stage 2;

[0086] Since all modules for discharging are already present and are part of the same charge pump circuit 20, no additional capacity is connected to the charge pump output terminal OUT;

[0087] All control signals S for discharge operation c1 -S c3 All are in the low voltage range, so no additional high voltage circuits are generated to manage them;

[0088] The charge pump intermediate node NS will never exceed the charge pump output voltage V out ;and

[0089] The charge pump output voltage after discharge is V out Reach safe voltage (meet SOA requirements).

[0090] like Figure 6 As schematically shown in FIG. 2 , the charge pump circuit 20 may advantageously be used in a non-volatile memory device 50 , for example of the CMOS Flash type, which comprises an array 51 of memory cells 42 .

[0091] In a manner known per se, the memory cells 42 have their gate terminals connected to the respective word lines WL and their drain terminals connected to the respective bit lines BL. In the schematic illustration shown, the charge pump circuits 20 are connected to the drain terminals of the memory cells 42 by interposing a column decoder 45 .

[0092] In this case, the load of the charge pump circuit 20 is substantially constituted by the capacitance of the bit lines BL of the memory array 51. In this case, the charge pump circuit 20 is used to generate the high programming (writing / erasing) and low reading voltages required by the memory cells 42.

[0093] Same as Figure 6 As shown in FIG. 4 , another charge pump circuit 20 may be connected to a row decoder 46 coupled to a word line WL of a memory cell 42 .

[0094] Finally, it is evident that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present invention as defined in the appended claims.

[0095] In particular, generation of the control signal Sc1 by the discharge control stage 22 may be avoided - even though its presence is preferred as it is beneficial in helping to further reduce the discharge time. In general, the generation of the control signal Sc1 is more beneficial the more capacitive the load of the charge pump circuit 20 is, while the presence of the control signal Sc1 may be more disadvantageous when the quiescent current consumption of the charge pump load is high.

[0096] Similarly, if, for example, the modification made to the output voltage detection stage 4 by the control signal Sc1 (by short-circuiting one or more load elements 5 of the same output voltage detection stage 4) causes the feedback voltage Vf to always be lower than the reference voltage Vref during the discharge phase, thereby disabling the output voltage regulation feedback loop, the generation of the control signal Sc2 can be avoided.

[0097] It is also emphasized that the reduction factor between the first and second frequency values ​​CLK_Freq, CLK_Freq′ of the clock signal CLK may be different (and may also be equal to 1), depending on the specific application requirements.

[0098] Furthermore, it is obvious that the charge pump circuit may find advantageous, though not exclusive, application in non-volatile memory devices to generate the required voltages for programming and reading operations, but other uses are equally conceivable in all cases where it is required to generate a boosted voltage starting from a lower voltage value (and where high voltage transistors cannot be used).

Claims

1. A charge pump circuit, comprising: an input terminal configured to receive an input voltage; Output terminals; a plurality of charge pump stages cascaded to each other between the input terminal and the output terminal, the plurality of charge pump stages being configured to collectively perform a voltage boost on the input voltage to provide an output voltage having a boosted value relative to the input voltage at the output terminal; a clock generator configured to generate a clock signal having a first frequency value, the clock signal being provided to the plurality of charge pump stages to perform the boosting of the input voltage; an output voltage regulation feedback loop coupled to the clock generator and configured to detect a feedback voltage according to the output voltage and to generate a control signal provided to the clock generator to perform regulation of the output voltage based on the feedback voltage, wherein the output voltage regulation feedback loop comprises a voltage detection stage coupled to the output terminal and configured to provide the feedback voltage according to the output voltage; and a discharge control stage configured to control the discharge of the charge pump circuit by generating a first discharge control signal configured to disable the output voltage regulation feedback loop, a second discharge control signal configured to reduce the frequency of the clock signal from the first frequency value to a second frequency value lower than the first frequency value, and further control the discharge of the charge pump circuit by generating a third discharge control signal configured to cause an increase in current load on the output terminal through the voltage detection stage. 2 . The circuit of claim 1 , wherein the discharge control stage is configured to generate the first discharge control signal and the second discharge control signal.

3. The circuit of claim 1, wherein the second frequency value is greater than zero such that the plurality of charge pump stages perform a boost operation during a discharge period of the charge pump circuit. The circuit according to claim 1 , wherein the second frequency value is comprised between 1 / 20 and 1 / 10 of the first frequency value.

5. The circuit of claim 1 , wherein the output voltage regulation feedback closed loop comprises: A comparator stage is configured to perform a comparison between the feedback voltage and a reference voltage and to generate the control signal based on the comparison.

6. The circuit of claim 5 , wherein the voltage detection stage comprises a plurality of load elements, the plurality of load elements being connected in series between the output terminal and a reference terminal to form a voltage divider, the feedback voltage being a voltage at an intermediate node between the plurality of load elements, wherein the third discharge control signal is configured to short-circuit a first load element among the plurality of load elements. 7 . The circuit of claim 6 , wherein the third discharge control signal is configured to selectively close a load switch coupled in parallel with the first load element.

8. The circuit of claim 5, wherein the first discharge control signal is configured to disable the comparator stage.

9. A non-volatile memory device comprising: a memory array comprising a plurality of memory cells; and a charge pump circuit having an output terminal coupled to the memory array, the charge pump circuit being configured to generate a boosted output voltage for a first memory operation and being configured to undergo a discharge to provide a low output voltage for a second memory operation different from the first memory operation, the low output voltage being lower than the boosted output voltage, wherein the charge pump circuit comprises: a plurality of charge pump stages coupled between an input terminal of the charge pump circuit and the output terminal, a clock generator configured to provide a clock signal to the plurality of charge pump stages, an output voltage regulation feedback loop coupled to the clock generator and configured to detect a feedback voltage according to the output voltage and to generate a control signal provided to the clock generator to perform regulation of the output voltage based on the feedback voltage, wherein the output voltage regulation feedback loop comprises a voltage detection stage coupled to the output terminal and configured to provide the feedback voltage according to the output voltage; and A discharge control stage is configured to discharge the charge pump circuit by generating a first discharge control signal or a second discharge control signal, the first discharge control signal is configured to disable a feedback loop of the charge pump circuit, the second discharge control signal is configured to reduce the frequency of the clock signal, and further control the discharge of the charge pump circuit by generating a third discharge control signal, the third discharge control signal is configured to cause an increase in current load on the output terminal through the voltage detection stage.

10. The apparatus of claim 9, wherein the first memory operation comprises a write operation, and wherein the second memory operation comprises a read operation.

11. The apparatus of claim 9, wherein the discharge control stage is configured to generate the first discharge control signal and the second discharge control signal.

12. A method for discharging a charge pump circuit, the method comprising: receiving an input voltage at an input terminal; boosting the input voltage using a plurality of charge pump stages coupled between the input terminal and an output terminal to produce an output voltage at the output terminal; providing a clock signal to the plurality of charge pump stages; as well as Using a comparator of an output voltage regulation feedback closed loop, a stop signal is provided to a clock generator providing the clock signal; receiving a reference voltage by the comparator; as well as receiving, by the comparator, a feedback voltage from a voltage divider coupled to the output terminal, The charge pump circuit is discharged by: disabling the output voltage regulation feedback loop of the charge pump circuit, or reducing the frequency of the clock signal, and Discharging the charge pump circuit includes shorting a resistor of the voltage divider, causing an increase in current load on the output terminal.

13. The method of claim 12, wherein discharging the charge pump circuit comprises: The output voltage regulation feedback loop of the charge pump circuit is disabled, and the frequency of the clock signal is reduced from a first frequency to a second frequency lower than the first frequency, the second frequency being greater than zero. The method of claim 13 , wherein the second frequency is between 1 / 20 and 1 / 10 of the first frequency.

15. The method of claim 12, wherein discharging the charge pump circuit comprises: disabling the output voltage regulation feedback loop after causing the increase in the current load; as well as After disabling the output voltage regulation feedback loop, the frequency of the clock signal is reduced.

16. The method according to claim 12, further comprising: The output voltage regulation feedback loop is disabled by disabling the comparator.

17. The method of claim 12, wherein the plurality of charge pump stages continue to boost the input voltage while the charge pump circuit is discharged.

18. A charge pump circuit, comprising: Input terminal; Output terminals; a plurality of charge pump stages coupled between the input terminal and the output terminal; a voltage divider coupled between the output terminal and ground; a switch coupled in parallel with the resistor of the voltage divider; a comparator having a first input coupled to an intermediate node of the voltage divider and a second input configured to receive a reference voltage; a clock generator coupled to the plurality of charge pump stages and having an input coupled to an output of the comparator; and A discharge control stage is configured to short-circuit the resistor of the voltage divider by closing the switch, thereby causing an increase in current load on the output terminal.

19. The charge pump circuit of claim 18, wherein the discharge control stage is configured to discharge the charge pump circuit by disabling the comparator.

20. The charge pump circuit of claim 18, wherein the discharge control stage is configured to discharge the charge pump circuit by causing a frequency reduction of a clock signal provided by the clock generator.

21. The charge pump circuit of claim 20, wherein the discharge control stage is configured to discharge the charge pump circuit by: disabling the comparator after closing the switch; and A decrease in the frequency of the clock signal is caused after disabling the comparator.

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