Semiconductor structure and method for manufacturing the same

Abstract

The present invention provides a semiconductor structure and a preparation method thereof, the method comprising: forming a groove in a semiconductor substrate; forming a silicon oxide layer on the bottom and sidewalls of the groove by an in-situ water vapor generation process; doping nitrogen atoms in the silicon oxide layer to form a nitrogen-doped silicon oxide layer; repeatedly performing the above-mentioned oxidation-nitrogen doping process until the thickness target requirement is reached; filling a gate metal layer in the groove of the remaining part surrounded by the bottom and sidewalls of the nitrogen-doped silicon oxide layer, and the top of the gate metal layer is lower than the upper surface of the semiconductor substrate. While forming the silicon oxide layer, nitrogen doping is performed on the silicon oxide layer, and after repeated cycles of oxidation-nitrogen doping for multiple times, the nitrogen content in the gate insulating layer is increased, and the nitrogen doping is made more uniform, so that the diffusion problem of the doped ions in the gate structure is effectively improved while ensuring the performance of the transistor gate structure, and the leakage current of the gate structure is reduced, thereby improving the performance of the transistor.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a transistor gate structure and a preparation method thereof. Background Art

[0002] For many years, silicon dioxide has been used as the gate dielectric layer of choice for transistors. The reason is that silicon dioxide can provide a desired combination of properties, including good electron and hole mobility, the ability to keep electron (surface) states low at interfaces, low hole and electron capture rates, and good compatibility with CMOS processing. Generally, a thin gate dielectric layer is desired to allow for better connection and control of the potential from the gate electrode to the channel.

[0003] With the continuous development of integrated circuit technology, the size of devices continues to decrease, and the thickness of the gate dielectric layer also continues to decrease. Traditionally, a layer of silicon oxynitride is formed on the surface of silicon oxide by remote plasma nitriding process (RPN for short). As the thickness of the oxide layer decreases, the density and depth of nitrogen atoms in the nitride layer formed by RPN are no longer sufficient to meet the electrical requirements. It is easy to cause dopants (for example, boron) to penetrate from the gate into the gate dielectric layer, reducing the breakdown voltage of the gate.

[0004] Therefore, preparing a gate dielectric layer with low leakage current has always been one of the key issues that has attracted much attention in integrated circuit technology. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a transistor gate structure and a method for manufacturing the same, so as to solve the problem of easy leakage of the transistor gate dielectric layer in the prior art.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor structure, the method comprising at least the steps of:

[0007] 1) Providing a semiconductor substrate and forming a trench in the semiconductor substrate;

[0008] 2) forming a silicon oxide layer on the bottom and sidewalls of the trench using an in-situ water vapor generation process;

[0009] 3) doping nitrogen atoms into the silicon oxide layer to form a nitrogen-doped silicon oxide layer;

[0010] 4) Repeating step 2) and step 3) to obtain a nitrogen-doped silicon oxide layer of target thickness;

[0011] 5) forming a gate metal layer in the trench, wherein a top of the gate metal layer is lower than an upper surface of the semiconductor substrate.

[0012] Optionally, before forming the gate metal layer in step 5), the method further includes forming a silicon oxynitride layer on the bottom and sidewalls of the nitrogen-doped silicon oxide layer.

[0013] Furthermore, before forming the gate metal layer in step 5), the method further includes forming a work function layer on the bottom and sidewalls of the silicon oxynitride layer.

[0014] Optionally, the steps of forming the silicon oxide layer in step 2) and forming the nitrogen-doped silicon oxide layer in step 3) include:

[0015] A hydrogen-containing gas, a nitrogen-containing gas and an oxygen-containing gas are introduced into a working chamber, and an in-situ water vapor generation process is used to form the silicon oxide layer on the bottom and sidewall of the trench;

[0016] The introduction of the hydrogen-containing gas into the working chamber is stopped and other process parameters are kept unchanged, so as to dope nitrogen atoms into the silicon oxide layer to form the nitrogen-doped silicon oxide layer.

[0017] Furthermore, the hydrogen-containing gas is turned on and off in a pulse manner, the pulse time of the hydrogen-containing gas is between 0.1s and 5s, the time for forming the silicon oxide layer in step 2) is between 1s and 4s, and the time for doping nitrogen atoms in the silicon oxide layer in step 3) is between 0.1s and 5s.

[0018] Optionally, the hydrogen-containing gas includes hydrogen, the nitrogen-containing gas includes a mixed gas of one or more of the group consisting of nitrous oxide, nitric oxide, nitrogen and nitrogen oxides, and the oxygen-containing gas includes a mixed gas of one or more of the group consisting of nitrous oxide, nitric oxide, oxygen and nitrogen oxides.

[0019] Optionally, the thickness of the silicon oxide layer formed in step 2) is between The concentration of doped nitrogen atoms in step 3) accounts for 0.05% to 0.15% of the atomic concentration in the nitrogen-doped silicon oxide layer.

[0020] Optionally, the thickness of the nitrogen-doped silicon oxide layer formed in step 4) is between 2nm and 6nm, the thickness of the gate metal layer formed is between 15nm and 25nm, and the distance between the top of the gate metal layer and the upper surface of the semiconductor substrate is between 55nm and 75nm.

[0021] The present invention further provides a semiconductor structure, which can be manufactured by the above-mentioned manufacturing method, and the semiconductor structure at least comprises:

[0022] a semiconductor substrate having a trench located within the semiconductor substrate;

[0023] a nitrogen-doped silicon oxide layer, located on the bottom and sidewalls of the trench;

[0024] A gate metal layer is filled in the trench, and a top of the gate metal layer is lower than an upper surface of the semiconductor substrate.

[0025] Optionally, the transistor gate structure further includes a silicon oxynitride layer and a work function layer, the silicon oxynitride layer is located on the bottom and side walls of the nitrogen-doped silicon oxide layer, and the work function layer is located on the bottom and side walls of the silicon oxynitride layer.

[0026] Optionally, the thickness of the nitrogen-doped silicon oxide layer is between 2nm and 6nm, the thickness of the gate metal layer is between 15nm and 25nm, the distance between the top of the gate metal layer and the upper surface of the semiconductor substrate is between 55nm and 75nm, and the thickness of the silicon oxynitride layer is between 1.5nm and 3nm.

[0027] Optionally, the concentration of doped nitrogen atoms in the nitrogen-doped silicon oxide layer accounts for 0.05% to 0.15% of the atomic concentration in the nitrogen-doped silicon oxide layer.

[0028] As described above, the semiconductor structure and preparation method of the present invention perform nitrogen doping on the silicon oxide layer while forming the silicon oxide layer, and undergo multiple repeated cycles of oxidation-nitrogen doping to increase the nitrogen content in the gate insulating layer. In addition, due to the use of the oxidation-nitrogen doping cycle, the nitrogen doping is made more uniform, thereby effectively improving the diffusion problem of anti-doped ions (such as P-type boron ions and N-type phosphorus ions) in the gate structure while ensuring the performance of the transistor gate structure, reducing the leakage current of the gate structure, and thus improving the performance of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figures 1 to 5 It shows a schematic diagram of the cross-sectional structure corresponding to each step in a method for preparing a semiconductor structure in conventional technology.

[0030] Figure 6 The flowchart is a method for preparing a semiconductor structure according to the present invention.

[0031] Figures 7 to 15 It is a schematic diagram of the cross-sectional structure corresponding to each step in the method for preparing a semiconductor structure of the present invention, wherein Figures 9 to 11 Shown is a schematic diagram of forming a nitrogen-doped silicon oxide layer.

[0032] Fig.16 It is a schematic cross-sectional structure diagram of a semiconductor structure according to an embodiment of the present invention.

[0033] Component number description

[0034] 10 Semiconductor substrate

[0035] 11 Groove

[0036] 12 Silicon oxide layer

[0037] 13 Silicon Oxynitride Layer

[0038] 14 Titanium nitride layer

[0039] 15 Gate Metal Layer

[0040] 20 Semiconductor substrate

[0041] 21 Groove

[0042] 22 Silicon oxide layer

[0043] 23 Nitrogen-doped silicon oxide layer

[0044] 24 Gate metal layer

[0045] 25 Silicon Oxynitride Layer

[0046] 26 Work function layer

[0047] D1 Thickness of silicon oxide layer

[0048] D2 Thickness of nitrogen-doped silicon oxide layer

[0049] D3 Gate metal layer thickness

[0050] D4 Thickness of silicon oxynitride layer

[0051] W is the distance between the top of the gate metal layer and the upper surface of the semiconductor substrate

[0052] Steps S1 to S5 DETAILED DESCRIPTION

[0053] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] See also Figures 1 to 16 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0055] like Figures 1 to 5The conventional method for preparing a transistor gate structure in the prior art is shown, and here, a buried gate structure is taken as an example for description.

[0056] like Figure 1 As shown, a semiconductor substrate 10 is provided, and a trench 11 is formed in the semiconductor substrate 10;

[0057] like Figure 2 As shown, a silicon oxide layer 12 is formed on the bottom and sidewalls of the trench 11;

[0058] like Figure 3 As shown, a silicon oxynitride layer 13 is formed on the bottom and sidewall of the silicon oxide layer 12;

[0059] like Figure 4 As shown, a titanium nitride layer 14 is formed on the bottom and sidewall of the silicon nitride oxide layer 13;

[0060] like Figure 5 As shown, a gate metal layer 15 is filled in the trench 11 .

[0061] In the prior art, silicon oxide is commonly used as the gate insulating layer of transistors. This is because silicon oxide can provide the properties required as a gate insulating layer, such as good electron and hole mobility, and excellent process compatibility with CMOS. However, with the continuous development of integrated circuit technology, the size of devices continues to decrease, which inevitably requires the thickness of the gate insulating layer to continue to decrease. As the silicon oxide layer continues to decrease, the leakage current flowing through the gate insulating layer increases, and silicon oxide becomes unacceptable as a gate insulating layer. Therefore, in the above example, the silicon oxide layer 12 and the silicon oxynitride layer 13 are used as transistor gate insulating layers at the same time to reduce the leakage current of the gate structure. However, this method still cannot effectively solve the leakage current problem of the gate structure without affecting the gate threshold voltage of the transistor. Figure 5 As shown, the gate structure leakage problem still occurs in this structure. Therefore, there is a need in the art to continuously reduce the gate structure leakage current while ensuring the transistor gate performance, and therefore there are various technologies to improve the traditional transistor gate structure.

[0062] Based on the above, the present invention provides a method for preparing a semiconductor structure, in which nitrogen is doped into a silicon oxide layer while the silicon oxide layer is formed, and the nitrogen content in the gate insulating layer is increased through multiple cycles of oxidation-nitrogen doping. In addition, due to the use of the oxidation-nitrogen doping cycle, the nitrogen doping is more uniform, thereby effectively improving the diffusion problem of anti-doped ions (such as P-type boron ions and N-type phosphorus ions) in the gate structure while ensuring the performance of the transistor gate structure, reducing the leakage current of the gate structure, and thus improving the performance of the transistor.

[0063] Specifically, if Figure 6 As shown, the present invention provides a method for preparing a semiconductor structure, the preparation method at least comprising the steps of:

[0064] S1, providing a semiconductor substrate and forming a trench in the semiconductor substrate;

[0065] S2, forming a silicon oxide layer on the bottom and sidewalls of the trench by using an in-situ water vapor generation process;

[0066] S3, doping nitrogen atoms into the silicon oxide layer to form a nitrogen-doped silicon oxide layer;

[0067] S4, repeatedly performing step S2 and step S3 to obtain a nitrogen-doped silicon oxide layer of a target thickness;

[0068] S5, forming a gate metal layer in the trench, wherein a top of the gate metal layer is lower than an upper surface of the semiconductor substrate.

[0069] It should be noted that the transistor in the present invention can be either N-type or P-type, and those skilled in the art can choose according to practical applications. In addition to the gate structure shown in the method, other components can be formed in the semiconductor substrate, such as the source and drain of the transistor.

[0070] Example 1

[0071] The method for preparing the semiconductor structure of the present invention will be described in detail below with reference to the accompanying drawings.

[0072] like Figure 6 The figure is a flow chart of the method for preparing the semiconductor structure of the present invention. The shapes of the components in the transistor gate structure are only examples and are not limited to those shown in the figure. Those skilled in the art can modify the shapes according to different product requirements.

[0073] See also Figure 6 and Figure 7 First, step S1 is performed to provide a semiconductor substrate 20 and form a trench 21 in the semiconductor substrate 20 .

[0074] As an example, a plurality of shallow trench isolation structures (not shown) may be formed in the semiconductor substrate 20, and the shallow trench isolation structures isolate a plurality of active regions (not shown) in the semiconductor substrate 20. The trench 21 may be located in the active region, in the shallow trench isolation structure, or in the active region and the shallow trench isolation structure.

[0075] The shape and number of the grooves 21 can be set according to actual needs. Figure 7In the example, the groove 21 is a U-shaped groove and the number of the groove 21 is one, but in the actual example, it is not limited to this.

[0076] As an example, the semiconductor substrate 20 can be a silicon substrate or an epitaxial silicon layer formed on a substrate, and its material includes but is not limited to single crystal or polycrystalline semiconductor materials. In addition, it can also be an intrinsic single crystal silicon substrate or a lightly doped silicon substrate. Further, it can be an N-type polycrystalline silicon substrate or a P-type polycrystalline silicon substrate.

[0077] As an example, forming the trench 21 in the semiconductor substrate 20 includes the following steps:

[0078] 1-1) forming a mask layer (not shown) having a window (not shown) on the surface of the semiconductor substrate 20, wherein the window corresponds to the groove 21 in the upper and lower parts; and

[0079] 1-2) Etching the semiconductor substrate 20 based on the window to form the trench 21.

[0080] See also Figure 6 and Fig. 9 Then, step S2 is performed to form a silicon oxide layer 22 on the bottom and sidewalls of the trench 21 by using an in-situ steam generation (ISSG) process.

[0081] See also Figure 6 and Fig.10 Then, step S3 is performed to dope nitrogen atoms into the silicon oxide layer 22 formed in step S2 to form Fig.10 The nitrogen-doped silicon oxide layer 23 is shown in FIG.

[0082] See also Figure 6 , Figure 7 and Fig.11 Then, step S4 is performed, and steps S2 and S3 are repeated to obtain a nitrogen-doped silicon oxide layer 23 with a target thickness.

[0083] As an example, steps S2 to S4 can be completed in the same working chamber by controlling the on and off of the hydrogen-containing gas, specifically:

[0084] A hydrogen-containing gas, a nitrogen-containing gas and an oxygen-containing gas are introduced into the working chamber, and the silicon oxide layer 22 is formed on the bottom and sidewall of the trench 21 by an in-situ water vapor generation process;

[0085] Then, the hydrogen-containing gas is stopped from being introduced into the working chamber and other process parameters are kept unchanged, so as to dope nitrogen atoms into the silicon oxide layer 22 to form the nitrogen-doped silicon oxide layer 23;

[0086] The above two steps are repeated several times until the thickness of the nitrogen-doped silicon oxide layer 23 reaches the target requirement. Figure 8 and Fig.11 shown.

[0087] As an example, a rapid thermal nitriding process (RTN for short) is used to dope nitrogen atoms into the silicon oxide layer 22 to form the nitrogen-doped silicon oxide layer 23 .

[0088] It should be noted here that in the formation of Figure 8 When the nitrogen-doped silicon oxide layer 23 is formed, the nitrogen-doped silicon oxide layer 23 is not only formed at the bottom and sidewalls of the trench 21, but also formed on the surface of the semiconductor substrate 20. The nitrogen-doped silicon oxide layer 23 formed on the surface of the semiconductor substrate 20 can be removed in time after formation, and can also be removed together with other deposited layers in a subsequent process to save steps. In this embodiment, the nitrogen-doped silicon oxide layer 23 formed on the surface of the semiconductor substrate 20 is removed together after all structures of the gate structure are formed.

[0089] As an example, the hydrogen-containing gas can be turned on and off in a pulsed manner. Preferably, the pulse time of the hydrogen-containing gas is between 0.1s and 5s, the time for forming the silicon oxide layer 22 each time is between 1s and 4s, and the time for doping nitrogen atoms in the silicon oxide layer 22 each time is between 0.1s and 5s.

[0090] As an example, the temperature of the in-situ water vapor generation process is between 800°C and 1200°C, the pressure is between 1 Torr and 20 Torr, and the concentration of the hydrogen-containing gas introduced into the working chamber accounts for 1% to 33% of the total gas concentration of the hydrogen-containing gas, the nitrogen-containing gas and the oxygen-containing gas.

[0091] As an example, each time the silicon oxide layer 22 is formed, the thickness is between The concentration of nitrogen atoms doped in the silicon oxide layer 22 each time accounts for 0.05% to 0.15% of the atomic concentration in the nitrogen-doped silicon oxide layer.

[0092] As an example, the hydrogen-containing gas includes hydrogen, the nitrogen-containing gas includes a mixture of one or more of the group consisting of nitrous oxide, nitric oxide, nitrogen and nitrogen oxides, and the oxygen-containing gas includes a mixture of one or more of the group consisting of nitrous oxide, nitric oxide, oxygen and nitrogen oxides. In this embodiment, the hydrogen-containing gas is selected to be hydrogen, and the nitrogen-containing gas and the oxygen-containing gas are nitrous oxide.

[0093] See also Figure 6 and Fig.15Then, step S5 is performed to fill the trench 21 with a gate metal layer 24 , wherein the top of the gate metal layer 24 is lower than the upper surface of the semiconductor substrate 20 .

[0094] As an example, the material of the gate metal layer 24 may be but is not limited to tungsten (W). The gate metal layer 24 may be formed by any known process. In this embodiment, the gate metal layer 24 is formed by a physical vapor deposition process.

[0095] As an example, Fig.12 As shown, before forming the gate metal layer 24, a step of forming a silicon nitride oxide layer 25 on the bottom and sidewalls of the nitrogen-doped silicon oxide layer 23 is also included. The silicon nitride oxide layer 25 can be formed by any existing known process, for example, a remote plasma nitrogen doping process, a decoupled plasma nitrogen doping process, and a chemical vapor deposition process. In this embodiment, a remote plasma nitrogen doping process is selected to form the silicon nitride oxide layer 25. It should be noted here that the silicon nitride oxide layer 25 will not only be formed on the bottom and sidewalls of the trench 21, but also on the surface of the semiconductor substrate 20. In order to save steps, in this embodiment, the silicon nitride oxide layer 25 formed on the surface of the semiconductor substrate 20 is selected to be removed after all structures of the gate structure are formed. Generally, the silicon nitride oxide layer 25 is formed by a remote plasma nitriding process (abbreviated as RPN) or a decoupled plasma nitriding process (abbreviated as DPN). The nitrogen-doped silicon oxide layer 23 is formed by the method in this embodiment. The formed nitrogen-doped silicon oxide layer 23 can further improve the nitridation effect of the silicon oxynitride layer 25 formed by RPN or DPN, increase the density and depth of nitrogen atoms in the silicon oxynitride layer 25, further increase the nitrogen density in the gate insulating layer, and improve the insulating performance of the gate insulating layer.

[0096] As an example, Fig.13 As shown in FIG. 2 , before forming the gate metal layer 24, the step of forming a work function layer 26 on the bottom and sidewalls of the nitrogen-doped silicon oxide layer 23 is also included. Specifically, when the silicon oxynitride layer 25 is formed on the nitrogen-doped silicon oxide layer 23, the work function layer 26 is formed on the bottom and sidewalls of the silicon oxynitride layer 25. Fig.13As shown; when the silicon nitride oxide layer 25 is not on the nitrogen-doped silicon oxide layer 23, the work function layer 26 is formed on the bottom and side walls of the nitrogen-doped silicon oxide layer 23. The work function layer 26 can be formed by any existing known process. In this embodiment, a physical vapor deposition process is selected to form the work function layer 26. The material of the work function layer 26 can be but is not limited to titanium nitride (TiN). It should be noted here that the work function layer 26 will not only be formed on the bottom and side walls of the groove 21, but also on the surface of the semiconductor substrate 20. In order to save steps, this embodiment chooses to remove the work function layer 26 formed on the surface of the semiconductor substrate 20 after all structures of the gate structure are formed.

[0097] As an example, Fig.14 and Fig.15 As shown, after all structures of the gate structure are formed, the nitrogen-doped silicon oxide layer 23, the silicon oxynitride layer 25, the work function layer 26 and the gate metal layer 24 on the surface of the semiconductor substrate 20 can be removed together. The removal method can be any existing known etching method, such as chemical mechanical polishing, dry etching and wet etching. It should be noted here that when removing the nitrogen-doped silicon oxide layer 23 and the silicon oxynitride layer 25, only the nitrogen-doped silicon oxide layer 23 and the silicon oxynitride layer 25 on the surface of the semiconductor substrate 20 can be removed; the nitrogen-doped silicon oxide layer 23 and the silicon oxynitride layer 25 on the surface of the semiconductor substrate 20 and in part of the groove 21 can also be removed. Fig.15 When removing the work function layer 26 and the gate metal layer 24, the work function layer 26 and the gate metal layer 24 on the surface of the semiconductor substrate 20 and in part of the trench 21 need to be removed. Fig.15 shown.

[0098] As an example, Fig.16 The thickness D2 of the nitrogen-doped silicon oxide layer is between 2nm and 6nm, the thickness D3 of the gate metal layer is between 15nm and 25nm, the distance W between the top of the gate metal layer and the upper surface of the semiconductor substrate is between 55nm and 75nm, and the thickness D4 of the silicon oxynitride layer is between 1.5nm and 3nm.

[0099] The method for preparing the semiconductor structure provided in the present embodiment performs nitrogen doping on the silicon oxide layer 22 while forming the silicon oxide layer 22, and increases the nitrogen content in the gate insulating layer through repeated cycles of oxidation-nitrogen doping. In addition, due to the use of the oxidation-nitrogen doping cycle, the nitrogen doping is made more uniform, thereby effectively improving the diffusion problem of anti-doped ions (such as P-type boron ions and N-type phosphorus ions) in the gate structure while ensuring the performance of the transistor gate structure, reducing the leakage current of the gate structure, and thus improving the performance of the transistor.

[0100] Example 2

[0101] The semiconductor structure of the present invention will be described in detail below in conjunction with the accompanying drawings. The semiconductor structure of this embodiment can be prepared using the preparation method of the above embodiment.

[0102] like Fig.16 FIG. 2 is a schematic diagram showing a cross-sectional structure of a semiconductor structure of this embodiment. The semiconductor structure at least comprises:

[0103] A semiconductor substrate 20 having a trench 21 located in the semiconductor substrate 20;

[0104] A nitrogen-doped silicon oxide layer 23 is located on the bottom and sidewalls of the trench 21;

[0105] The gate metal layer 24 is filled in the trench 21 , and the top of the gate metal layer 24 is lower than the upper surface of the semiconductor substrate 20 .

[0106] As an example, Fig.16 As shown, the transistor gate structure further includes a silicon oxynitride layer 25 , and the silicon oxynitride layer 25 is located on the bottom and sidewalls of the nitrogen-doped silicon oxide layer 23 .

[0107] As an example, Fig.16 As shown in FIG. 1 , the transistor gate structure further includes a work function layer 26, and the work function layer 26 is located on the bottom and sidewalls of the nitrogen-doped silicon oxide layer 23. Specifically, when the silicon oxynitride layer 25 is formed on the nitrogen-doped silicon oxide layer 23, the work function layer 26 is formed on the bottom and sidewalls of the silicon oxynitride layer 25. Fig.16 When the nitrogen-doped silicon oxide layer 23 does not have the silicon nitride oxide layer 25 , the work function layer 26 is formed on the bottom and sidewalls of the nitrogen-doped silicon oxide layer 23 .

[0108] As an example, Fig.16As shown, the thickness D2 of the nitrogen-doped silicon oxide layer is between 2nm and 6nm, the thickness D3 of the gate metal layer is between 15nm and 25nm, the distance W between the top of the gate metal layer and the upper surface of the semiconductor substrate is between 55nm and 75nm, and the thickness of the silicon nitride oxide layer D4 is between 1.5nm and 3nm. The concentration of doped nitrogen atoms in the nitrogen-doped silicon oxide layer 23 accounts for 0.05% to 0.15% of the atomic concentration in the nitrogen-doped silicon oxide layer.

[0109] In summary, the semiconductor structure and preparation method provided by the present invention perform nitrogen doping on the silicon oxide layer while forming the silicon oxide layer, and after repeated cycles of oxidation-nitrogen doping for many times, the nitrogen content in the gate insulating layer is increased. In addition, due to the use of the oxidation-nitrogen doping cycle, the nitrogen doping is more uniform, thereby effectively improving the diffusion problem of anti-doped ions (such as P-type boron ions and N-type phosphorus ions) in the gate structure while ensuring the performance of the transistor gate structure, reducing the leakage current of the gate structure, thereby improving the performance of the transistor. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0110] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The preparation method comprises at least the following steps: 1) Providing a semiconductor substrate and forming a trench in the semiconductor substrate; 2) forming a silicon oxide layer on the bottom and sidewalls of the trench using an in-situ water vapor generation process; 3) doping nitrogen atoms into the silicon oxide layer to form a nitrogen-doped silicon oxide layer; 4) Repeat step 2) and step 3) to obtain a nitrogen-doped silicon oxide layer of target thickness; 5) forming a gate metal layer in the trench, wherein a top of the gate metal layer is lower than an upper surface of the semiconductor substrate.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before forming the gate metal layer in step 5), the method further includes forming a silicon oxynitride layer on the bottom and sidewalls of the nitrogen-doped silicon oxide layer.

3. The method for preparing a semiconductor structure according to claim 2, wherein: Before forming the gate metal layer in step 5), a work function layer is formed on the bottom and sidewalls of the silicon oxynitride layer.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that: The steps of forming the silicon oxide layer in step 2) and forming the nitrogen-doped silicon oxide layer in step 3) include: A hydrogen-containing gas, a nitrogen-containing gas and an oxygen-containing gas are introduced into a working chamber, and an in-situ water vapor generation process is used to form the silicon oxide layer on the bottom and sidewall of the trench; The introduction of the hydrogen-containing gas into the working chamber is stopped and other process parameters are kept unchanged, so as to dope nitrogen atoms into the silicon oxide layer to form the nitrogen-doped silicon oxide layer.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The hydrogen-containing gas is turned on and off in a pulsed manner, the pulse time of the hydrogen-containing gas is between 0.1s and 5s, the time for forming the silicon oxide layer in step 2) is between 1s and 4s, and the time for doping nitrogen atoms in the silicon oxide layer in step 3) is between 0.1s and 5s.

6. The method for preparing a semiconductor structure according to claim 4, characterized in that: The hydrogen-containing gas includes hydrogen, the nitrogen-containing gas includes a mixed gas of one or more of the group consisting of nitrous oxide, nitric oxide, nitrogen and nitrogen oxides, and the oxygen-containing gas includes a mixed gas of one or more of the group consisting of nitrous oxide, nitric oxide, oxygen and nitrogen oxides.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that: The thickness of the silicon oxide layer formed in step 2) is between 2Å and 10Å, and the concentration of doped nitrogen atoms in step 3) accounts for 0.05% to 0.15% of the atomic concentration in the nitrogen-doped silicon oxide layer.

8. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the nitrogen-doped silicon oxide layer formed in step 4) is between 2nm and 6nm, the thickness of the gate metal layer formed is between 15nm and 25nm, and the distance between the top of the gate metal layer and the upper surface of the semiconductor substrate is between 55nm and 75nm.

9. A semiconductor structure prepared according to any one of claims 1 to 8, characterized in that: The semiconductor structure at least comprises: A semiconductor substrate having a trench located in the semiconductor substrate; the material of the semiconductor substrate is silicon; a nitrogen-doped silicon oxide layer, located on the bottom and sidewalls of the trench; a silicon oxynitride layer, the silicon oxynitride layer being located on the bottom and sidewalls of the nitrogen-doped silicon oxide layer; A gate metal layer is filled in the trench, and a top of the gate metal layer is lower than an upper surface of the semiconductor substrate.

10. The semiconductor structure according to claim 9, characterized in that: The invention also comprises a work function layer, wherein the work function layer is located on the bottom and the side wall of the silicon oxynitride layer.

11. The semiconductor structure according to claim 10, characterized in that: The thickness of the nitrogen-doped silicon oxide layer is between 2nm and 6nm, the thickness of the gate metal layer is between 15nm and 25nm, the distance between the top of the gate metal layer and the upper surface of the semiconductor substrate is between 55nm and 75nm, and the thickness of the silicon oxynitride layer is between 1.5nm and 3nm.

12. The semiconductor structure according to claim 9, wherein: The concentration of doped nitrogen atoms in the nitrogen-doped silicon oxide layer accounts for 0.05% to 0.15% of the atomic concentration in the nitrogen-doped silicon oxide layer.

Images