Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, the substrate including a plurality of active regions extending longitudinally in a direction and an isolation region electrically isolating the plurality of active regions from each other. The semiconductor device includes a gate trench extending through the plurality of active regions and the isolation region. The semiconductor device includes a gate structure extending in the gate trench. The semiconductor device includes a gate dielectric layer located between the gate trench and the gate structure in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions, and has a second width in the direction different from the first width in the isolation region.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2018-0147680 filed on November 26, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor device. Background Art

[0003] As the size of semiconductor devices decreases, the distance between elements decreases, and thus, problems may arise. For example, in a memory device, the possibility of interference between two adjacent signal lines increases as the size of the device decreases. Summary of the invention

[0004] The inventive concept provides a semiconductor device having appropriate operating characteristics and high reliability.

[0005] The inventive concept provides a method of manufacturing a semiconductor device having appropriate operating characteristics and high reliability.

[0006] According to some embodiments of the present invention, there is provided a semiconductor device, the semiconductor device comprising a substrate, the substrate comprising a plurality of active regions that can extend longitudinally in a direction and an isolation region that can electrically isolate the plurality of active regions from each other. The semiconductor device may include a gate trench extending through the plurality of active regions and the isolation region. The semiconductor device may include a gate structure extending in the gate trench. The semiconductor device may include a gate dielectric layer located between the gate trench and the gate structure in each of the plurality of active regions. In addition, the gate structure may have a first width in the direction in each of the plurality of active regions, and may have a second width in the direction different from the first width in the isolation region.

[0007] According to some embodiments of the present invention, there is provided a semiconductor device, the semiconductor device comprising a substrate, the substrate comprising a plurality of active regions that can extend longitudinally in a first direction and an isolation region that can electrically isolate the plurality of active regions from each other. The semiconductor device may include a gate trench extending through the plurality of active regions and the isolation region. The semiconductor device may include a gate structure extending in the gate trench. The semiconductor device may include a gate dielectric layer located between the gate trench and the gate structure in each of the plurality of active regions. In addition, the width of the gate structure in the first direction may gradually increase or decrease based on the length position of the gate structure.

[0008] According to some embodiments of the present invention, there is provided a semiconductor device, the semiconductor device including a substrate, the substrate including a plurality of active regions extending longitudinally in a direction and an isolation region that can electrically isolate the plurality of active regions from each other. The semiconductor device may include a first gate trench and a second gate trench that each extend through the plurality of active regions and the isolation region. The first gate trench may be adjacent to the second gate trench. The semiconductor device may include a first gate structure and a second gate structure extending in the first gate trench and the second gate trench, respectively. The semiconductor device may include a first gate dielectric layer located between the first gate trench and the first gate structure in the plurality of active regions. The semiconductor device may include a second gate dielectric layer located between the second gate trench and the second gate structure in the plurality of active regions. In addition, the distance between the first gate structure and the second gate structure in the direction may vary based on the length position of each of the first gate structure and the second gate structure.

[0009] According to some embodiments of the present invention, a method for manufacturing a semiconductor device is provided. The method may include forming a plurality of active areas extending longitudinally in a direction on a substrate and an isolation region that electrically isolates the plurality of active areas from each other. The method may include forming a gate trench extending through the plurality of active areas and the isolation region. The method may include expanding the gate trench in each of the plurality of active areas. The method may include forming a gate dielectric layer on an inner surface of the gate trench in each of the plurality of active areas. In addition, the method may include forming a gate structure in the gate trench. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Embodiments of the present invention will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view showing a schematic configuration of an integrated circuit device according to some embodiments;

[0012] Figure 2 is a block diagram for depicting an example configuration of an integrated circuit device including a dynamic random access memory (DRAM);

[0013] Figure 3 is a plan view showing a schematic configuration of an integrated circuit device according to some embodiments;

[0014] Figure 4 It is used to depict Figure 3 A planar layout of the main components of the memory cell array region shown in;

[0015] Figure 5 is a diagram for describing main elements of a semiconductor device according to some embodiments, Figure 5is shown along Figure 4 A cross-sectional view of some elements of the cross section taken along the line V-V';

[0016] Figure 6 is a diagram for depicting main elements of a semiconductor device according to some embodiments;

[0017] Figure 7 is a plan view showing a plurality of active regions and gate structures in a semiconductor device according to some embodiments;

[0018] Figure 8 is an image obtained by photographing a semiconductor device manufactured according to some embodiments using a scanning electron microscope (SEM);

[0019] 9A to 9D is a side cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments; and

[0020] Fig.10 is a perspective view showing the active area enlarged by the etchant. DETAILED DESCRIPTION

[0021] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals denote like elements, and their repeated description may be omitted.

[0022] Figure 1 is a plan view showing a schematic configuration of an integrated circuit device 10 according to some embodiments.

[0023] The integrated circuit device 10 may include a first region 22 , a second region 24 surrounding the first region 22 , and a substrate 12 including an interface region 26 disposed between the first region 22 and the second region 24 .

[0024] The substrate 12 may include a semiconductor material such as silicon (Si) or germanium (Ge), or may include at least one compound semiconductor selected from SiGe, silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The substrate 12 may include a conductive region (e.g., an impurity-doped well or an impurity-doped structure).

[0025] In some embodiments, the first region 22 may be a memory cell region of the integrated circuit device 10. In some embodiments, the first region 22 may be a memory cell region of a dynamic random access memory (DRAM). The first region 22 may include a unit memory cell having a transistor and a capacitor, or a unit memory cell having a switching element and a variable resistor.

[0026] The second region 24 may be a core region or a peripheral circuit region. A peripheral circuit for driving the memory cells of the first region 22 may be provided in the second region 24.

[0027] A plurality of conductive lines and a plurality of insulating structures may be disposed in the interface region 26 . The plurality of conductive lines are installed to enable electrical connection between the first region 22 and the second region 24 . The plurality of insulating structures are used to insulate the first region 22 from the second region 24 .

[0028] Figure 2 is a block diagram for depicting an example configuration of an integrated circuit device including a DRAM.

[0029] Reference Figure 2 , in the integrated circuit device 10, the first area 22 may be a memory cell area of ​​a DRAM, and the second area 24 may be a peripheral circuit area of ​​the DRAM. The first area 22 may include a memory cell array 22A. In the memory cell array 22A, a plurality of memory cells for storing data may be arranged in row directions and column directions. The plurality of memory cells may each include a cell capacitor and an access transistor. The gate of the access transistor may be connected to a corresponding word line among a plurality of word lines arranged in the row direction, one of the source and the drain of the access transistor may be connected to a complementary bit line or a bit line arranged in the column direction, and the other of the source and the drain may be connected to the cell capacitor.

[0030] The second region 24 may include a row decoder 52 , a sense amplifier 54 , a column decoder 56 , a self-refresh control circuit 58 , a command decoder 60 , a mode register set / extended mode register set (MRS / EMRS) circuit 62 , an address buffer 64 , and a data input / output circuit 66 .

[0031] The sense amplifier 54 may sense and amplify data of the memory cell and may store the amplified data in the memory cell. The sense amplifier 54 may be implemented as a cross-coupled amplifier connected between a bit line and a complementary bit line, both of which are included in the memory cell array 22A.

[0032] The data DQ input through the data input / output circuit 66 may be written into the memory cell array 22A based on the address signal ADD. The data DQ read from the memory cell array 22A based on the address signal ADD may be output to a destination outside the integrated circuit device 10 through the data input / output circuit 66. The address signal ADD may be input to the address buffer 64 for specifying a memory cell in which or from which data is to be written or read. The address buffer 64 may temporarily store the address signal ADD input from a source outside the integrated circuit device 10.

[0033] The row decoder 52 may decode a row address included in the address signal ADD output from the address buffer 64 to specify a word line connected to a memory cell to which data is to be input or output. That is, in a data write or read mode, the row decoder 52 may decode a row address output from the address buffer 64 to enable a corresponding word line. In addition, in a self-refresh mode, the row decoder 52 may decode a row address generated from an address counter to enable a corresponding word line.

[0034] The column decoder 56 can decode the column address included in the address signal ADD output from the address buffer 64 to specify the bit line connected to the memory cell to which data is to be input or output. The memory cell array 22A can output data from the memory cell specified by the row address and the column address, or can write data in the memory cell.

[0035] The command decoder 60 may receive a command signal CMD applied from a source external to the integrated circuit device 10 , and may decode the command signal CMD to internally generate a decoded command signal (eg, a self refresh entry command or a self refresh exit command).

[0036] The MRS / EMRS circuit 62 may set an internal mode register in response to an MRS / EMRS command and an address signal ADD to specify an operation mode of the integrated circuit device 10 .

[0037] In some embodiments, the integrated circuit device 10 may further include a clock circuit for generating a clock signal and a power supply circuit for receiving a source voltage applied from a source outside the integrated circuit device 10 to generate an internal voltage or divide the internal voltage.

[0038] The self-refresh control circuit 58 may control the self-refresh operation of the integrated circuit device 10 in response to a command output from the command decoder 60. The command decoder 60 may include an address counter, a timer, and a core voltage generator. In response to the self-refresh entry command output from the command decoder 60, the address counter may generate a row address signal for specifying a row address to be self-refreshed, and may apply the generated row address signal to the row decoder 52. The address counter may end the counting operation in response to the self-refresh exit command output from the command decoder 60.

[0039] Figure 3 is a plan view showing a schematic configuration of an integrated circuit device 70 according to some embodiments. Figure 1 and Figure 3 In the drawings, like reference numerals denote like elements, and thus, in Figure 3 Their detailed description may be omitted.

[0040] Reference Figure 3, the integrated circuit device 70 may include a plurality of first regions 22. Each of the plurality of first regions 22 may be surrounded by a second region 24, and an interface region 26 is between the first region 22 and the second region 24. In the integrated circuit device 70, each of the plurality of first regions 22 may be a memory cell array region MCA of a DRAM, and the second region 24 may be a peripheral circuit region of the DRAM.

[0041] In the plurality of first regions 22, the memory cell array region MCA may include Figure 2 Memory cell array 22A is depicted. Each of the plurality of first regions 22 may be surrounded by interface region 26 .

[0042] The second region 24 may include a sub-word line driver block SWD, a sense amplifier block S / A, and a coupling block CJT. In the second region 24, a plurality of sub-word line driver blocks SWD may be arranged in the word line direction of the memory cell array region MCA, and a plurality of sense amplifier blocks S / A may be arranged in the bit line direction of the memory cell array region MCA. A plurality of bit line sense amplifiers may be provided in each sense amplifier block S / A. The coupling block CJT may be provided at a point where each sub-word line driver block SWD intersects with the corresponding sense amplifier block S / A. A plurality of power drivers and a plurality of ground drivers for driving the bit line sense amplifiers may be alternately arranged in the coupling block CJT.

[0043] In some embodiments, peripheral circuits such as input / output circuits and inverter chains may also be disposed in the second region 24 .

[0044] Figure 4 It is used to depict Figure 3 1 is a plan layout of main components of the memory cell array area MCA shown in FIG.

[0045] Reference Figure 4 , the memory cell array area MCA may include a plurality of active areas A1. The plurality of active areas A1 may be arranged to include a long axis extending in a first direction (W-axis direction) (i.e., extending longitudinally). Some of the plurality of active areas A1 may be arranged in a row in a second direction (X-axis direction) intersecting the first direction (W-axis direction). Other active areas A1 in the plurality of active areas A1 may be arranged in a row in a third direction (Y-axis direction).

[0046] The plurality of word lines WL may extend in parallel through the plurality of active regions A1 in the second direction (X-axis direction). The plurality of bit lines BL may be disposed on the plurality of word lines WL and may extend in parallel in a third direction (Y-axis direction) intersecting the second direction (X-axis direction). Each of the plurality of bit lines BL may be connected to the corresponding active region A1 through a direct contact DC.

[0047] A plurality of buried contacts BC may be disposed between two adjacent bit lines BL among the plurality of bit lines BL. The plurality of buried contacts BC may be arranged roughly in a row in the second direction (X-axis direction) and the third direction (Y-axis direction). In some embodiments, a plurality of landing pads may be disposed on the plurality of buried contacts BC. Each of the plurality of buried contacts BC and the corresponding landing pad may connect the bottom electrode of the capacitor disposed on the corresponding bit line BL to the corresponding active area A1. Each of the plurality of landing pads may be arranged to partially overlap with the corresponding buried contact BC.

[0048] Figure 5 is a diagram for describing main elements of a semiconductor device according to some embodiments, Figure 5 is shown along Figure 4 A cross-sectional view of some elements of the cross section taken along line V-V'.

[0049] Reference Figure 4 and Figure 5 , a substrate 101 may be provided, and the substrate 101 may include a plurality of active regions A1 and an isolation region ISO electrically isolating the plurality of active regions A1.

[0050] The substrate 101 may include a bulk silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon germanium substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG).

[0051] Each active region A1 of the substrate 101 may have a bar shape, and a major axis of each active region A1 may extend in a first direction (W-axis direction) that is an oblique direction with respect to an extending direction of the plurality of word lines WL and the plurality of bit lines BL.

[0052] The isolation region ISO may surround the plurality of active regions A1 and may electrically isolate the plurality of active regions A1 from each other. The isolation region ISO may include high density plasma (HDP) oxide, tetraethyl orthosilicate (TEOS), plasma enhanced TEOS (PE-TEOS), O 3 - TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), spin-on glass (SOG), toner silazene (TOSZ), or a combination thereof.

[0053] A plurality of gate trenches (eg, first to fourth gate trenches) GT1 to GT4 may be provided to extend through the plurality of active regions A1 and the isolation region ISO. The plurality of gate trenches GT1 to GT4 may extend in their length direction and may alternately pass through the plurality of active regions A1 and the isolation region ISO. Figure 4 As shown in FIG. 1 , the plurality of gate trenches GT1 to GT4 may have different widths in the first direction (W-axis direction) by extending along the length direction thereof and alternately passing through the plurality of active regions A1 and the isolation regions ISO.

[0054] exist Figure 5 In the embodiment, the first gate trench GT1 and the fourth gate trench GT4 may pass through the isolation area ISO, and the second gate trench GT2 and the third gate trench GT3 may pass through the corresponding active area A1. However, it can be understood by those skilled in the art that in the process of extending the first gate trench GT1 to the fourth gate trench GT4, the first gate trench GT1 and the fourth gate trench GT4 may pass through the corresponding active area A1 simultaneously or independently based on their length positions, and the second gate trench GT2 and the third gate trench GT3 may pass through the isolation area ISO simultaneously or independently based on their length positions.

[0055] The second gate trench GT2 and the third gate trench GT3 may pass through the corresponding active area A1 to have a first trench width TW1 in the first direction (W-axis direction). In addition, the first gate trench GT1 and the fourth gate trench GT4 may pass through the isolation area ISO to have a second trench width TW2 in the first direction (W-axis direction).

[0056] The first trench width TW1 may be greater than the second trench width TW2. In some embodiments, the first trench width TW1 may be about 100% to about 140% (or about 110% to about 140%) of the second trench width TW2.

[0057] If the second trench width TW2 is too narrower than the first trench width TW1 (for example, if the first trench width TW1 is significantly larger than approximately 140% of the second trench width TW2), the resistance of the multiple gate structures (for example, the first gate structure to the fourth gate structure) 110A to 110D respectively arranged in the gate trenches GT1 to GT4 will increase, resulting in reduced performance of the semiconductor device.

[0058] Furthermore, when the second trench width TW2 has the same or similar size as the first trench width TW1 , electrical interference between the gate structures 110A to 110D respectively disposed in the gate trenches GT1 to GT4 may increase, resulting in reduced reliability of the semiconductor device.

[0059] In each active region A1, a gate dielectric layer 120 may be disposed on an inner surface of each of the gate trenches GT1 to GT4. The gate dielectric layer 120 may include silicon oxide, silicon oxynitride, an oxide / nitride / oxide (ONO) film, or a high-k dielectric film having a dielectric constant higher than that of silicon oxide. The high-k dielectric film may have a dielectric constant of about 10 to about 25, and may include, for example, hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), hafnium aluminum oxide (HfAlO 3 ), Tantalum Oxide (Ta 2 O 3 ) or titanium oxide (TiO 2 ).

[0060] In some embodiments, at least a portion of the gate dielectric layer 120 may be obtained by thermally oxidizing each active region A1. However, the inventive concept is not limited thereto.

[0061] In the case where the gate dielectric layer 120 is formed by deposition, the gate dielectric layer 120 may be disposed on an inner surface of each of the gate trenches GT1 to GT4 in the isolation region ISO.

[0062] The gate structures 110A to 110D may be disposed in the gate trenches GT1 to GT4 , respectively. Each of the gate structures 110A to 110D may include a lower gate line 110M, an upper gate line 110P, and a capping layer 110K covering the upper gate line 110P.

[0063] The lower gate line 110M may include, for example, a conductive metal or a conductive nitride of a conductive metal. In some embodiments, the lower gate line 110M may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), or a combination thereof. However, the inventive concept is not limited thereto.

[0064] The upper gate line 110P may include, for example, doped polysilicon. However, the inventive concept is not limited thereto.

[0065] The capping layer 110K may include silicon nitride, silicon oxynitride, silicon oxide, or a combination thereof.

[0066] Each of the gate structures 110A to 110D may extend through the plurality of active regions A1 and the isolation region ISO. Each of the gate structures 110A to 110D may extend in a length direction thereof and may alternately pass through the plurality of active regions A1 and the isolation region ISO. Figure 4As shown in FIG. 1 , the plurality of gate structures 110A to 110D may have different widths in the first direction (W-axis direction) by extending in a length direction thereof and alternately passing through the plurality of active regions A1 and the isolation regions ISO.

[0067] exist Figure 5 In the embodiment, the first gate structure 110A and the fourth gate structure 110D may pass through the isolation region ISO, and the second gate structure 110B and the third gate structure 110C may pass through the active region A1. However, it can be understood by those skilled in the art that in the process of extending the first gate structure 110A to the fourth gate structure 110D, the first gate structure 110A and the fourth gate structure 110D may pass through the corresponding active region A1 simultaneously or independently based on their length positions, and the second gate structure 110B and the third gate structure 110C may pass through the isolation region ISO simultaneously or independently based on their length positions.

[0068] The second gate structure 110B and the third gate structure 110C may pass through the corresponding active area A1 to have a first width W1 in the first direction (W-axis direction). In addition, the first gate structure 110A and the fourth gate structure 110D may pass through the isolation area ISO to have a second width W2 in the first direction (W-axis direction). The first width W1 is an average value of multiple widths of the gate structures 110A to 110D in each of the active areas A1 in the first direction, and the second width W2 is an average value of multiple widths of the gate structures 110A to 110D in the isolation area ISO in the first direction.

[0069] The first width W1 may be greater than the second width W2. In some embodiments, the first width W1 may be about 110% to about 140% of the second width W2.

[0070] If the second width W2 is instead too narrower than the first width TW (eg, if the first width W1 is significantly greater than about 140% of the second width W2 ), the resistance of the plurality of gate structures 110A to 110D may increase, resulting in reduced performance of the semiconductor device.

[0071] Furthermore, when the second width W2 has the same or similar size as the first width W1 , electrical interference between the gate structures 110A to 110D may increase, resulting in reduced reliability of the semiconductor device.

[0072] Two gate structures (eg, both shown in FIG. 1 ) passing through the common active area A1 Figure 5 The second gate structure 110B and the third gate structure 110C in FIG. 1 may be separated from each other by a first distance GD1. In addition, the gate structure passing through the common active region A1 and another gate structure adjacent thereto that does not pass through the common active region A1 (for example, both shown in FIG. 1 ) may be separated from each other by a first distance GD1. Figure 5 The second gate structure 110B and the first gate structure 110A in the embodiment may be separated from each other by a second distance GD2. In some embodiments, the first distance GD1 may be smaller than the second distance GD2.

[0073] As the size of semiconductor devices decreases, the current of the wires passing through the semiconductor devices adjacent to the semiconductor devices may affect the operation of the semiconductor devices, and therefore, the distance between the semiconductor devices and the wires passing through the semiconductor devices may be greatly reduced, which may reduce the reliability of the devices. Figure 4 and Figure 5 In the example, the distance to the gate structure passing through the isolation area ISO (e.g., the second distance GD2) can be greater than the distance between the two gate structures in each active area A1 (e.g., the first distance GD1), and thus the possibility of electrical interference between the gate structures can be reduced, thereby enhancing device reliability.

[0074] In some embodiments, lower ends of the gate trenches GT1 to GT4 may be disposed at substantially the same level. A first depth of the gate trenches GT1 to GT4 in each of the plurality of active areas A1 is substantially equal to a second depth of the gate trenches GT1 to GT4 in the isolation area ISO.

[0075] A plurality of source / drain regions SD may be disposed near upper surfaces of the plurality of active regions A1.

[0076] In addition, in the corresponding active area A1, the bit line BL may extend in a direction different from the first direction (W-axis direction). In some embodiments, the bit line BL may extend in a third direction (Y-axis direction) that intersects the second direction (X-axis direction) along which the word line WL (i.e., the gate structure) extends. Therefore, the gate structures 110A to 110D may include corresponding word lines WL, and the word lines WL may each have a first portion in one or more active areas A1, and the first portion is wider than the second portion in the isolation area ISO in the first direction (W-axis direction).

[0077] The bit lines BL may be connected to the corresponding active regions A1 through direct contacts DC.

[0078] The direct contact DC may include a contact semiconductor layer. In some embodiments, the contact semiconductor layer may include polysilicon doped with a P-type dopant or an N-type dopant. For example, the direct contact DC may include a contact semiconductor layer having a thickness of about 1×10 20 cm -3 Up to about 9×10 20 cm -3 The polysilicon layer is doped with a doping concentration selected within a range.

[0079] The bit line BL may include a first conductive layer 131 , a second conductive layer 132 disposed on the first conductive layer 131 , and a spacer SP covering a side surface of each of the first conductive layer 131 and the second conductive layer 132 .

[0080] The first conductive layer 131 may include a semiconductor layer and may contact an upper surface of the direct contact DC. The first conductive layer 131 may have a doping concentration higher than a doping concentration of a contact semiconductor layer of the direct contact DC. In some embodiments, the first conductive layer 131 may include polysilicon doped with a P-type dopant or an N-type dopant. The first conductive layer 131 may be doped with a dopant having the same conductivity type as that of the dopant included in the direct contact DC. For example, the first conductive layer 131 may include a dopant having a conductivity of about 2×10 20 cm -3 Up to about 9×10 21 cm -3 The polysilicon layer is doped with a doping concentration selected within a range.

[0081] The second conductive layer 132 may include TiSiN, TiN, TaN, cobalt nitride (CoN), a metal, a metal silicide, or a combination thereof. The metal and its silicide may include tungsten (W), molybdenum (Mo), gold (Au), copper (Cu), aluminum (Al), nickel (Ni), or cobalt (Co). The second conductive layer 132 may include a single layer, or may include two or more layers of a stack. In some embodiments, the second conductive layer 132 may include a lower layer having TiSiN and an upper layer having W and disposed on the lower layer.

[0082] The spacers SP may include oxide, nitride, air spacers, or a combination thereof. The air spacers may include air or other gases occurring in a process of manufacturing a semiconductor device.

[0083] The corresponding active area A1 may be connected to the capacitor CAP through a buried contact BC.

[0084] The buried contact BC may include a conductive material, and may include, for example, at least one of doped polysilicon, a metal material, and a conductive metal nitride. For example, the buried contact BC may include W and tungsten nitride (W x N 1-x ).

[0085] The buried contact BC may be disposed in the interlayer insulating layer IL1. The interlayer insulating layer IL1 may include, for example, a silicon oxide film formed by a chemical vapor deposition (CVD) process.

[0086] The capacitor CAP may include a bottom electrode 180 , a dielectric layer 181 , and a top electrode 182 .

[0087] The bottom electrode 180 and the top electrode 182 may each include at least one of an impurity-doped semiconductor material (e.g., doped polysilicon), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), and a conductive metal compound (e.g., iridium oxide).

[0088] The dielectric layer 181 may include a single layer including a metal oxide (eg, HfO 2 、ZrO 2 )、Al 2 O 3 , lanthanum oxide (La 2 O 3 ), Ta 2 O 3 or TiO 2 ) and dielectric materials (e.g., strontium titanate (SrTiO 3 (STO)), barium strontium titanate ((Ba,Sr)TiO 3 (BST)), BaTiO 3 , lead zirconate titanate (PZT) or lead lanthanum zirconate titanate (PLZT) having a perovskite structure, or may include a combination thereof.

[0089] Figure 6 is a diagram for describing main elements of a semiconductor device according to some embodiments, Figure 6 Can correspond to along Figure 4 The cross-sectional surface is taken along the line V-V'.

[0090] In terms of the level of the lower end of each of the second gate structure 110B and the third gate structure 110C and the first gate trench GT1 and the fourth gate trench GT4 contacting the active area A1, Figure 6 The semiconductor device shown in FIG. Figure 5 Therefore, hereinafter, the differences will be mainly described, and the description of the differences may be omitted. Figure 6 Components and Figure 5 Duplicate description of the element.

[0091] In the active region A1, a gate trench (eg, Figure 6 The second gate trench GT2 or the third gate trench GT3 in the isolation region ISO may have a first level LV1 relative to the bottom surface of the isolation region ISO. Figure 6The first gate trench GT1 or the fourth gate trench GT4 in the isolation region A1 may have a second level LV2 relative to the bottom surface of the isolation region ISO. The second level LV2 may be lower than the first level LV1. In other words, the depth of the first gate trench GT1 or the fourth gate trench GT4 passing through the isolation region ISO may be deeper than the depth of the second gate trench GT2 or the third gate trench GT3 passing through the active region A1.

[0092] This may be because the second gate structure 110B or the third gate structure 110C passing through the active area A1 partially surrounds the active area A1 , contacts the sidewall contact portion SDL, and passes through the active area A1 .

[0093] Figure 7 is a plan view illustrating a plurality of active regions A1 and a gate structure 110 in a semiconductor device according to some embodiments.

[0094] Reference Figure 7 , the gate structure 110 may extend through the plurality of active regions A1 in the second direction (X-axis direction). Figure 7 The gate structures 110 shown in FIG. 1 may have a side profile with each gate structure having a straight line. Figure 4 Different curved side profiles.

[0095] Specifically, the gate structure 110 may have a side profile 110VX that protrudes convexly in the active area A1. In some embodiments, the width of the gate structure 110 in the first direction (W-axis direction) may decrease in a direction away from the active area A1. In some embodiments, the width of the gate structure 110 in the first direction may have its highest value in the active area A1.

[0096] The gate structure 110 may have a first average width WA1 in the first direction (W-axis direction) in the first active region A11 in the active region A1, and in an embodiment in which the gate structure 110 extends in the length direction thereof toward the second active region A12 in the active region A1, the width of the gate structure 110 in the first direction may gradually change. In some embodiments, in an embodiment in which the gate structure 110 extends from the first active region A11 to the second active region A12 in the length direction thereof, the width of the gate structure 110 in the first direction may gradually decrease. Here, the "gradual decrease" in the width of the gate structure 110 in the first direction may not mean that the width of the gate structure 110 in the first direction gradually decreases relative to the total length between the first active region A11 and the second active region A12.

[0097] The width of the gate structure 110 in the first direction may be reduced by a specific size from the first active region A11, and then, as the gate structure 110 becomes closer to the second active region A12, the width of the gate structure 110 in the first direction may be increased again. In some embodiments, the reduction and increase of the width of the gate structure 110 in the first direction may be repeated one or more times between the first active region A11 and the second active region A12.

[0098] In addition, the gate structure 110 may have a second average width WA2 in the first direction in the second active area A12, and in an embodiment in which the gate structure 110 extends toward the first active area A11 in its length direction, the width of the gate structure 110 in the first direction may gradually change. The first average width WA1 may be the same as or different from the second average width WA2.

[0099] The gate structure 110 may have a third average width WA3 in the isolation region ISO. The first average width WA1 may be about 110% to about 140% of the third average width WA3. If the first average width WA1 is much larger than the third average width WA3 (e.g., substantially higher than 140% of the third average width WA3), the resistance may be excessively increased, and thus, the device performance may be reduced. On the other hand, when the first average width WA1 is the same as or similar to the third average width WA3, the electrical interference between the two adjacent gate structures 110 may be increased, and thus, the reliability of the semiconductor device may be reduced.

[0100] In addition, two adjacent gate structures 110 may be separated from each other by a first distance GD in the first direction, and the first distance GD may gradually change based on the positions in the length direction of the two adjacent gate structures 110. As used herein with respect to two gate trenches GT (or two gate structures 110), the term "adjacent" means that no other gate trench GT (or no other gate structure 110) is interposed between the two gate trenches GT (or two gate structures 110).

[0101] Refer again Figure 7 , the gate trench GT may extend through the plurality of active regions A1 in the second direction (X-axis direction). Figure 7 The gate trenches GT shown in FIG. 1 may have a side profile with each gate trench having a straight line. Figure 4 Different curved side profiles.

[0102] The gate trench GT may have a first trench average width TWA1 in the first direction (W-axis direction) in the first active area A11, and in an embodiment in which the gate trench GT extends toward the second active area A12 in the length direction thereof, the width of the gate trench GT in the first direction may gradually change. In some embodiments, in an embodiment in which the gate trench GT extends from the first active area A11 to the second active area A12 in the length direction thereof, the width of the gate trench GT in the first direction may gradually decrease. Here, the "gradual decrease" in the width of the gate trench GT in the first direction may not mean that the width of the gate trench GT in the first direction gradually decreases relative to the total length between the first active area A11 and the second active area A12.

[0103] The width of the gate trench GT in the first direction may be reduced by a specific size from the first active area A11, and then, as the gate trench GT becomes closer to the second active area A12, the width of the gate trench GT in the first direction may be increased again. In some embodiments, the reduction and increase of the width of the gate trench GT in the first direction may be repeated one or more times between the first active area A11 and the second active area A12.

[0104] In addition, the gate trench GT may have a second trench average width TWA2 in the first direction in the second active area A12, and in an embodiment in which the gate trench GT extends toward the first active area A11 in its length direction, the width of the gate trench GT in the first direction may gradually change. The first trench average width TWA1 may be the same as or different from the second trench average width TWA2.

[0105] The gate trench GT may have a third trench average width TWA3 in the isolation region ISO. The first trench average width TWA1 may be about 110% to about 140% of the third trench average width TWA3. If the first trench average width TWA1 is too much larger than the third trench average width TWA3 (e.g., substantially higher than 140% of the third trench average width TWA3), the resistance may be excessively increased, and thus, the device performance may be reduced. On the other hand, when the first trench average width TWA1 is the same as or similar to the third trench average width TWA3, the electrical interference between the two adjacent gate structures 110 may be increased, and thus, the reliability of the semiconductor device may be reduced.

[0106] In some embodiments, in the active area A1, the concave portion of the gate trench GT may correspond to the convex portion A1CC of the gate structure 110. That is, in the active area A1, the gate structure 110 may have a convex shape based on the concave shape of the gate trench GT. In this case, the gate dielectric layer 120 may be disposed between the gate structure 110 and the gate trench GT.

[0107] Figure 8 is an image obtained by photographing a semiconductor device manufactured according to some embodiments using a scanning electron microscope (SEM).

[0108] Reference Figure 8 , multiple active areas A1 can be connected with Figure 4 The arrangement shown in is similarly arranged in the isolation area ISO. In addition, the plurality of gate structures 110 may extend through the plurality of active areas A1 in the second direction (X-axis direction). The width of each gate structure 110 may not be constant and may vary based on its length position. Specifically, each gate structure 110 may have a wider width in a portion overlapping the active area A1 and may have a narrower width in the isolation area ISO.

[0109] Furthermore, it can be seen that the width of each gate structure 110 gradually changes based on its length position.

[0110] 9A to 9D is a side cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments.

[0111] Reference Fig. 9A , an active area A1 and an isolation area ISO may be defined on the substrate 101. Figure 5 The isolation region ISO and the substrate 101 including the active region A1 are described, and thus, repetition of their detailed descriptions may be omitted.

[0112] A recess for forming the isolation region ISO may be formed in the substrate 101. A mask pattern may be formed, and then the recess may be formed by performing an anisotropic etching process. Subsequently, a gap filling oxide layer may be formed in the recess and planarized. The gap filling oxide layer may include HDP oxide, TEOS, PE-TEOS, O 3 -TEOS, USG, PSG, BSG, BPSG, FSG, SOG, TOSZ or a combination thereof.

[0113] Reference Fig. 9B , a plurality of gate trenches GT1 to GT4 may be formed to extend in one direction. The gate trenches GT1 to GT4 may be formed by a photolithography process.

[0114] The gate trenches GT1 to GT4 may pass through the isolation region ISO and the active region A1 and may extend in one direction. The extension direction of each of the gate trenches GT1 to GT4 may be perpendicular to the long axis direction of the active region A1 or may be obliquely inclined.

[0115] The gate trenches GT1 to GT4 may have substantially the same width.

[0116] Reference Fig. 9C , in the active area A1, gate trenches GT2 and GT3 may be formed / enlarged. The gate trenches GT2 and GT3 may both have an enlarged width.

[0117] In order to enlarge the gate trenches GT1 to GT4 in the active area A1, a wet etching process may be performed on the gate trenches GT1 to GT4 in the active area A1. The wet etching process may be performed by using an etchant that does not etch the isolation area ISO or etches the isolation area ISO very slowly and etches silicon included in the active area A1 very quickly.

[0118] The etchant may be, for example, one that does not etch silicon oxide or one that etches silicon oxide very slowly and etches silicon very quickly.

[0119] In some embodiments, the etchant may be ammonium hydroxide (NH 4 OH), hydrogen peroxide (H 2 O 2 ) and water (H 2 In some embodiments, the etchant may be hydrochloric acid (HCl), H 2 O 2 and H 2 In some embodiments, the etchant may be sulfuric acid (H 2 SO 4 ), H 2 O 2 and H 2 The content of each component can be adjusted according to the situation.

[0120] In some embodiments, the etchant may be, for example, SC1, SC2, an ammonia hydrogen peroxide mixture (APM), a sulfuric acid hydrogen peroxide mixture (SPM), a hydrochloric acid hydrogen peroxide mixture (HPM), or a combination thereof. However, the etchant is not limited thereto.

[0121] In some embodiments, the etchant may contact the active area A1 at a temperature of about 60° C. to about 90° C. for about 1 minute to about 30 minutes.

[0122] Fig.10 is a perspective view showing the active area enlarged by the etchant. Fig.10 , the plurality of gate trenches GT2 and GT3 may penetrate the isolation region ISO and the active region A1 buried in the isolation region ISO, and may extend.

[0123] The gate trenches GT2 and GT3 may each have a fifth trench width TWa in a portion other than the active area A1 , and may each have a sixth trench width TWb greater than the fifth trench width TWa.

[0124] Specifically, in the active area A1, the gate trenches GT2 and GT3 may both have a concave surface. An isotropic etching process using an etchant may be performed based on a chemical reaction. The speed of the chemical reaction may be affected by various variables, and the concentration of the reactant may be one of the various variables.

[0125] The exposed sidewalls of the active area A1 may be partially and isotropically removed by an etchant. Fig.10 The examples shown in are not limited to a specific theory. The transfer of material can be smoothly performed in the horizontal center portion of the exposed sidewall of the active area A1, and therefore, the concentration of the etchant in the horizontal center portion of the exposed sidewall of the active area A1 can be higher than the concentration of the etchant in the horizontal edge portion of the exposed sidewall of the active area A1, so that the isotropic etching reaction can be performed more smoothly. Therefore, the horizontal center portion of the exposed sidewall of the active area A1 can be removed more, and thus can have a concave sidewall profile.

[0126] As described above, the etchant may be selected from various materials so that an etching speed difference occurs with respect to the isolation area ISO and the active area A1, and thus, when the active area A1 is etched, the isolation area ISO may not be etched or may be slightly etched.

[0127] The sixth trench width TWb of each of the gate trenches GT2 and GT3 in the active area A1 may be about 110% to about 140% of the fifth trench width TWa of each of the gate trenches GT2 and GT3 in the isolation area ISO. Each of the fifth trench width TWa and the sixth trench width TWb may vary based on the length direction in the isolation area ISO and the active area A1. In some embodiments, in the isolation area ISO and the active area A1, each of the fifth trench width TWa and the sixth trench width TWb may be represented by an average value based on the length direction.

[0128] Refer again Fig. 9C , the gate trenches GT2 and GT3 of the active area A1 may each have a width wider than the width of each of the gate trenches GT1 and GT4 passing through the isolation area ISO. The lateral width (i.e., the width in the first direction (W-axis direction)) of each of the gate trenches GT2 and GT3 of the active area A1 may be enlarged by the etchant, and therefore, the depth of each of the gate trenches GT2 and GT3 of the active area A1 may be slightly deepened (in the vertical / Z-axis direction).

[0129] However, the gate trenches GT1 to GT4 may have a structure having a high aspect ratio, and therefore, an increase in the longitudinal depth is not large compared to an enlargement in the lateral width and may very slightly affect the shape of each gate trench.

[0130] Reference Fig.9D A gate dielectric layer 120 may be formed in each of the gate trenches GT1 to GT4 , and a plurality of gate structures 110A to 110D may be formed on the gate dielectric layer 120 , each of the plurality of gate structures 110A to 110D including a lower gate line 110M, an upper gate line 110P, and a capping layer 110K.

[0131] The gate dielectric layer 120 may be formed by performing thermal oxidation on the active region A1 or performing deposition on the dielectric material. The thermal oxidation of the active region A1 may be performed by heating the active region A1 under an oxidizing atmosphere. The deposition of the dielectric material may be performed by a CVD process, an atomic layer deposition (ALD) process, or a physical vapor deposition (PVD) process, but the deposition of the dielectric material is not limited thereto. Figure 4 and Figure 5 The material of the gate dielectric layer 120 is described, and thus, a repeated description thereof may be omitted.

[0132] Material layers (eg, a gate dielectric layer 120 , a lower gate line 110M, an upper gate line 110P, and a capping layer 110K) may be formed, and then, by performing an etch-back process on each material, gate structures 110A to 110D may be formed.

[0133] In some embodiments, before forming the gate dielectric layer 120, the isolation region ISO may be partially removed by an anisotropic etching process. Figure 6 . In detail, when a portion of the isolation region ISO (specifically, a portion of the bottom of each of the gate trenches GT1 to GT4 in the isolation region ISO) is removed, a portion of the bottom of each of the gate trenches GT1 to GT4 in the active region A1 may protrude relatively toward the upper portion. Subsequently, when the gate structures 110A to 110D are formed, the semiconductor device may have a wider channel width because the gate structures 110A to 110D partially surround the active region A1 and contact the sidewall contact portion SDL when passing through the active region A1 (see FIG. 1 ). Figure 6 ).

[0134] After forming the gate structures 110A to 110D, a direct contact DC and a bit line BL may be formed, which are electrically connected to the active region A1 at a first position on / adjacent to one side of each of the gate structures 110B and 110C. In addition, a capacitor CAP may be formed, which is electrically connected to the active region A1 at a second position on / adjacent to the other side (e.g., the opposite side) of each of the gate structures 110B and 110C (see FIG. 1 ). Figure 5 ). The capacitor CAP may be electrically connected to the active area A1 through the interlayer insulating layer IL1 and a buried contact BC passing through the interlayer insulating layer IL1.

[0135] According to the method of manufacturing a semiconductor device according to some embodiments, a semiconductor device having appropriate operation characteristics and high reliability may be provided.

[0136] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the scope of the following claims.

Claims

1. A semiconductor device, comprising: A substrate including a plurality of active regions extending longitudinally in a direction and an isolation region electrically isolating the plurality of active regions from each other; a gate trench extending through the plurality of active regions and the isolation region; a gate structure extending in the gate trench; as well as a gate dielectric layer between the gate trench and the gate structure in each of the plurality of active regions, wherein the gate structure has a first width in the direction in each of the plurality of active regions, and has a second width in the direction different from the first width in the isolation region, The first width is 110% to 140% of the second width.

2. The semiconductor device according to claim 1, in, The gate trench includes a recessed sidewall profile in each of the plurality of active areas, wherein the first width is an average value of a plurality of widths in each of the plurality of active regions in the direction, and The second width is an average value of a plurality of widths in the isolation region in the direction.

3. The semiconductor device according to claim 2, wherein: In each of the plurality of active regions, the gate structure has a convex sidewall profile based on the concave sidewall profile of the gate trench in each of the plurality of active regions.

4. The semiconductor device according to claim 1, wherein The width of the gate structure in the direction gradually increases or decreases based on the length position of the gate structure.

5. The semiconductor device according to claim 1, wherein The gate trench has a first trench width in the direction in each of the plurality of active regions, and has a second trench width in the direction different from the first trench width in the isolation region.

6. The semiconductor device according to claim 5, wherein: The first trench width is greater than the second trench width.

7. The semiconductor device according to claim 1, further comprising: a capacitor electrically connected to one of the plurality of active regions at a first location adjacent to a first side of the gate structure; as well as A bit line is electrically connected to the one of the plurality of active regions at a second location adjacent to a second side of the gate structure, the second side being opposite to the first side.

8. The semiconductor device according to claim 1, wherein A first depth of the gate trench in each of the plurality of active regions is equal to a second depth of the gate trench in the isolation region.

9. The semiconductor device according to claim 1, wherein: A first depth of the gate trench in each of the plurality of active regions is shallower than a second depth of the gate trench in the isolation region.

10. A semiconductor device, comprising: a substrate including a plurality of active regions extending longitudinally in a first direction and an isolation region electrically isolating the plurality of active regions from each other; a gate trench extending through the plurality of active regions and the isolation region; a gate structure extending in the gate trench; as well as a gate dielectric layer between the gate trench and the gate structure in each of the plurality of active regions, The width of the gate structure in the first direction gradually increases or decreases based on the length position of the gate structure. wherein the gate structure has a first width in the first direction in each of the plurality of active regions and has a second width in the first direction in the isolation region, The first width is 110% to 140% of the second width.

11. The semiconductor device according to claim 10, in, The gate structure includes a word line, and the word line includes: a first portion located in one or more active regions of the plurality of active regions; and The second part, located in the quarantine area, and In the first direction, a first portion of the word line is wider than a second portion of the word line.

12. The semiconductor device according to claim 10, wherein: The gate structure has a convex sidewall profile in each of the plurality of active regions.

13. The semiconductor device according to claim 12, in, In the isolation region, a width of the gate structure decreases along a second direction away from one of the plurality of active regions, and The second direction intersects with the first direction.

14. A semiconductor device, comprising: A substrate including a plurality of active regions extending longitudinally in a direction and an isolation region electrically isolating the plurality of active regions from each other; A first gate trench and a second gate trench, both extending through the plurality of active regions and the isolation region, the first gate trench being adjacent to the second gate trench; A first gate structure and a second gate structure extending in the first gate trench and the second gate trench, respectively; a first gate dielectric layer located between the first gate trench and the first gate structure in the plurality of active regions; as well as a second gate dielectric layer located between the second gate trench and the second gate structure in the plurality of active regions, wherein a distance between the first gate structure and the second gate structure in the direction varies based on a length position of each of the first gate structure and the second gate structure, wherein each of the first gate structure and the second gate structure has a first width in the direction in each active region and a second width in the direction in the isolation region, The first width is 110% to 140% of the second width.

15. The semiconductor device according to claim 14, wherein: A distance between the first gate structure and the second gate structure in the direction gradually changes based on a length position of each of the first gate structure and the second gate structure.

16. The semiconductor device according to claim 15, in, Where the first gate structure and the second gate structure pass through a first active region of the plurality of active regions, the first gate structure and the second gate structure are separated from each other by a first distance in the direction, wherein, where the first gate structure passes through a second active region of the plurality of active regions and the second gate structure passes through the isolation region, the first gate structure and the second gate structure are separated from each other by a second distance in the direction, and The first distance is shorter than the second distance.

17. The semiconductor device according to claim 14, wherein: A first lowest level of each of the first gate trench and the second gate trench in each of the plurality of active regions is equal to or higher than a second lowest level of each of the first gate trench and the second gate trench in the isolation region.

18. The semiconductor device according to claim 14, further comprising: a third gate trench extending through the isolation region and through a first active region of the plurality of active regions, the second gate trench extending through the first active region; as well as A third gate structure extends in the third gate trench, wherein the distance between the first gate structure and the second gate structure in the direction includes a first distance, a portion of the first gate structure and a portion of the second gate structure are spaced apart from each other by the first distance in a second active region of the plurality of active regions, and The portion of the third gate structure in the isolation region is spaced apart from the portion of the first gate structure in the second active region of the plurality of active regions by a second distance in the direction that is longer than the first distance.

19. A method for manufacturing a semiconductor device, the method comprising: forming a plurality of active regions extending longitudinally in one direction and an isolation region electrically isolating the plurality of active regions from each other on a substrate; forming a gate trench extending through the plurality of active regions and the isolation region; enlarging a gate trench in each of the plurality of active regions; forming a gate dielectric layer on an inner surface of a gate trench in each of the plurality of active regions; as well as forming a gate structure in the gate trench, The step of expanding the gate trench comprises: expanding a first width of the gate trench in each of the plurality of active regions in the direction to be greater than a second width of the gate trench in the isolation region in the direction; The first width is 110% to 140% of the second width.

20. The method according to claim 19, wherein: The step of enlarging the gate trench is performed by wet etching the gate trench in each of the plurality of active areas.

21. The method according to claim 20, wherein: The wet etching is performed by SC1, SC2, an ammonia hydrogen peroxide mixture APM, a sulfuric acid hydrogen peroxide mixture SPM, a hydrochloric acid hydrogen peroxide mixture HPM, or a combination thereof.

22. The method according to claim 19, further comprising: forming a plurality of capacitors electrically connected to the plurality of active regions at first locations adjacent to a first side of the gate structure, respectively; as well as A plurality of bit lines are formed, the plurality of bit lines being electrically connected to the plurality of active regions at second locations adjacent to a second side of the gate structure, the second side being opposite to the first side.

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