A circuit and method for implementing IAP program upgrade based on single-chip microcomputer ISP

Abstract

The present invention relates to a circuit and method for implementing IAP program upgrade based on single-chip microcomputer ISP, which solves the problem of insufficient existing IAP program upgrade methods. The circuit is provided with a single-chip microcomputer, an ISP transient enabling circuit and a timed long reset circuit. The single-chip microcomputer is connected to the ISP transient enabling circuit and the timed long reset circuit respectively. A FLASH area is provided inside the single-chip microcomputer, and the FLASH area stores a firmware program. The ISP transient enabling circuit drives the single-chip microcomputer to restart and enter the ISP state, and upgrades the FLASH area firmware program. The timed long reset circuit hardware resets the single-chip microcomputer, and the FLASH area firmware program is normally operated. The present invention can be widely applied to the IAP program upgrade of a single-chip microcomputer with a level-controlled ISP pin.

Description

Technical Field

[0001] The present invention relates to the technical field of embedded device program upgrade, and in particular to a circuit and method for implementing IAP program upgrade based on single-chip microcomputer ISP. Background Art

[0002] There are two common methods for upgrading the microcontroller program of embedded devices: ISP and IAP. ISP (In System Programming) is a method provided by the microcontroller manufacturer. Through some auxiliary means, the microcontroller does not start from the normal internal FLASH area when it starts, but enters the internally solidified ISP upgrade program, receives data from the serial port, SPI or I2C, and completes the program update and writing of the entire FLASH area. IAP (In applicaTIng Programing) is a program upgrade method implemented by microcontroller developers. When writing programs, developers divide the FLASH area inside the microcontroller into the BOOT area and the APP area, respectively storing the upgrade program and the application program. When the microcontroller is running, it first enters the BOOT area to run the upgrade program. If it is determined that no upgrade is needed, it jumps to the APP area to execute the application program. Otherwise, the program upgrade process begins and the application program in the APP area is rewritten.

[0003] The characteristics and problems of ISP and IAP are as follows:

[0004] 1. The ISP upgrade program is a program that is fixed in a specific address inside the MCU by the MCU manufacturer when it leaves the factory. It does not need to occupy the internal FLASH area provided by the MCU to the user, and does not consume additional storage space. However, the ISP function is provided by the MCU manufacturer and requires auxiliary circuit means to control. It is often used by manufacturers to download programs during research and development and production processes, and cannot be used after the equipment leaves the factory.

[0005] 2. The IAP method is more flexible and does not require additional auxiliary means. The upgrade process can be completed through a standard serial interface or even a remote network. It is often used for program upgrades after leaving the factory, but it requires additional storage space. Storage resources in low-end devices are relatively limited, and the jump function support of some microcontrollers is not perfect. The implementation of the BOOT and APP two-level programs is relatively complicated. Summary of the invention

[0006] In order to solve the deficiencies of the prior art, the present invention provides a circuit and method for implementing IAP program upgrade based on single-chip microcomputer ISP, performs hardware circuit and software function expansion on the basis of the ISP function of the single-chip microcomputer, automatically enters the ISP state after the single-chip microcomputer is reset, and the host computer uses the ISP upgrade protocol to implement program upgrade like the IAP function, thereby saving the FLASH resources of the single-chip microcomputer and reducing the difficulty of developing BOOT and APP two-level programs, and is suitable for single-chip microcomputers with level-controlled ISP pins.

[0007] The invention provides a circuit for implementing IAP program upgrade based on single-chip microcomputer ISP. The circuit comprises a single-chip microcomputer, an ISP transient enabling circuit and a timed long reset circuit. The single-chip microcomputer is respectively connected with the ISP transient enabling circuit and the timed long reset circuit. A FLASH area is arranged inside the single-chip microcomputer, and the FLASH area stores a firmware program. The ISP transient enabling circuit drives the single-chip microcomputer to restart and enter an ISP state, and upgrades the FLASH area firmware program. The timed long reset circuit resets the single-chip microcomputer by hardware, and the FLASH area firmware program is normally operated.

[0008] Preferably, the single-chip microcomputer is provided with an ISP pin, a RESET reset pin, a serial communication pin, and a general IO pin, the general IO pin is provided with a GPIO1 pin and a GPIO2 pin, the general IO pins are respectively connected to the ISP transient enable circuit and the timed long reset circuit, the GPIO1 pin and the GPIO2 pin are respectively used to connect the ISP transient enable circuit and the timed long reset circuit, the program upgrade instruction drives the single-chip microcomputer through the GPIO1 pin, and runs the ISP program solidified inside the single-chip microcomputer to download the firmware program from the communication serial port.

[0009] Preferably, the high level state of the ISP pin enables the single chip microcomputer to enter the ISP enable function, and the level adaptation circuit is directly connected to the ISP pin.

[0010] Preferably, the low level state of the ISP pin enables the single chip microcomputer to enter the ISP enable function, and an inverter is added to the level adaptation circuit to connect the ISP pin.

[0011] Preferably, the ISP transient enabling circuit comprises a capacitor C1, a resistor R1 and an ISP level adaptation circuit, the capacitor C1 is a uF-level energy storage capacitor, and the capacitor C1 can maintain a level threshold for more than 10 milliseconds.

[0012] Preferably, the timing long reset circuit includes a watchdog U2 TPL5010 and a reset time setting resistor R2; the ISP serial port of the single-chip microcomputer is interconnected with external devices, and after the single-chip microcomputer enters the ISP state, the ISP serial port upgrade protocol is used to upgrade the program.

[0013] The present invention also provides a method for implementing IAP program upgrade based on single-chip microcomputer ISP, which is characterized by comprising the following steps:

[0014] Step 1, connect the single-chip microcomputer to the ISP transient enable circuit and the timer long reset circuit through the general IO pins GPIO1 and GPIO2 respectively, and at the same time, the ISP transient enable circuit is connected to the ISP pin of the single-chip microcomputer through the level adaptation circuit, and the timer long reset circuit is also connected to the single-chip microcomputer through the RESET reset pin;

[0015] Step 2: The MCU FLASH area firmware program receives the program upgrade instruction from the communication serial port, and the GPIO1 pin outputs a high level to fully charge the capacitor C1 in the ISP transient enabling circuit, and enables the ISP pin function through the level adaptation circuit. After the software resets the MCU, the MCU enters the ISP state, and runs the ISP program that is internally solidified when the MCU leaves the factory to download the program from the communication serial port to upgrade the FLASH area firmware program;

[0016] Step 3: After the upgrade is completed, the ISP pin has been restored to the disabled state, the timed long reset circuit hardware resets the MCU, and the application is started to run normally.

[0017] Preferably, in step 2, when the microcontroller application is running, the dog is fed regularly through the GPIO2 pin. If the watchdog U2 times out and does not receive the dog feeding signal, the microcontroller is reset by pulling down the RESET pin. The time interval set by the chip is confirmed by the resistance value of the resistor R2. This value is greater than the dog feeding time interval in the microcontroller and the time required for the microcontroller ISP upgrade.

[0018] Preferably, when the device in step 2 is operating normally, the host computer sends a program upgrade instruction through the serial port, and the ISP enable control program sets the GPIO1 pin to output a high level, charges the capacitor C1 for at least 1 second, and resets the microcontroller after the level stabilizes. At the reset moment, the ISP pin remains in the enabled state due to the charging of the capacitor C1, and the microcontroller enters the ISP state.

[0019] Preferably, in step 3, after the ISP program upgrade is completed, when the single-chip microcomputer is still in the ISP state, the single-chip microcomputer is reset after the watchdog in the timing long reset circuit times out, and the single-chip microcomputer is in a normal operating state after restarting.

[0020] The beneficial effects of the present invention are:

[0021] (1) Since the upgrade interface of the present invention is completely controlled by the host computer software program, the operation method is exactly the same as the IAP upgrade process, and the user does not perceive the complex ISP control method, which is simple and easy to operate.

[0022] (2) Since the present invention is based on the ISP program of the single-chip microcomputer for upgrading, the user does not need to develop a BOOT program separately, which greatly reduces the consumption of FLASH resources and the difficulty of developing the BOOT program.

[0023] (3) Since the present invention is based on the ISP serial port of the single-chip microcomputer, it can be easily expanded to local upgrades such as RS232, RS485 or remote upgrades such as Ethernet, GPRS, etc., and has strong applicability.

[0024] The present invention proposes a circuit and method for implementing IAP program upgrade based on single-chip microcomputer ISP, which has the function of hardware fully automatically implementing ISP enabling and resetting and restarting. The user does not need to understand the ISP control method. The process is exactly the same as the common IAP upgrade process, which is simple and easy to operate. At the same time, there is no need to develop a BOOT program, which greatly reduces the FLASH resource consumption and the difficulty of developing the BOOT program, and has strong applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a structural schematic diagram of the present invention.

[0026] Description of the accompanying symbols:

[0027] 1. ISP transient enable circuit; 11. ISP level adaptation circuit; 2. Single chip microcomputer; 21. Communication serial port pin; 3. Timing long reset circuit. DETAILED DESCRIPTION

[0028] The present invention will be further described below in conjunction with the accompanying drawings and embodiments so that those skilled in the art can easily implement the present invention.

[0029] Example 1: Figure 1 As shown, the present invention is provided with a hardware circuit including a single-chip microcomputer 2, an ISP transient enabling circuit 1 and a timed long reset circuit 3. The single-chip microcomputer 2 has an ISP pin, a RESET reset pin, two general IO pins, namely GPIO1 and GPIO2 peripheral circuit control pins, and a communication serial port pin 21. The communication serial port pin 21 includes TX and RX serial port communication pins; the ISP transient enabling circuit 1 includes a capacitor C1, a resistor R1 and an ISP level adaptation circuit 11; the timed long reset circuit 3 includes a watchdog U2 and a reset time setting resistor R2. The two general IO pins GPIO1 and GPIO2 are respectively used to connect the watchdog timing feeding in the ISP transient enabling and timed long reset circuits.

[0030] The single-chip computer 2 has the function of entering the ISP enable state through the high or low level state of the dedicated ISP pin when powered on. When the ISP is enabled at a high level, the ISP level adaptation circuit 11 does not need any device and is directly connected. When the ISP is enabled at a low level, an inverter is added to the ISP level adaptation circuit 11. The energy storage capacitor C1 in the ISP transient enable circuit 1 is a uF-level capacitor that can maintain a level threshold of more than 10 milliseconds to ensure that the ISP pin is enabled to enter the ISP state after the single-chip computer 2 is reset. The discharge resistor R1 and C1 are connected in series to form a discharge loop to ensure that the ISP pin quickly returns to the disabled state after the single-chip computer is started. When the single-chip computer 2 application is running, the dog is fed regularly through the GPIO2 pin. If U2 does not receive the dog feeding signal after the timeout, the single-chip computer 2 is reset by pulling the RESET pin to the bottom. The time interval set by the chip is confirmed by the resistance value of the resistor R2. This value is greater than the dog feeding time interval in the single-chip computer 2 and the time required for the single-chip computer ISP upgrade.

[0031] The software program of single-chip microcomputer 2 includes a serial port instruction processing program, an ISP enable control program, and a reset program. When the device is operating normally, the host computer sends a program upgrade instruction through the serial port. The ISP enable control program sets the GPIO1 pin to output a high level, charges capacitor C1 for at least 1 second, and resets the single-chip microcomputer 2 after the level stabilizes. At the reset moment, the ISP pin remains in the enabled state due to the charging of capacitor C1, and the single-chip microcomputer 2 enters the ISP state. The ISP serial port of single-chip microcomputer 2 is designed to interconnect with external devices. After single-chip microcomputer 2 enters the ISP state, the host computer uses the ISP serial port upgrade protocol to upgrade the program. After the ISP program upgrade is completed, single-chip microcomputer 2 is still in the ISP state until the watchdog in the timing long reset circuit times out and resets the single-chip microcomputer 2. After the single-chip microcomputer 2 restarts, it is in a normal operating state.

[0032] The serial port for communication between the single-chip computer 2 and the external device should use a serial port with ISP function instead of an ordinary serial port. The serial port can directly output TTL level to the outside. The host computer can upgrade the program through the TTL serial port, or it can realize wired methods such as RS232, RS485, M-Bus, or wireless methods such as infrared. The host computer still upgrades the program according to the ISP serial port protocol. The host computer can also remotely upgrade the program through Ethernet or GPRS.

[0033] It is completed by the timeout reset of the watchdog circuit. The circuit uses the TPL5010 low-power watchdog chip with settable reset time to ensure sufficient upgrade time for the ISP. After the upgrade is completed, the device is reset through the RSET pin and re-enters the normal operating program state. When the program is operating normally, a high-level pulse with a width of 1us is periodically sent to the DOG pin of TPL5010 to realize the dog feeding function.

[0034] Embodiment 2: A method for implementing IAP program upgrade based on single-chip microcomputer ISP includes the following steps:

[0035] Step 1, the single-chip microcomputer 2 is provided with an ISP pin, a RESET pin, a TX serial port communication pin, an RX serial port communication pin, and general IO pins GPIO1 and GPIO2, wherein the GPIO1 and GPIO2 are respectively used to connect the ISP transient enable and the timed long reset circuit, and at the same time, the ISP transient enable circuit is connected to the single-chip microcomputer ISP pin through a level adaptation circuit, and the timed long reset circuit is also connected to the single-chip microcomputer through the RESET pin.

[0036] Step 2, the application receives a program upgrade instruction from the communication serial port, the GPIO1 pin outputs a high level, the capacitor C1 in the ISP transient enable circuit is fully charged, the ISP pin function is enabled through the level adaptation circuit, the single-chip microcomputer 2 enters the ISP state after the software resets the single-chip microcomputer 2, and the application is downloaded from the communication serial port using the internal ISP fixed program to upgrade the entire user FLASH area; when the single-chip microcomputer 2 application is running, the watchdog is fed regularly through the GPIO2 pin. If the watchdog does not receive the feeding signal when the timeout expires, the single-chip microcomputer 2 is reset by pulling down the RESET pin. The time interval set by the chip is confirmed by the resistance value of the resistor R2. This value is greater than the feeding time interval in the single-chip microcomputer 2 and the time required for the ISP upgrade of the single-chip microcomputer; when the equipment is operating normally, the upper computer sends a program upgrade instruction through the serial port, the ISP enable control program sets the GPIO1 pin to output a high level, charges the capacitor C1 for at least 1 second, and the reset program software resets the single-chip microcomputer 2 after the level is stable. At the reset moment, the ISP pin remains in the enabled state due to the charging of the capacitor C1, and the single-chip microcomputer 2 enters the ISP state.

[0037] Step 3, after the upgrade is completed, the ISP pin has been restored to the disabled state, the timer long reset circuit hardware resets the MCU 2, and the application is started to run normally. After the ISP program upgrade is completed, the MCU 2 is still in the ISP state until the watchdog in the timer long reset circuit times out and resets the MCU 2. After the MCU 2 restarts, it is in normal operation.

[0038] The above description is only for the preferred embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the scope of the claims of the present invention shall be within the scope of protection of the present invention.

Claims

1. A circuit for implementing IAP program upgrade based on single-chip microcomputer ISP, characterized in that: With single chip microcomputer , ISP transient enabling circuit and timed long reset circuit, the single-chip microcomputer is connected with the ISP transient enabling circuit and the timed long reset circuit respectively, the single-chip microcomputer is provided with a FLASH area inside, the FLASH area stores the firmware program, the ISP transient enabling circuit drives the single-chip microcomputer to restart and enter the ISP state, upgrades the firmware program in the FLASH area, the timed long reset circuit hardware resets the single-chip microcomputer, and runs the firmware program in the FLASH area normally; the single-chip microcomputer is provided with an ISP pin, a RESET reset pin, a serial communication pin, and a general IO pin, and the general IO pin is provided with a GPIO1 pin and a GPIO2 pin The GPIO1 pin and the GPIO2 pin are respectively used to connect the ISP transient enabling circuit and the timed long reset circuit. The ISP transient enabling circuit is provided with an ISP level adapting circuit. The program upgrade instruction drives the single-chip microcomputer through the GPIO1 pin, and runs the ISP program solidified inside the single-chip microcomputer to download the firmware program from the communication serial port. The ISP transient enabling circuit includes a capacitor C1, which is a uF-level energy storage capacitor. The capacitor C1 can maintain a level threshold of more than 10 milliseconds. The timed long reset circuit includes a watchdog U2 TPL5010 and a reset time setting resistor R2. The ISP serial port of the single-chip microcomputer is interconnected with the external device through the serial port upgrade protocol. After the single-chip microcomputer enters the ISP state, the ISP serial port upgrade protocol is used to upgrade the program.

2. According to the circuit for implementing IAP program upgrade based on single-chip microcomputer ISP according to claim 1, it is characterized in that: The high level state of the ISP pin enables the single chip microcomputer to enter the ISP enable function, and the ISP level adaptation circuit is directly connected to the ISP pin.

3. According to the circuit for implementing IAP program upgrade based on single chip microcomputer ISP according to claim 1, it is characterized in that: The low level state of the ISP pin enables the single chip microcomputer to enter the ISP enable function, and an inverter is added to the ISP level adaptation circuit to connect the ISP pin.

4. A method for implementing IAP program upgrade based on single-chip microcomputer ISP, characterized in that: The steps include: Step 1, connect the single-chip microcomputer to the ISP transient enable circuit and the timer long reset circuit through the general IO pins GPIO1 and GPIO2 respectively, and at the same time, the ISP transient enable circuit is connected to the ISP pin of the single-chip microcomputer through the level adaptation circuit, and the timer long reset circuit is also connected to the single-chip microcomputer through the RESET reset pin; Step 2, the firmware program in the FLASH area of ​​the single-chip microcomputer receives a program upgrade instruction from the communication serial port, the GPIO1 pin outputs a high level, the capacitor C1 in the ISP transient enabling circuit is fully charged, the ISP pin function is enabled through the level adaptation circuit, the single-chip microcomputer enters the ISP state after the software resets the single-chip microcomputer, and the ISP program solidified internally when the single-chip microcomputer leaves the factory is run to download the program from the communication serial port to upgrade the firmware program in the FLASH area; when the single-chip microcomputer application program in step 2 is running, the dog is fed regularly through the GPIO2 pin. If the watchdog times out and does not receive the dog feeding signal, the single-chip microcomputer is reset by pulling down the RESET pin. The time interval set by the chip is confirmed by the resistance value of the resistor R2. This value is greater than the dog feeding time interval in the single-chip microcomputer and the time required for the ISP upgrade of the single-chip microcomputer; when the device in step 2 is operating normally, the host computer sends a program upgrade instruction through the serial port, the ISP enable control program sets the GPIO1 pin to output a high level, charges the capacitor C1 for at least 1 second, and the reset program software resets the single-chip microcomputer after the level is stable. At the reset moment, the ISP pin remains in the enabled state due to the charging of the capacitor C1, and the single-chip microcomputer enters the ISP state; Step 3: After the upgrade is completed, the ISP pin has been restored to the disabled state, the timed long reset circuit hardware resets the MCU, and the application is started to run normally.

5. According to claim 4, the method for implementing IAP program upgrade based on single-chip microcomputer ISP is characterized in that: In step 3, after the ISP program upgrade is completed, when the single-chip microcomputer is still in the ISP state, the single-chip microcomputer is reset after the watchdog in the timing long reset circuit times out, and the single-chip microcomputer is in a normal operating state after restarting.

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