Packaged electronic device and packaged electronic device structure

Abstract

Packaged electronic device and packaged electronic device structure. A packaged electronic device includes a substrate having a first major surface and an opposing second major surface. An electronic device is attached to the first major surface of the substrate, and a first conductive structure is connected to at least a first portion of the substrate. A dielectric layer covers at least a portion of the first conductive structure. A conductive layer covers the dielectric layer and is connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an enclosure structure or a reinforcement structure of the packaged electronic device.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly to semiconductor packages, structures thereof, and methods of forming semiconductor packages. Background Art

[0002] Existing semiconductor packages and methods for forming semiconductor packages have deficiencies such as excessive cost, poor thermal performance, reduced reliability, relatively low performance, or package size that is too large. Additional limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing such methods with the present disclosure and referring to the accompanying drawings.

[0003] More specifically, some semiconductor packages include a combination of passive components and one or more semiconductor dies. In the past, passive components such as capacitors were mounted on a package substrate laterally adjacent to the semiconductor die, to which the semiconductor die was also mounted. This conventional assembly method consumes valuable substrate space and significantly increases the overall size of the semiconductor package. The next generation of semiconductor packages will require significantly increased total capacitance values ​​per package, which will greatly increase the size of such packages formed using conventional assembly methods.

[0004] Therefore, it is desirable to have a packaging structure and method for packaging electronic devices that overcomes the disadvantages of the prior art. It is also desirable to have the structure and method easily incorporated into the manufacturing process, adaptable to a variety of die interconnect schemes, and cost-effective. Summary of the invention

[0005] The present specification includes, among other features, a packaged electronic device structure and associated methods, the packaged electronic device structure including one or more capacitor structures embedded in or as part of a cover or reinforcement assembly. In some instances, one or more portions of the capacitor structure are provided using 3D printing technology. The structure and method provide one or more higher capacity capacitors, which reduces bill of materials count and increases assembly yield by, for example, reducing package size. In some instances, the present specification provides for placing one or more capacitors per 25 square millimeters (mm 2 ) is replaced by the capacitive structure of one 0201 capacitor. For example, a 65 mm x 65 mm cap according to the present specification can provide the equivalent capacitance of about 170 0201 capacitors while requiring less substrate space than that required for so many 0201 capacitors.

[0006] More specifically, in one example, a method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure, the first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer, the dielectric layer covering at least a portion of the first conductive structure. The method includes forming a conductive layer, the conductive layer covering the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an enclosure structure or a reinforcement structure of the packaged electronic device.

[0007] In another example, a method for forming a packaged electronic device includes providing a substrate. The method includes electrically coupling an electronic device to the substrate; providing a first conductive structure, the first conductive structure coupled to a first portion of the substrate, wherein the first conductive structure has an upper surface disposed outward from the substrate. The method includes providing a dielectric structure, the dielectric structure covering at least a portion of the upper surface of the first conductive structure. The method includes providing a conductive layer, the conductive layer covering the dielectric structure and coupled to a second portion of the substrate, so that the conductive layer has a first portion overlapping the dielectric structure and a second portion coupled to the substrate, wherein the first conductive structure, the dielectric structure, and the conductive layer include a capacitor structure. In one example, the first conductive structure includes a lid structure, the lid structure is configured to cover an enclosure structure of the electronic device. In another example, the first conductive structure, the dielectric structure, and the conductive structure are configured as a reinforcement structure of the packaged electronic device.

[0008] In another example, a packaged electronic device structure includes a substrate and an electronic device electrically coupled to the substrate. A first conductive structure is coupled to at least a first portion of the substrate, and a dielectric structure covers at least a portion of the first conductive structure. A conductive layer covers the dielectric layer and is coupled to a second portion of the substrate, wherein the first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an enclosure structure or a reinforcement structure.

[0009] In another example, a packaged electronic device includes: a substrate having a first major surface and an opposite second major surface; an electronic device attached to the first major surface of the substrate; a first conductive structure coupled to at least a first portion of the substrate; a dielectric layer covering at least a portion of the first conductive structure; and a conductive layer covering the dielectric layer and coupled to a second portion of the substrate, wherein the first conductive structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an encapsulation structure or a reinforcement structure of the packaged electronic device. Further, the first conductive structure includes a lid structure attached to the substrate so that the lid structure encloses the electronic device; and the dielectric layer is located on an upper surface of the lid structure. Further, the lid structure is attached to a conductive pattern that is part of the substrate; and the conductive layer is coupled to the substrate using a second conductive structure. Further, the lid structure is attached to the electronic device via an attachment layer. Further, the attachment layer includes a 3D printed layer. Further, the cover structure includes a fin structure extending outwardly from an outer surface of the cover structure. Further, the dielectric layer includes a 3D printed layer. Further, the dielectric layer includes one or more of aluminum oxide, zirconium oxide, or hafnium dioxide; and the thickness of the dielectric layer is in the range of about 2 microns to about 5 microns. Further, the packaged electronic device further includes a second conductive structure, the second conductive structure is adjacent to the substrate, wherein: the conductive layer is attached to the second conductive structure; the conductive layer includes a 3D printed layer; and the conductive layer spans a gap of less than 50 microns between an outer edge of the first conductive structure and an inner edge of the second conductive structure. Further, the first conductive structure, the dielectric layer, and the conductive layer include a capacitor structure and a reinforcement structure of the packaged electronic device; and at least two of the first conductive structure, the dielectric layer, and the conductive layer are 3D printed layers.

[0010] In another example, a packaged electronic device includes: a substrate; an electronic device electrically coupled to the substrate; a first conductive structure coupled to a first portion of the substrate, wherein the first conductive structure has an upper surface disposed outward from the substrate; a dielectric structure covering at least a portion of the upper surface of the first conductive structure; and a conductive layer covering the dielectric layer and coupled to a second portion of the substrate, such that the conductive layer has a first portion overlapping the dielectric layer and a second portion coupled to the substrate, wherein: the first conductive structure, the dielectric layer, and the conductive layer define a capacitor structure. Further, the first conductive structure includes a lid structure coupled to the substrate such that the lid structure encloses the electronic device; the dielectric layer is located on an upper surface of the lid structure; the conductive layer is coupled to the substrate using a second conductive structure; and the conductive layer includes a third portion that overlaps a gap of less than 50 microns between an outer edge of the first conductive structure and an inner edge of the second conductive structure. Further, the first conductive structure includes a lid structure, the lid structure is coupled to the substrate, so that the lid structure encloses the electronic device; and the lid structure includes a fin structure extending outward from the outer surface of the lid structure. Further, the dielectric layer includes a 3D printed dielectric layer; the dielectric layer includes one or more of aluminum oxide, zirconium oxide, or hafnium dioxide; and the thickness of the dielectric layer is in the range of 2 microns to 5 microns. Further, the first conductive structure, the dielectric layer, and the conductive layer further include a reinforcement structure for the packaged electronic device; the conductive layer does not overlap with the electronic device in a cross-sectional view; and at least one of the first conductive structure, the dielectric layer, or the conductive layer includes a 3D printed layer.

[0011] In another example, a packaged electronic device structure includes: a substrate; an electronic device electrically coupled to the substrate;

[0012] A cover structure coupled to at least a first portion of the substrate; a dielectric structure covering at least a portion of the first conductive structure; and a conductive layer covering the dielectric layer and coupled to a second portion of the substrate, wherein: the cover structure, the dielectric layer, and the conductive layer are configured as a capacitor structure and are further configured as one or more of an enclosure structure or a reinforcement structure. Further, the cover structure is attached to the substrate so that the cover structure encloses the electronic device. Further, the cover structure includes a fin structure extending outward from an outer surface of the cover structure. Further, the dielectric layer includes a 3D printed dielectric layer; the dielectric layer includes one or more of aluminum oxide, zirconium oxide, or hafnium dioxide; and the thickness of the dielectric layer is in the range of 2 microns to 5 microns. Further, the first conductive structure, the dielectric layer, and the conductive layer further include a reinforcement structure for the packaged electronic device.

[0013] The present disclosure includes other examples. Such examples may be found in the drawings, claims, and / or description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A cross-sectional view of an example packaged electronic device of the present specification is illustrated;

[0015] Figure 2 is a flow chart of an example method of forming a packaged electronic device of the present specification;

[0016] Figure 3-6 illustrates cross-sectional views of a packaged electronic device according to the present specification at various stages of manufacture;

[0017] Figure 7 illustrates a cross-sectional view of an example packaged electronic device of the present specification; and

[0018] Figure 8 A cross-sectional view of an example packaged electronic device of the present description is illustrated.

[0019] For the sake of simplicity and clarity of explanation, the elements in the drawings are not necessarily drawn to scale, and the same reference numerals in different drawings indicate the same elements. In addition, in order to simplify the description, the description and details of the well-known steps and elements are omitted. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the terms used herein are only for the purpose of describing specific example embodiments and are not intended to limit the present disclosure. As used herein, the singular form is intended to also include the plural form unless the context clearly indicates otherwise. It should be further understood that when used in this specification, the terms "include" and / or "include" specify the presence of stated features, quantities, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components and / or groups thereof. It should be understood that although the terms "first, second" and the like can be used herein to describe various components, elements, regions, layers and / or sections, these components, elements, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one component, element, region, layer and / or section from another. Thus, for example, without departing from the teachings of the present disclosure, the first member, first element, first region, first layer and / or first section discussed below may be referred to as the second member, second element, second region, second layer and / or second section. Reference to "one example" or "an example" means that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one example of the present invention. Therefore, the phrases "in one example" or "in an example" appearing in various places in this specification do not necessarily all refer to the same example, but may do so in some cases. In addition, in one or more example embodiments, particular features, structures or characteristics may be combined in any suitable manner, as will be apparent to those of ordinary skill in the art. In addition, the term "while" means that an action occurs at least within a portion of the duration of the initiating action. The use of the words "about, approximately or substantially" means that the value of an element is expected to be close to a state value or position. However, as is well known in the art, there are always slight differences, thereby preventing the value or position from being accurately stated. Unless otherwise indicated, as used herein, the words "above" or "on" include orientations, placements, or relationships in which the specified elements may be in direct or indirect physical contact. It should be further understood that the examples suitably illustrated and described below may have examples and / or may be practiced without any elements not specifically disclosed herein. DETAILED DESCRIPTION

[0020] Figure 1A cross-sectional view of a packaged electronic device 10 (e.g., a packaged semiconductor device 10) according to an example of the present description is illustrated. Although the example is illustrated as a semiconductor device structure of a ball grid array (BGA) package, the present description is not limited to such packaging. Figure 1 In the illustrated example, the packaged semiconductor device 10 includes a substrate 11, an electronic component 16 (such as the semiconductor device 16), a protective layer 17, an attachment material 18, conductive interconnect structures 19 and 21, and a capacitor structure 31. According to the present specification and the present example, the capacitor structure 31 is configured not only as a capacitive device but also as a structure that encloses and protects the semiconductor device 16.

[0021] Conductive interconnect structures 19 and 21, substrate 11, protective layer 17, attachment material 18, and capacitor structure 31 may be referred to as a semiconductor package 190, and package 190 may protect semiconductor device 16 from external elements and / or environmental exposure. In addition, semiconductor package 190 may provide electrical coupling of external electronic components (not shown) to conductive interconnect structures 19 and semiconductor device 16.

[0022] The semiconductor device 16 can be attached to the capacitor structure 31 by an attachment material 18, which can be an insulating material, a thermally conductive and electrically conductive material, or a thermally conductive but non-conductive material. In some examples, the attachment material 18 includes a dielectric material, such as aluminum oxide, zirconium oxide, hafnium dioxide, or a similar material as known to those skilled in the art. The semiconductor device 16 can be further electrically connected to the substrate 11 using an interconnect structure 19, which can include solder balls, solder bumps, copper bumps, nickel gold bumps, or similar materials as known to those of ordinary skill in the art. The protective layer 17 can include a bottom fill material configured to reduce the interconnect strain level generated by the conductive interconnect structure 19. Such a material can include a mixture of a liquid organic resin adhesive and an inorganic filler, and can be formed using, for example, a capillary dispensing technique.

[0023] The substrate 11 may be selected from common circuit boards (e.g., rigid circuit boards and flexible circuit boards), multilayer substrates, laminated substrates, core substrates with built-up layers, coreless substrates, ceramic substrates, lead frame substrates, molded lead frame substrates, or similar substrates as known to those of ordinary skill in the art. In this regard, the present specification is not intended to be limited to any particular type of substrate 11. By way of example and not limitation, the substrate 11 may include an insulating structure 114 having a top surface and a bottom surface that are relatively planar in general. It should be understood that a plurality of insulating layer portions may be used to provide the insulating structure 114. A conductive pattern 112 or a conductive pattern layer 112 may be disposed near the top surface of the insulating structure 114, and a conductive pad 113 may be disposed near the bottom surface of the insulating structure 114.

[0024] The conductive pattern 112 and the conductive pad 113 are electrically interconnected with each other in a prescribed pattern or arrangement using a conductive interconnection path 111 defined by a portion of one or more conductive layers extending from the conductive pattern 112 through the insulating structure 114 to the conductive pad 113. The conductive pattern 112, the conductive pad 113, and the conductive interconnection layer 111 include conductive materials, such as one or more metals. In some examples, the conductive pattern 112, the conductive pad 113, and the conductive interconnection layer 111 include copper. In some examples, a solder mask 115 may be provided near at least multiple portions of the conductive pattern 112 and the top surface of the insulating structure 114. In addition, in some examples, a solder mask 116 may be provided on at least multiple portions of the pad 113 and the bottom surface of the insulating structure 114. The solder mask 115 is used to protect portions of the conductive pattern 112 that will be susceptible to electrical short circuit problems. The solder mask 116 is used to protect portions of the pad 113 that will be exposed to the surrounding environment.

[0025] The semiconductor device 16 can be attached to a portion of the conductive pattern 112 through the conductive interconnect structure 19 in a flip chip configuration. In other examples, the semiconductor device 16 can be attached to the substrate 11 in a device active area upward (or die upward) configuration, and the semiconductor device 16 can be electrically connected to the conductive pattern 112 using wire bonding. In some examples, the conductive interconnect structure 21 can be attached to the conductive pad 113 and can include a conductive material such as a solder ball, a solder bump, a copper bump, a nickel gold bump, or a similar material known to a person of ordinary skill in the art. In other examples, the conductive pad 113 can be configured to be directly connected or attached to a next-level assembly such as a printed circuit board.

[0026] In some examples, semiconductor device 16 is an integrated circuit device, a power semiconductor device, an optical device, any type of sensor device, or other device known to those skilled in the art. Those of ordinary skill in the art will appreciate that semiconductor device 16 is illustrated in simplified form and may further include multiple diffusion regions, multiple conductive layers, and multiple dielectric layers.

[0027] According to the present example, the capacitor structure 31 includes a cover structure 310, a cap structure 310, a first conductive structure 310, a first conductive layer 310, an electrode layer 310, or an enclosure structure 310 including a conductive material such as a metal. In some examples, the cover structure 310 includes copper; aluminum; a metal alloy material such as ASTM-F15 alloy (Kovar 42, 46, 48, and 49), 300 / 400 series stainless steel; a cladding material such as aluminum-copper; a metal-coated ceramic material; or other similar materials known to those of ordinary skill in the art. In some examples, the cover structure 310 can be attached to the conductive pattern 112 using an attachment layer 311, which can include a conductive material such as a solder material, an adhesive, an epoxy resin, or a similar material known to those of ordinary skill in the art. In some examples, the cover structure 310 can be provided using stamping, punching, drawing, etching, laser trimming, and / or electroplating techniques.

[0028] In addition, the capacitor structure 31 includes a dielectric layer 314, a dielectric structure 314, or a dielectric region 314 disposed to cover the upper surface of the cap structure 310. In some examples, the dielectric layer 314 includes an oxide material such as aluminum oxide, zirconium oxide, hafnium dioxide, or similar materials known to those of ordinary skill in the art. In one example, the dielectric layer 314 can be zirconium oxide in a polymer suspension (e.g., polyvinyl pyrrolidone (PVP)), and its thickness can be in the range of about 2 microns to about 5 microns.

[0029] In some instances, the dielectric layer 314 is provided using 3D printing technology, which generally refers to a method of forming an object based on a digitally created file of a three-dimensional object using an additive process. More specifically, an object can be produced by continuously laying down multiple thin layers of material using a 3D printing device. Examples of types of 3D printing include metal printing, such as selective laser melting (SLM) and electron beam melting (EBM); selective laser sintering (SLS); jetting; stereolithography (SLA); and fused deposition modeling (FDM). In other instances, the dielectric layer 314 can be formed using deposition, coating, or screen printing techniques. In other instances, the dielectric layer 314 can include one or more layers including different materials. In some instances, the cover structure 310 can also be formed using 3D printing technology.

[0030] The capacitor structure 31 further includes a conductive electrode layer 317, a top electrode layer 317, or a second conductive layer 317 disposed to cover the dielectric layer 314 (e.g., an upper surface or outer surface of the dielectric layer 314). In some examples, the conductive layer 317 includes one or more metal materials, such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. In some examples, the conductive layer 317 can be connected or attached to the substrate 11 using a conductive stud structure 318, a conductive structure 318, or a conductive structure 318. In some examples, the conductive structure 318 is attached to a portion of the conductive pattern 112 of the substrate 11, such as Figure 1 318 is generally illustrated and may include similar materials as conductive layer 317. Conductive structure 318 is configured to provide an attachment location or stand-off structure for conductive layer 317. Conductive structure 318 may be formed or placed directly onto conductive pattern 112, such as by 3D printing, without an intermediate attachment layer, such as Figure 1 In other examples, the conductive structure 318 can be attached to the substrate 11 using the attachment layer 311 .

[0031] In some examples, the conductive layer 317 is provided using 3D printing. In an example, the conductive layer 317 is arranged so that it overlaps with an air gap 56 that can be less than about 50 microns between the outer edge of the cover structure 310 and / or the dielectric layer 314 and the inner edge of the conductive structure 318. In another example, the gap 56 is less than about 30 microns. The size of the gap 56 is particularly suitable for allowing the use of 3D printing technology, which can allow the gap to be spanned to a certain extent. In other examples, the conductive layer 317 is provided in the form of an external cover structure, which is combined with a connection structure for attaching the external cover structure to the substrate 11. There may be examples in which the conductive structure 318 can be formed in the same process or step as the conductive layer 317, and / or the conductive structure 318 can be integrated with the conductive layer 317 and / or include a portion of the conductive layer.

[0032] According to the present example, the capacitor structure 31 is configured as a parallel plate capacitor, in which the resistance value depends on the area of ​​the plate (i.e., the overlapping area of ​​the conductive layer 317 and the cover structure 310) and the thickness of the dielectric layer 314 (i.e., the distance between the conductive layer 317 and the cover structure 310) and the relative dielectric constant. By providing a capacitor structure 31 configured according to the present specification, the packaged semiconductor device 10 can have a higher capacitance without increasing the lateral size of the substrate 11 as in previous devices. Another advantage of the capacitor structure 31 is that it is provided in the form of a structure that can provide a capacitor function, an EMI (electromagnetic interference) shielding function, and / or a protection function by enclosing the semiconductor device 16. More specifically, the capacitor structure 31 is configured as both a capacitor structure and an encapsulation structure that encloses the semiconductor device 16.

[0033] Figure 2 is a flow chart illustrating an example method 200 for manufacturing a packaged semiconductor device 10 according to the present specification, and Figure 3-6 The packaged semiconductor device 10 is described in accordance with Figure 2 In block S10, a semiconductor device subassembly is provided, the semiconductor device subassembly including a substrate and a semiconductor device attached to a surface of the substrate. In block S20, a first conductive structure is attached to the semiconductor subassembly, such as the substrate.

[0034] Figure 3 The packaged semiconductor device 10 is illustrated at a certain stage of manufacture and further illustrates Figure 2 A semiconductor device subassembly 201 is provided, wherein the substrate may be similar to Figure 1 The substrate 11 (or its variant) and the semiconductor device may be similar to Figure 116 (or its variant) in the semiconductor device 16 (or its variant). In one example, the semiconductor device 16 can be attached to the conductive pattern 112 on the substrate 11 using an interconnect structure 19. The interconnect structure 19 can include solder bumps, metal bumps (such as silver bumps, gold bumps or copper bumps) or other conductive structures known to those of ordinary skill in the art. In this example, a protective layer 17 can be added before or after the semiconductor device 16 is attached to the substrate 11, so that the protective layer 17 is interposed between the semiconductor device 16 and the substrate 11. In some examples, the protective layer 17 can be formed using a capillary dispensing technique and can include materials such as a mixture of a liquid organic resin adhesive and an inorganic filler. In some examples, the protective layer 17 can include a flux material for assisting the reflow process of the interconnect structure 19. In some examples, a conductive interconnect structure 21 can be attached to the conductive pad 13. The conductive interconnect structure 21 can be a metal bump, including a solder bump or other conductive structures known to those of ordinary skill in the art. In other examples, the conductive interconnect structure 21 may not be included, and the conductive pads 113 may be configured to be attached to a next level assembly.

[0035] According to block S20 of method 200, a first conductive structure such as a lid structure 310 is attached to substrate 11, and in some examples, the first conductive structure is further attached to semiconductor device 16 using an attachment material 18. In some examples, lid structure 310 includes copper; aluminum; metal alloy materials such as ASTM-F15 alloys (Kovar 42, 46, 48, and 49), 300 / 400 series stainless steel; cladding materials such as aluminum-copper; metal-coated ceramic materials; or other similar materials known to those of ordinary skill in the art. In one example, attachment material 18 can be formed using 3D printing technology (e.g., 3D printed onto semiconductor device 16 or lid structure 310) and can include dielectric materials such as aluminum oxide, zirconium oxide, hafnium dioxide, or similar materials known to those of ordinary skill in the art. In some examples, cover structure 310 is electrically connected to a portion of conductive pattern 112 of substrate 11 using, for example, attachment layer 311, which may include a conductive material such as a solder material, an adhesive, an epoxy, or a similar material known to one of ordinary skill in the art. In some examples, cover structure 310 may be electrically connected to semiconductor device 16 through conductive pattern 112. In the same or other examples, cover structure 310 may be electrically connected to an external device through conductive pattern 112, conductive interconnect layer 111, conductive pad 113, and conductive interconnect structure 21.

[0036] The method 200 also includes a block S30 of forming a dielectric layer covering an upper surface of the first conductive structure. Figure 4The packaged semiconductor device 10 after processing according to block S30 of method 200 is illustrated. In some examples, the subassembly 201 with the cover structure 310 is placed in a 3D printing device, and a dielectric layer 314 is provided, which covers the upper surface or outer surface 310A of the cover structure 310. In some examples, the dielectric layer 314 includes an oxide material, such as aluminum oxide, zirconium oxide, hafnium dioxide, or similar materials known to those of ordinary skill in the art. In one example, the dielectric layer 314 can be zirconium oxide in a polymer suspension (e.g., PVP), and its thickness can be in the range of about 2 microns to about 5 microns. In other examples, the dielectric layer 314 can be formed using deposition, coating, or screen printing techniques. In other examples, the dielectric layer 314 can include one or more different material layers. In some examples, the dielectric layer 314 can further extend to cover a portion of the lower sidewall of the cover structure 310. In the same or other examples, the dielectric layer 314 can further extend to reach the top surface of the substrate 11.

[0037] The method 200 includes block S40 of forming a second conductive structure on a semiconductor device subassembly, such as a substrate. Figure 5 The packaged semiconductor device 10 is illustrated after processing according to block S40 of the method 200. In some examples, the second conductive structure of block S40 may include Figure 1 A conductive structure 318 is provided, which can be formed on a portion of the substrate 11 and is laterally spaced apart from the semiconductor device 16. In some instances, the conductive structure 318 is a continuous structure that laterally encloses the semiconductor device 16 without interruption or breakage. In one example, the conductive structure 318 is formed using 3D printing technology and can include one or more metal materials, such as copper, gold, silver, stainless steel, or other similar materials known to a person of ordinary skill in the art. In some instances, the conductive structure 318 is electrically connected to another portion of the conductive pattern 112 of the substrate 11 and can be electrically connected to the semiconductor device 16 and / or electrically connected to an external device through the conductive pattern 112, the conductive interconnect layer 111, the conductive pad 113, and the conductive interconnect structure 21.

[0038] The method 200 includes block S50 of forming a conductive layer over the dielectric layer and connected to the second conductive structure. Figure 6 2 illustrates a packaged semiconductor device 10 after processing according to block S50 of method 200. The conductive layer of block S50 may include Figure 1Conductive layer 317. In some instances, conductive layer 317 includes one or more metallic materials, such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. Conductive layer 317 may include one or more sublayers stacked on each other consisting of any such one or more metallic materials. In some instances, conductive layer 317 is provided using 3D printing. In one instance, conductive layer 317 is configured so that it overlaps air gap 56, which may be less than or equal to about 50 microns. In another instance, gap 56 is less than or equal to about 30 microns. In one instance, both conductive structure 318 and conductive layer 317 are provided in the form of an integral structure using a single 3D printing step.

[0039] According to method 200, packaged semiconductor device 10 is provided with capacitor structure 31, which includes cap structure 310, dielectric layer 314 and conductive layer 317. In some examples of method 200, one or more (including all) of attachment layer 18, dielectric layer 314, conductive structure 318 and conductive layer 317 are provided using 3D printing technology.

[0040] Figure 7 A cross-sectional view of an example packaged electronic device 70, such as a packaged semiconductor device 70, is illustrated. The packaged semiconductor device 70 is another example of a semiconductor package 190 according to the present specification. The packaged semiconductor device 70 is similar to the packaged semiconductor device 10, and only the differences will be described below. The packaged semiconductor device 70 includes a capacitor structure 71, which is different from the capacitor structure 71. Figure 1 . According to the present specification, the capacitor structure 71 includes a cover structure 710, a cap structure 710, a first conductive layer 710, an electrode layer 710, or an enclosure structure 710 including one or more fin structures 710A, the fin structures extending outwardly from an outer surface 710B of the cover structure 710. The fin structure 710A is configured to provide the capacitor structure 71 with an increased conductive plate surface area and thus provide a structure with higher capacitance without increasing the lateral size. The number of fins can be increased or decreased depending on the desired capacitance value.

[0041] Similar to the cover structure 310, the cover structure 710 includes a conductive material such as a metal. In some examples, the cover structure 710 includes copper; aluminum; a metal alloy material such as ASTM-F15 alloy (Kovar 42, 46, 48, and 49), 300 / 400 series stainless steel; a cladding material such as aluminum-copper; a metal-coated ceramic material; or other similar materials known to those of ordinary skill in the art.

[0042] In addition, the capacitor structure 71 further includes a dielectric layer 714, a dielectric structure 714, or a dielectric region 714 disposed to cover the cap structure 710 including the fin structure 710A. That is, the dielectric layer 714 conforms to the shape of the cap structure 710. The dielectric layer 714 may include a material similar to that previously described for the dielectric layer 314 of the packaged semiconductor device 10. In an example, the dielectric layer 714 is formed using a 3D printing technique.

[0043] The capacitor structure 71 further includes a conductive electrode layer 717, a top electrode layer 717, or a second conductive layer 717 that is arranged to cover the dielectric layer 714 and the lid structure 710 including the fin structure. That is, the conductive layer 717 conforms to the shape of the dielectric layer 714 and the lid structure 710. The conductive layer 717 may include a material similar to the material described previously for the conductive layer 317 of the packaged semiconductor device 10. As with the capacitor structure 31, the conductive layer 717 may be connected or attached to the substrate 11 using the conductive structure 318. In an example, the conductive layer 717 is formed using 3D printing technology. In the same or other examples, the conductive layer 717 is arranged so that it overlaps with the air gap 56, which may be less than or equal to about 50 microns. In another example, the gap 56 is less than or equal to about 30 microns. These dimensions are suitable for 3D printing technology, which may allow the gap to be crossed to a certain extent when forming the conductive layer 717.

[0044] Figure 2 The method 200 described in the foregoing may be used to form a packaged semiconductor device 70. By way of example, the first conductive structure of block S20 may be a lid structure 710 having one or more fin structures 710A; the dielectric layer of block S30 may be a dielectric layer 714; the second conductive structure of block S40 may be a conductive structure 318; and the conductive layer of block S50 may be a conductive layer 717.

[0045] Figure 8 A cross-sectional view of an example packaged electronic device 80, such as a packaged semiconductor device 80, is illustrated. The packaged semiconductor device 80 is another example of a semiconductor package 190 according to the present specification. The packaged semiconductor device 80 is similar to the packaged semiconductor device 10, and only the differences will be described below. The packaged semiconductor device 80 includes a capacitor structure 81, which is different from the capacitor structure 31 of the packaged semiconductor device 10. According to the present specification, the capacitor structure 81 is configured as a reinforcement structure or a reinforcement ring structure of the substrate 11.

[0046] In some examples, in Figure 8In the cross-sectional view generally described, the capacitor structure 81 is disposed on the substrate 11 in a peripheral position laterally separated from the side edge of the semiconductor device 16. More specifically, the capacitor structure 81 can be configured as a continuous ring structure that laterally encloses the semiconductor device 16 without breaks or interruptions. The capacitor structure 81 includes a conductive layer 810, a first conductive structure 810, a first conductive electrode structure 810, or a conductive structure 810. In some examples, the conductive structure 810 can provide a reinforcing structural property for the substrate 11 and can include one or more metal materials, such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. In some examples, the conductive structure 810 can be attached to the conductive pattern 112 using an attachment layer 311, which can include a conductive material, such as a welding material, an adhesive, an epoxy resin, or a similar material known to those of ordinary skill in the art. In one example, the conductive structure 810 is formed using 3D printing technology. In other examples, the conductive structure 810 can be formed using electroplating, evaporation, sputtering, or other deposition techniques. In another example, the conductive structure can be directly placed on the conductive pattern 112 without an intermediate attachment layer. One difference between the conductive structure 810 and the conductive structure 310 is that the conductive structure 810 is configured to not laterally overlap any portion of the semiconductor device, while the conductive structure 310 completely laterally overlaps the semiconductor device 16.

[0047] The capacitor structure 81 also includes a dielectric layer 814, a dielectric structure 814, or a dielectric region 814 disposed to cover the upper surface of the conductive structure 810. In some examples, the dielectric layer 814 includes an oxide material, such as aluminum oxide, zirconium oxide, hafnium dioxide, or similar materials known to those of ordinary skill in the art. In one example, the dielectric layer 814 can be zirconium oxide in a polymer suspension (e.g., polyvinyl pyrrolidone (PVP)), and its thickness can be in the range of about 2 microns to about 5 microns. In one example, the dielectric layer 814 is formed using 3D printing technology. In other examples, the dielectric layer 814 can be formed using deposition, coating, or screen printing techniques. In other examples, the dielectric layer 814 can include one or more different material layers.

[0048] The capacitor structure 81 further includes a conductive electrode layer 817, a top electrode layer 817, or a second conductive layer 817 disposed to cover the dielectric layer 814. In some examples, the conductive layer 817 includes one or more metal materials, such as copper, gold, silver, stainless steel, or other similar materials known to those of ordinary skill in the art. In some examples, the conductive layer 817 can be connected or attached to the substrate 11 using a conductive stud structure 818 or a conductive structure 818. In some examples, the conductive structure 818 is attached to a portion of the conductive pattern 112, such as Figure 8810 , and may include materials similar to the conductive layer 817. The conductive structure 818 may be attached to the substrate 11 by the attachment layer 311. In other examples, the conductive structure 818 may be placed directly on the conductive pattern 112 without an intermediate attachment layer. In some examples, the conductive layer 817 and the conductive structure 818 are formed using 3D printing technology. In the same or other examples, the conductive layer 817 is arranged so that it overlaps with the air gap 856, which may be less than about 50 microns. In another example, the gap 856 is less than about 30 microns. The size of the gap 856 is suitable for 3D printing technology, which may allow a specific span of the gap when forming the conductive layer 817. Although the present example shows the conductive structure 818 as being located above the substrate 11 inside the conductive structure 810, there may be an example in which this relationship may be reversed, for example, to allow the capacitor structure 81 to adjust the reinforcing effect of the substrate 11.

[0049] like Figure 8 Generally illustrated, conductive layer 817 includes: a first portion 817A, which in cross-sectional view directly overlaps dielectric layer 814 and conductive structure 810 laterally; a second portion 817B, which in cross-sectional view overlaps gap 856; and further includes a third portion 817C, which in cross-sectional view laterally overlaps conductive structure 818. In other examples, conductive layer 817 and conductive structure 818 can be a single component or integrated structure. In further examples, packaged semiconductor device 80 can include a package that includes, for example, an encapsulation material that encapsulates at least semiconductor device 16.

[0050] According to the present specification, capacitor structure 81 provides multiple functions including a capacitance function and a reinforcement function for packaged semiconductor device 80. This allows packaged semiconductor devices using separate reinforcement structures and capacitors to have more functions in a smaller packaging space, because the additional capacitance structure that occupied space on substrate 11 in the previous device can be replaced by the capacitance structure 81 that also provides the function of the reinforcement structure. In other examples, capacitor structure 81 can be combined with capacitor structure 31 or capacitor structure 71 in a packaged electronic device.

[0051] Figure 2 The method 200 described in the foregoing may be used to form a packaged semiconductor device 80. By way of example, the first conductive structure of block S20 may be conductive structure 810; the dielectric layer of block S30 may be dielectric layer 814; the second conductive structure of block S40 may be conductive structure 818; and the conductive layer of block S50 may be conductive layer 817.

[0052] In summary, a person of ordinary skill in the art can determine that, according to one example, a method for forming a packaged semiconductor device includes: providing a substrate having a first main surface and an opposite second main surface; attaching an electronic device to the first main surface of the substrate; providing a first conductive structure, the first conductive structure coupled to at least a first portion of the substrate; forming a dielectric layer, the dielectric layer covering at least a portion of the first conductive structure; and forming a conductive layer, the conductive layer covering the dielectric layer and coupled to the second portion of the substrate, wherein the first conductive structure, the dielectric layer and the conductive layer are configured as a capacitor structure and are further configured as one or more of an encapsulation structure or a reinforcement structure of the packaged electronic device.

[0053] In another example, providing the first conductive structure includes attaching a cover structure to the substrate such that the cover structure encloses the electronic device; and forming the dielectric layer includes forming the dielectric layer on an upper surface of the cover structure. In another example, attaching the cover structure includes attaching the cover structure to a conductive pattern provided as a portion of the substrate; and forming the conductive layer includes coupling the conductive layer to the substrate using a second conductive structure. In still another example, attaching the cover structure further includes attaching the cover structure to the electronic device via an attachment layer.

[0054] In another example, the method includes forming the attachment layer over at least a portion of the electronic device using 3D printing; and attaching the cover structure to the attachment layer. In another example, attaching the cover structure includes attaching the cover structure including a fin structure, the fin structure extending outward from the outer surface of the cover structure. In still another example, forming the dielectric layer includes 3D printing the dielectric layer. In another example, the dielectric layer includes one or more of aluminum oxide, zirconium oxide, or hafnium dioxide; and the thickness of the dielectric layer is in the range of about 2 microns to about 5 microns. In another example, the method further includes forming a second conductive structure adjacent to the substrate; forming the conductive layer includes attaching the conductive layer to the second conductive structure; forming the conductive layer includes 3D printing the conductive layer; and the conductive layer spans a gap of less than 50 microns between an outer edge of the first conductive structure and an inner edge of the second conductive structure. In still another example, the first conductive structure, the dielectric layer, and the conductive layer include a capacitor structure and a reinforcement structure of the packaged electronic device; and at least two of the first conductive structure, the dielectric layer, and the conductive layer are formed using 3D printing.

[0055] In summary, a person of ordinary skill in the art can determine that, according to one example, a method for forming a packaged electronic device may include providing a substrate; electrically coupling an electronic device to the substrate; providing a first conductive structure, the first conductive structure coupled to a first portion of the substrate, wherein the first conductive structure has an upper surface disposed outward from the substrate; providing a dielectric structure, the dielectric structure covering at least a portion of the upper surface of the first conductive structure; and providing a conductive layer, the conductive layer covering the dielectric layer and coupled to a second portion of the substrate, such that the conductive layer has a first portion overlapping the dielectric layer and a second portion coupled to the substrate, wherein the first conductive structure, the dielectric layer, and the conductive layer define a capacitor structure.

[0056] In another example, providing the first conductive structure may include attaching a cover structure to the substrate such that the cover structure encloses the electronic device; providing the dielectric layer may include providing the dielectric layer on an upper surface of the cover structure; providing the conductive layer may include providing the conductive layer coupled to the substrate using a second conductive structure; and the conductive layer may include a third portion that overlaps a gap of less than about 50 microns between an outer edge of the first conductive structure and an inner edge of the second conductive structure. In another example, providing the first conductive structure may include attaching the cover structure to the substrate such that the cover structure encloses the electronic device. In still another example, attaching the cover structure may include attaching the cover structure including a fin structure that extends outwardly from an outer surface of the cover structure. In another example, providing the dielectric layer may include 3D printing the dielectric layer. In another example, the dielectric layer may include one or more of aluminum oxide, zirconium oxide, or hafnium dioxide. In still another example, the thickness of the dielectric layer may be in a range of about 2 microns to about 5 microns. In another example, the first conductive structure, the dielectric layer, and the conductive layer may further include a reinforcement structure of the packaged electronic device. In another example, the conductive layer does not overlap with the electronic device in a cross-sectional view. In another example, at least one of the first conductive structure, the dielectric layer, or the conductive layer is formed using 3D printing.

[0057] In summary, methods for forming packaged electronic devices and related packaged electronic device structures including capacitor structures are disclosed. In one example, the capacitor structure is configured as part of a conductive cover structure. In another example, the capacitor structure is part of a reinforcement structure. According to one method, one or more portions of the capacitor structure are formed using 3D printing technology. The structures and methods provide one or more higher capacity capacitors, which reduce bill of materials count and increase assembly yield by, for example, reducing package size. In some examples, the specification provides for placing capacitors every 25 mm. 2 The lid area is replaced by the capacitive structure of one 0201 capacitor. For example, a 65 mm x 65 mm lid according to the present specification can provide the equivalent capacitance of about 170 0201 capacitors while requiring less substrate space than that required for so many 0201 capacitors.

[0058] Although the subject matter of the present invention has been described using specific example steps and example embodiments, the foregoing drawings and descriptions of the drawings depict only typical examples of the subject matter and should not be considered to limit its scope. Obviously, many alternatives and variations will be apparent to those skilled in the art. By way of example, multiple electronic devices may be attached to the pad in a side-by-side configuration, a stacked configuration, a combination thereof, or other configurations known to those skilled in the art.

[0059] As reflected in the following claims, inventive aspects may lie in less than all of the features of a single aforementioned disclosed example. Therefore, the claims expressed below are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate example of the present invention. In addition, while some examples described herein include some and not other features included in other examples, as will be appreciated by those skilled in the art, the combination of features of different examples is intended to be within the scope of the present invention and is intended to form different examples.

Claims

1. A packaged electronic device, comprising: a substrate having a first major surface and an opposing second major surface; an electronic device attached to the first major surface of the substrate; a single component cover structure attached to a first portion of the first major surface of the substrate, the single component cover structure comprising a conductive material, a top portion, and side portions, the side portions extending downward from the top portion to vertically cover the sides of the electronic device to form an enclosure structure, the enclosure structure vertically and horizontally covering the electronic device; a dielectric layer on the top portion and the side portions of the single component cover structure; as well as a conductive layer on the dielectric layer on the top portion of the single component lid structure, on the dielectric layer on the side portions of the single component lid structure and coupled to a second portion of the first major surface of the substrate, wherein: said side portions and said top portion of said single component cover structure forming a first capacitive plate; the dielectric layer on the top portion of the single component cover structure and on the side portions of the single component cover structure forming a capacitor dielectric; forming a second capacitive plate with the conductive layer on the dielectric layer on the top portion of the single component cover structure and on the dielectric layer on the side portions of the single component cover structure; and The first capacitive plate, the capacitor dielectric, and the second capacitive plate form a capacitor structure for the packaged electronic device.

2. The packaged electronic device according to claim 1, wherein: The single component cover structure includes an edge portion projecting outwardly from the side edge portion of the single component cover structure; and The edge portion is attached to the first portion of the first major surface of the substrate such that the single component cover structure encloses the electronic device without breaking.

3. The packaged electronic device according to claim 1, wherein: The substrate includes a first conductive pattern and a second conductive pattern; The single component cover structure is attached to the first conductive pattern; and The conductive layer is coupled to the second conductive pattern.

4. The packaged electronic device according to claim 1, wherein: The single component cover structure is attached to the electronic device via an attachment layer.

5. The packaged electronic device according to claim 1, wherein: The conductive layer includes a second single component cover structure attached to the first major surface of the substrate and to the dielectric layer.

6. The packaged electronic device according to claim 1, wherein: The single component cover structure includes a portion extending outwardly from the top portion of the single component cover structure and forming the first capacitive plate.

7. The packaged electronic device according to claim 1, wherein: The dielectric layer comprises a 3D printed layer.

8. The packaged electronic device according to claim 7, wherein: The dielectric layer comprises zirconium oxide; and The thickness of the dielectric layer is in the range of 2 microns to 5 microns.

9. The packaged electronic device of claim 1, further comprising: a second conductive structure adjacent to the first major surface of the substrate such that an outer edge of the single component cover structure and an inner edge of the second conductive structure define an air gap, wherein: The conductive layer is a 3D printed layer; and The air gap is less than 50 microns.

10. The packaged electronic device of claim 1, wherein: The dielectric layer and the conductive layer are 3D printed components.

11. A packaged electronic device, comprising: substrate; an electronic device electrically coupled to the substrate; a single component cover structure attached to the substrate covered with the electronic device, the single component cover structure comprising a conductive structure having a top portion and side portions extending from the top portion, wherein: The single component cover structure forms an enclosure structure that vertically and horizontally encloses the electronic device; and The single component cover structure includes one or more fin structures extending outwardly from the top portion; a dielectric structure on the top portion of the single component cover structure, on the side portions of the single component cover structure, and on the one or more fin structures; and a conductive layer on the dielectric structure on the top portion of the single component lid structure, on the dielectric structure on the side portions of the single component lid structure, on the dielectric structure on the one or more fin structures, and coupled to the substrate such that the conductive layer has a first portion on the dielectric structure and a second portion attached to the substrate, wherein: The side portions, the top portion, and the one or more fin structures of the single component cover structure form a first capacitive plate; the dielectric structure on the top portion of the single component cover structure, on the side portions of the single component cover structure, and on the one or more fin structures forming a capacitor dielectric; forming a second capacitive plate with the conductive layer on the dielectric structure on the top portion of the single component cover structure, on the dielectric structure on the side portions of the single component cover structure, and on the dielectric structure on the one or more fin structures; and The first capacitive plate, the capacitor dielectric, and the second capacitive plate form a capacitor structure for the packaged electronic device.

12. The packaged electronic device of claim 11, wherein: attaching the second portion of the conductive layer to the substrate using a conductive structure such that an outer edge of the single component cover structure and an inner edge of the conductive structure define a gap; The conductive layer includes a third portion, the third portion overlapping the gap; and The gap is less than 50 microns.

13. The packaged electronic device of claim 11, wherein: The single component lid structure includes a plurality of fin structures including at least one fin structure on a top side of the packaged electronic device; and The single component cover structure laterally encloses the electronic device without breaking.

14. The packaged electronic device of claim 11, wherein: The dielectric structure comprises a 3D printed dielectric structure; and The dielectric structure includes zirconium oxide zirconium oxide in a polymer suspension.

15. The packaged electronic device of claim 14, wherein: The thickness of the dielectric structure is in the range of 2 microns to 5 microns.

16. A packaged electronic device comprising: substrate; an electronic device electrically coupled to the substrate; a single component cover structure coupled to the substrate and to the electronic device by an attaching material, the single component cover structure comprising a conductive structure having a top portion and side portions extending from the top portion; a dielectric structure overlying the single component cover structure; as well as a conductive structure over the dielectric structure and coupled to the substrate, wherein: The single component cover structure forms an enclosure structure that vertically and horizontally encloses the electronic device; The single component cover structure forms a first capacitive plate; The dielectric structure forms a capacitor dielectric; The conductive structure forms a second capacitive plate; and The first capacitive plate, the capacitor dielectric, and the second capacitive plate form a capacitor structure for the packaged electronic device.

17. The packaged electronic device of claim 16, wherein: The side portion includes a continuous portion that laterally encloses an edge of the electronic device without being broken.

18. The packaged electronic device of claim 17, wherein: The single component cover structure includes a fin structure extending outwardly in a direction perpendicular to the top side of the electronic device and covering over the top side of the electronic device; and The conductive structure and the dielectric structure cover the fin structure.

19. The packaged electronic device of claim 16, wherein: The dielectric structure comprises a 3D printed dielectric structure; and The dielectric structure includes zirconium oxide.

20. The packaged electronic device structure of claim 19, wherein: The thickness of the dielectric structure is in the range of 2 microns to 5 microns.

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